1 /* 2 * Marvell 88e6xxx Ethernet switch single-chip support 3 * 4 * Copyright (c) 2008 Marvell Semiconductor 5 * 6 * Copyright (c) 2015 CMC Electronics, Inc. 7 * Added support for VLAN Table Unit operations 8 * 9 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #include <linux/delay.h> 18 #include <linux/etherdevice.h> 19 #include <linux/ethtool.h> 20 #include <linux/if_bridge.h> 21 #include <linux/interrupt.h> 22 #include <linux/irq.h> 23 #include <linux/irqdomain.h> 24 #include <linux/jiffies.h> 25 #include <linux/list.h> 26 #include <linux/mdio.h> 27 #include <linux/module.h> 28 #include <linux/of_device.h> 29 #include <linux/of_irq.h> 30 #include <linux/of_mdio.h> 31 #include <linux/netdevice.h> 32 #include <linux/gpio/consumer.h> 33 #include <linux/phy.h> 34 #include <net/dsa.h> 35 #include <net/switchdev.h> 36 37 #include "mv88e6xxx.h" 38 #include "global1.h" 39 #include "global2.h" 40 #include "port.h" 41 42 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 43 { 44 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 45 dev_err(chip->dev, "Switch registers lock not held!\n"); 46 dump_stack(); 47 } 48 } 49 50 /* The switch ADDR[4:1] configuration pins define the chip SMI device address 51 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped). 52 * 53 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it 54 * is the only device connected to the SMI master. In this mode it responds to 55 * all 32 possible SMI addresses, and thus maps directly the internal devices. 56 * 57 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing 58 * multiple devices to share the SMI interface. In this mode it responds to only 59 * 2 registers, used to indirectly access the internal SMI devices. 60 */ 61 62 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip, 63 int addr, int reg, u16 *val) 64 { 65 if (!chip->smi_ops) 66 return -EOPNOTSUPP; 67 68 return chip->smi_ops->read(chip, addr, reg, val); 69 } 70 71 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip, 72 int addr, int reg, u16 val) 73 { 74 if (!chip->smi_ops) 75 return -EOPNOTSUPP; 76 77 return chip->smi_ops->write(chip, addr, reg, val); 78 } 79 80 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip, 81 int addr, int reg, u16 *val) 82 { 83 int ret; 84 85 ret = mdiobus_read_nested(chip->bus, addr, reg); 86 if (ret < 0) 87 return ret; 88 89 *val = ret & 0xffff; 90 91 return 0; 92 } 93 94 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip, 95 int addr, int reg, u16 val) 96 { 97 int ret; 98 99 ret = mdiobus_write_nested(chip->bus, addr, reg, val); 100 if (ret < 0) 101 return ret; 102 103 return 0; 104 } 105 106 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = { 107 .read = mv88e6xxx_smi_single_chip_read, 108 .write = mv88e6xxx_smi_single_chip_write, 109 }; 110 111 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip) 112 { 113 int ret; 114 int i; 115 116 for (i = 0; i < 16; i++) { 117 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD); 118 if (ret < 0) 119 return ret; 120 121 if ((ret & SMI_CMD_BUSY) == 0) 122 return 0; 123 } 124 125 return -ETIMEDOUT; 126 } 127 128 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip, 129 int addr, int reg, u16 *val) 130 { 131 int ret; 132 133 /* Wait for the bus to become free. */ 134 ret = mv88e6xxx_smi_multi_chip_wait(chip); 135 if (ret < 0) 136 return ret; 137 138 /* Transmit the read command. */ 139 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, 140 SMI_CMD_OP_22_READ | (addr << 5) | reg); 141 if (ret < 0) 142 return ret; 143 144 /* Wait for the read command to complete. */ 145 ret = mv88e6xxx_smi_multi_chip_wait(chip); 146 if (ret < 0) 147 return ret; 148 149 /* Read the data. */ 150 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA); 151 if (ret < 0) 152 return ret; 153 154 *val = ret & 0xffff; 155 156 return 0; 157 } 158 159 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip, 160 int addr, int reg, u16 val) 161 { 162 int ret; 163 164 /* Wait for the bus to become free. */ 165 ret = mv88e6xxx_smi_multi_chip_wait(chip); 166 if (ret < 0) 167 return ret; 168 169 /* Transmit the data to write. */ 170 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val); 171 if (ret < 0) 172 return ret; 173 174 /* Transmit the write command. */ 175 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, 176 SMI_CMD_OP_22_WRITE | (addr << 5) | reg); 177 if (ret < 0) 178 return ret; 179 180 /* Wait for the write command to complete. */ 181 ret = mv88e6xxx_smi_multi_chip_wait(chip); 182 if (ret < 0) 183 return ret; 184 185 return 0; 186 } 187 188 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = { 189 .read = mv88e6xxx_smi_multi_chip_read, 190 .write = mv88e6xxx_smi_multi_chip_write, 191 }; 192 193 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 194 { 195 int err; 196 197 assert_reg_lock(chip); 198 199 err = mv88e6xxx_smi_read(chip, addr, reg, val); 200 if (err) 201 return err; 202 203 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 204 addr, reg, *val); 205 206 return 0; 207 } 208 209 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 210 { 211 int err; 212 213 assert_reg_lock(chip); 214 215 err = mv88e6xxx_smi_write(chip, addr, reg, val); 216 if (err) 217 return err; 218 219 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 220 addr, reg, val); 221 222 return 0; 223 } 224 225 static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy, 226 int reg, u16 *val) 227 { 228 int addr = phy; /* PHY devices addresses start at 0x0 */ 229 230 if (!chip->info->ops->phy_read) 231 return -EOPNOTSUPP; 232 233 return chip->info->ops->phy_read(chip, addr, reg, val); 234 } 235 236 static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy, 237 int reg, u16 val) 238 { 239 int addr = phy; /* PHY devices addresses start at 0x0 */ 240 241 if (!chip->info->ops->phy_write) 242 return -EOPNOTSUPP; 243 244 return chip->info->ops->phy_write(chip, addr, reg, val); 245 } 246 247 static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page) 248 { 249 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE)) 250 return -EOPNOTSUPP; 251 252 return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page); 253 } 254 255 static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy) 256 { 257 int err; 258 259 /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */ 260 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER); 261 if (unlikely(err)) { 262 dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n", 263 phy, err); 264 } 265 } 266 267 static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy, 268 u8 page, int reg, u16 *val) 269 { 270 int err; 271 272 /* There is no paging for registers 22 */ 273 if (reg == PHY_PAGE) 274 return -EINVAL; 275 276 err = mv88e6xxx_phy_page_get(chip, phy, page); 277 if (!err) { 278 err = mv88e6xxx_phy_read(chip, phy, reg, val); 279 mv88e6xxx_phy_page_put(chip, phy); 280 } 281 282 return err; 283 } 284 285 static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy, 286 u8 page, int reg, u16 val) 287 { 288 int err; 289 290 /* There is no paging for registers 22 */ 291 if (reg == PHY_PAGE) 292 return -EINVAL; 293 294 err = mv88e6xxx_phy_page_get(chip, phy, page); 295 if (!err) { 296 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page); 297 mv88e6xxx_phy_page_put(chip, phy); 298 } 299 300 return err; 301 } 302 303 static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val) 304 { 305 return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER, 306 reg, val); 307 } 308 309 static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val) 310 { 311 return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER, 312 reg, val); 313 } 314 315 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 316 { 317 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 318 unsigned int n = d->hwirq; 319 320 chip->g1_irq.masked |= (1 << n); 321 } 322 323 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 324 { 325 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 326 unsigned int n = d->hwirq; 327 328 chip->g1_irq.masked &= ~(1 << n); 329 } 330 331 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 332 { 333 struct mv88e6xxx_chip *chip = dev_id; 334 unsigned int nhandled = 0; 335 unsigned int sub_irq; 336 unsigned int n; 337 u16 reg; 338 int err; 339 340 mutex_lock(&chip->reg_lock); 341 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, ®); 342 mutex_unlock(&chip->reg_lock); 343 344 if (err) 345 goto out; 346 347 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 348 if (reg & (1 << n)) { 349 sub_irq = irq_find_mapping(chip->g1_irq.domain, n); 350 handle_nested_irq(sub_irq); 351 ++nhandled; 352 } 353 } 354 out: 355 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 356 } 357 358 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 359 { 360 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 361 362 mutex_lock(&chip->reg_lock); 363 } 364 365 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 366 { 367 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 368 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 369 u16 reg; 370 int err; 371 372 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, ®); 373 if (err) 374 goto out; 375 376 reg &= ~mask; 377 reg |= (~chip->g1_irq.masked & mask); 378 379 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg); 380 if (err) 381 goto out; 382 383 out: 384 mutex_unlock(&chip->reg_lock); 385 } 386 387 static struct irq_chip mv88e6xxx_g1_irq_chip = { 388 .name = "mv88e6xxx-g1", 389 .irq_mask = mv88e6xxx_g1_irq_mask, 390 .irq_unmask = mv88e6xxx_g1_irq_unmask, 391 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 392 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 393 }; 394 395 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 396 unsigned int irq, 397 irq_hw_number_t hwirq) 398 { 399 struct mv88e6xxx_chip *chip = d->host_data; 400 401 irq_set_chip_data(irq, d->host_data); 402 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 403 irq_set_noprobe(irq); 404 405 return 0; 406 } 407 408 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 409 .map = mv88e6xxx_g1_irq_domain_map, 410 .xlate = irq_domain_xlate_twocell, 411 }; 412 413 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 414 { 415 int irq, virq; 416 u16 mask; 417 418 mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask); 419 mask |= GENMASK(chip->g1_irq.nirqs, 0); 420 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask); 421 422 free_irq(chip->irq, chip); 423 424 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 425 virq = irq_find_mapping(chip->g1_irq.domain, irq); 426 irq_dispose_mapping(virq); 427 } 428 429 irq_domain_remove(chip->g1_irq.domain); 430 } 431 432 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 433 { 434 int err, irq, virq; 435 u16 reg, mask; 436 437 chip->g1_irq.nirqs = chip->info->g1_irqs; 438 chip->g1_irq.domain = irq_domain_add_simple( 439 NULL, chip->g1_irq.nirqs, 0, 440 &mv88e6xxx_g1_irq_domain_ops, chip); 441 if (!chip->g1_irq.domain) 442 return -ENOMEM; 443 444 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 445 irq_create_mapping(chip->g1_irq.domain, irq); 446 447 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 448 chip->g1_irq.masked = ~0; 449 450 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask); 451 if (err) 452 goto out_mapping; 453 454 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 455 456 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask); 457 if (err) 458 goto out_disable; 459 460 /* Reading the interrupt status clears (most of) them */ 461 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, ®); 462 if (err) 463 goto out_disable; 464 465 err = request_threaded_irq(chip->irq, NULL, 466 mv88e6xxx_g1_irq_thread_fn, 467 IRQF_ONESHOT | IRQF_TRIGGER_FALLING, 468 dev_name(chip->dev), chip); 469 if (err) 470 goto out_disable; 471 472 return 0; 473 474 out_disable: 475 mask |= GENMASK(chip->g1_irq.nirqs, 0); 476 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask); 477 478 out_mapping: 479 for (irq = 0; irq < 16; irq++) { 480 virq = irq_find_mapping(chip->g1_irq.domain, irq); 481 irq_dispose_mapping(virq); 482 } 483 484 irq_domain_remove(chip->g1_irq.domain); 485 486 return err; 487 } 488 489 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask) 490 { 491 int i; 492 493 for (i = 0; i < 16; i++) { 494 u16 val; 495 int err; 496 497 err = mv88e6xxx_read(chip, addr, reg, &val); 498 if (err) 499 return err; 500 501 if (!(val & mask)) 502 return 0; 503 504 usleep_range(1000, 2000); 505 } 506 507 dev_err(chip->dev, "Timeout while waiting for switch\n"); 508 return -ETIMEDOUT; 509 } 510 511 /* Indirect write to single pointer-data register with an Update bit */ 512 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update) 513 { 514 u16 val; 515 int err; 516 517 /* Wait until the previous operation is completed */ 518 err = mv88e6xxx_wait(chip, addr, reg, BIT(15)); 519 if (err) 520 return err; 521 522 /* Set the Update bit to trigger a write operation */ 523 val = BIT(15) | update; 524 525 return mv88e6xxx_write(chip, addr, reg, val); 526 } 527 528 static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip) 529 { 530 if (!chip->info->ops->ppu_disable) 531 return 0; 532 533 return chip->info->ops->ppu_disable(chip); 534 } 535 536 static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip) 537 { 538 if (!chip->info->ops->ppu_enable) 539 return 0; 540 541 return chip->info->ops->ppu_enable(chip); 542 } 543 544 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly) 545 { 546 struct mv88e6xxx_chip *chip; 547 548 chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work); 549 550 mutex_lock(&chip->reg_lock); 551 552 if (mutex_trylock(&chip->ppu_mutex)) { 553 if (mv88e6xxx_ppu_enable(chip) == 0) 554 chip->ppu_disabled = 0; 555 mutex_unlock(&chip->ppu_mutex); 556 } 557 558 mutex_unlock(&chip->reg_lock); 559 } 560 561 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps) 562 { 563 struct mv88e6xxx_chip *chip = (void *)_ps; 564 565 schedule_work(&chip->ppu_work); 566 } 567 568 static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip) 569 { 570 int ret; 571 572 mutex_lock(&chip->ppu_mutex); 573 574 /* If the PHY polling unit is enabled, disable it so that 575 * we can access the PHY registers. If it was already 576 * disabled, cancel the timer that is going to re-enable 577 * it. 578 */ 579 if (!chip->ppu_disabled) { 580 ret = mv88e6xxx_ppu_disable(chip); 581 if (ret < 0) { 582 mutex_unlock(&chip->ppu_mutex); 583 return ret; 584 } 585 chip->ppu_disabled = 1; 586 } else { 587 del_timer(&chip->ppu_timer); 588 ret = 0; 589 } 590 591 return ret; 592 } 593 594 static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip) 595 { 596 /* Schedule a timer to re-enable the PHY polling unit. */ 597 mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10)); 598 mutex_unlock(&chip->ppu_mutex); 599 } 600 601 static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip) 602 { 603 mutex_init(&chip->ppu_mutex); 604 INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work); 605 setup_timer(&chip->ppu_timer, mv88e6xxx_ppu_reenable_timer, 606 (unsigned long)chip); 607 } 608 609 static void mv88e6xxx_ppu_state_destroy(struct mv88e6xxx_chip *chip) 610 { 611 del_timer_sync(&chip->ppu_timer); 612 } 613 614 static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip, int addr, 615 int reg, u16 *val) 616 { 617 int err; 618 619 err = mv88e6xxx_ppu_access_get(chip); 620 if (!err) { 621 err = mv88e6xxx_read(chip, addr, reg, val); 622 mv88e6xxx_ppu_access_put(chip); 623 } 624 625 return err; 626 } 627 628 static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip, int addr, 629 int reg, u16 val) 630 { 631 int err; 632 633 err = mv88e6xxx_ppu_access_get(chip); 634 if (!err) { 635 err = mv88e6xxx_write(chip, addr, reg, val); 636 mv88e6xxx_ppu_access_put(chip); 637 } 638 639 return err; 640 } 641 642 static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip) 643 { 644 return chip->info->family == MV88E6XXX_FAMILY_6095; 645 } 646 647 static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip) 648 { 649 return chip->info->family == MV88E6XXX_FAMILY_6097; 650 } 651 652 static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip) 653 { 654 return chip->info->family == MV88E6XXX_FAMILY_6165; 655 } 656 657 static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip *chip) 658 { 659 return chip->info->family == MV88E6XXX_FAMILY_6185; 660 } 661 662 static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip) 663 { 664 return chip->info->family == MV88E6XXX_FAMILY_6320; 665 } 666 667 static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip) 668 { 669 return chip->info->family == MV88E6XXX_FAMILY_6351; 670 } 671 672 static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip) 673 { 674 return chip->info->family == MV88E6XXX_FAMILY_6352; 675 } 676 677 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 678 int link, int speed, int duplex, 679 phy_interface_t mode) 680 { 681 int err; 682 683 if (!chip->info->ops->port_set_link) 684 return 0; 685 686 /* Port's MAC control must not be changed unless the link is down */ 687 err = chip->info->ops->port_set_link(chip, port, 0); 688 if (err) 689 return err; 690 691 if (chip->info->ops->port_set_speed) { 692 err = chip->info->ops->port_set_speed(chip, port, speed); 693 if (err && err != -EOPNOTSUPP) 694 goto restore_link; 695 } 696 697 if (chip->info->ops->port_set_duplex) { 698 err = chip->info->ops->port_set_duplex(chip, port, duplex); 699 if (err && err != -EOPNOTSUPP) 700 goto restore_link; 701 } 702 703 if (chip->info->ops->port_set_rgmii_delay) { 704 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode); 705 if (err && err != -EOPNOTSUPP) 706 goto restore_link; 707 } 708 709 err = 0; 710 restore_link: 711 if (chip->info->ops->port_set_link(chip, port, link)) 712 netdev_err(chip->ds->ports[port].netdev, 713 "failed to restore MAC's link\n"); 714 715 return err; 716 } 717 718 /* We expect the switch to perform auto negotiation if there is a real 719 * phy. However, in the case of a fixed link phy, we force the port 720 * settings from the fixed link settings. 721 */ 722 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port, 723 struct phy_device *phydev) 724 { 725 struct mv88e6xxx_chip *chip = ds->priv; 726 int err; 727 728 if (!phy_is_pseudo_fixed_link(phydev)) 729 return; 730 731 mutex_lock(&chip->reg_lock); 732 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed, 733 phydev->duplex, phydev->interface); 734 mutex_unlock(&chip->reg_lock); 735 736 if (err && err != -EOPNOTSUPP) 737 netdev_err(ds->ports[port].netdev, "failed to configure MAC\n"); 738 } 739 740 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 741 { 742 if (!chip->info->ops->stats_snapshot) 743 return -EOPNOTSUPP; 744 745 return chip->info->ops->stats_snapshot(chip, port); 746 } 747 748 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 749 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 750 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 751 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 752 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 753 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 754 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 755 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 756 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 757 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 758 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 759 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 760 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 761 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 762 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 763 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 764 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 765 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 766 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 767 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 768 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 769 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 770 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 771 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 772 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 773 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 774 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 775 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 776 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 777 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 778 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 779 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 780 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 781 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 782 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 783 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 784 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 785 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 786 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 787 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 788 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 789 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 790 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 791 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 792 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 793 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 794 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 795 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 796 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 797 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 798 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 799 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 800 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 801 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 802 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 803 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 804 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 805 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 806 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 807 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 808 }; 809 810 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 811 struct mv88e6xxx_hw_stat *s, 812 int port, u16 bank1_select, 813 u16 histogram) 814 { 815 u32 low; 816 u32 high = 0; 817 u16 reg = 0; 818 int err; 819 u64 value; 820 821 switch (s->type) { 822 case STATS_TYPE_PORT: 823 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 824 if (err) 825 return UINT64_MAX; 826 827 low = reg; 828 if (s->sizeof_stat == 4) { 829 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 830 if (err) 831 return UINT64_MAX; 832 high = reg; 833 } 834 break; 835 case STATS_TYPE_BANK1: 836 reg = bank1_select; 837 /* fall through */ 838 case STATS_TYPE_BANK0: 839 reg |= s->reg | histogram; 840 mv88e6xxx_g1_stats_read(chip, reg, &low); 841 if (s->sizeof_stat == 8) 842 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 843 } 844 value = (((u64)high) << 16) | low; 845 return value; 846 } 847 848 static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 849 uint8_t *data, int types) 850 { 851 struct mv88e6xxx_hw_stat *stat; 852 int i, j; 853 854 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 855 stat = &mv88e6xxx_hw_stats[i]; 856 if (stat->type & types) { 857 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 858 ETH_GSTRING_LEN); 859 j++; 860 } 861 } 862 } 863 864 static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 865 uint8_t *data) 866 { 867 mv88e6xxx_stats_get_strings(chip, data, 868 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 869 } 870 871 static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 872 uint8_t *data) 873 { 874 mv88e6xxx_stats_get_strings(chip, data, 875 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 876 } 877 878 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 879 uint8_t *data) 880 { 881 struct mv88e6xxx_chip *chip = ds->priv; 882 883 if (chip->info->ops->stats_get_strings) 884 chip->info->ops->stats_get_strings(chip, data); 885 } 886 887 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 888 int types) 889 { 890 struct mv88e6xxx_hw_stat *stat; 891 int i, j; 892 893 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 894 stat = &mv88e6xxx_hw_stats[i]; 895 if (stat->type & types) 896 j++; 897 } 898 return j; 899 } 900 901 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 902 { 903 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 904 STATS_TYPE_PORT); 905 } 906 907 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 908 { 909 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 910 STATS_TYPE_BANK1); 911 } 912 913 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds) 914 { 915 struct mv88e6xxx_chip *chip = ds->priv; 916 917 if (chip->info->ops->stats_get_sset_count) 918 return chip->info->ops->stats_get_sset_count(chip); 919 920 return 0; 921 } 922 923 static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 924 uint64_t *data, int types, 925 u16 bank1_select, u16 histogram) 926 { 927 struct mv88e6xxx_hw_stat *stat; 928 int i, j; 929 930 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 931 stat = &mv88e6xxx_hw_stats[i]; 932 if (stat->type & types) { 933 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 934 bank1_select, 935 histogram); 936 j++; 937 } 938 } 939 } 940 941 static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 942 uint64_t *data) 943 { 944 return mv88e6xxx_stats_get_stats(chip, port, data, 945 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 946 0, GLOBAL_STATS_OP_HIST_RX_TX); 947 } 948 949 static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 950 uint64_t *data) 951 { 952 return mv88e6xxx_stats_get_stats(chip, port, data, 953 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 954 GLOBAL_STATS_OP_BANK_1_BIT_9, 955 GLOBAL_STATS_OP_HIST_RX_TX); 956 } 957 958 static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 959 uint64_t *data) 960 { 961 return mv88e6xxx_stats_get_stats(chip, port, data, 962 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 963 GLOBAL_STATS_OP_BANK_1_BIT_10, 0); 964 } 965 966 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 967 uint64_t *data) 968 { 969 if (chip->info->ops->stats_get_stats) 970 chip->info->ops->stats_get_stats(chip, port, data); 971 } 972 973 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 974 uint64_t *data) 975 { 976 struct mv88e6xxx_chip *chip = ds->priv; 977 int ret; 978 979 mutex_lock(&chip->reg_lock); 980 981 ret = mv88e6xxx_stats_snapshot(chip, port); 982 if (ret < 0) { 983 mutex_unlock(&chip->reg_lock); 984 return; 985 } 986 987 mv88e6xxx_get_stats(chip, port, data); 988 989 mutex_unlock(&chip->reg_lock); 990 } 991 992 static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip) 993 { 994 if (chip->info->ops->stats_set_histogram) 995 return chip->info->ops->stats_set_histogram(chip); 996 997 return 0; 998 } 999 1000 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1001 { 1002 return 32 * sizeof(u16); 1003 } 1004 1005 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1006 struct ethtool_regs *regs, void *_p) 1007 { 1008 struct mv88e6xxx_chip *chip = ds->priv; 1009 int err; 1010 u16 reg; 1011 u16 *p = _p; 1012 int i; 1013 1014 regs->version = 0; 1015 1016 memset(p, 0xff, 32 * sizeof(u16)); 1017 1018 mutex_lock(&chip->reg_lock); 1019 1020 for (i = 0; i < 32; i++) { 1021 1022 err = mv88e6xxx_port_read(chip, port, i, ®); 1023 if (!err) 1024 p[i] = reg; 1025 } 1026 1027 mutex_unlock(&chip->reg_lock); 1028 } 1029 1030 static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip) 1031 { 1032 return mv88e6xxx_g1_wait(chip, GLOBAL_ATU_OP, GLOBAL_ATU_OP_BUSY); 1033 } 1034 1035 static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, 1036 struct ethtool_eee *e) 1037 { 1038 struct mv88e6xxx_chip *chip = ds->priv; 1039 u16 reg; 1040 int err; 1041 1042 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE)) 1043 return -EOPNOTSUPP; 1044 1045 mutex_lock(&chip->reg_lock); 1046 1047 err = mv88e6xxx_phy_read(chip, port, 16, ®); 1048 if (err) 1049 goto out; 1050 1051 e->eee_enabled = !!(reg & 0x0200); 1052 e->tx_lpi_enabled = !!(reg & 0x0100); 1053 1054 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, ®); 1055 if (err) 1056 goto out; 1057 1058 e->eee_active = !!(reg & PORT_STATUS_EEE); 1059 out: 1060 mutex_unlock(&chip->reg_lock); 1061 1062 return err; 1063 } 1064 1065 static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port, 1066 struct phy_device *phydev, struct ethtool_eee *e) 1067 { 1068 struct mv88e6xxx_chip *chip = ds->priv; 1069 u16 reg; 1070 int err; 1071 1072 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE)) 1073 return -EOPNOTSUPP; 1074 1075 mutex_lock(&chip->reg_lock); 1076 1077 err = mv88e6xxx_phy_read(chip, port, 16, ®); 1078 if (err) 1079 goto out; 1080 1081 reg &= ~0x0300; 1082 if (e->eee_enabled) 1083 reg |= 0x0200; 1084 if (e->tx_lpi_enabled) 1085 reg |= 0x0100; 1086 1087 err = mv88e6xxx_phy_write(chip, port, 16, reg); 1088 out: 1089 mutex_unlock(&chip->reg_lock); 1090 1091 return err; 1092 } 1093 1094 static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd) 1095 { 1096 u16 val; 1097 int err; 1098 1099 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_ATU_FID)) { 1100 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_FID, fid); 1101 if (err) 1102 return err; 1103 } else if (mv88e6xxx_num_databases(chip) == 256) { 1104 /* ATU DBNum[7:4] are located in ATU Control 15:12 */ 1105 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val); 1106 if (err) 1107 return err; 1108 1109 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, 1110 (val & 0xfff) | ((fid << 8) & 0xf000)); 1111 if (err) 1112 return err; 1113 1114 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */ 1115 cmd |= fid & 0xf; 1116 } 1117 1118 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_OP, cmd); 1119 if (err) 1120 return err; 1121 1122 return _mv88e6xxx_atu_wait(chip); 1123 } 1124 1125 static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip, 1126 struct mv88e6xxx_atu_entry *entry) 1127 { 1128 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK; 1129 1130 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) { 1131 unsigned int mask, shift; 1132 1133 if (entry->trunk) { 1134 data |= GLOBAL_ATU_DATA_TRUNK; 1135 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK; 1136 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT; 1137 } else { 1138 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK; 1139 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT; 1140 } 1141 1142 data |= (entry->portv_trunkid << shift) & mask; 1143 } 1144 1145 return mv88e6xxx_g1_write(chip, GLOBAL_ATU_DATA, data); 1146 } 1147 1148 static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip, 1149 struct mv88e6xxx_atu_entry *entry, 1150 bool static_too) 1151 { 1152 int op; 1153 int err; 1154 1155 err = _mv88e6xxx_atu_wait(chip); 1156 if (err) 1157 return err; 1158 1159 err = _mv88e6xxx_atu_data_write(chip, entry); 1160 if (err) 1161 return err; 1162 1163 if (entry->fid) { 1164 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB : 1165 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB; 1166 } else { 1167 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL : 1168 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC; 1169 } 1170 1171 return _mv88e6xxx_atu_cmd(chip, entry->fid, op); 1172 } 1173 1174 static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip, 1175 u16 fid, bool static_too) 1176 { 1177 struct mv88e6xxx_atu_entry entry = { 1178 .fid = fid, 1179 .state = 0, /* EntryState bits must be 0 */ 1180 }; 1181 1182 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too); 1183 } 1184 1185 static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid, 1186 int from_port, int to_port, bool static_too) 1187 { 1188 struct mv88e6xxx_atu_entry entry = { 1189 .trunk = false, 1190 .fid = fid, 1191 }; 1192 1193 /* EntryState bits must be 0xF */ 1194 entry.state = GLOBAL_ATU_DATA_STATE_MASK; 1195 1196 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */ 1197 entry.portv_trunkid = (to_port & 0x0f) << 4; 1198 entry.portv_trunkid |= from_port & 0x0f; 1199 1200 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too); 1201 } 1202 1203 static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid, 1204 int port, bool static_too) 1205 { 1206 /* Destination port 0xF means remove the entries */ 1207 return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too); 1208 } 1209 1210 static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port) 1211 { 1212 struct net_device *bridge = chip->ports[port].bridge_dev; 1213 struct dsa_switch *ds = chip->ds; 1214 u16 output_ports = 0; 1215 int i; 1216 1217 /* allow CPU port or DSA link(s) to send frames to every port */ 1218 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) { 1219 output_ports = ~0; 1220 } else { 1221 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1222 /* allow sending frames to every group member */ 1223 if (bridge && chip->ports[i].bridge_dev == bridge) 1224 output_ports |= BIT(i); 1225 1226 /* allow sending frames to CPU port and DSA link(s) */ 1227 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)) 1228 output_ports |= BIT(i); 1229 } 1230 } 1231 1232 /* prevent frames from going back out of the port they came in on */ 1233 output_ports &= ~BIT(port); 1234 1235 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1236 } 1237 1238 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1239 u8 state) 1240 { 1241 struct mv88e6xxx_chip *chip = ds->priv; 1242 int stp_state; 1243 int err; 1244 1245 switch (state) { 1246 case BR_STATE_DISABLED: 1247 stp_state = PORT_CONTROL_STATE_DISABLED; 1248 break; 1249 case BR_STATE_BLOCKING: 1250 case BR_STATE_LISTENING: 1251 stp_state = PORT_CONTROL_STATE_BLOCKING; 1252 break; 1253 case BR_STATE_LEARNING: 1254 stp_state = PORT_CONTROL_STATE_LEARNING; 1255 break; 1256 case BR_STATE_FORWARDING: 1257 default: 1258 stp_state = PORT_CONTROL_STATE_FORWARDING; 1259 break; 1260 } 1261 1262 mutex_lock(&chip->reg_lock); 1263 err = mv88e6xxx_port_set_state(chip, port, stp_state); 1264 mutex_unlock(&chip->reg_lock); 1265 1266 if (err) 1267 netdev_err(ds->ports[port].netdev, "failed to update state\n"); 1268 } 1269 1270 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1271 { 1272 struct mv88e6xxx_chip *chip = ds->priv; 1273 int err; 1274 1275 mutex_lock(&chip->reg_lock); 1276 err = _mv88e6xxx_atu_remove(chip, 0, port, false); 1277 mutex_unlock(&chip->reg_lock); 1278 1279 if (err) 1280 netdev_err(ds->ports[port].netdev, "failed to flush ATU\n"); 1281 } 1282 1283 static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip) 1284 { 1285 return mv88e6xxx_g1_wait(chip, GLOBAL_VTU_OP, GLOBAL_VTU_OP_BUSY); 1286 } 1287 1288 static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op) 1289 { 1290 int err; 1291 1292 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_OP, op); 1293 if (err) 1294 return err; 1295 1296 return _mv88e6xxx_vtu_wait(chip); 1297 } 1298 1299 static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip) 1300 { 1301 int ret; 1302 1303 ret = _mv88e6xxx_vtu_wait(chip); 1304 if (ret < 0) 1305 return ret; 1306 1307 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL); 1308 } 1309 1310 static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip, 1311 struct mv88e6xxx_vtu_entry *entry, 1312 unsigned int nibble_offset) 1313 { 1314 u16 regs[3]; 1315 int i, err; 1316 1317 for (i = 0; i < 3; ++i) { 1318 u16 *reg = ®s[i]; 1319 1320 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_DATA_0_3 + i, reg); 1321 if (err) 1322 return err; 1323 } 1324 1325 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1326 unsigned int shift = (i % 4) * 4 + nibble_offset; 1327 u16 reg = regs[i / 4]; 1328 1329 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK; 1330 } 1331 1332 return 0; 1333 } 1334 1335 static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip, 1336 struct mv88e6xxx_vtu_entry *entry) 1337 { 1338 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0); 1339 } 1340 1341 static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip, 1342 struct mv88e6xxx_vtu_entry *entry) 1343 { 1344 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2); 1345 } 1346 1347 static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip, 1348 struct mv88e6xxx_vtu_entry *entry, 1349 unsigned int nibble_offset) 1350 { 1351 u16 regs[3] = { 0 }; 1352 int i, err; 1353 1354 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1355 unsigned int shift = (i % 4) * 4 + nibble_offset; 1356 u8 data = entry->data[i]; 1357 1358 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift; 1359 } 1360 1361 for (i = 0; i < 3; ++i) { 1362 u16 reg = regs[i]; 1363 1364 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_DATA_0_3 + i, reg); 1365 if (err) 1366 return err; 1367 } 1368 1369 return 0; 1370 } 1371 1372 static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip, 1373 struct mv88e6xxx_vtu_entry *entry) 1374 { 1375 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0); 1376 } 1377 1378 static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip, 1379 struct mv88e6xxx_vtu_entry *entry) 1380 { 1381 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2); 1382 } 1383 1384 static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid) 1385 { 1386 return mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, 1387 vid & GLOBAL_VTU_VID_MASK); 1388 } 1389 1390 static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip, 1391 struct mv88e6xxx_vtu_entry *entry) 1392 { 1393 struct mv88e6xxx_vtu_entry next = { 0 }; 1394 u16 val; 1395 int err; 1396 1397 err = _mv88e6xxx_vtu_wait(chip); 1398 if (err) 1399 return err; 1400 1401 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT); 1402 if (err) 1403 return err; 1404 1405 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val); 1406 if (err) 1407 return err; 1408 1409 next.vid = val & GLOBAL_VTU_VID_MASK; 1410 next.valid = !!(val & GLOBAL_VTU_VID_VALID); 1411 1412 if (next.valid) { 1413 err = mv88e6xxx_vtu_data_read(chip, &next); 1414 if (err) 1415 return err; 1416 1417 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) { 1418 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_FID, &val); 1419 if (err) 1420 return err; 1421 1422 next.fid = val & GLOBAL_VTU_FID_MASK; 1423 } else if (mv88e6xxx_num_databases(chip) == 256) { 1424 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and 1425 * VTU DBNum[3:0] are located in VTU Operation 3:0 1426 */ 1427 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_OP, &val); 1428 if (err) 1429 return err; 1430 1431 next.fid = (val & 0xf00) >> 4; 1432 next.fid |= val & 0xf; 1433 } 1434 1435 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) { 1436 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val); 1437 if (err) 1438 return err; 1439 1440 next.sid = val & GLOBAL_VTU_SID_MASK; 1441 } 1442 } 1443 1444 *entry = next; 1445 return 0; 1446 } 1447 1448 static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port, 1449 struct switchdev_obj_port_vlan *vlan, 1450 int (*cb)(struct switchdev_obj *obj)) 1451 { 1452 struct mv88e6xxx_chip *chip = ds->priv; 1453 struct mv88e6xxx_vtu_entry next; 1454 u16 pvid; 1455 int err; 1456 1457 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) 1458 return -EOPNOTSUPP; 1459 1460 mutex_lock(&chip->reg_lock); 1461 1462 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 1463 if (err) 1464 goto unlock; 1465 1466 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK); 1467 if (err) 1468 goto unlock; 1469 1470 do { 1471 err = _mv88e6xxx_vtu_getnext(chip, &next); 1472 if (err) 1473 break; 1474 1475 if (!next.valid) 1476 break; 1477 1478 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1479 continue; 1480 1481 /* reinit and dump this VLAN obj */ 1482 vlan->vid_begin = next.vid; 1483 vlan->vid_end = next.vid; 1484 vlan->flags = 0; 1485 1486 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED) 1487 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED; 1488 1489 if (next.vid == pvid) 1490 vlan->flags |= BRIDGE_VLAN_INFO_PVID; 1491 1492 err = cb(&vlan->obj); 1493 if (err) 1494 break; 1495 } while (next.vid < GLOBAL_VTU_VID_MASK); 1496 1497 unlock: 1498 mutex_unlock(&chip->reg_lock); 1499 1500 return err; 1501 } 1502 1503 static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1504 struct mv88e6xxx_vtu_entry *entry) 1505 { 1506 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE; 1507 u16 reg = 0; 1508 int err; 1509 1510 err = _mv88e6xxx_vtu_wait(chip); 1511 if (err) 1512 return err; 1513 1514 if (!entry->valid) 1515 goto loadpurge; 1516 1517 /* Write port member tags */ 1518 err = mv88e6xxx_vtu_data_write(chip, entry); 1519 if (err) 1520 return err; 1521 1522 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) { 1523 reg = entry->sid & GLOBAL_VTU_SID_MASK; 1524 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg); 1525 if (err) 1526 return err; 1527 } 1528 1529 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) { 1530 reg = entry->fid & GLOBAL_VTU_FID_MASK; 1531 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_FID, reg); 1532 if (err) 1533 return err; 1534 } else if (mv88e6xxx_num_databases(chip) == 256) { 1535 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and 1536 * VTU DBNum[3:0] are located in VTU Operation 3:0 1537 */ 1538 op |= (entry->fid & 0xf0) << 8; 1539 op |= entry->fid & 0xf; 1540 } 1541 1542 reg = GLOBAL_VTU_VID_VALID; 1543 loadpurge: 1544 reg |= entry->vid & GLOBAL_VTU_VID_MASK; 1545 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg); 1546 if (err) 1547 return err; 1548 1549 return _mv88e6xxx_vtu_cmd(chip, op); 1550 } 1551 1552 static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid, 1553 struct mv88e6xxx_vtu_entry *entry) 1554 { 1555 struct mv88e6xxx_vtu_entry next = { 0 }; 1556 u16 val; 1557 int err; 1558 1559 err = _mv88e6xxx_vtu_wait(chip); 1560 if (err) 1561 return err; 1562 1563 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, 1564 sid & GLOBAL_VTU_SID_MASK); 1565 if (err) 1566 return err; 1567 1568 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT); 1569 if (err) 1570 return err; 1571 1572 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val); 1573 if (err) 1574 return err; 1575 1576 next.sid = val & GLOBAL_VTU_SID_MASK; 1577 1578 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val); 1579 if (err) 1580 return err; 1581 1582 next.valid = !!(val & GLOBAL_VTU_VID_VALID); 1583 1584 if (next.valid) { 1585 err = mv88e6xxx_stu_data_read(chip, &next); 1586 if (err) 1587 return err; 1588 } 1589 1590 *entry = next; 1591 return 0; 1592 } 1593 1594 static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip, 1595 struct mv88e6xxx_vtu_entry *entry) 1596 { 1597 u16 reg = 0; 1598 int err; 1599 1600 err = _mv88e6xxx_vtu_wait(chip); 1601 if (err) 1602 return err; 1603 1604 if (!entry->valid) 1605 goto loadpurge; 1606 1607 /* Write port states */ 1608 err = mv88e6xxx_stu_data_write(chip, entry); 1609 if (err) 1610 return err; 1611 1612 reg = GLOBAL_VTU_VID_VALID; 1613 loadpurge: 1614 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg); 1615 if (err) 1616 return err; 1617 1618 reg = entry->sid & GLOBAL_VTU_SID_MASK; 1619 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg); 1620 if (err) 1621 return err; 1622 1623 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE); 1624 } 1625 1626 static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid) 1627 { 1628 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1629 struct mv88e6xxx_vtu_entry vlan; 1630 int i, err; 1631 1632 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1633 1634 /* Set every FID bit used by the (un)bridged ports */ 1635 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1636 err = mv88e6xxx_port_get_fid(chip, i, fid); 1637 if (err) 1638 return err; 1639 1640 set_bit(*fid, fid_bitmap); 1641 } 1642 1643 /* Set every FID bit used by the VLAN entries */ 1644 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK); 1645 if (err) 1646 return err; 1647 1648 do { 1649 err = _mv88e6xxx_vtu_getnext(chip, &vlan); 1650 if (err) 1651 return err; 1652 1653 if (!vlan.valid) 1654 break; 1655 1656 set_bit(vlan.fid, fid_bitmap); 1657 } while (vlan.vid < GLOBAL_VTU_VID_MASK); 1658 1659 /* The reset value 0x000 is used to indicate that multiple address 1660 * databases are not needed. Return the next positive available. 1661 */ 1662 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1663 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1664 return -ENOSPC; 1665 1666 /* Clear the database */ 1667 return _mv88e6xxx_atu_flush(chip, *fid, true); 1668 } 1669 1670 static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid, 1671 struct mv88e6xxx_vtu_entry *entry) 1672 { 1673 struct dsa_switch *ds = chip->ds; 1674 struct mv88e6xxx_vtu_entry vlan = { 1675 .valid = true, 1676 .vid = vid, 1677 }; 1678 int i, err; 1679 1680 err = _mv88e6xxx_fid_new(chip, &vlan.fid); 1681 if (err) 1682 return err; 1683 1684 /* exclude all ports except the CPU and DSA ports */ 1685 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1686 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i) 1687 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED 1688 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1689 1690 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) || 1691 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) { 1692 struct mv88e6xxx_vtu_entry vstp; 1693 1694 /* Adding a VTU entry requires a valid STU entry. As VSTP is not 1695 * implemented, only one STU entry is needed to cover all VTU 1696 * entries. Thus, validate the SID 0. 1697 */ 1698 vlan.sid = 0; 1699 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp); 1700 if (err) 1701 return err; 1702 1703 if (vstp.sid != vlan.sid || !vstp.valid) { 1704 memset(&vstp, 0, sizeof(vstp)); 1705 vstp.valid = true; 1706 vstp.sid = vlan.sid; 1707 1708 err = _mv88e6xxx_stu_loadpurge(chip, &vstp); 1709 if (err) 1710 return err; 1711 } 1712 } 1713 1714 *entry = vlan; 1715 return 0; 1716 } 1717 1718 static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1719 struct mv88e6xxx_vtu_entry *entry, bool creat) 1720 { 1721 int err; 1722 1723 if (!vid) 1724 return -EINVAL; 1725 1726 err = _mv88e6xxx_vtu_vid_write(chip, vid - 1); 1727 if (err) 1728 return err; 1729 1730 err = _mv88e6xxx_vtu_getnext(chip, entry); 1731 if (err) 1732 return err; 1733 1734 if (entry->vid != vid || !entry->valid) { 1735 if (!creat) 1736 return -EOPNOTSUPP; 1737 /* -ENOENT would've been more appropriate, but switchdev expects 1738 * -EOPNOTSUPP to inform bridge about an eventual software VLAN. 1739 */ 1740 1741 err = _mv88e6xxx_vtu_new(chip, vid, entry); 1742 } 1743 1744 return err; 1745 } 1746 1747 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1748 u16 vid_begin, u16 vid_end) 1749 { 1750 struct mv88e6xxx_chip *chip = ds->priv; 1751 struct mv88e6xxx_vtu_entry vlan; 1752 int i, err; 1753 1754 if (!vid_begin) 1755 return -EOPNOTSUPP; 1756 1757 mutex_lock(&chip->reg_lock); 1758 1759 err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1); 1760 if (err) 1761 goto unlock; 1762 1763 do { 1764 err = _mv88e6xxx_vtu_getnext(chip, &vlan); 1765 if (err) 1766 goto unlock; 1767 1768 if (!vlan.valid) 1769 break; 1770 1771 if (vlan.vid > vid_end) 1772 break; 1773 1774 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1775 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) 1776 continue; 1777 1778 if (vlan.data[i] == 1779 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1780 continue; 1781 1782 if (chip->ports[i].bridge_dev == 1783 chip->ports[port].bridge_dev) 1784 break; /* same bridge, check next VLAN */ 1785 1786 netdev_warn(ds->ports[port].netdev, 1787 "hardware VLAN %d already used by %s\n", 1788 vlan.vid, 1789 netdev_name(chip->ports[i].bridge_dev)); 1790 err = -EOPNOTSUPP; 1791 goto unlock; 1792 } 1793 } while (vlan.vid < vid_end); 1794 1795 unlock: 1796 mutex_unlock(&chip->reg_lock); 1797 1798 return err; 1799 } 1800 1801 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1802 bool vlan_filtering) 1803 { 1804 struct mv88e6xxx_chip *chip = ds->priv; 1805 u16 mode = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE : 1806 PORT_CONTROL_2_8021Q_DISABLED; 1807 int err; 1808 1809 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) 1810 return -EOPNOTSUPP; 1811 1812 mutex_lock(&chip->reg_lock); 1813 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 1814 mutex_unlock(&chip->reg_lock); 1815 1816 return err; 1817 } 1818 1819 static int 1820 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1821 const struct switchdev_obj_port_vlan *vlan, 1822 struct switchdev_trans *trans) 1823 { 1824 struct mv88e6xxx_chip *chip = ds->priv; 1825 int err; 1826 1827 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) 1828 return -EOPNOTSUPP; 1829 1830 /* If the requested port doesn't belong to the same bridge as the VLAN 1831 * members, do not support it (yet) and fallback to software VLAN. 1832 */ 1833 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin, 1834 vlan->vid_end); 1835 if (err) 1836 return err; 1837 1838 /* We don't need any dynamic resource from the kernel (yet), 1839 * so skip the prepare phase. 1840 */ 1841 return 0; 1842 } 1843 1844 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port, 1845 u16 vid, bool untagged) 1846 { 1847 struct mv88e6xxx_vtu_entry vlan; 1848 int err; 1849 1850 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true); 1851 if (err) 1852 return err; 1853 1854 vlan.data[port] = untagged ? 1855 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED : 1856 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED; 1857 1858 return _mv88e6xxx_vtu_loadpurge(chip, &vlan); 1859 } 1860 1861 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 1862 const struct switchdev_obj_port_vlan *vlan, 1863 struct switchdev_trans *trans) 1864 { 1865 struct mv88e6xxx_chip *chip = ds->priv; 1866 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1867 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1868 u16 vid; 1869 1870 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) 1871 return; 1872 1873 mutex_lock(&chip->reg_lock); 1874 1875 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) 1876 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged)) 1877 netdev_err(ds->ports[port].netdev, 1878 "failed to add VLAN %d%c\n", 1879 vid, untagged ? 'u' : 't'); 1880 1881 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end)) 1882 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n", 1883 vlan->vid_end); 1884 1885 mutex_unlock(&chip->reg_lock); 1886 } 1887 1888 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip, 1889 int port, u16 vid) 1890 { 1891 struct dsa_switch *ds = chip->ds; 1892 struct mv88e6xxx_vtu_entry vlan; 1893 int i, err; 1894 1895 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false); 1896 if (err) 1897 return err; 1898 1899 /* Tell switchdev if this VLAN is handled in software */ 1900 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1901 return -EOPNOTSUPP; 1902 1903 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1904 1905 /* keep the VLAN unless all ports are excluded */ 1906 vlan.valid = false; 1907 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1908 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)) 1909 continue; 1910 1911 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 1912 vlan.valid = true; 1913 break; 1914 } 1915 } 1916 1917 err = _mv88e6xxx_vtu_loadpurge(chip, &vlan); 1918 if (err) 1919 return err; 1920 1921 return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false); 1922 } 1923 1924 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 1925 const struct switchdev_obj_port_vlan *vlan) 1926 { 1927 struct mv88e6xxx_chip *chip = ds->priv; 1928 u16 pvid, vid; 1929 int err = 0; 1930 1931 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) 1932 return -EOPNOTSUPP; 1933 1934 mutex_lock(&chip->reg_lock); 1935 1936 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 1937 if (err) 1938 goto unlock; 1939 1940 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1941 err = _mv88e6xxx_port_vlan_del(chip, port, vid); 1942 if (err) 1943 goto unlock; 1944 1945 if (vid == pvid) { 1946 err = mv88e6xxx_port_set_pvid(chip, port, 0); 1947 if (err) 1948 goto unlock; 1949 } 1950 } 1951 1952 unlock: 1953 mutex_unlock(&chip->reg_lock); 1954 1955 return err; 1956 } 1957 1958 static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip, 1959 const unsigned char *addr) 1960 { 1961 int i, err; 1962 1963 for (i = 0; i < 3; i++) { 1964 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_MAC_01 + i, 1965 (addr[i * 2] << 8) | addr[i * 2 + 1]); 1966 if (err) 1967 return err; 1968 } 1969 1970 return 0; 1971 } 1972 1973 static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip, 1974 unsigned char *addr) 1975 { 1976 u16 val; 1977 int i, err; 1978 1979 for (i = 0; i < 3; i++) { 1980 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_MAC_01 + i, &val); 1981 if (err) 1982 return err; 1983 1984 addr[i * 2] = val >> 8; 1985 addr[i * 2 + 1] = val & 0xff; 1986 } 1987 1988 return 0; 1989 } 1990 1991 static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip, 1992 struct mv88e6xxx_atu_entry *entry) 1993 { 1994 int ret; 1995 1996 ret = _mv88e6xxx_atu_wait(chip); 1997 if (ret < 0) 1998 return ret; 1999 2000 ret = _mv88e6xxx_atu_mac_write(chip, entry->mac); 2001 if (ret < 0) 2002 return ret; 2003 2004 ret = _mv88e6xxx_atu_data_write(chip, entry); 2005 if (ret < 0) 2006 return ret; 2007 2008 return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB); 2009 } 2010 2011 static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid, 2012 struct mv88e6xxx_atu_entry *entry); 2013 2014 static int mv88e6xxx_atu_get(struct mv88e6xxx_chip *chip, int fid, 2015 const u8 *addr, struct mv88e6xxx_atu_entry *entry) 2016 { 2017 struct mv88e6xxx_atu_entry next; 2018 int err; 2019 2020 eth_broadcast_addr(next.mac); 2021 2022 err = _mv88e6xxx_atu_mac_write(chip, next.mac); 2023 if (err) 2024 return err; 2025 2026 do { 2027 err = _mv88e6xxx_atu_getnext(chip, fid, &next); 2028 if (err) 2029 return err; 2030 2031 if (next.state == GLOBAL_ATU_DATA_STATE_UNUSED) 2032 break; 2033 2034 if (ether_addr_equal(next.mac, addr)) { 2035 *entry = next; 2036 return 0; 2037 } 2038 } while (!is_broadcast_ether_addr(next.mac)); 2039 2040 memset(entry, 0, sizeof(*entry)); 2041 entry->fid = fid; 2042 ether_addr_copy(entry->mac, addr); 2043 2044 return 0; 2045 } 2046 2047 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 2048 const unsigned char *addr, u16 vid, 2049 u8 state) 2050 { 2051 struct mv88e6xxx_vtu_entry vlan; 2052 struct mv88e6xxx_atu_entry entry; 2053 int err; 2054 2055 /* Null VLAN ID corresponds to the port private database */ 2056 if (vid == 0) 2057 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid); 2058 else 2059 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false); 2060 if (err) 2061 return err; 2062 2063 err = mv88e6xxx_atu_get(chip, vlan.fid, addr, &entry); 2064 if (err) 2065 return err; 2066 2067 /* Purge the ATU entry only if no port is using it anymore */ 2068 if (state == GLOBAL_ATU_DATA_STATE_UNUSED) { 2069 entry.portv_trunkid &= ~BIT(port); 2070 if (!entry.portv_trunkid) 2071 entry.state = GLOBAL_ATU_DATA_STATE_UNUSED; 2072 } else { 2073 entry.portv_trunkid |= BIT(port); 2074 entry.state = state; 2075 } 2076 2077 return _mv88e6xxx_atu_load(chip, &entry); 2078 } 2079 2080 static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port, 2081 const struct switchdev_obj_port_fdb *fdb, 2082 struct switchdev_trans *trans) 2083 { 2084 /* We don't need any dynamic resource from the kernel (yet), 2085 * so skip the prepare phase. 2086 */ 2087 return 0; 2088 } 2089 2090 static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2091 const struct switchdev_obj_port_fdb *fdb, 2092 struct switchdev_trans *trans) 2093 { 2094 struct mv88e6xxx_chip *chip = ds->priv; 2095 2096 mutex_lock(&chip->reg_lock); 2097 if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid, 2098 GLOBAL_ATU_DATA_STATE_UC_STATIC)) 2099 netdev_err(ds->ports[port].netdev, "failed to load unicast MAC address\n"); 2100 mutex_unlock(&chip->reg_lock); 2101 } 2102 2103 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2104 const struct switchdev_obj_port_fdb *fdb) 2105 { 2106 struct mv88e6xxx_chip *chip = ds->priv; 2107 int err; 2108 2109 mutex_lock(&chip->reg_lock); 2110 err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid, 2111 GLOBAL_ATU_DATA_STATE_UNUSED); 2112 mutex_unlock(&chip->reg_lock); 2113 2114 return err; 2115 } 2116 2117 static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid, 2118 struct mv88e6xxx_atu_entry *entry) 2119 { 2120 struct mv88e6xxx_atu_entry next = { 0 }; 2121 u16 val; 2122 int err; 2123 2124 next.fid = fid; 2125 2126 err = _mv88e6xxx_atu_wait(chip); 2127 if (err) 2128 return err; 2129 2130 err = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB); 2131 if (err) 2132 return err; 2133 2134 err = _mv88e6xxx_atu_mac_read(chip, next.mac); 2135 if (err) 2136 return err; 2137 2138 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_DATA, &val); 2139 if (err) 2140 return err; 2141 2142 next.state = val & GLOBAL_ATU_DATA_STATE_MASK; 2143 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) { 2144 unsigned int mask, shift; 2145 2146 if (val & GLOBAL_ATU_DATA_TRUNK) { 2147 next.trunk = true; 2148 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK; 2149 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT; 2150 } else { 2151 next.trunk = false; 2152 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK; 2153 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT; 2154 } 2155 2156 next.portv_trunkid = (val & mask) >> shift; 2157 } 2158 2159 *entry = next; 2160 return 0; 2161 } 2162 2163 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2164 u16 fid, u16 vid, int port, 2165 struct switchdev_obj *obj, 2166 int (*cb)(struct switchdev_obj *obj)) 2167 { 2168 struct mv88e6xxx_atu_entry addr = { 2169 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, 2170 }; 2171 int err; 2172 2173 err = _mv88e6xxx_atu_mac_write(chip, addr.mac); 2174 if (err) 2175 return err; 2176 2177 do { 2178 err = _mv88e6xxx_atu_getnext(chip, fid, &addr); 2179 if (err) 2180 return err; 2181 2182 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED) 2183 break; 2184 2185 if (addr.trunk || (addr.portv_trunkid & BIT(port)) == 0) 2186 continue; 2187 2188 if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) { 2189 struct switchdev_obj_port_fdb *fdb; 2190 2191 if (!is_unicast_ether_addr(addr.mac)) 2192 continue; 2193 2194 fdb = SWITCHDEV_OBJ_PORT_FDB(obj); 2195 fdb->vid = vid; 2196 ether_addr_copy(fdb->addr, addr.mac); 2197 if (addr.state == GLOBAL_ATU_DATA_STATE_UC_STATIC) 2198 fdb->ndm_state = NUD_NOARP; 2199 else 2200 fdb->ndm_state = NUD_REACHABLE; 2201 } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) { 2202 struct switchdev_obj_port_mdb *mdb; 2203 2204 if (!is_multicast_ether_addr(addr.mac)) 2205 continue; 2206 2207 mdb = SWITCHDEV_OBJ_PORT_MDB(obj); 2208 mdb->vid = vid; 2209 ether_addr_copy(mdb->addr, addr.mac); 2210 } else { 2211 return -EOPNOTSUPP; 2212 } 2213 2214 err = cb(obj); 2215 if (err) 2216 return err; 2217 } while (!is_broadcast_ether_addr(addr.mac)); 2218 2219 return err; 2220 } 2221 2222 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2223 struct switchdev_obj *obj, 2224 int (*cb)(struct switchdev_obj *obj)) 2225 { 2226 struct mv88e6xxx_vtu_entry vlan = { 2227 .vid = GLOBAL_VTU_VID_MASK, /* all ones */ 2228 }; 2229 u16 fid; 2230 int err; 2231 2232 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2233 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2234 if (err) 2235 return err; 2236 2237 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb); 2238 if (err) 2239 return err; 2240 2241 /* Dump VLANs' Filtering Information Databases */ 2242 err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid); 2243 if (err) 2244 return err; 2245 2246 do { 2247 err = _mv88e6xxx_vtu_getnext(chip, &vlan); 2248 if (err) 2249 return err; 2250 2251 if (!vlan.valid) 2252 break; 2253 2254 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port, 2255 obj, cb); 2256 if (err) 2257 return err; 2258 } while (vlan.vid < GLOBAL_VTU_VID_MASK); 2259 2260 return err; 2261 } 2262 2263 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2264 struct switchdev_obj_port_fdb *fdb, 2265 int (*cb)(struct switchdev_obj *obj)) 2266 { 2267 struct mv88e6xxx_chip *chip = ds->priv; 2268 int err; 2269 2270 mutex_lock(&chip->reg_lock); 2271 err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb); 2272 mutex_unlock(&chip->reg_lock); 2273 2274 return err; 2275 } 2276 2277 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 2278 struct net_device *bridge) 2279 { 2280 struct mv88e6xxx_chip *chip = ds->priv; 2281 int i, err = 0; 2282 2283 mutex_lock(&chip->reg_lock); 2284 2285 /* Assign the bridge and remap each port's VLANTable */ 2286 chip->ports[port].bridge_dev = bridge; 2287 2288 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2289 if (chip->ports[i].bridge_dev == bridge) { 2290 err = _mv88e6xxx_port_based_vlan_map(chip, i); 2291 if (err) 2292 break; 2293 } 2294 } 2295 2296 mutex_unlock(&chip->reg_lock); 2297 2298 return err; 2299 } 2300 2301 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port) 2302 { 2303 struct mv88e6xxx_chip *chip = ds->priv; 2304 struct net_device *bridge = chip->ports[port].bridge_dev; 2305 int i; 2306 2307 mutex_lock(&chip->reg_lock); 2308 2309 /* Unassign the bridge and remap each port's VLANTable */ 2310 chip->ports[port].bridge_dev = NULL; 2311 2312 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 2313 if (i == port || chip->ports[i].bridge_dev == bridge) 2314 if (_mv88e6xxx_port_based_vlan_map(chip, i)) 2315 netdev_warn(ds->ports[i].netdev, 2316 "failed to remap\n"); 2317 2318 mutex_unlock(&chip->reg_lock); 2319 } 2320 2321 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 2322 { 2323 if (chip->info->ops->reset) 2324 return chip->info->ops->reset(chip); 2325 2326 return 0; 2327 } 2328 2329 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 2330 { 2331 struct gpio_desc *gpiod = chip->reset; 2332 2333 /* If there is a GPIO connected to the reset pin, toggle it */ 2334 if (gpiod) { 2335 gpiod_set_value_cansleep(gpiod, 1); 2336 usleep_range(10000, 20000); 2337 gpiod_set_value_cansleep(gpiod, 0); 2338 usleep_range(10000, 20000); 2339 } 2340 } 2341 2342 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 2343 { 2344 int i, err; 2345 2346 /* Set all ports to the Disabled state */ 2347 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2348 err = mv88e6xxx_port_set_state(chip, i, 2349 PORT_CONTROL_STATE_DISABLED); 2350 if (err) 2351 return err; 2352 } 2353 2354 /* Wait for transmit queues to drain, 2355 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 2356 */ 2357 usleep_range(2000, 4000); 2358 2359 return 0; 2360 } 2361 2362 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 2363 { 2364 int err; 2365 2366 err = mv88e6xxx_disable_ports(chip); 2367 if (err) 2368 return err; 2369 2370 mv88e6xxx_hardware_reset(chip); 2371 2372 return mv88e6xxx_software_reset(chip); 2373 } 2374 2375 static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip) 2376 { 2377 u16 val; 2378 int err; 2379 2380 /* Clear Power Down bit */ 2381 err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val); 2382 if (err) 2383 return err; 2384 2385 if (val & BMCR_PDOWN) { 2386 val &= ~BMCR_PDOWN; 2387 err = mv88e6xxx_serdes_write(chip, MII_BMCR, val); 2388 } 2389 2390 return err; 2391 } 2392 2393 static int mv88e6xxx_setup_port_dsa(struct mv88e6xxx_chip *chip, int port, 2394 int upstream_port) 2395 { 2396 int err; 2397 2398 err = chip->info->ops->port_set_frame_mode( 2399 chip, port, MV88E6XXX_FRAME_MODE_DSA); 2400 if (err) 2401 return err; 2402 2403 return chip->info->ops->port_set_egress_unknowns( 2404 chip, port, port == upstream_port); 2405 } 2406 2407 static int mv88e6xxx_setup_port_cpu(struct mv88e6xxx_chip *chip, int port) 2408 { 2409 int err; 2410 2411 switch (chip->info->tag_protocol) { 2412 case DSA_TAG_PROTO_EDSA: 2413 err = chip->info->ops->port_set_frame_mode( 2414 chip, port, MV88E6XXX_FRAME_MODE_ETHERTYPE); 2415 if (err) 2416 return err; 2417 2418 err = mv88e6xxx_port_set_egress_mode( 2419 chip, port, PORT_CONTROL_EGRESS_ADD_TAG); 2420 if (err) 2421 return err; 2422 2423 if (chip->info->ops->port_set_ether_type) 2424 err = chip->info->ops->port_set_ether_type( 2425 chip, port, ETH_P_EDSA); 2426 break; 2427 2428 case DSA_TAG_PROTO_DSA: 2429 err = chip->info->ops->port_set_frame_mode( 2430 chip, port, MV88E6XXX_FRAME_MODE_DSA); 2431 if (err) 2432 return err; 2433 2434 err = mv88e6xxx_port_set_egress_mode( 2435 chip, port, PORT_CONTROL_EGRESS_UNMODIFIED); 2436 break; 2437 default: 2438 err = -EINVAL; 2439 } 2440 2441 if (err) 2442 return err; 2443 2444 return chip->info->ops->port_set_egress_unknowns(chip, port, true); 2445 } 2446 2447 static int mv88e6xxx_setup_port_normal(struct mv88e6xxx_chip *chip, int port) 2448 { 2449 int err; 2450 2451 err = chip->info->ops->port_set_frame_mode( 2452 chip, port, MV88E6XXX_FRAME_MODE_NORMAL); 2453 if (err) 2454 return err; 2455 2456 return chip->info->ops->port_set_egress_unknowns(chip, port, false); 2457 } 2458 2459 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 2460 { 2461 struct dsa_switch *ds = chip->ds; 2462 int err; 2463 u16 reg; 2464 2465 /* MAC Forcing register: don't force link, speed, duplex or flow control 2466 * state to any particular values on physical ports, but force the CPU 2467 * port and all DSA ports to their maximum bandwidth and full duplex. 2468 */ 2469 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 2470 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 2471 SPEED_MAX, DUPLEX_FULL, 2472 PHY_INTERFACE_MODE_NA); 2473 else 2474 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 2475 SPEED_UNFORCED, DUPLEX_UNFORCED, 2476 PHY_INTERFACE_MODE_NA); 2477 if (err) 2478 return err; 2479 2480 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 2481 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 2482 * tunneling, determine priority by looking at 802.1p and IP 2483 * priority fields (IP prio has precedence), and set STP state 2484 * to Forwarding. 2485 * 2486 * If this is the CPU link, use DSA or EDSA tagging depending 2487 * on which tagging mode was configured. 2488 * 2489 * If this is a link to another switch, use DSA tagging mode. 2490 * 2491 * If this is the upstream port for this switch, enable 2492 * forwarding of unknown unicasts and multicasts. 2493 */ 2494 reg = PORT_CONTROL_IGMP_MLD_SNOOP | 2495 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP | 2496 PORT_CONTROL_STATE_FORWARDING; 2497 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg); 2498 if (err) 2499 return err; 2500 2501 if (dsa_is_cpu_port(ds, port)) { 2502 err = mv88e6xxx_setup_port_cpu(chip, port); 2503 } else if (dsa_is_dsa_port(ds, port)) { 2504 err = mv88e6xxx_setup_port_dsa(chip, port, 2505 dsa_upstream_port(ds)); 2506 } else { 2507 err = mv88e6xxx_setup_port_normal(chip, port); 2508 } 2509 if (err) 2510 return err; 2511 2512 /* If this port is connected to a SerDes, make sure the SerDes is not 2513 * powered down. 2514 */ 2515 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) { 2516 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, ®); 2517 if (err) 2518 return err; 2519 reg &= PORT_STATUS_CMODE_MASK; 2520 if ((reg == PORT_STATUS_CMODE_100BASE_X) || 2521 (reg == PORT_STATUS_CMODE_1000BASE_X) || 2522 (reg == PORT_STATUS_CMODE_SGMII)) { 2523 err = mv88e6xxx_serdes_power_on(chip); 2524 if (err < 0) 2525 return err; 2526 } 2527 } 2528 2529 /* Port Control 2: don't force a good FCS, set the maximum frame size to 2530 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or 2531 * untagged frames on this port, do a destination address lookup on all 2532 * received packets as usual, disable ARP mirroring and don't send a 2533 * copy of all transmitted/received frames on this port to the CPU. 2534 */ 2535 reg = 0; 2536 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) || 2537 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) || 2538 mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) || 2539 mv88e6xxx_6185_family(chip)) 2540 reg = PORT_CONTROL_2_MAP_DA; 2541 2542 if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) { 2543 /* Set the upstream port this port should use */ 2544 reg |= dsa_upstream_port(ds); 2545 /* enable forwarding of unknown multicast addresses to 2546 * the upstream port 2547 */ 2548 if (port == dsa_upstream_port(ds)) 2549 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN; 2550 } 2551 2552 reg |= PORT_CONTROL_2_8021Q_DISABLED; 2553 2554 if (reg) { 2555 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg); 2556 if (err) 2557 return err; 2558 } 2559 2560 if (chip->info->ops->port_jumbo_config) { 2561 err = chip->info->ops->port_jumbo_config(chip, port); 2562 if (err) 2563 return err; 2564 } 2565 2566 /* Port Association Vector: when learning source addresses 2567 * of packets, add the address to the address database using 2568 * a port bitmap that has only the bit for this port set and 2569 * the other bits clear. 2570 */ 2571 reg = 1 << port; 2572 /* Disable learning for CPU port */ 2573 if (dsa_is_cpu_port(ds, port)) 2574 reg = 0; 2575 2576 err = mv88e6xxx_port_write(chip, port, PORT_ASSOC_VECTOR, reg); 2577 if (err) 2578 return err; 2579 2580 /* Egress rate control 2: disable egress rate control. */ 2581 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL_2, 0x0000); 2582 if (err) 2583 return err; 2584 2585 if (chip->info->ops->port_pause_config) { 2586 err = chip->info->ops->port_pause_config(chip, port); 2587 if (err) 2588 return err; 2589 } 2590 2591 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) || 2592 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) || 2593 mv88e6xxx_6320_family(chip)) { 2594 /* Port ATU control: disable limiting the number of 2595 * address database entries that this port is allowed 2596 * to use. 2597 */ 2598 err = mv88e6xxx_port_write(chip, port, PORT_ATU_CONTROL, 2599 0x0000); 2600 /* Priority Override: disable DA, SA and VTU priority 2601 * override. 2602 */ 2603 err = mv88e6xxx_port_write(chip, port, PORT_PRI_OVERRIDE, 2604 0x0000); 2605 if (err) 2606 return err; 2607 } 2608 2609 if (chip->info->ops->port_tag_remap) { 2610 err = chip->info->ops->port_tag_remap(chip, port); 2611 if (err) 2612 return err; 2613 } 2614 2615 if (chip->info->ops->port_egress_rate_limiting) { 2616 err = chip->info->ops->port_egress_rate_limiting(chip, port); 2617 if (err) 2618 return err; 2619 } 2620 2621 /* Port Control 1: disable trunking, disable sending 2622 * learning messages to this port. 2623 */ 2624 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, 0x0000); 2625 if (err) 2626 return err; 2627 2628 /* Port based VLAN map: give each port the same default address 2629 * database, and allow bidirectional communication between the 2630 * CPU and DSA port(s), and the other ports. 2631 */ 2632 err = mv88e6xxx_port_set_fid(chip, port, 0); 2633 if (err) 2634 return err; 2635 2636 err = _mv88e6xxx_port_based_vlan_map(chip, port); 2637 if (err) 2638 return err; 2639 2640 /* Default VLAN ID and priority: don't set a default VLAN 2641 * ID, and set the default packet priority to zero. 2642 */ 2643 return mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, 0x0000); 2644 } 2645 2646 static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr) 2647 { 2648 int err; 2649 2650 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]); 2651 if (err) 2652 return err; 2653 2654 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]); 2655 if (err) 2656 return err; 2657 2658 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]); 2659 if (err) 2660 return err; 2661 2662 return 0; 2663 } 2664 2665 static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip, 2666 unsigned int msecs) 2667 { 2668 const unsigned int coeff = chip->info->age_time_coeff; 2669 const unsigned int min = 0x01 * coeff; 2670 const unsigned int max = 0xff * coeff; 2671 u8 age_time; 2672 u16 val; 2673 int err; 2674 2675 if (msecs < min || msecs > max) 2676 return -ERANGE; 2677 2678 /* Round to nearest multiple of coeff */ 2679 age_time = (msecs + coeff / 2) / coeff; 2680 2681 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val); 2682 if (err) 2683 return err; 2684 2685 /* AgeTime is 11:4 bits */ 2686 val &= ~0xff0; 2687 val |= age_time << 4; 2688 2689 return mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, val); 2690 } 2691 2692 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 2693 unsigned int ageing_time) 2694 { 2695 struct mv88e6xxx_chip *chip = ds->priv; 2696 int err; 2697 2698 mutex_lock(&chip->reg_lock); 2699 err = mv88e6xxx_g1_set_age_time(chip, ageing_time); 2700 mutex_unlock(&chip->reg_lock); 2701 2702 return err; 2703 } 2704 2705 static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip) 2706 { 2707 struct dsa_switch *ds = chip->ds; 2708 u32 upstream_port = dsa_upstream_port(ds); 2709 int err; 2710 2711 /* Enable the PHY Polling Unit if present, don't discard any packets, 2712 * and mask all interrupt sources. 2713 */ 2714 err = mv88e6xxx_ppu_enable(chip); 2715 if (err) 2716 return err; 2717 2718 if (chip->info->ops->g1_set_cpu_port) { 2719 err = chip->info->ops->g1_set_cpu_port(chip, upstream_port); 2720 if (err) 2721 return err; 2722 } 2723 2724 if (chip->info->ops->g1_set_egress_port) { 2725 err = chip->info->ops->g1_set_egress_port(chip, upstream_port); 2726 if (err) 2727 return err; 2728 } 2729 2730 /* Disable remote management, and set the switch's DSA device number. */ 2731 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL_2, 2732 GLOBAL_CONTROL_2_MULTIPLE_CASCADE | 2733 (ds->index & 0x1f)); 2734 if (err) 2735 return err; 2736 2737 /* Clear all the VTU and STU entries */ 2738 err = _mv88e6xxx_vtu_stu_flush(chip); 2739 if (err < 0) 2740 return err; 2741 2742 /* Set the default address aging time to 5 minutes, and 2743 * enable address learn messages to be sent to all message 2744 * ports. 2745 */ 2746 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, 2747 GLOBAL_ATU_CONTROL_LEARN2ALL); 2748 if (err) 2749 return err; 2750 2751 err = mv88e6xxx_g1_set_age_time(chip, 300000); 2752 if (err) 2753 return err; 2754 2755 /* Clear all ATU entries */ 2756 err = _mv88e6xxx_atu_flush(chip, 0, true); 2757 if (err) 2758 return err; 2759 2760 /* Configure the IP ToS mapping registers. */ 2761 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_0, 0x0000); 2762 if (err) 2763 return err; 2764 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_1, 0x0000); 2765 if (err) 2766 return err; 2767 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_2, 0x5555); 2768 if (err) 2769 return err; 2770 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_3, 0x5555); 2771 if (err) 2772 return err; 2773 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_4, 0xaaaa); 2774 if (err) 2775 return err; 2776 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_5, 0xaaaa); 2777 if (err) 2778 return err; 2779 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_6, 0xffff); 2780 if (err) 2781 return err; 2782 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_7, 0xffff); 2783 if (err) 2784 return err; 2785 2786 /* Configure the IEEE 802.1p priority mapping register. */ 2787 err = mv88e6xxx_g1_write(chip, GLOBAL_IEEE_PRI, 0xfa41); 2788 if (err) 2789 return err; 2790 2791 /* Initialize the statistics unit */ 2792 err = mv88e6xxx_stats_set_histogram(chip); 2793 if (err) 2794 return err; 2795 2796 /* Clear the statistics counters for all ports */ 2797 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP, 2798 GLOBAL_STATS_OP_FLUSH_ALL); 2799 if (err) 2800 return err; 2801 2802 /* Wait for the flush to complete. */ 2803 err = mv88e6xxx_g1_stats_wait(chip); 2804 if (err) 2805 return err; 2806 2807 return 0; 2808 } 2809 2810 static int mv88e6xxx_setup(struct dsa_switch *ds) 2811 { 2812 struct mv88e6xxx_chip *chip = ds->priv; 2813 int err; 2814 int i; 2815 2816 chip->ds = ds; 2817 ds->slave_mii_bus = chip->mdio_bus; 2818 2819 mutex_lock(&chip->reg_lock); 2820 2821 /* Setup Switch Port Registers */ 2822 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2823 err = mv88e6xxx_setup_port(chip, i); 2824 if (err) 2825 goto unlock; 2826 } 2827 2828 /* Setup Switch Global 1 Registers */ 2829 err = mv88e6xxx_g1_setup(chip); 2830 if (err) 2831 goto unlock; 2832 2833 /* Setup Switch Global 2 Registers */ 2834 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) { 2835 err = mv88e6xxx_g2_setup(chip); 2836 if (err) 2837 goto unlock; 2838 } 2839 2840 /* Some generations have the configuration of sending reserved 2841 * management frames to the CPU in global2, others in 2842 * global1. Hence it does not fit the two setup functions 2843 * above. 2844 */ 2845 if (chip->info->ops->mgmt_rsvd2cpu) { 2846 err = chip->info->ops->mgmt_rsvd2cpu(chip); 2847 if (err) 2848 goto unlock; 2849 } 2850 2851 unlock: 2852 mutex_unlock(&chip->reg_lock); 2853 2854 return err; 2855 } 2856 2857 static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr) 2858 { 2859 struct mv88e6xxx_chip *chip = ds->priv; 2860 int err; 2861 2862 if (!chip->info->ops->set_switch_mac) 2863 return -EOPNOTSUPP; 2864 2865 mutex_lock(&chip->reg_lock); 2866 err = chip->info->ops->set_switch_mac(chip, addr); 2867 mutex_unlock(&chip->reg_lock); 2868 2869 return err; 2870 } 2871 2872 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 2873 { 2874 struct mv88e6xxx_chip *chip = bus->priv; 2875 u16 val; 2876 int err; 2877 2878 if (phy >= mv88e6xxx_num_ports(chip)) 2879 return 0xffff; 2880 2881 mutex_lock(&chip->reg_lock); 2882 err = mv88e6xxx_phy_read(chip, phy, reg, &val); 2883 mutex_unlock(&chip->reg_lock); 2884 2885 return err ? err : val; 2886 } 2887 2888 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 2889 { 2890 struct mv88e6xxx_chip *chip = bus->priv; 2891 int err; 2892 2893 if (phy >= mv88e6xxx_num_ports(chip)) 2894 return 0xffff; 2895 2896 mutex_lock(&chip->reg_lock); 2897 err = mv88e6xxx_phy_write(chip, phy, reg, val); 2898 mutex_unlock(&chip->reg_lock); 2899 2900 return err; 2901 } 2902 2903 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 2904 struct device_node *np) 2905 { 2906 static int index; 2907 struct mii_bus *bus; 2908 int err; 2909 2910 if (np) 2911 chip->mdio_np = of_get_child_by_name(np, "mdio"); 2912 2913 bus = devm_mdiobus_alloc(chip->dev); 2914 if (!bus) 2915 return -ENOMEM; 2916 2917 bus->priv = (void *)chip; 2918 if (np) { 2919 bus->name = np->full_name; 2920 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name); 2921 } else { 2922 bus->name = "mv88e6xxx SMI"; 2923 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 2924 } 2925 2926 bus->read = mv88e6xxx_mdio_read; 2927 bus->write = mv88e6xxx_mdio_write; 2928 bus->parent = chip->dev; 2929 2930 if (chip->mdio_np) 2931 err = of_mdiobus_register(bus, chip->mdio_np); 2932 else 2933 err = mdiobus_register(bus); 2934 if (err) { 2935 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 2936 goto out; 2937 } 2938 chip->mdio_bus = bus; 2939 2940 return 0; 2941 2942 out: 2943 if (chip->mdio_np) 2944 of_node_put(chip->mdio_np); 2945 2946 return err; 2947 } 2948 2949 static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip *chip) 2950 2951 { 2952 struct mii_bus *bus = chip->mdio_bus; 2953 2954 mdiobus_unregister(bus); 2955 2956 if (chip->mdio_np) 2957 of_node_put(chip->mdio_np); 2958 } 2959 2960 #ifdef CONFIG_NET_DSA_HWMON 2961 2962 static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp) 2963 { 2964 struct mv88e6xxx_chip *chip = ds->priv; 2965 u16 val; 2966 int ret; 2967 2968 *temp = 0; 2969 2970 mutex_lock(&chip->reg_lock); 2971 2972 ret = mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x6); 2973 if (ret < 0) 2974 goto error; 2975 2976 /* Enable temperature sensor */ 2977 ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val); 2978 if (ret < 0) 2979 goto error; 2980 2981 ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val | (1 << 5)); 2982 if (ret < 0) 2983 goto error; 2984 2985 /* Wait for temperature to stabilize */ 2986 usleep_range(10000, 12000); 2987 2988 ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val); 2989 if (ret < 0) 2990 goto error; 2991 2992 /* Disable temperature sensor */ 2993 ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val & ~(1 << 5)); 2994 if (ret < 0) 2995 goto error; 2996 2997 *temp = ((val & 0x1f) - 5) * 5; 2998 2999 error: 3000 mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x0); 3001 mutex_unlock(&chip->reg_lock); 3002 return ret; 3003 } 3004 3005 static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp) 3006 { 3007 struct mv88e6xxx_chip *chip = ds->priv; 3008 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0; 3009 u16 val; 3010 int ret; 3011 3012 *temp = 0; 3013 3014 mutex_lock(&chip->reg_lock); 3015 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 27, &val); 3016 mutex_unlock(&chip->reg_lock); 3017 if (ret < 0) 3018 return ret; 3019 3020 *temp = (val & 0xff) - 25; 3021 3022 return 0; 3023 } 3024 3025 static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp) 3026 { 3027 struct mv88e6xxx_chip *chip = ds->priv; 3028 3029 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP)) 3030 return -EOPNOTSUPP; 3031 3032 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip)) 3033 return mv88e63xx_get_temp(ds, temp); 3034 3035 return mv88e61xx_get_temp(ds, temp); 3036 } 3037 3038 static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp) 3039 { 3040 struct mv88e6xxx_chip *chip = ds->priv; 3041 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0; 3042 u16 val; 3043 int ret; 3044 3045 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT)) 3046 return -EOPNOTSUPP; 3047 3048 *temp = 0; 3049 3050 mutex_lock(&chip->reg_lock); 3051 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val); 3052 mutex_unlock(&chip->reg_lock); 3053 if (ret < 0) 3054 return ret; 3055 3056 *temp = (((val >> 8) & 0x1f) * 5) - 25; 3057 3058 return 0; 3059 } 3060 3061 static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp) 3062 { 3063 struct mv88e6xxx_chip *chip = ds->priv; 3064 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0; 3065 u16 val; 3066 int err; 3067 3068 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT)) 3069 return -EOPNOTSUPP; 3070 3071 mutex_lock(&chip->reg_lock); 3072 err = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val); 3073 if (err) 3074 goto unlock; 3075 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f); 3076 err = mv88e6xxx_phy_page_write(chip, phy, 6, 26, 3077 (val & 0xe0ff) | (temp << 8)); 3078 unlock: 3079 mutex_unlock(&chip->reg_lock); 3080 3081 return err; 3082 } 3083 3084 static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm) 3085 { 3086 struct mv88e6xxx_chip *chip = ds->priv; 3087 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0; 3088 u16 val; 3089 int ret; 3090 3091 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT)) 3092 return -EOPNOTSUPP; 3093 3094 *alarm = false; 3095 3096 mutex_lock(&chip->reg_lock); 3097 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val); 3098 mutex_unlock(&chip->reg_lock); 3099 if (ret < 0) 3100 return ret; 3101 3102 *alarm = !!(val & 0x40); 3103 3104 return 0; 3105 } 3106 #endif /* CONFIG_NET_DSA_HWMON */ 3107 3108 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 3109 { 3110 struct mv88e6xxx_chip *chip = ds->priv; 3111 3112 return chip->eeprom_len; 3113 } 3114 3115 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 3116 struct ethtool_eeprom *eeprom, u8 *data) 3117 { 3118 struct mv88e6xxx_chip *chip = ds->priv; 3119 int err; 3120 3121 if (!chip->info->ops->get_eeprom) 3122 return -EOPNOTSUPP; 3123 3124 mutex_lock(&chip->reg_lock); 3125 err = chip->info->ops->get_eeprom(chip, eeprom, data); 3126 mutex_unlock(&chip->reg_lock); 3127 3128 if (err) 3129 return err; 3130 3131 eeprom->magic = 0xc3ec4951; 3132 3133 return 0; 3134 } 3135 3136 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 3137 struct ethtool_eeprom *eeprom, u8 *data) 3138 { 3139 struct mv88e6xxx_chip *chip = ds->priv; 3140 int err; 3141 3142 if (!chip->info->ops->set_eeprom) 3143 return -EOPNOTSUPP; 3144 3145 if (eeprom->magic != 0xc3ec4951) 3146 return -EINVAL; 3147 3148 mutex_lock(&chip->reg_lock); 3149 err = chip->info->ops->set_eeprom(chip, eeprom, data); 3150 mutex_unlock(&chip->reg_lock); 3151 3152 return err; 3153 } 3154 3155 static const struct mv88e6xxx_ops mv88e6085_ops = { 3156 /* MV88E6XXX_FAMILY_6097 */ 3157 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3158 .phy_read = mv88e6xxx_phy_ppu_read, 3159 .phy_write = mv88e6xxx_phy_ppu_write, 3160 .port_set_link = mv88e6xxx_port_set_link, 3161 .port_set_duplex = mv88e6xxx_port_set_duplex, 3162 .port_set_speed = mv88e6185_port_set_speed, 3163 .port_tag_remap = mv88e6095_port_tag_remap, 3164 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3165 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3166 .port_set_ether_type = mv88e6351_port_set_ether_type, 3167 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3168 .port_pause_config = mv88e6097_port_pause_config, 3169 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3170 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3171 .stats_get_strings = mv88e6095_stats_get_strings, 3172 .stats_get_stats = mv88e6095_stats_get_stats, 3173 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3174 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3175 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3176 .ppu_enable = mv88e6185_g1_ppu_enable, 3177 .ppu_disable = mv88e6185_g1_ppu_disable, 3178 .reset = mv88e6185_g1_reset, 3179 }; 3180 3181 static const struct mv88e6xxx_ops mv88e6095_ops = { 3182 /* MV88E6XXX_FAMILY_6095 */ 3183 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3184 .phy_read = mv88e6xxx_phy_ppu_read, 3185 .phy_write = mv88e6xxx_phy_ppu_write, 3186 .port_set_link = mv88e6xxx_port_set_link, 3187 .port_set_duplex = mv88e6xxx_port_set_duplex, 3188 .port_set_speed = mv88e6185_port_set_speed, 3189 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3190 .port_set_egress_unknowns = mv88e6085_port_set_egress_unknowns, 3191 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3192 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3193 .stats_get_strings = mv88e6095_stats_get_strings, 3194 .stats_get_stats = mv88e6095_stats_get_stats, 3195 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3196 .ppu_enable = mv88e6185_g1_ppu_enable, 3197 .ppu_disable = mv88e6185_g1_ppu_disable, 3198 .reset = mv88e6185_g1_reset, 3199 }; 3200 3201 static const struct mv88e6xxx_ops mv88e6097_ops = { 3202 /* MV88E6XXX_FAMILY_6097 */ 3203 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3204 .phy_read = mv88e6xxx_g2_smi_phy_read, 3205 .phy_write = mv88e6xxx_g2_smi_phy_write, 3206 .port_set_link = mv88e6xxx_port_set_link, 3207 .port_set_duplex = mv88e6xxx_port_set_duplex, 3208 .port_set_speed = mv88e6185_port_set_speed, 3209 .port_tag_remap = mv88e6095_port_tag_remap, 3210 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3211 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3212 .port_set_ether_type = mv88e6351_port_set_ether_type, 3213 .port_jumbo_config = mv88e6165_port_jumbo_config, 3214 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3215 .port_pause_config = mv88e6097_port_pause_config, 3216 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3217 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3218 .stats_get_strings = mv88e6095_stats_get_strings, 3219 .stats_get_stats = mv88e6095_stats_get_stats, 3220 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3221 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3222 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3223 .reset = mv88e6352_g1_reset, 3224 }; 3225 3226 static const struct mv88e6xxx_ops mv88e6123_ops = { 3227 /* MV88E6XXX_FAMILY_6165 */ 3228 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3229 .phy_read = mv88e6xxx_read, 3230 .phy_write = mv88e6xxx_write, 3231 .port_set_link = mv88e6xxx_port_set_link, 3232 .port_set_duplex = mv88e6xxx_port_set_duplex, 3233 .port_set_speed = mv88e6185_port_set_speed, 3234 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3235 .port_set_egress_unknowns = mv88e6085_port_set_egress_unknowns, 3236 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3237 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3238 .stats_get_strings = mv88e6095_stats_get_strings, 3239 .stats_get_stats = mv88e6095_stats_get_stats, 3240 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3241 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3242 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3243 .reset = mv88e6352_g1_reset, 3244 }; 3245 3246 static const struct mv88e6xxx_ops mv88e6131_ops = { 3247 /* MV88E6XXX_FAMILY_6185 */ 3248 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3249 .phy_read = mv88e6xxx_phy_ppu_read, 3250 .phy_write = mv88e6xxx_phy_ppu_write, 3251 .port_set_link = mv88e6xxx_port_set_link, 3252 .port_set_duplex = mv88e6xxx_port_set_duplex, 3253 .port_set_speed = mv88e6185_port_set_speed, 3254 .port_tag_remap = mv88e6095_port_tag_remap, 3255 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3256 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3257 .port_set_ether_type = mv88e6351_port_set_ether_type, 3258 .port_jumbo_config = mv88e6165_port_jumbo_config, 3259 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3260 .port_pause_config = mv88e6097_port_pause_config, 3261 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3262 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3263 .stats_get_strings = mv88e6095_stats_get_strings, 3264 .stats_get_stats = mv88e6095_stats_get_stats, 3265 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3266 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3267 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3268 .ppu_enable = mv88e6185_g1_ppu_enable, 3269 .ppu_disable = mv88e6185_g1_ppu_disable, 3270 .reset = mv88e6185_g1_reset, 3271 }; 3272 3273 static const struct mv88e6xxx_ops mv88e6161_ops = { 3274 /* MV88E6XXX_FAMILY_6165 */ 3275 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3276 .phy_read = mv88e6xxx_read, 3277 .phy_write = mv88e6xxx_write, 3278 .port_set_link = mv88e6xxx_port_set_link, 3279 .port_set_duplex = mv88e6xxx_port_set_duplex, 3280 .port_set_speed = mv88e6185_port_set_speed, 3281 .port_tag_remap = mv88e6095_port_tag_remap, 3282 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3283 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3284 .port_set_ether_type = mv88e6351_port_set_ether_type, 3285 .port_jumbo_config = mv88e6165_port_jumbo_config, 3286 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3287 .port_pause_config = mv88e6097_port_pause_config, 3288 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3289 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3290 .stats_get_strings = mv88e6095_stats_get_strings, 3291 .stats_get_stats = mv88e6095_stats_get_stats, 3292 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3293 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3294 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3295 .reset = mv88e6352_g1_reset, 3296 }; 3297 3298 static const struct mv88e6xxx_ops mv88e6165_ops = { 3299 /* MV88E6XXX_FAMILY_6165 */ 3300 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3301 .phy_read = mv88e6xxx_read, 3302 .phy_write = mv88e6xxx_write, 3303 .port_set_link = mv88e6xxx_port_set_link, 3304 .port_set_duplex = mv88e6xxx_port_set_duplex, 3305 .port_set_speed = mv88e6185_port_set_speed, 3306 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3307 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3308 .stats_get_strings = mv88e6095_stats_get_strings, 3309 .stats_get_stats = mv88e6095_stats_get_stats, 3310 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3311 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3312 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3313 .reset = mv88e6352_g1_reset, 3314 }; 3315 3316 static const struct mv88e6xxx_ops mv88e6171_ops = { 3317 /* MV88E6XXX_FAMILY_6351 */ 3318 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3319 .phy_read = mv88e6xxx_g2_smi_phy_read, 3320 .phy_write = mv88e6xxx_g2_smi_phy_write, 3321 .port_set_link = mv88e6xxx_port_set_link, 3322 .port_set_duplex = mv88e6xxx_port_set_duplex, 3323 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3324 .port_set_speed = mv88e6185_port_set_speed, 3325 .port_tag_remap = mv88e6095_port_tag_remap, 3326 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3327 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3328 .port_set_ether_type = mv88e6351_port_set_ether_type, 3329 .port_jumbo_config = mv88e6165_port_jumbo_config, 3330 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3331 .port_pause_config = mv88e6097_port_pause_config, 3332 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3333 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3334 .stats_get_strings = mv88e6095_stats_get_strings, 3335 .stats_get_stats = mv88e6095_stats_get_stats, 3336 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3337 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3338 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3339 .reset = mv88e6352_g1_reset, 3340 }; 3341 3342 static const struct mv88e6xxx_ops mv88e6172_ops = { 3343 /* MV88E6XXX_FAMILY_6352 */ 3344 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3345 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3346 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3347 .phy_read = mv88e6xxx_g2_smi_phy_read, 3348 .phy_write = mv88e6xxx_g2_smi_phy_write, 3349 .port_set_link = mv88e6xxx_port_set_link, 3350 .port_set_duplex = mv88e6xxx_port_set_duplex, 3351 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3352 .port_set_speed = mv88e6352_port_set_speed, 3353 .port_tag_remap = mv88e6095_port_tag_remap, 3354 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3355 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3356 .port_set_ether_type = mv88e6351_port_set_ether_type, 3357 .port_jumbo_config = mv88e6165_port_jumbo_config, 3358 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3359 .port_pause_config = mv88e6097_port_pause_config, 3360 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3361 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3362 .stats_get_strings = mv88e6095_stats_get_strings, 3363 .stats_get_stats = mv88e6095_stats_get_stats, 3364 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3365 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3366 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3367 .reset = mv88e6352_g1_reset, 3368 }; 3369 3370 static const struct mv88e6xxx_ops mv88e6175_ops = { 3371 /* MV88E6XXX_FAMILY_6351 */ 3372 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3373 .phy_read = mv88e6xxx_g2_smi_phy_read, 3374 .phy_write = mv88e6xxx_g2_smi_phy_write, 3375 .port_set_link = mv88e6xxx_port_set_link, 3376 .port_set_duplex = mv88e6xxx_port_set_duplex, 3377 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3378 .port_set_speed = mv88e6185_port_set_speed, 3379 .port_tag_remap = mv88e6095_port_tag_remap, 3380 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3381 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3382 .port_set_ether_type = mv88e6351_port_set_ether_type, 3383 .port_jumbo_config = mv88e6165_port_jumbo_config, 3384 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3385 .port_pause_config = mv88e6097_port_pause_config, 3386 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3387 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3388 .stats_get_strings = mv88e6095_stats_get_strings, 3389 .stats_get_stats = mv88e6095_stats_get_stats, 3390 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3391 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3392 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3393 .reset = mv88e6352_g1_reset, 3394 }; 3395 3396 static const struct mv88e6xxx_ops mv88e6176_ops = { 3397 /* MV88E6XXX_FAMILY_6352 */ 3398 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3399 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3400 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3401 .phy_read = mv88e6xxx_g2_smi_phy_read, 3402 .phy_write = mv88e6xxx_g2_smi_phy_write, 3403 .port_set_link = mv88e6xxx_port_set_link, 3404 .port_set_duplex = mv88e6xxx_port_set_duplex, 3405 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3406 .port_set_speed = mv88e6352_port_set_speed, 3407 .port_tag_remap = mv88e6095_port_tag_remap, 3408 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3409 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3410 .port_set_ether_type = mv88e6351_port_set_ether_type, 3411 .port_jumbo_config = mv88e6165_port_jumbo_config, 3412 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3413 .port_pause_config = mv88e6097_port_pause_config, 3414 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3415 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3416 .stats_get_strings = mv88e6095_stats_get_strings, 3417 .stats_get_stats = mv88e6095_stats_get_stats, 3418 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3419 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3420 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3421 .reset = mv88e6352_g1_reset, 3422 }; 3423 3424 static const struct mv88e6xxx_ops mv88e6185_ops = { 3425 /* MV88E6XXX_FAMILY_6185 */ 3426 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3427 .phy_read = mv88e6xxx_phy_ppu_read, 3428 .phy_write = mv88e6xxx_phy_ppu_write, 3429 .port_set_link = mv88e6xxx_port_set_link, 3430 .port_set_duplex = mv88e6xxx_port_set_duplex, 3431 .port_set_speed = mv88e6185_port_set_speed, 3432 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3433 .port_set_egress_unknowns = mv88e6085_port_set_egress_unknowns, 3434 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3435 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3436 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3437 .stats_get_strings = mv88e6095_stats_get_strings, 3438 .stats_get_stats = mv88e6095_stats_get_stats, 3439 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3440 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3441 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3442 .ppu_enable = mv88e6185_g1_ppu_enable, 3443 .ppu_disable = mv88e6185_g1_ppu_disable, 3444 .reset = mv88e6185_g1_reset, 3445 }; 3446 3447 static const struct mv88e6xxx_ops mv88e6190_ops = { 3448 /* MV88E6XXX_FAMILY_6390 */ 3449 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3450 .phy_read = mv88e6xxx_g2_smi_phy_read, 3451 .phy_write = mv88e6xxx_g2_smi_phy_write, 3452 .port_set_link = mv88e6xxx_port_set_link, 3453 .port_set_duplex = mv88e6xxx_port_set_duplex, 3454 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3455 .port_set_speed = mv88e6390_port_set_speed, 3456 .port_tag_remap = mv88e6390_port_tag_remap, 3457 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3458 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3459 .port_set_ether_type = mv88e6351_port_set_ether_type, 3460 .port_pause_config = mv88e6390_port_pause_config, 3461 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3462 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3463 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3464 .stats_get_strings = mv88e6320_stats_get_strings, 3465 .stats_get_stats = mv88e6390_stats_get_stats, 3466 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port, 3467 .g1_set_egress_port = mv88e6390_g1_set_egress_port, 3468 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3469 .reset = mv88e6352_g1_reset, 3470 }; 3471 3472 static const struct mv88e6xxx_ops mv88e6190x_ops = { 3473 /* MV88E6XXX_FAMILY_6390 */ 3474 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3475 .phy_read = mv88e6xxx_g2_smi_phy_read, 3476 .phy_write = mv88e6xxx_g2_smi_phy_write, 3477 .port_set_link = mv88e6xxx_port_set_link, 3478 .port_set_duplex = mv88e6xxx_port_set_duplex, 3479 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3480 .port_set_speed = mv88e6390x_port_set_speed, 3481 .port_tag_remap = mv88e6390_port_tag_remap, 3482 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3483 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3484 .port_set_ether_type = mv88e6351_port_set_ether_type, 3485 .port_pause_config = mv88e6390_port_pause_config, 3486 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3487 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3488 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3489 .stats_get_strings = mv88e6320_stats_get_strings, 3490 .stats_get_stats = mv88e6390_stats_get_stats, 3491 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port, 3492 .g1_set_egress_port = mv88e6390_g1_set_egress_port, 3493 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3494 .reset = mv88e6352_g1_reset, 3495 }; 3496 3497 static const struct mv88e6xxx_ops mv88e6191_ops = { 3498 /* MV88E6XXX_FAMILY_6390 */ 3499 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3500 .phy_read = mv88e6xxx_g2_smi_phy_read, 3501 .phy_write = mv88e6xxx_g2_smi_phy_write, 3502 .port_set_link = mv88e6xxx_port_set_link, 3503 .port_set_duplex = mv88e6xxx_port_set_duplex, 3504 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3505 .port_set_speed = mv88e6390_port_set_speed, 3506 .port_tag_remap = mv88e6390_port_tag_remap, 3507 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3508 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3509 .port_set_ether_type = mv88e6351_port_set_ether_type, 3510 .port_pause_config = mv88e6390_port_pause_config, 3511 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3512 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3513 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3514 .stats_get_strings = mv88e6320_stats_get_strings, 3515 .stats_get_stats = mv88e6390_stats_get_stats, 3516 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port, 3517 .g1_set_egress_port = mv88e6390_g1_set_egress_port, 3518 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3519 .reset = mv88e6352_g1_reset, 3520 }; 3521 3522 static const struct mv88e6xxx_ops mv88e6240_ops = { 3523 /* MV88E6XXX_FAMILY_6352 */ 3524 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3525 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3526 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3527 .phy_read = mv88e6xxx_g2_smi_phy_read, 3528 .phy_write = mv88e6xxx_g2_smi_phy_write, 3529 .port_set_link = mv88e6xxx_port_set_link, 3530 .port_set_duplex = mv88e6xxx_port_set_duplex, 3531 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3532 .port_set_speed = mv88e6352_port_set_speed, 3533 .port_tag_remap = mv88e6095_port_tag_remap, 3534 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3535 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3536 .port_set_ether_type = mv88e6351_port_set_ether_type, 3537 .port_jumbo_config = mv88e6165_port_jumbo_config, 3538 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3539 .port_pause_config = mv88e6097_port_pause_config, 3540 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3541 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3542 .stats_get_strings = mv88e6095_stats_get_strings, 3543 .stats_get_stats = mv88e6095_stats_get_stats, 3544 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3545 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3546 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3547 .reset = mv88e6352_g1_reset, 3548 }; 3549 3550 static const struct mv88e6xxx_ops mv88e6290_ops = { 3551 /* MV88E6XXX_FAMILY_6390 */ 3552 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3553 .phy_read = mv88e6xxx_g2_smi_phy_read, 3554 .phy_write = mv88e6xxx_g2_smi_phy_write, 3555 .port_set_link = mv88e6xxx_port_set_link, 3556 .port_set_duplex = mv88e6xxx_port_set_duplex, 3557 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3558 .port_set_speed = mv88e6390_port_set_speed, 3559 .port_tag_remap = mv88e6390_port_tag_remap, 3560 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3561 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3562 .port_set_ether_type = mv88e6351_port_set_ether_type, 3563 .port_pause_config = mv88e6390_port_pause_config, 3564 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3565 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3566 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3567 .stats_get_strings = mv88e6320_stats_get_strings, 3568 .stats_get_stats = mv88e6390_stats_get_stats, 3569 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port, 3570 .g1_set_egress_port = mv88e6390_g1_set_egress_port, 3571 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3572 .reset = mv88e6352_g1_reset, 3573 }; 3574 3575 static const struct mv88e6xxx_ops mv88e6320_ops = { 3576 /* MV88E6XXX_FAMILY_6320 */ 3577 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3578 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3579 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3580 .phy_read = mv88e6xxx_g2_smi_phy_read, 3581 .phy_write = mv88e6xxx_g2_smi_phy_write, 3582 .port_set_link = mv88e6xxx_port_set_link, 3583 .port_set_duplex = mv88e6xxx_port_set_duplex, 3584 .port_set_speed = mv88e6185_port_set_speed, 3585 .port_tag_remap = mv88e6095_port_tag_remap, 3586 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3587 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3588 .port_set_ether_type = mv88e6351_port_set_ether_type, 3589 .port_jumbo_config = mv88e6165_port_jumbo_config, 3590 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3591 .port_pause_config = mv88e6097_port_pause_config, 3592 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3593 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3594 .stats_get_strings = mv88e6320_stats_get_strings, 3595 .stats_get_stats = mv88e6320_stats_get_stats, 3596 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3597 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3598 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3599 .reset = mv88e6352_g1_reset, 3600 }; 3601 3602 static const struct mv88e6xxx_ops mv88e6321_ops = { 3603 /* MV88E6XXX_FAMILY_6321 */ 3604 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3605 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3606 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3607 .phy_read = mv88e6xxx_g2_smi_phy_read, 3608 .phy_write = mv88e6xxx_g2_smi_phy_write, 3609 .port_set_link = mv88e6xxx_port_set_link, 3610 .port_set_duplex = mv88e6xxx_port_set_duplex, 3611 .port_set_speed = mv88e6185_port_set_speed, 3612 .port_tag_remap = mv88e6095_port_tag_remap, 3613 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3614 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3615 .port_set_ether_type = mv88e6351_port_set_ether_type, 3616 .port_jumbo_config = mv88e6165_port_jumbo_config, 3617 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3618 .port_pause_config = mv88e6097_port_pause_config, 3619 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3620 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3621 .stats_get_strings = mv88e6320_stats_get_strings, 3622 .stats_get_stats = mv88e6320_stats_get_stats, 3623 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3624 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3625 .reset = mv88e6352_g1_reset, 3626 }; 3627 3628 static const struct mv88e6xxx_ops mv88e6350_ops = { 3629 /* MV88E6XXX_FAMILY_6351 */ 3630 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3631 .phy_read = mv88e6xxx_g2_smi_phy_read, 3632 .phy_write = mv88e6xxx_g2_smi_phy_write, 3633 .port_set_link = mv88e6xxx_port_set_link, 3634 .port_set_duplex = mv88e6xxx_port_set_duplex, 3635 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3636 .port_set_speed = mv88e6185_port_set_speed, 3637 .port_tag_remap = mv88e6095_port_tag_remap, 3638 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3639 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3640 .port_set_ether_type = mv88e6351_port_set_ether_type, 3641 .port_jumbo_config = mv88e6165_port_jumbo_config, 3642 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3643 .port_pause_config = mv88e6097_port_pause_config, 3644 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3645 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3646 .stats_get_strings = mv88e6095_stats_get_strings, 3647 .stats_get_stats = mv88e6095_stats_get_stats, 3648 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3649 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3650 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3651 .reset = mv88e6352_g1_reset, 3652 }; 3653 3654 static const struct mv88e6xxx_ops mv88e6351_ops = { 3655 /* MV88E6XXX_FAMILY_6351 */ 3656 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3657 .phy_read = mv88e6xxx_g2_smi_phy_read, 3658 .phy_write = mv88e6xxx_g2_smi_phy_write, 3659 .port_set_link = mv88e6xxx_port_set_link, 3660 .port_set_duplex = mv88e6xxx_port_set_duplex, 3661 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3662 .port_set_speed = mv88e6185_port_set_speed, 3663 .port_tag_remap = mv88e6095_port_tag_remap, 3664 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3665 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3666 .port_set_ether_type = mv88e6351_port_set_ether_type, 3667 .port_jumbo_config = mv88e6165_port_jumbo_config, 3668 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3669 .port_pause_config = mv88e6097_port_pause_config, 3670 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3671 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3672 .stats_get_strings = mv88e6095_stats_get_strings, 3673 .stats_get_stats = mv88e6095_stats_get_stats, 3674 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3675 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3676 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3677 .reset = mv88e6352_g1_reset, 3678 }; 3679 3680 static const struct mv88e6xxx_ops mv88e6352_ops = { 3681 /* MV88E6XXX_FAMILY_6352 */ 3682 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3683 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3684 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3685 .phy_read = mv88e6xxx_g2_smi_phy_read, 3686 .phy_write = mv88e6xxx_g2_smi_phy_write, 3687 .port_set_link = mv88e6xxx_port_set_link, 3688 .port_set_duplex = mv88e6xxx_port_set_duplex, 3689 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3690 .port_set_speed = mv88e6352_port_set_speed, 3691 .port_tag_remap = mv88e6095_port_tag_remap, 3692 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3693 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3694 .port_set_ether_type = mv88e6351_port_set_ether_type, 3695 .port_jumbo_config = mv88e6165_port_jumbo_config, 3696 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3697 .port_pause_config = mv88e6097_port_pause_config, 3698 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3699 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3700 .stats_get_strings = mv88e6095_stats_get_strings, 3701 .stats_get_stats = mv88e6095_stats_get_stats, 3702 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3703 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3704 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3705 .reset = mv88e6352_g1_reset, 3706 }; 3707 3708 static const struct mv88e6xxx_ops mv88e6390_ops = { 3709 /* MV88E6XXX_FAMILY_6390 */ 3710 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3711 .phy_read = mv88e6xxx_g2_smi_phy_read, 3712 .phy_write = mv88e6xxx_g2_smi_phy_write, 3713 .port_set_link = mv88e6xxx_port_set_link, 3714 .port_set_duplex = mv88e6xxx_port_set_duplex, 3715 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3716 .port_set_speed = mv88e6390_port_set_speed, 3717 .port_tag_remap = mv88e6390_port_tag_remap, 3718 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3719 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3720 .port_set_ether_type = mv88e6351_port_set_ether_type, 3721 .port_jumbo_config = mv88e6165_port_jumbo_config, 3722 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3723 .port_pause_config = mv88e6390_port_pause_config, 3724 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3725 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3726 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3727 .stats_get_strings = mv88e6320_stats_get_strings, 3728 .stats_get_stats = mv88e6390_stats_get_stats, 3729 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port, 3730 .g1_set_egress_port = mv88e6390_g1_set_egress_port, 3731 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3732 .reset = mv88e6352_g1_reset, 3733 }; 3734 3735 static const struct mv88e6xxx_ops mv88e6390x_ops = { 3736 /* MV88E6XXX_FAMILY_6390 */ 3737 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3738 .phy_read = mv88e6xxx_g2_smi_phy_read, 3739 .phy_write = mv88e6xxx_g2_smi_phy_write, 3740 .port_set_link = mv88e6xxx_port_set_link, 3741 .port_set_duplex = mv88e6xxx_port_set_duplex, 3742 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3743 .port_set_speed = mv88e6390x_port_set_speed, 3744 .port_tag_remap = mv88e6390_port_tag_remap, 3745 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3746 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3747 .port_set_ether_type = mv88e6351_port_set_ether_type, 3748 .port_jumbo_config = mv88e6165_port_jumbo_config, 3749 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3750 .port_pause_config = mv88e6390_port_pause_config, 3751 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3752 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3753 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3754 .stats_get_strings = mv88e6320_stats_get_strings, 3755 .stats_get_stats = mv88e6390_stats_get_stats, 3756 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port, 3757 .g1_set_egress_port = mv88e6390_g1_set_egress_port, 3758 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3759 .reset = mv88e6352_g1_reset, 3760 }; 3761 3762 static const struct mv88e6xxx_ops mv88e6391_ops = { 3763 /* MV88E6XXX_FAMILY_6390 */ 3764 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3765 .phy_read = mv88e6xxx_g2_smi_phy_read, 3766 .phy_write = mv88e6xxx_g2_smi_phy_write, 3767 .port_set_link = mv88e6xxx_port_set_link, 3768 .port_set_duplex = mv88e6xxx_port_set_duplex, 3769 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3770 .port_set_speed = mv88e6390_port_set_speed, 3771 .port_tag_remap = mv88e6390_port_tag_remap, 3772 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3773 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3774 .port_set_ether_type = mv88e6351_port_set_ether_type, 3775 .port_pause_config = mv88e6390_port_pause_config, 3776 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3777 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3778 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3779 .stats_get_strings = mv88e6320_stats_get_strings, 3780 .stats_get_stats = mv88e6390_stats_get_stats, 3781 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port, 3782 .g1_set_egress_port = mv88e6390_g1_set_egress_port, 3783 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3784 .reset = mv88e6352_g1_reset, 3785 }; 3786 3787 static int mv88e6xxx_verify_madatory_ops(struct mv88e6xxx_chip *chip, 3788 const struct mv88e6xxx_ops *ops) 3789 { 3790 if (!ops->port_set_frame_mode) { 3791 dev_err(chip->dev, "Missing port_set_frame_mode"); 3792 return -EINVAL; 3793 } 3794 3795 if (!ops->port_set_egress_unknowns) { 3796 dev_err(chip->dev, "Missing port_set_egress_mode"); 3797 return -EINVAL; 3798 } 3799 3800 return 0; 3801 } 3802 3803 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 3804 [MV88E6085] = { 3805 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085, 3806 .family = MV88E6XXX_FAMILY_6097, 3807 .name = "Marvell 88E6085", 3808 .num_databases = 4096, 3809 .num_ports = 10, 3810 .port_base_addr = 0x10, 3811 .global1_addr = 0x1b, 3812 .age_time_coeff = 15000, 3813 .g1_irqs = 8, 3814 .tag_protocol = DSA_TAG_PROTO_DSA, 3815 .flags = MV88E6XXX_FLAGS_FAMILY_6097, 3816 .ops = &mv88e6085_ops, 3817 }, 3818 3819 [MV88E6095] = { 3820 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095, 3821 .family = MV88E6XXX_FAMILY_6095, 3822 .name = "Marvell 88E6095/88E6095F", 3823 .num_databases = 256, 3824 .num_ports = 11, 3825 .port_base_addr = 0x10, 3826 .global1_addr = 0x1b, 3827 .age_time_coeff = 15000, 3828 .g1_irqs = 8, 3829 .tag_protocol = DSA_TAG_PROTO_DSA, 3830 .flags = MV88E6XXX_FLAGS_FAMILY_6095, 3831 .ops = &mv88e6095_ops, 3832 }, 3833 3834 [MV88E6097] = { 3835 .prod_num = PORT_SWITCH_ID_PROD_NUM_6097, 3836 .family = MV88E6XXX_FAMILY_6097, 3837 .name = "Marvell 88E6097/88E6097F", 3838 .num_databases = 4096, 3839 .num_ports = 11, 3840 .port_base_addr = 0x10, 3841 .global1_addr = 0x1b, 3842 .age_time_coeff = 15000, 3843 .g1_irqs = 8, 3844 .tag_protocol = DSA_TAG_PROTO_EDSA, 3845 .flags = MV88E6XXX_FLAGS_FAMILY_6097, 3846 .ops = &mv88e6097_ops, 3847 }, 3848 3849 [MV88E6123] = { 3850 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123, 3851 .family = MV88E6XXX_FAMILY_6165, 3852 .name = "Marvell 88E6123", 3853 .num_databases = 4096, 3854 .num_ports = 3, 3855 .port_base_addr = 0x10, 3856 .global1_addr = 0x1b, 3857 .age_time_coeff = 15000, 3858 .g1_irqs = 9, 3859 .tag_protocol = DSA_TAG_PROTO_DSA, 3860 .flags = MV88E6XXX_FLAGS_FAMILY_6165, 3861 .ops = &mv88e6123_ops, 3862 }, 3863 3864 [MV88E6131] = { 3865 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131, 3866 .family = MV88E6XXX_FAMILY_6185, 3867 .name = "Marvell 88E6131", 3868 .num_databases = 256, 3869 .num_ports = 8, 3870 .port_base_addr = 0x10, 3871 .global1_addr = 0x1b, 3872 .age_time_coeff = 15000, 3873 .g1_irqs = 9, 3874 .tag_protocol = DSA_TAG_PROTO_DSA, 3875 .flags = MV88E6XXX_FLAGS_FAMILY_6185, 3876 .ops = &mv88e6131_ops, 3877 }, 3878 3879 [MV88E6161] = { 3880 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161, 3881 .family = MV88E6XXX_FAMILY_6165, 3882 .name = "Marvell 88E6161", 3883 .num_databases = 4096, 3884 .num_ports = 6, 3885 .port_base_addr = 0x10, 3886 .global1_addr = 0x1b, 3887 .age_time_coeff = 15000, 3888 .g1_irqs = 9, 3889 .tag_protocol = DSA_TAG_PROTO_DSA, 3890 .flags = MV88E6XXX_FLAGS_FAMILY_6165, 3891 .ops = &mv88e6161_ops, 3892 }, 3893 3894 [MV88E6165] = { 3895 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165, 3896 .family = MV88E6XXX_FAMILY_6165, 3897 .name = "Marvell 88E6165", 3898 .num_databases = 4096, 3899 .num_ports = 6, 3900 .port_base_addr = 0x10, 3901 .global1_addr = 0x1b, 3902 .age_time_coeff = 15000, 3903 .g1_irqs = 9, 3904 .tag_protocol = DSA_TAG_PROTO_DSA, 3905 .flags = MV88E6XXX_FLAGS_FAMILY_6165, 3906 .ops = &mv88e6165_ops, 3907 }, 3908 3909 [MV88E6171] = { 3910 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171, 3911 .family = MV88E6XXX_FAMILY_6351, 3912 .name = "Marvell 88E6171", 3913 .num_databases = 4096, 3914 .num_ports = 7, 3915 .port_base_addr = 0x10, 3916 .global1_addr = 0x1b, 3917 .age_time_coeff = 15000, 3918 .g1_irqs = 9, 3919 .tag_protocol = DSA_TAG_PROTO_EDSA, 3920 .flags = MV88E6XXX_FLAGS_FAMILY_6351, 3921 .ops = &mv88e6171_ops, 3922 }, 3923 3924 [MV88E6172] = { 3925 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172, 3926 .family = MV88E6XXX_FAMILY_6352, 3927 .name = "Marvell 88E6172", 3928 .num_databases = 4096, 3929 .num_ports = 7, 3930 .port_base_addr = 0x10, 3931 .global1_addr = 0x1b, 3932 .age_time_coeff = 15000, 3933 .g1_irqs = 9, 3934 .tag_protocol = DSA_TAG_PROTO_EDSA, 3935 .flags = MV88E6XXX_FLAGS_FAMILY_6352, 3936 .ops = &mv88e6172_ops, 3937 }, 3938 3939 [MV88E6175] = { 3940 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175, 3941 .family = MV88E6XXX_FAMILY_6351, 3942 .name = "Marvell 88E6175", 3943 .num_databases = 4096, 3944 .num_ports = 7, 3945 .port_base_addr = 0x10, 3946 .global1_addr = 0x1b, 3947 .age_time_coeff = 15000, 3948 .g1_irqs = 9, 3949 .tag_protocol = DSA_TAG_PROTO_EDSA, 3950 .flags = MV88E6XXX_FLAGS_FAMILY_6351, 3951 .ops = &mv88e6175_ops, 3952 }, 3953 3954 [MV88E6176] = { 3955 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176, 3956 .family = MV88E6XXX_FAMILY_6352, 3957 .name = "Marvell 88E6176", 3958 .num_databases = 4096, 3959 .num_ports = 7, 3960 .port_base_addr = 0x10, 3961 .global1_addr = 0x1b, 3962 .age_time_coeff = 15000, 3963 .g1_irqs = 9, 3964 .tag_protocol = DSA_TAG_PROTO_EDSA, 3965 .flags = MV88E6XXX_FLAGS_FAMILY_6352, 3966 .ops = &mv88e6176_ops, 3967 }, 3968 3969 [MV88E6185] = { 3970 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185, 3971 .family = MV88E6XXX_FAMILY_6185, 3972 .name = "Marvell 88E6185", 3973 .num_databases = 256, 3974 .num_ports = 10, 3975 .port_base_addr = 0x10, 3976 .global1_addr = 0x1b, 3977 .age_time_coeff = 15000, 3978 .g1_irqs = 8, 3979 .tag_protocol = DSA_TAG_PROTO_EDSA, 3980 .flags = MV88E6XXX_FLAGS_FAMILY_6185, 3981 .ops = &mv88e6185_ops, 3982 }, 3983 3984 [MV88E6190] = { 3985 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190, 3986 .family = MV88E6XXX_FAMILY_6390, 3987 .name = "Marvell 88E6190", 3988 .num_databases = 4096, 3989 .num_ports = 11, /* 10 + Z80 */ 3990 .port_base_addr = 0x0, 3991 .global1_addr = 0x1b, 3992 .tag_protocol = DSA_TAG_PROTO_DSA, 3993 .age_time_coeff = 15000, 3994 .g1_irqs = 9, 3995 .flags = MV88E6XXX_FLAGS_FAMILY_6390, 3996 .ops = &mv88e6190_ops, 3997 }, 3998 3999 [MV88E6190X] = { 4000 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190X, 4001 .family = MV88E6XXX_FAMILY_6390, 4002 .name = "Marvell 88E6190X", 4003 .num_databases = 4096, 4004 .num_ports = 11, /* 10 + Z80 */ 4005 .port_base_addr = 0x0, 4006 .global1_addr = 0x1b, 4007 .age_time_coeff = 15000, 4008 .g1_irqs = 9, 4009 .tag_protocol = DSA_TAG_PROTO_DSA, 4010 .flags = MV88E6XXX_FLAGS_FAMILY_6390, 4011 .ops = &mv88e6190x_ops, 4012 }, 4013 4014 [MV88E6191] = { 4015 .prod_num = PORT_SWITCH_ID_PROD_NUM_6191, 4016 .family = MV88E6XXX_FAMILY_6390, 4017 .name = "Marvell 88E6191", 4018 .num_databases = 4096, 4019 .num_ports = 11, /* 10 + Z80 */ 4020 .port_base_addr = 0x0, 4021 .global1_addr = 0x1b, 4022 .age_time_coeff = 15000, 4023 .g1_irqs = 9, 4024 .tag_protocol = DSA_TAG_PROTO_DSA, 4025 .flags = MV88E6XXX_FLAGS_FAMILY_6390, 4026 .ops = &mv88e6391_ops, 4027 }, 4028 4029 [MV88E6240] = { 4030 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240, 4031 .family = MV88E6XXX_FAMILY_6352, 4032 .name = "Marvell 88E6240", 4033 .num_databases = 4096, 4034 .num_ports = 7, 4035 .port_base_addr = 0x10, 4036 .global1_addr = 0x1b, 4037 .age_time_coeff = 15000, 4038 .g1_irqs = 9, 4039 .tag_protocol = DSA_TAG_PROTO_EDSA, 4040 .flags = MV88E6XXX_FLAGS_FAMILY_6352, 4041 .ops = &mv88e6240_ops, 4042 }, 4043 4044 [MV88E6290] = { 4045 .prod_num = PORT_SWITCH_ID_PROD_NUM_6290, 4046 .family = MV88E6XXX_FAMILY_6390, 4047 .name = "Marvell 88E6290", 4048 .num_databases = 4096, 4049 .num_ports = 11, /* 10 + Z80 */ 4050 .port_base_addr = 0x0, 4051 .global1_addr = 0x1b, 4052 .age_time_coeff = 15000, 4053 .g1_irqs = 9, 4054 .tag_protocol = DSA_TAG_PROTO_DSA, 4055 .flags = MV88E6XXX_FLAGS_FAMILY_6390, 4056 .ops = &mv88e6290_ops, 4057 }, 4058 4059 [MV88E6320] = { 4060 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320, 4061 .family = MV88E6XXX_FAMILY_6320, 4062 .name = "Marvell 88E6320", 4063 .num_databases = 4096, 4064 .num_ports = 7, 4065 .port_base_addr = 0x10, 4066 .global1_addr = 0x1b, 4067 .age_time_coeff = 15000, 4068 .g1_irqs = 8, 4069 .tag_protocol = DSA_TAG_PROTO_EDSA, 4070 .flags = MV88E6XXX_FLAGS_FAMILY_6320, 4071 .ops = &mv88e6320_ops, 4072 }, 4073 4074 [MV88E6321] = { 4075 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321, 4076 .family = MV88E6XXX_FAMILY_6320, 4077 .name = "Marvell 88E6321", 4078 .num_databases = 4096, 4079 .num_ports = 7, 4080 .port_base_addr = 0x10, 4081 .global1_addr = 0x1b, 4082 .age_time_coeff = 15000, 4083 .g1_irqs = 8, 4084 .tag_protocol = DSA_TAG_PROTO_EDSA, 4085 .flags = MV88E6XXX_FLAGS_FAMILY_6320, 4086 .ops = &mv88e6321_ops, 4087 }, 4088 4089 [MV88E6350] = { 4090 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350, 4091 .family = MV88E6XXX_FAMILY_6351, 4092 .name = "Marvell 88E6350", 4093 .num_databases = 4096, 4094 .num_ports = 7, 4095 .port_base_addr = 0x10, 4096 .global1_addr = 0x1b, 4097 .age_time_coeff = 15000, 4098 .g1_irqs = 9, 4099 .tag_protocol = DSA_TAG_PROTO_EDSA, 4100 .flags = MV88E6XXX_FLAGS_FAMILY_6351, 4101 .ops = &mv88e6350_ops, 4102 }, 4103 4104 [MV88E6351] = { 4105 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351, 4106 .family = MV88E6XXX_FAMILY_6351, 4107 .name = "Marvell 88E6351", 4108 .num_databases = 4096, 4109 .num_ports = 7, 4110 .port_base_addr = 0x10, 4111 .global1_addr = 0x1b, 4112 .age_time_coeff = 15000, 4113 .g1_irqs = 9, 4114 .tag_protocol = DSA_TAG_PROTO_EDSA, 4115 .flags = MV88E6XXX_FLAGS_FAMILY_6351, 4116 .ops = &mv88e6351_ops, 4117 }, 4118 4119 [MV88E6352] = { 4120 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352, 4121 .family = MV88E6XXX_FAMILY_6352, 4122 .name = "Marvell 88E6352", 4123 .num_databases = 4096, 4124 .num_ports = 7, 4125 .port_base_addr = 0x10, 4126 .global1_addr = 0x1b, 4127 .age_time_coeff = 15000, 4128 .g1_irqs = 9, 4129 .tag_protocol = DSA_TAG_PROTO_EDSA, 4130 .flags = MV88E6XXX_FLAGS_FAMILY_6352, 4131 .ops = &mv88e6352_ops, 4132 }, 4133 [MV88E6390] = { 4134 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390, 4135 .family = MV88E6XXX_FAMILY_6390, 4136 .name = "Marvell 88E6390", 4137 .num_databases = 4096, 4138 .num_ports = 11, /* 10 + Z80 */ 4139 .port_base_addr = 0x0, 4140 .global1_addr = 0x1b, 4141 .age_time_coeff = 15000, 4142 .g1_irqs = 9, 4143 .tag_protocol = DSA_TAG_PROTO_DSA, 4144 .flags = MV88E6XXX_FLAGS_FAMILY_6390, 4145 .ops = &mv88e6390_ops, 4146 }, 4147 [MV88E6390X] = { 4148 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390X, 4149 .family = MV88E6XXX_FAMILY_6390, 4150 .name = "Marvell 88E6390X", 4151 .num_databases = 4096, 4152 .num_ports = 11, /* 10 + Z80 */ 4153 .port_base_addr = 0x0, 4154 .global1_addr = 0x1b, 4155 .age_time_coeff = 15000, 4156 .g1_irqs = 9, 4157 .tag_protocol = DSA_TAG_PROTO_DSA, 4158 .flags = MV88E6XXX_FLAGS_FAMILY_6390, 4159 .ops = &mv88e6390x_ops, 4160 }, 4161 }; 4162 4163 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 4164 { 4165 int i; 4166 4167 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 4168 if (mv88e6xxx_table[i].prod_num == prod_num) 4169 return &mv88e6xxx_table[i]; 4170 4171 return NULL; 4172 } 4173 4174 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 4175 { 4176 const struct mv88e6xxx_info *info; 4177 unsigned int prod_num, rev; 4178 u16 id; 4179 int err; 4180 4181 mutex_lock(&chip->reg_lock); 4182 err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id); 4183 mutex_unlock(&chip->reg_lock); 4184 if (err) 4185 return err; 4186 4187 prod_num = (id & 0xfff0) >> 4; 4188 rev = id & 0x000f; 4189 4190 info = mv88e6xxx_lookup_info(prod_num); 4191 if (!info) 4192 return -ENODEV; 4193 4194 /* Update the compatible info with the probed one */ 4195 chip->info = info; 4196 4197 err = mv88e6xxx_g2_require(chip); 4198 if (err) 4199 return err; 4200 4201 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 4202 chip->info->prod_num, chip->info->name, rev); 4203 4204 return 0; 4205 } 4206 4207 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 4208 { 4209 struct mv88e6xxx_chip *chip; 4210 4211 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 4212 if (!chip) 4213 return NULL; 4214 4215 chip->dev = dev; 4216 4217 mutex_init(&chip->reg_lock); 4218 4219 return chip; 4220 } 4221 4222 static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip) 4223 { 4224 if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable) 4225 mv88e6xxx_ppu_state_init(chip); 4226 } 4227 4228 static void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip) 4229 { 4230 if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable) 4231 mv88e6xxx_ppu_state_destroy(chip); 4232 } 4233 4234 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip, 4235 struct mii_bus *bus, int sw_addr) 4236 { 4237 /* ADDR[0] pin is unavailable externally and considered zero */ 4238 if (sw_addr & 0x1) 4239 return -EINVAL; 4240 4241 if (sw_addr == 0) 4242 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops; 4243 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP)) 4244 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops; 4245 else 4246 return -EINVAL; 4247 4248 chip->bus = bus; 4249 chip->sw_addr = sw_addr; 4250 4251 return 0; 4252 } 4253 4254 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds) 4255 { 4256 struct mv88e6xxx_chip *chip = ds->priv; 4257 4258 return chip->info->tag_protocol; 4259 } 4260 4261 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev, 4262 struct device *host_dev, int sw_addr, 4263 void **priv) 4264 { 4265 struct mv88e6xxx_chip *chip; 4266 struct mii_bus *bus; 4267 int err; 4268 4269 bus = dsa_host_dev_to_mii_bus(host_dev); 4270 if (!bus) 4271 return NULL; 4272 4273 chip = mv88e6xxx_alloc_chip(dsa_dev); 4274 if (!chip) 4275 return NULL; 4276 4277 /* Legacy SMI probing will only support chips similar to 88E6085 */ 4278 chip->info = &mv88e6xxx_table[MV88E6085]; 4279 4280 err = mv88e6xxx_smi_init(chip, bus, sw_addr); 4281 if (err) 4282 goto free; 4283 4284 err = mv88e6xxx_detect(chip); 4285 if (err) 4286 goto free; 4287 4288 mutex_lock(&chip->reg_lock); 4289 err = mv88e6xxx_switch_reset(chip); 4290 mutex_unlock(&chip->reg_lock); 4291 if (err) 4292 goto free; 4293 4294 mv88e6xxx_phy_init(chip); 4295 4296 err = mv88e6xxx_mdio_register(chip, NULL); 4297 if (err) 4298 goto free; 4299 4300 *priv = chip; 4301 4302 return chip->info->name; 4303 free: 4304 devm_kfree(dsa_dev, chip); 4305 4306 return NULL; 4307 } 4308 4309 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port, 4310 const struct switchdev_obj_port_mdb *mdb, 4311 struct switchdev_trans *trans) 4312 { 4313 /* We don't need any dynamic resource from the kernel (yet), 4314 * so skip the prepare phase. 4315 */ 4316 4317 return 0; 4318 } 4319 4320 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 4321 const struct switchdev_obj_port_mdb *mdb, 4322 struct switchdev_trans *trans) 4323 { 4324 struct mv88e6xxx_chip *chip = ds->priv; 4325 4326 mutex_lock(&chip->reg_lock); 4327 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 4328 GLOBAL_ATU_DATA_STATE_MC_STATIC)) 4329 netdev_err(ds->ports[port].netdev, "failed to load multicast MAC address\n"); 4330 mutex_unlock(&chip->reg_lock); 4331 } 4332 4333 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 4334 const struct switchdev_obj_port_mdb *mdb) 4335 { 4336 struct mv88e6xxx_chip *chip = ds->priv; 4337 int err; 4338 4339 mutex_lock(&chip->reg_lock); 4340 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 4341 GLOBAL_ATU_DATA_STATE_UNUSED); 4342 mutex_unlock(&chip->reg_lock); 4343 4344 return err; 4345 } 4346 4347 static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port, 4348 struct switchdev_obj_port_mdb *mdb, 4349 int (*cb)(struct switchdev_obj *obj)) 4350 { 4351 struct mv88e6xxx_chip *chip = ds->priv; 4352 int err; 4353 4354 mutex_lock(&chip->reg_lock); 4355 err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb); 4356 mutex_unlock(&chip->reg_lock); 4357 4358 return err; 4359 } 4360 4361 static struct dsa_switch_ops mv88e6xxx_switch_ops = { 4362 .probe = mv88e6xxx_drv_probe, 4363 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 4364 .setup = mv88e6xxx_setup, 4365 .set_addr = mv88e6xxx_set_addr, 4366 .adjust_link = mv88e6xxx_adjust_link, 4367 .get_strings = mv88e6xxx_get_strings, 4368 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 4369 .get_sset_count = mv88e6xxx_get_sset_count, 4370 .set_eee = mv88e6xxx_set_eee, 4371 .get_eee = mv88e6xxx_get_eee, 4372 #ifdef CONFIG_NET_DSA_HWMON 4373 .get_temp = mv88e6xxx_get_temp, 4374 .get_temp_limit = mv88e6xxx_get_temp_limit, 4375 .set_temp_limit = mv88e6xxx_set_temp_limit, 4376 .get_temp_alarm = mv88e6xxx_get_temp_alarm, 4377 #endif 4378 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 4379 .get_eeprom = mv88e6xxx_get_eeprom, 4380 .set_eeprom = mv88e6xxx_set_eeprom, 4381 .get_regs_len = mv88e6xxx_get_regs_len, 4382 .get_regs = mv88e6xxx_get_regs, 4383 .set_ageing_time = mv88e6xxx_set_ageing_time, 4384 .port_bridge_join = mv88e6xxx_port_bridge_join, 4385 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 4386 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 4387 .port_fast_age = mv88e6xxx_port_fast_age, 4388 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 4389 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare, 4390 .port_vlan_add = mv88e6xxx_port_vlan_add, 4391 .port_vlan_del = mv88e6xxx_port_vlan_del, 4392 .port_vlan_dump = mv88e6xxx_port_vlan_dump, 4393 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare, 4394 .port_fdb_add = mv88e6xxx_port_fdb_add, 4395 .port_fdb_del = mv88e6xxx_port_fdb_del, 4396 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 4397 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare, 4398 .port_mdb_add = mv88e6xxx_port_mdb_add, 4399 .port_mdb_del = mv88e6xxx_port_mdb_del, 4400 .port_mdb_dump = mv88e6xxx_port_mdb_dump, 4401 }; 4402 4403 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip, 4404 struct device_node *np) 4405 { 4406 struct device *dev = chip->dev; 4407 struct dsa_switch *ds; 4408 4409 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 4410 if (!ds) 4411 return -ENOMEM; 4412 4413 ds->dev = dev; 4414 ds->priv = chip; 4415 ds->ops = &mv88e6xxx_switch_ops; 4416 4417 dev_set_drvdata(dev, ds); 4418 4419 return dsa_register_switch(ds, np); 4420 } 4421 4422 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 4423 { 4424 dsa_unregister_switch(chip->ds); 4425 } 4426 4427 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 4428 { 4429 struct device *dev = &mdiodev->dev; 4430 struct device_node *np = dev->of_node; 4431 const struct mv88e6xxx_info *compat_info; 4432 struct mv88e6xxx_chip *chip; 4433 u32 eeprom_len; 4434 int err; 4435 4436 compat_info = of_device_get_match_data(dev); 4437 if (!compat_info) 4438 return -EINVAL; 4439 4440 chip = mv88e6xxx_alloc_chip(dev); 4441 if (!chip) 4442 return -ENOMEM; 4443 4444 chip->info = compat_info; 4445 4446 err = mv88e6xxx_verify_madatory_ops(chip, chip->info->ops); 4447 if (err) 4448 return err; 4449 4450 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 4451 if (err) 4452 return err; 4453 4454 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 4455 if (IS_ERR(chip->reset)) 4456 return PTR_ERR(chip->reset); 4457 4458 err = mv88e6xxx_detect(chip); 4459 if (err) 4460 return err; 4461 4462 mv88e6xxx_phy_init(chip); 4463 4464 if (chip->info->ops->get_eeprom && 4465 !of_property_read_u32(np, "eeprom-length", &eeprom_len)) 4466 chip->eeprom_len = eeprom_len; 4467 4468 mutex_lock(&chip->reg_lock); 4469 err = mv88e6xxx_switch_reset(chip); 4470 mutex_unlock(&chip->reg_lock); 4471 if (err) 4472 goto out; 4473 4474 chip->irq = of_irq_get(np, 0); 4475 if (chip->irq == -EPROBE_DEFER) { 4476 err = chip->irq; 4477 goto out; 4478 } 4479 4480 if (chip->irq > 0) { 4481 /* Has to be performed before the MDIO bus is created, 4482 * because the PHYs will link there interrupts to these 4483 * interrupt controllers 4484 */ 4485 mutex_lock(&chip->reg_lock); 4486 err = mv88e6xxx_g1_irq_setup(chip); 4487 mutex_unlock(&chip->reg_lock); 4488 4489 if (err) 4490 goto out; 4491 4492 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT)) { 4493 err = mv88e6xxx_g2_irq_setup(chip); 4494 if (err) 4495 goto out_g1_irq; 4496 } 4497 } 4498 4499 err = mv88e6xxx_mdio_register(chip, np); 4500 if (err) 4501 goto out_g2_irq; 4502 4503 err = mv88e6xxx_register_switch(chip, np); 4504 if (err) 4505 goto out_mdio; 4506 4507 return 0; 4508 4509 out_mdio: 4510 mv88e6xxx_mdio_unregister(chip); 4511 out_g2_irq: 4512 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT) && chip->irq > 0) 4513 mv88e6xxx_g2_irq_free(chip); 4514 out_g1_irq: 4515 if (chip->irq > 0) { 4516 mutex_lock(&chip->reg_lock); 4517 mv88e6xxx_g1_irq_free(chip); 4518 mutex_unlock(&chip->reg_lock); 4519 } 4520 out: 4521 return err; 4522 } 4523 4524 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 4525 { 4526 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 4527 struct mv88e6xxx_chip *chip = ds->priv; 4528 4529 mv88e6xxx_phy_destroy(chip); 4530 mv88e6xxx_unregister_switch(chip); 4531 mv88e6xxx_mdio_unregister(chip); 4532 4533 if (chip->irq > 0) { 4534 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT)) 4535 mv88e6xxx_g2_irq_free(chip); 4536 mv88e6xxx_g1_irq_free(chip); 4537 } 4538 } 4539 4540 static const struct of_device_id mv88e6xxx_of_match[] = { 4541 { 4542 .compatible = "marvell,mv88e6085", 4543 .data = &mv88e6xxx_table[MV88E6085], 4544 }, 4545 { 4546 .compatible = "marvell,mv88e6190", 4547 .data = &mv88e6xxx_table[MV88E6190], 4548 }, 4549 { /* sentinel */ }, 4550 }; 4551 4552 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 4553 4554 static struct mdio_driver mv88e6xxx_driver = { 4555 .probe = mv88e6xxx_probe, 4556 .remove = mv88e6xxx_remove, 4557 .mdiodrv.driver = { 4558 .name = "mv88e6085", 4559 .of_match_table = mv88e6xxx_of_match, 4560 }, 4561 }; 4562 4563 static int __init mv88e6xxx_init(void) 4564 { 4565 register_switch_driver(&mv88e6xxx_switch_ops); 4566 return mdio_driver_register(&mv88e6xxx_driver); 4567 } 4568 module_init(mv88e6xxx_init); 4569 4570 static void __exit mv88e6xxx_cleanup(void) 4571 { 4572 mdio_driver_unregister(&mv88e6xxx_driver); 4573 unregister_switch_driver(&mv88e6xxx_switch_ops); 4574 } 4575 module_exit(mv88e6xxx_cleanup); 4576 4577 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 4578 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 4579 MODULE_LICENSE("GPL"); 4580