1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Mediatek MT7530 DSA Switch driver 4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 5 */ 6 #include <linux/etherdevice.h> 7 #include <linux/if_bridge.h> 8 #include <linux/iopoll.h> 9 #include <linux/mdio.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/module.h> 12 #include <linux/netdevice.h> 13 #include <linux/of_irq.h> 14 #include <linux/of_mdio.h> 15 #include <linux/of_net.h> 16 #include <linux/of_platform.h> 17 #include <linux/phylink.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/gpio/consumer.h> 22 #include <linux/gpio/driver.h> 23 #include <net/dsa.h> 24 #include <net/pkt_cls.h> 25 26 #include "mt7530.h" 27 28 #define MT7530_STATS_POLL_INTERVAL (1 * HZ) 29 #define MT7530_STATS_RATE_LIMIT (HZ / 10) 30 31 static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs) 32 { 33 return container_of(pcs, struct mt753x_pcs, pcs); 34 } 35 36 /* String, offset, and register size in bytes if different from 4 bytes */ 37 static const struct mt7530_mib_desc mt7530_mib[] = { 38 MIB_DESC(1, MT7530_PORT_MIB_TX_DROP, "TxDrop"), 39 MIB_DESC(1, MT7530_PORT_MIB_TX_CRC_ERR, "TxCrcErr"), 40 MIB_DESC(1, MT7530_PORT_MIB_TX_COLLISION, "TxCollision"), 41 MIB_DESC(1, MT7530_PORT_MIB_RX_DROP, "RxDrop"), 42 MIB_DESC(1, MT7530_PORT_MIB_RX_FILTERING, "RxFiltering"), 43 MIB_DESC(1, MT7530_PORT_MIB_RX_CRC_ERR, "RxCrcErr"), 44 MIB_DESC(1, MT7530_PORT_MIB_RX_CTRL_DROP, "RxCtrlDrop"), 45 MIB_DESC(1, MT7530_PORT_MIB_RX_INGRESS_DROP, "RxIngressDrop"), 46 MIB_DESC(1, MT7530_PORT_MIB_RX_ARL_DROP, "RxArlDrop"), 47 }; 48 49 static void 50 mt7530_mutex_lock(struct mt7530_priv *priv) 51 { 52 if (priv->bus) 53 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); 54 } 55 56 static void 57 mt7530_mutex_unlock(struct mt7530_priv *priv) 58 { 59 if (priv->bus) 60 mutex_unlock(&priv->bus->mdio_lock); 61 } 62 63 static void 64 core_write(struct mt7530_priv *priv, u32 reg, u32 val) 65 { 66 struct mii_bus *bus = priv->bus; 67 int ret; 68 69 mt7530_mutex_lock(priv); 70 71 /* Write the desired MMD Devad */ 72 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 73 MII_MMD_CTRL, MDIO_MMD_VEND2); 74 if (ret < 0) 75 goto err; 76 77 /* Write the desired MMD register address */ 78 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 79 MII_MMD_DATA, reg); 80 if (ret < 0) 81 goto err; 82 83 /* Select the Function : DATA with no post increment */ 84 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 85 MII_MMD_CTRL, MDIO_MMD_VEND2 | MII_MMD_CTRL_NOINCR); 86 if (ret < 0) 87 goto err; 88 89 /* Write the data into MMD's selected register */ 90 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 91 MII_MMD_DATA, val); 92 err: 93 if (ret < 0) 94 dev_err(&bus->dev, "failed to write mmd register\n"); 95 96 mt7530_mutex_unlock(priv); 97 } 98 99 static void 100 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set) 101 { 102 struct mii_bus *bus = priv->bus; 103 u32 val; 104 int ret; 105 106 mt7530_mutex_lock(priv); 107 108 /* Write the desired MMD Devad */ 109 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 110 MII_MMD_CTRL, MDIO_MMD_VEND2); 111 if (ret < 0) 112 goto err; 113 114 /* Write the desired MMD register address */ 115 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 116 MII_MMD_DATA, reg); 117 if (ret < 0) 118 goto err; 119 120 /* Select the Function : DATA with no post increment */ 121 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 122 MII_MMD_CTRL, MDIO_MMD_VEND2 | MII_MMD_CTRL_NOINCR); 123 if (ret < 0) 124 goto err; 125 126 /* Read the content of the MMD's selected register */ 127 val = bus->read(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 128 MII_MMD_DATA); 129 val &= ~mask; 130 val |= set; 131 /* Write the data into MMD's selected register */ 132 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 133 MII_MMD_DATA, val); 134 err: 135 if (ret < 0) 136 dev_err(&bus->dev, "failed to write mmd register\n"); 137 138 mt7530_mutex_unlock(priv); 139 } 140 141 static void 142 core_set(struct mt7530_priv *priv, u32 reg, u32 val) 143 { 144 core_rmw(priv, reg, 0, val); 145 } 146 147 static void 148 core_clear(struct mt7530_priv *priv, u32 reg, u32 val) 149 { 150 core_rmw(priv, reg, val, 0); 151 } 152 153 static int 154 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val) 155 { 156 int ret; 157 158 ret = regmap_write(priv->regmap, reg, val); 159 160 if (ret < 0) 161 dev_err(priv->dev, 162 "failed to write mt7530 register\n"); 163 164 return ret; 165 } 166 167 static u32 168 mt7530_mii_read(struct mt7530_priv *priv, u32 reg) 169 { 170 int ret; 171 u32 val; 172 173 ret = regmap_read(priv->regmap, reg, &val); 174 if (ret) { 175 WARN_ON_ONCE(1); 176 dev_err(priv->dev, 177 "failed to read mt7530 register\n"); 178 return 0; 179 } 180 181 return val; 182 } 183 184 static void 185 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val) 186 { 187 mt7530_mutex_lock(priv); 188 189 mt7530_mii_write(priv, reg, val); 190 191 mt7530_mutex_unlock(priv); 192 } 193 194 static u32 195 _mt7530_unlocked_read(struct mt7530_dummy_poll *p) 196 { 197 return mt7530_mii_read(p->priv, p->reg); 198 } 199 200 static u32 201 _mt7530_read(struct mt7530_dummy_poll *p) 202 { 203 u32 val; 204 205 mt7530_mutex_lock(p->priv); 206 207 val = mt7530_mii_read(p->priv, p->reg); 208 209 mt7530_mutex_unlock(p->priv); 210 211 return val; 212 } 213 214 static u32 215 mt7530_read(struct mt7530_priv *priv, u32 reg) 216 { 217 struct mt7530_dummy_poll p; 218 219 INIT_MT7530_DUMMY_POLL(&p, priv, reg); 220 return _mt7530_read(&p); 221 } 222 223 static void 224 mt7530_rmw(struct mt7530_priv *priv, u32 reg, 225 u32 mask, u32 set) 226 { 227 mt7530_mutex_lock(priv); 228 229 regmap_update_bits(priv->regmap, reg, mask, set); 230 231 mt7530_mutex_unlock(priv); 232 } 233 234 static void 235 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val) 236 { 237 mt7530_rmw(priv, reg, val, val); 238 } 239 240 static void 241 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val) 242 { 243 mt7530_rmw(priv, reg, val, 0); 244 } 245 246 static int 247 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp) 248 { 249 u32 val; 250 int ret; 251 struct mt7530_dummy_poll p; 252 253 /* Set the command operating upon the MAC address entries */ 254 val = ATC_BUSY | ATC_MAT(0) | cmd; 255 mt7530_write(priv, MT7530_ATC, val); 256 257 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC); 258 ret = readx_poll_timeout(_mt7530_read, &p, val, 259 !(val & ATC_BUSY), 20, 20000); 260 if (ret < 0) { 261 dev_err(priv->dev, "reset timeout\n"); 262 return ret; 263 } 264 265 /* Additional sanity for read command if the specified 266 * entry is invalid 267 */ 268 val = mt7530_read(priv, MT7530_ATC); 269 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID)) 270 return -EINVAL; 271 272 if (rsp) 273 *rsp = val; 274 275 return 0; 276 } 277 278 static void 279 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb) 280 { 281 u32 reg[3]; 282 int i; 283 284 /* Read from ARL table into an array */ 285 for (i = 0; i < 3; i++) { 286 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4)); 287 288 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", 289 __func__, __LINE__, i, reg[i]); 290 } 291 292 fdb->vid = (reg[1] >> CVID) & CVID_MASK; 293 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; 294 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; 295 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; 296 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; 297 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; 298 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; 299 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; 300 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; 301 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; 302 } 303 304 static void 305 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid, 306 u8 port_mask, const u8 *mac, 307 u8 aging, u8 type) 308 { 309 u32 reg[3] = { 0 }; 310 int i; 311 312 reg[1] |= vid & CVID_MASK; 313 reg[1] |= ATA2_IVL; 314 reg[1] |= ATA2_FID(FID_BRIDGED); 315 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER; 316 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP; 317 /* STATIC_ENT indicate that entry is static wouldn't 318 * be aged out and STATIC_EMP specified as erasing an 319 * entry 320 */ 321 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS; 322 reg[1] |= mac[5] << MAC_BYTE_5; 323 reg[1] |= mac[4] << MAC_BYTE_4; 324 reg[0] |= mac[3] << MAC_BYTE_3; 325 reg[0] |= mac[2] << MAC_BYTE_2; 326 reg[0] |= mac[1] << MAC_BYTE_1; 327 reg[0] |= mac[0] << MAC_BYTE_0; 328 329 /* Write array into the ARL table */ 330 for (i = 0; i < 3; i++) 331 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]); 332 } 333 334 /* Set up switch core clock for MT7530 */ 335 static void mt7530_pll_setup(struct mt7530_priv *priv) 336 { 337 /* Disable core clock */ 338 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 339 340 /* Disable PLL */ 341 core_write(priv, CORE_GSWPLL_GRP1, 0); 342 343 /* Set core clock into 500Mhz */ 344 core_write(priv, CORE_GSWPLL_GRP2, 345 RG_GSWPLL_POSDIV_500M(1) | 346 RG_GSWPLL_FBKDIV_500M(25)); 347 348 /* Enable PLL */ 349 core_write(priv, CORE_GSWPLL_GRP1, 350 RG_GSWPLL_EN_PRE | 351 RG_GSWPLL_POSDIV_200M(2) | 352 RG_GSWPLL_FBKDIV_200M(32)); 353 354 udelay(20); 355 356 /* Enable core clock */ 357 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 358 } 359 360 /* If port 6 is available as a CPU port, always prefer that as the default, 361 * otherwise don't care. 362 */ 363 static struct dsa_port * 364 mt753x_preferred_default_local_cpu_port(struct dsa_switch *ds) 365 { 366 struct dsa_port *cpu_dp = dsa_to_port(ds, 6); 367 368 if (dsa_port_is_cpu(cpu_dp)) 369 return cpu_dp; 370 371 return NULL; 372 } 373 374 /* Setup port 6 interface mode and TRGMII TX circuit */ 375 static void 376 mt7530_setup_port6(struct dsa_switch *ds, phy_interface_t interface) 377 { 378 struct mt7530_priv *priv = ds->priv; 379 u32 ncpo1, ssc_delta, xtal; 380 381 /* Disable the MT7530 TRGMII clocks */ 382 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); 383 384 if (interface == PHY_INTERFACE_MODE_RGMII) { 385 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, 386 P6_INTF_MODE(0)); 387 return; 388 } 389 390 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, P6_INTF_MODE(1)); 391 392 xtal = mt7530_read(priv, MT753X_MTRAP) & MT7530_XTAL_MASK; 393 394 if (xtal == MT7530_XTAL_25MHZ) 395 ssc_delta = 0x57; 396 else 397 ssc_delta = 0x87; 398 399 if (priv->id == ID_MT7621) { 400 /* PLL frequency: 125MHz: 1.0GBit */ 401 if (xtal == MT7530_XTAL_40MHZ) 402 ncpo1 = 0x0640; 403 if (xtal == MT7530_XTAL_25MHZ) 404 ncpo1 = 0x0a00; 405 } else { /* PLL frequency: 250MHz: 2.0Gbit */ 406 if (xtal == MT7530_XTAL_40MHZ) 407 ncpo1 = 0x0c80; 408 if (xtal == MT7530_XTAL_25MHZ) 409 ncpo1 = 0x1400; 410 } 411 412 /* Setup the MT7530 TRGMII Tx Clock */ 413 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); 414 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); 415 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); 416 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); 417 core_write(priv, CORE_PLL_GROUP4, RG_SYSPLL_DDSFBK_EN | 418 RG_SYSPLL_BIAS_EN | RG_SYSPLL_BIAS_LPF_EN); 419 core_write(priv, CORE_PLL_GROUP2, RG_SYSPLL_EN_NORMAL | 420 RG_SYSPLL_VODEN | RG_SYSPLL_POSDIV(1)); 421 core_write(priv, CORE_PLL_GROUP7, RG_LCDDS_PCW_NCPO_CHG | 422 RG_LCCDS_C(3) | RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); 423 424 /* Enable the MT7530 TRGMII clocks */ 425 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); 426 } 427 428 static void 429 mt7531_pll_setup(struct mt7530_priv *priv) 430 { 431 enum mt7531_xtal_fsel xtal; 432 u32 top_sig; 433 u32 hwstrap; 434 u32 val; 435 436 val = mt7530_read(priv, MT7531_CREV); 437 top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR); 438 hwstrap = mt7530_read(priv, MT753X_TRAP); 439 if ((val & CHIP_REV_M) > 0) 440 xtal = (top_sig & PAD_MCM_SMI_EN) ? MT7531_XTAL_FSEL_40MHZ : 441 MT7531_XTAL_FSEL_25MHZ; 442 else 443 xtal = (hwstrap & MT7531_XTAL25) ? MT7531_XTAL_FSEL_25MHZ : 444 MT7531_XTAL_FSEL_40MHZ; 445 446 /* Step 1 : Disable MT7531 COREPLL */ 447 val = mt7530_read(priv, MT7531_PLLGP_EN); 448 val &= ~EN_COREPLL; 449 mt7530_write(priv, MT7531_PLLGP_EN, val); 450 451 /* Step 2: switch to XTAL output */ 452 val = mt7530_read(priv, MT7531_PLLGP_EN); 453 val |= SW_CLKSW; 454 mt7530_write(priv, MT7531_PLLGP_EN, val); 455 456 val = mt7530_read(priv, MT7531_PLLGP_CR0); 457 val &= ~RG_COREPLL_EN; 458 mt7530_write(priv, MT7531_PLLGP_CR0, val); 459 460 /* Step 3: disable PLLGP and enable program PLLGP */ 461 val = mt7530_read(priv, MT7531_PLLGP_EN); 462 val |= SW_PLLGP; 463 mt7530_write(priv, MT7531_PLLGP_EN, val); 464 465 /* Step 4: program COREPLL output frequency to 500MHz */ 466 val = mt7530_read(priv, MT7531_PLLGP_CR0); 467 val &= ~RG_COREPLL_POSDIV_M; 468 val |= 2 << RG_COREPLL_POSDIV_S; 469 mt7530_write(priv, MT7531_PLLGP_CR0, val); 470 usleep_range(25, 35); 471 472 switch (xtal) { 473 case MT7531_XTAL_FSEL_25MHZ: 474 val = mt7530_read(priv, MT7531_PLLGP_CR0); 475 val &= ~RG_COREPLL_SDM_PCW_M; 476 val |= 0x140000 << RG_COREPLL_SDM_PCW_S; 477 mt7530_write(priv, MT7531_PLLGP_CR0, val); 478 break; 479 case MT7531_XTAL_FSEL_40MHZ: 480 val = mt7530_read(priv, MT7531_PLLGP_CR0); 481 val &= ~RG_COREPLL_SDM_PCW_M; 482 val |= 0x190000 << RG_COREPLL_SDM_PCW_S; 483 mt7530_write(priv, MT7531_PLLGP_CR0, val); 484 break; 485 } 486 487 /* Set feedback divide ratio update signal to high */ 488 val = mt7530_read(priv, MT7531_PLLGP_CR0); 489 val |= RG_COREPLL_SDM_PCW_CHG; 490 mt7530_write(priv, MT7531_PLLGP_CR0, val); 491 /* Wait for at least 16 XTAL clocks */ 492 usleep_range(10, 20); 493 494 /* Step 5: set feedback divide ratio update signal to low */ 495 val = mt7530_read(priv, MT7531_PLLGP_CR0); 496 val &= ~RG_COREPLL_SDM_PCW_CHG; 497 mt7530_write(priv, MT7531_PLLGP_CR0, val); 498 499 /* Enable 325M clock for SGMII */ 500 mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000); 501 502 /* Enable 250SSC clock for RGMII */ 503 mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000); 504 505 /* Step 6: Enable MT7531 PLL */ 506 val = mt7530_read(priv, MT7531_PLLGP_CR0); 507 val |= RG_COREPLL_EN; 508 mt7530_write(priv, MT7531_PLLGP_CR0, val); 509 510 val = mt7530_read(priv, MT7531_PLLGP_EN); 511 val |= EN_COREPLL; 512 mt7530_write(priv, MT7531_PLLGP_EN, val); 513 usleep_range(25, 35); 514 } 515 516 static void 517 mt7530_mib_reset(struct dsa_switch *ds) 518 { 519 struct mt7530_priv *priv = ds->priv; 520 521 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH); 522 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); 523 } 524 525 static int mt7530_phy_read_c22(struct mt7530_priv *priv, int port, int regnum) 526 { 527 return mdiobus_read_nested(priv->bus, port, regnum); 528 } 529 530 static int mt7530_phy_write_c22(struct mt7530_priv *priv, int port, int regnum, 531 u16 val) 532 { 533 return mdiobus_write_nested(priv->bus, port, regnum, val); 534 } 535 536 static int mt7530_phy_read_c45(struct mt7530_priv *priv, int port, 537 int devad, int regnum) 538 { 539 return mdiobus_c45_read_nested(priv->bus, port, devad, regnum); 540 } 541 542 static int mt7530_phy_write_c45(struct mt7530_priv *priv, int port, int devad, 543 int regnum, u16 val) 544 { 545 return mdiobus_c45_write_nested(priv->bus, port, devad, regnum, val); 546 } 547 548 static int 549 mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad, 550 int regnum) 551 { 552 struct mt7530_dummy_poll p; 553 u32 reg, val; 554 int ret; 555 556 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 557 558 mt7530_mutex_lock(priv); 559 560 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 561 !(val & MT7531_PHY_ACS_ST), 20, 100000); 562 if (ret < 0) { 563 dev_err(priv->dev, "poll timeout\n"); 564 goto out; 565 } 566 567 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 568 MT7531_MDIO_DEV_ADDR(devad) | regnum; 569 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 570 571 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 572 !(val & MT7531_PHY_ACS_ST), 20, 100000); 573 if (ret < 0) { 574 dev_err(priv->dev, "poll timeout\n"); 575 goto out; 576 } 577 578 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) | 579 MT7531_MDIO_DEV_ADDR(devad); 580 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 581 582 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 583 !(val & MT7531_PHY_ACS_ST), 20, 100000); 584 if (ret < 0) { 585 dev_err(priv->dev, "poll timeout\n"); 586 goto out; 587 } 588 589 ret = val & MT7531_MDIO_RW_DATA_MASK; 590 out: 591 mt7530_mutex_unlock(priv); 592 593 return ret; 594 } 595 596 static int 597 mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad, 598 int regnum, u16 data) 599 { 600 struct mt7530_dummy_poll p; 601 u32 val, reg; 602 int ret; 603 604 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 605 606 mt7530_mutex_lock(priv); 607 608 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 609 !(val & MT7531_PHY_ACS_ST), 20, 100000); 610 if (ret < 0) { 611 dev_err(priv->dev, "poll timeout\n"); 612 goto out; 613 } 614 615 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 616 MT7531_MDIO_DEV_ADDR(devad) | regnum; 617 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 618 619 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 620 !(val & MT7531_PHY_ACS_ST), 20, 100000); 621 if (ret < 0) { 622 dev_err(priv->dev, "poll timeout\n"); 623 goto out; 624 } 625 626 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) | 627 MT7531_MDIO_DEV_ADDR(devad) | data; 628 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 629 630 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 631 !(val & MT7531_PHY_ACS_ST), 20, 100000); 632 if (ret < 0) { 633 dev_err(priv->dev, "poll timeout\n"); 634 goto out; 635 } 636 637 out: 638 mt7530_mutex_unlock(priv); 639 640 return ret; 641 } 642 643 static int 644 mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum) 645 { 646 struct mt7530_dummy_poll p; 647 int ret; 648 u32 val; 649 650 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 651 652 mt7530_mutex_lock(priv); 653 654 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 655 !(val & MT7531_PHY_ACS_ST), 20, 100000); 656 if (ret < 0) { 657 dev_err(priv->dev, "poll timeout\n"); 658 goto out; 659 } 660 661 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) | 662 MT7531_MDIO_REG_ADDR(regnum); 663 664 mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST); 665 666 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 667 !(val & MT7531_PHY_ACS_ST), 20, 100000); 668 if (ret < 0) { 669 dev_err(priv->dev, "poll timeout\n"); 670 goto out; 671 } 672 673 ret = val & MT7531_MDIO_RW_DATA_MASK; 674 out: 675 mt7530_mutex_unlock(priv); 676 677 return ret; 678 } 679 680 static int 681 mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum, 682 u16 data) 683 { 684 struct mt7530_dummy_poll p; 685 int ret; 686 u32 reg; 687 688 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 689 690 mt7530_mutex_lock(priv); 691 692 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 693 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 694 if (ret < 0) { 695 dev_err(priv->dev, "poll timeout\n"); 696 goto out; 697 } 698 699 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) | 700 MT7531_MDIO_REG_ADDR(regnum) | data; 701 702 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 703 704 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 705 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 706 if (ret < 0) { 707 dev_err(priv->dev, "poll timeout\n"); 708 goto out; 709 } 710 711 out: 712 mt7530_mutex_unlock(priv); 713 714 return ret; 715 } 716 717 static int 718 mt753x_phy_read_c22(struct mii_bus *bus, int port, int regnum) 719 { 720 struct mt7530_priv *priv = bus->priv; 721 722 return priv->info->phy_read_c22(priv, port, regnum); 723 } 724 725 static int 726 mt753x_phy_read_c45(struct mii_bus *bus, int port, int devad, int regnum) 727 { 728 struct mt7530_priv *priv = bus->priv; 729 730 return priv->info->phy_read_c45(priv, port, devad, regnum); 731 } 732 733 static int 734 mt753x_phy_write_c22(struct mii_bus *bus, int port, int regnum, u16 val) 735 { 736 struct mt7530_priv *priv = bus->priv; 737 738 return priv->info->phy_write_c22(priv, port, regnum, val); 739 } 740 741 static int 742 mt753x_phy_write_c45(struct mii_bus *bus, int port, int devad, int regnum, 743 u16 val) 744 { 745 struct mt7530_priv *priv = bus->priv; 746 747 return priv->info->phy_write_c45(priv, port, devad, regnum, val); 748 } 749 750 static void 751 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, 752 uint8_t *data) 753 { 754 int i; 755 756 if (stringset != ETH_SS_STATS) 757 return; 758 759 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) 760 ethtool_puts(&data, mt7530_mib[i].name); 761 } 762 763 static void 764 mt7530_read_port_stats(struct mt7530_priv *priv, int port, 765 u32 offset, u8 size, uint64_t *data) 766 { 767 u32 val, reg = MT7530_PORT_MIB_COUNTER(port) + offset; 768 769 val = mt7530_read(priv, reg); 770 *data = val; 771 772 if (size == 2) { 773 val = mt7530_read(priv, reg + 4); 774 *data |= (u64)val << 32; 775 } 776 } 777 778 static void 779 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, 780 uint64_t *data) 781 { 782 struct mt7530_priv *priv = ds->priv; 783 const struct mt7530_mib_desc *mib; 784 int i; 785 786 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) { 787 mib = &mt7530_mib[i]; 788 789 mt7530_read_port_stats(priv, port, mib->offset, mib->size, 790 data + i); 791 } 792 } 793 794 static int 795 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) 796 { 797 if (sset != ETH_SS_STATS) 798 return 0; 799 800 return ARRAY_SIZE(mt7530_mib); 801 } 802 803 static void mt7530_get_eth_mac_stats(struct dsa_switch *ds, int port, 804 struct ethtool_eth_mac_stats *mac_stats) 805 { 806 struct mt7530_priv *priv = ds->priv; 807 808 /* MIB counter doesn't provide a FramesTransmittedOK but instead 809 * provide stats for Unicast, Broadcast and Multicast frames separately. 810 * To simulate a global frame counter, read Unicast and addition Multicast 811 * and Broadcast later 812 */ 813 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_UNICAST, 1, 814 &mac_stats->FramesTransmittedOK); 815 816 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_SINGLE_COLLISION, 1, 817 &mac_stats->SingleCollisionFrames); 818 819 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_MULTIPLE_COLLISION, 1, 820 &mac_stats->MultipleCollisionFrames); 821 822 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_UNICAST, 1, 823 &mac_stats->FramesReceivedOK); 824 825 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BYTES, 2, 826 &mac_stats->OctetsTransmittedOK); 827 828 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_ALIGN_ERR, 1, 829 &mac_stats->AlignmentErrors); 830 831 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_DEFERRED, 1, 832 &mac_stats->FramesWithDeferredXmissions); 833 834 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_LATE_COLLISION, 1, 835 &mac_stats->LateCollisions); 836 837 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_EXCESSIVE_COLLISION, 1, 838 &mac_stats->FramesAbortedDueToXSColls); 839 840 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BYTES, 2, 841 &mac_stats->OctetsReceivedOK); 842 843 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_MULTICAST, 1, 844 &mac_stats->MulticastFramesXmittedOK); 845 mac_stats->FramesTransmittedOK += mac_stats->MulticastFramesXmittedOK; 846 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BROADCAST, 1, 847 &mac_stats->BroadcastFramesXmittedOK); 848 mac_stats->FramesTransmittedOK += mac_stats->BroadcastFramesXmittedOK; 849 850 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_MULTICAST, 1, 851 &mac_stats->MulticastFramesReceivedOK); 852 mac_stats->FramesReceivedOK += mac_stats->MulticastFramesReceivedOK; 853 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BROADCAST, 1, 854 &mac_stats->BroadcastFramesReceivedOK); 855 mac_stats->FramesReceivedOK += mac_stats->BroadcastFramesReceivedOK; 856 } 857 858 static const struct ethtool_rmon_hist_range mt7530_rmon_ranges[] = { 859 { 0, 64 }, 860 { 65, 127 }, 861 { 128, 255 }, 862 { 256, 511 }, 863 { 512, 1023 }, 864 { 1024, MT7530_MAX_MTU }, 865 {} 866 }; 867 868 static void mt7530_get_rmon_stats(struct dsa_switch *ds, int port, 869 struct ethtool_rmon_stats *rmon_stats, 870 const struct ethtool_rmon_hist_range **ranges) 871 { 872 struct mt7530_priv *priv = ds->priv; 873 874 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_UNDER_SIZE_ERR, 1, 875 &rmon_stats->undersize_pkts); 876 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_OVER_SZ_ERR, 1, 877 &rmon_stats->oversize_pkts); 878 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_FRAG_ERR, 1, 879 &rmon_stats->fragments); 880 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_JABBER_ERR, 1, 881 &rmon_stats->jabbers); 882 883 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_64, 1, 884 &rmon_stats->hist[0]); 885 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_65_TO_127, 1, 886 &rmon_stats->hist[1]); 887 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_128_TO_255, 1, 888 &rmon_stats->hist[2]); 889 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_256_TO_511, 1, 890 &rmon_stats->hist[3]); 891 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_512_TO_1023, 1, 892 &rmon_stats->hist[4]); 893 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_1024_TO_MAX, 1, 894 &rmon_stats->hist[5]); 895 896 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_64, 1, 897 &rmon_stats->hist_tx[0]); 898 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_65_TO_127, 1, 899 &rmon_stats->hist_tx[1]); 900 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_128_TO_255, 1, 901 &rmon_stats->hist_tx[2]); 902 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_256_TO_511, 1, 903 &rmon_stats->hist_tx[3]); 904 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_512_TO_1023, 1, 905 &rmon_stats->hist_tx[4]); 906 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_1024_TO_MAX, 1, 907 &rmon_stats->hist_tx[5]); 908 909 *ranges = mt7530_rmon_ranges; 910 } 911 912 static void mt7530_read_port_stats64(struct mt7530_priv *priv, int port, 913 struct rtnl_link_stats64 *storage) 914 { 915 uint64_t data; 916 917 /* MIB counter doesn't provide a FramesTransmittedOK but instead 918 * provide stats for Unicast, Broadcast and Multicast frames separately. 919 * To simulate a global frame counter, read Unicast and addition Multicast 920 * and Broadcast later 921 */ 922 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_UNICAST, 1, 923 &storage->rx_packets); 924 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_MULTICAST, 1, 925 &storage->multicast); 926 storage->rx_packets += storage->multicast; 927 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BROADCAST, 1, 928 &data); 929 storage->rx_packets += data; 930 931 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_UNICAST, 1, 932 &storage->tx_packets); 933 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_MULTICAST, 1, 934 &data); 935 storage->tx_packets += data; 936 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BROADCAST, 1, 937 &data); 938 storage->tx_packets += data; 939 940 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BYTES, 2, 941 &storage->rx_bytes); 942 943 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BYTES, 2, 944 &storage->tx_bytes); 945 946 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_DROP, 1, 947 &storage->rx_dropped); 948 949 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_DROP, 1, 950 &storage->tx_dropped); 951 952 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_CRC_ERR, 1, 953 &storage->rx_crc_errors); 954 } 955 956 static void mt7530_stats_refresh(struct mt7530_priv *priv) 957 { 958 struct rtnl_link_stats64 stats = {}; 959 struct dsa_port *dp; 960 int port; 961 962 dsa_switch_for_each_user_port(dp, priv->ds) { 963 port = dp->index; 964 965 mt7530_read_port_stats64(priv, port, &stats); 966 967 spin_lock_bh(&priv->stats_lock); 968 priv->ports[port].stats = stats; 969 priv->stats_last = jiffies; 970 spin_unlock_bh(&priv->stats_lock); 971 } 972 } 973 974 static void mt7530_stats_poll(struct work_struct *work) 975 { 976 struct mt7530_priv *priv = container_of(work, struct mt7530_priv, 977 stats_work.work); 978 979 mt7530_stats_refresh(priv); 980 schedule_delayed_work(&priv->stats_work, 981 MT7530_STATS_POLL_INTERVAL); 982 } 983 984 static void mt7530_get_stats64(struct dsa_switch *ds, int port, 985 struct rtnl_link_stats64 *storage) 986 { 987 struct mt7530_priv *priv = ds->priv; 988 bool refresh; 989 990 if (priv->bus) { 991 spin_lock_bh(&priv->stats_lock); 992 *storage = priv->ports[port].stats; 993 refresh = time_after(jiffies, priv->stats_last + 994 MT7530_STATS_RATE_LIMIT); 995 spin_unlock_bh(&priv->stats_lock); 996 if (refresh) 997 mod_delayed_work(system_percpu_wq, 998 &priv->stats_work, 0); 999 } else { 1000 mt7530_read_port_stats64(priv, port, storage); 1001 } 1002 } 1003 1004 static void mt7530_get_eth_ctrl_stats(struct dsa_switch *ds, int port, 1005 struct ethtool_eth_ctrl_stats *ctrl_stats) 1006 { 1007 struct mt7530_priv *priv = ds->priv; 1008 1009 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PAUSE, 1, 1010 &ctrl_stats->MACControlFramesTransmitted); 1011 1012 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PAUSE, 1, 1013 &ctrl_stats->MACControlFramesReceived); 1014 } 1015 1016 static int 1017 mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 1018 { 1019 struct mt7530_priv *priv = ds->priv; 1020 unsigned int secs = msecs / 1000; 1021 unsigned int tmp_age_count; 1022 unsigned int error = -1; 1023 unsigned int age_count; 1024 unsigned int age_unit; 1025 1026 /* Applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds. 1027 * The DSA core has already validated the range using 1028 * ds->ageing_time_min and ds->ageing_time_max. 1029 * 1030 * Iterate through all possible age_count values to find the closest 1031 * pair. Start from 1 because the per-entry aging counter is 1032 * initialized to AGE_CNT and a value of 0 means the entry will 1033 * never be aged out. 1034 */ 1035 for (tmp_age_count = 1; tmp_age_count <= AGE_CNT_MAX; ++tmp_age_count) { 1036 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1; 1037 1038 if (tmp_age_unit <= AGE_UNIT_MAX) { 1039 unsigned int tmp_error = secs - 1040 (tmp_age_count + 1) * (tmp_age_unit + 1); 1041 1042 /* found a closer pair */ 1043 if (error > tmp_error) { 1044 error = tmp_error; 1045 age_count = tmp_age_count; 1046 age_unit = tmp_age_unit; 1047 } 1048 1049 /* found the exact match, so break the loop */ 1050 if (!error) 1051 break; 1052 } 1053 } 1054 1055 mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit)); 1056 1057 return 0; 1058 } 1059 1060 static const char *mt7530_p5_mode_str(unsigned int mode) 1061 { 1062 switch (mode) { 1063 case MUX_PHY_P0: 1064 return "MUX PHY P0"; 1065 case MUX_PHY_P4: 1066 return "MUX PHY P4"; 1067 default: 1068 return "GMAC5"; 1069 } 1070 } 1071 1072 static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) 1073 { 1074 struct mt7530_priv *priv = ds->priv; 1075 u8 tx_delay = 0; 1076 int val; 1077 1078 mutex_lock(&priv->reg_mutex); 1079 1080 val = mt7530_read(priv, MT753X_MTRAP); 1081 1082 val &= ~MT7530_P5_PHY0_SEL & ~MT7530_P5_MAC_SEL & ~MT7530_P5_RGMII_MODE; 1083 1084 switch (priv->p5_mode) { 1085 /* MUX_PHY_P0: P0 -> P5 -> SoC MAC */ 1086 case MUX_PHY_P0: 1087 val |= MT7530_P5_PHY0_SEL; 1088 fallthrough; 1089 1090 /* MUX_PHY_P4: P4 -> P5 -> SoC MAC */ 1091 case MUX_PHY_P4: 1092 /* Setup the MAC by default for the cpu port */ 1093 mt7530_write(priv, MT753X_PMCR_P(5), 0x56300); 1094 break; 1095 1096 /* GMAC5: P5 -> SoC MAC or external PHY */ 1097 default: 1098 val |= MT7530_P5_MAC_SEL; 1099 break; 1100 } 1101 1102 /* Setup RGMII settings */ 1103 if (phy_interface_mode_is_rgmii(interface)) { 1104 val |= MT7530_P5_RGMII_MODE; 1105 1106 /* P5 RGMII RX Clock Control: delay setting for 1000M */ 1107 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN); 1108 1109 /* Don't set delay in DSA mode */ 1110 if (!dsa_is_dsa_port(priv->ds, 5) && 1111 (interface == PHY_INTERFACE_MODE_RGMII_TXID || 1112 interface == PHY_INTERFACE_MODE_RGMII_ID)) 1113 tx_delay = 4; /* n * 0.5 ns */ 1114 1115 /* P5 RGMII TX Clock Control: delay x */ 1116 mt7530_write(priv, MT7530_P5RGMIITXCR, 1117 CSR_RGMII_TXC_CFG(0x10 + tx_delay)); 1118 1119 /* reduce P5 RGMII Tx driving, 8mA */ 1120 mt7530_write(priv, MT7530_IO_DRV_CR, 1121 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); 1122 } 1123 1124 mt7530_write(priv, MT753X_MTRAP, val); 1125 1126 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, mode=%s, phy-mode=%s\n", val, 1127 mt7530_p5_mode_str(priv->p5_mode), phy_modes(interface)); 1128 1129 mutex_unlock(&priv->reg_mutex); 1130 } 1131 1132 /* In Clause 5 of IEEE Std 802-2014, two sublayers of the data link layer (DLL) 1133 * of the Open Systems Interconnection basic reference model (OSI/RM) are 1134 * described; the medium access control (MAC) and logical link control (LLC) 1135 * sublayers. The MAC sublayer is the one facing the physical layer. 1136 * 1137 * In 8.2 of IEEE Std 802.1Q-2022, the Bridge architecture is described. A 1138 * Bridge component comprises a MAC Relay Entity for interconnecting the Ports 1139 * of the Bridge, at least two Ports, and higher layer entities with at least a 1140 * Spanning Tree Protocol Entity included. 1141 * 1142 * Each Bridge Port also functions as an end station and shall provide the MAC 1143 * Service to an LLC Entity. Each instance of the MAC Service is provided to a 1144 * distinct LLC Entity that supports protocol identification, multiplexing, and 1145 * demultiplexing, for protocol data unit (PDU) transmission and reception by 1146 * one or more higher layer entities. 1147 * 1148 * It is described in 8.13.9 of IEEE Std 802.1Q-2022 that in a Bridge, the LLC 1149 * Entity associated with each Bridge Port is modeled as being directly 1150 * connected to the attached Local Area Network (LAN). 1151 * 1152 * On the switch with CPU port architecture, CPU port functions as Management 1153 * Port, and the Management Port functionality is provided by software which 1154 * functions as an end station. Software is connected to an IEEE 802 LAN that is 1155 * wholly contained within the system that incorporates the Bridge. Software 1156 * provides access to the LLC Entity associated with each Bridge Port by the 1157 * value of the source port field on the special tag on the frame received by 1158 * software. 1159 * 1160 * We call frames that carry control information to determine the active 1161 * topology and current extent of each Virtual Local Area Network (VLAN), i.e., 1162 * spanning tree or Shortest Path Bridging (SPB) and Multiple VLAN Registration 1163 * Protocol Data Units (MVRPDUs), and frames from other link constrained 1164 * protocols, such as Extensible Authentication Protocol over LAN (EAPOL) and 1165 * Link Layer Discovery Protocol (LLDP), link-local frames. They are not 1166 * forwarded by a Bridge. Permanently configured entries in the filtering 1167 * database (FDB) ensure that such frames are discarded by the Forwarding 1168 * Process. In 8.6.3 of IEEE Std 802.1Q-2022, this is described in detail: 1169 * 1170 * Each of the reserved MAC addresses specified in Table 8-1 1171 * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]) shall be 1172 * permanently configured in the FDB in C-VLAN components and ERs. 1173 * 1174 * Each of the reserved MAC addresses specified in Table 8-2 1175 * (01-80-C2-00-00-[01,02,03,04,05,06,07,08,09,0A,0E]) shall be permanently 1176 * configured in the FDB in S-VLAN components. 1177 * 1178 * Each of the reserved MAC addresses specified in Table 8-3 1179 * (01-80-C2-00-00-[01,02,04,0E]) shall be permanently configured in the FDB in 1180 * TPMR components. 1181 * 1182 * The FDB entries for reserved MAC addresses shall specify filtering for all 1183 * Bridge Ports and all VIDs. Management shall not provide the capability to 1184 * modify or remove entries for reserved MAC addresses. 1185 * 1186 * The addresses in Table 8-1, Table 8-2, and Table 8-3 determine the scope of 1187 * propagation of PDUs within a Bridged Network, as follows: 1188 * 1189 * The Nearest Bridge group address (01-80-C2-00-00-0E) is an address that no 1190 * conformant Two-Port MAC Relay (TPMR) component, Service VLAN (S-VLAN) 1191 * component, Customer VLAN (C-VLAN) component, or MAC Bridge can forward. 1192 * PDUs transmitted using this destination address, or any other addresses 1193 * that appear in Table 8-1, Table 8-2, and Table 8-3 1194 * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]), can 1195 * therefore travel no further than those stations that can be reached via a 1196 * single individual LAN from the originating station. 1197 * 1198 * The Nearest non-TPMR Bridge group address (01-80-C2-00-00-03), is an 1199 * address that no conformant S-VLAN component, C-VLAN component, or MAC 1200 * Bridge can forward; however, this address is relayed by a TPMR component. 1201 * PDUs using this destination address, or any of the other addresses that 1202 * appear in both Table 8-1 and Table 8-2 but not in Table 8-3 1203 * (01-80-C2-00-00-[00,03,05,06,07,08,09,0A,0B,0C,0D,0F]), will be relayed by 1204 * any TPMRs but will propagate no further than the nearest S-VLAN component, 1205 * C-VLAN component, or MAC Bridge. 1206 * 1207 * The Nearest Customer Bridge group address (01-80-C2-00-00-00) is an address 1208 * that no conformant C-VLAN component, MAC Bridge can forward; however, it is 1209 * relayed by TPMR components and S-VLAN components. PDUs using this 1210 * destination address, or any of the other addresses that appear in Table 8-1 1211 * but not in either Table 8-2 or Table 8-3 (01-80-C2-00-00-[00,0B,0C,0D,0F]), 1212 * will be relayed by TPMR components and S-VLAN components but will propagate 1213 * no further than the nearest C-VLAN component or MAC Bridge. 1214 * 1215 * Because the LLC Entity associated with each Bridge Port is provided via CPU 1216 * port, we must not filter these frames but forward them to CPU port. 1217 * 1218 * In a Bridge, the transmission Port is majorly decided by ingress and egress 1219 * rules, FDB, and spanning tree Port State functions of the Forwarding Process. 1220 * For link-local frames, only CPU port should be designated as destination port 1221 * in the FDB, and the other functions of the Forwarding Process must not 1222 * interfere with the decision of the transmission Port. We call this process 1223 * trapping frames to CPU port. 1224 * 1225 * Therefore, on the switch with CPU port architecture, link-local frames must 1226 * be trapped to CPU port, and certain link-local frames received by a Port of a 1227 * Bridge comprising a TPMR component or an S-VLAN component must be excluded 1228 * from it. 1229 * 1230 * A Bridge of the switch with CPU port architecture cannot comprise a Two-Port 1231 * MAC Relay (TPMR) component as a TPMR component supports only a subset of the 1232 * functionality of a MAC Bridge. A Bridge comprising two Ports (Management Port 1233 * doesn't count) of this architecture will either function as a standard MAC 1234 * Bridge or a standard VLAN Bridge. 1235 * 1236 * Therefore, a Bridge of this architecture can only comprise S-VLAN components, 1237 * C-VLAN components, or MAC Bridge components. Since there's no TPMR component, 1238 * we don't need to relay PDUs using the destination addresses specified on the 1239 * Nearest non-TPMR section, and the proportion of the Nearest Customer Bridge 1240 * section where they must be relayed by TPMR components. 1241 * 1242 * One option to trap link-local frames to CPU port is to add static FDB entries 1243 * with CPU port designated as destination port. However, because that 1244 * Independent VLAN Learning (IVL) is being used on every VID, each entry only 1245 * applies to a single VLAN Identifier (VID). For a Bridge comprising a MAC 1246 * Bridge component or a C-VLAN component, there would have to be 16 times 4096 1247 * entries. This switch intellectual property can only hold a maximum of 2048 1248 * entries. Using this option, there also isn't a mechanism to prevent 1249 * link-local frames from being discarded when the spanning tree Port State of 1250 * the reception Port is discarding. 1251 * 1252 * The remaining option is to utilise the BPC, RGAC1, RGAC2, RGAC3, and RGAC4 1253 * registers. Whilst this applies to every VID, it doesn't contain all of the 1254 * reserved MAC addresses without affecting the remaining Standard Group MAC 1255 * Addresses. The REV_UN frame tag utilised using the RGAC4 register covers the 1256 * remaining 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] destination 1257 * addresses. It also includes the 01-80-C2-00-00-22 to 01-80-C2-00-00-FF 1258 * destination addresses which may be relayed by MAC Bridges or VLAN Bridges. 1259 * The latter option provides better but not complete conformance. 1260 * 1261 * This switch intellectual property also does not provide a mechanism to trap 1262 * link-local frames with specific destination addresses to CPU port by Bridge, 1263 * to conform to the filtering rules for the distinct Bridge components. 1264 * 1265 * Therefore, regardless of the type of the Bridge component, link-local frames 1266 * with these destination addresses will be trapped to CPU port: 1267 * 1268 * 01-80-C2-00-00-[00,01,02,03,0E] 1269 * 1270 * In a Bridge comprising a MAC Bridge component or a C-VLAN component: 1271 * 1272 * Link-local frames with these destination addresses won't be trapped to CPU 1273 * port which won't conform to IEEE Std 802.1Q-2022: 1274 * 1275 * 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] 1276 * 1277 * In a Bridge comprising an S-VLAN component: 1278 * 1279 * Link-local frames with these destination addresses will be trapped to CPU 1280 * port which won't conform to IEEE Std 802.1Q-2022: 1281 * 1282 * 01-80-C2-00-00-00 1283 * 1284 * Link-local frames with these destination addresses won't be trapped to CPU 1285 * port which won't conform to IEEE Std 802.1Q-2022: 1286 * 1287 * 01-80-C2-00-00-[04,05,06,07,08,09,0A] 1288 * 1289 * To trap link-local frames to CPU port as conformant as this switch 1290 * intellectual property can allow, link-local frames are made to be regarded as 1291 * Bridge Protocol Data Units (BPDUs). This is because this switch intellectual 1292 * property only lets the frames regarded as BPDUs bypass the spanning tree Port 1293 * State function of the Forwarding Process. 1294 * 1295 * The only remaining interference is the ingress rules. When the reception Port 1296 * has no PVID assigned on software, VLAN-untagged frames won't be allowed in. 1297 * There doesn't seem to be a mechanism on the switch intellectual property to 1298 * have link-local frames bypass this function of the Forwarding Process. 1299 */ 1300 static void 1301 mt753x_trap_frames(struct mt7530_priv *priv) 1302 { 1303 /* Trap 802.1X PAE frames and BPDUs to the CPU port(s) and egress 1304 * them with the EG_TAG attribute set to disabled (system default) 1305 * so that any VLAN tags in the frame are not modified by the 1306 * switch egress VLAN tag processing. This preserves VLAN tags 1307 * for reception on VLAN sub-interfaces. 1308 */ 1309 mt7530_rmw(priv, MT753X_BPC, 1310 PAE_BPDU_FR | PAE_EG_TAG_MASK | PAE_PORT_FW_MASK | 1311 BPDU_EG_TAG_MASK | BPDU_PORT_FW_MASK, 1312 PAE_BPDU_FR | PAE_EG_TAG(MT7530_VLAN_EG_DISABLED) | 1313 PAE_PORT_FW(TO_CPU_FW_CPU_ONLY) | 1314 BPDU_EG_TAG(MT7530_VLAN_EG_DISABLED) | 1315 TO_CPU_FW_CPU_ONLY); 1316 1317 /* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and 1318 * egress them with EG_TAG disabled. 1319 */ 1320 mt7530_rmw(priv, MT753X_RGAC1, 1321 R02_BPDU_FR | R02_EG_TAG_MASK | R02_PORT_FW_MASK | 1322 R01_BPDU_FR | R01_EG_TAG_MASK | R01_PORT_FW_MASK, 1323 R02_BPDU_FR | R02_EG_TAG(MT7530_VLAN_EG_DISABLED) | 1324 R02_PORT_FW(TO_CPU_FW_CPU_ONLY) | R01_BPDU_FR | 1325 R01_EG_TAG(MT7530_VLAN_EG_DISABLED) | 1326 TO_CPU_FW_CPU_ONLY); 1327 1328 /* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and 1329 * egress them with EG_TAG disabled. 1330 */ 1331 mt7530_rmw(priv, MT753X_RGAC2, 1332 R0E_BPDU_FR | R0E_EG_TAG_MASK | R0E_PORT_FW_MASK | 1333 R03_BPDU_FR | R03_EG_TAG_MASK | R03_PORT_FW_MASK, 1334 R0E_BPDU_FR | R0E_EG_TAG(MT7530_VLAN_EG_DISABLED) | 1335 R0E_PORT_FW(TO_CPU_FW_CPU_ONLY) | R03_BPDU_FR | 1336 R03_EG_TAG(MT7530_VLAN_EG_DISABLED) | 1337 TO_CPU_FW_CPU_ONLY); 1338 } 1339 1340 static void 1341 mt753x_cpu_port_enable(struct dsa_switch *ds, int port) 1342 { 1343 struct mt7530_priv *priv = ds->priv; 1344 1345 /* Enable Mediatek header mode on the cpu port */ 1346 mt7530_write(priv, MT7530_PVC_P(port), 1347 PORT_SPEC_TAG); 1348 1349 /* Enable flooding on the CPU port */ 1350 mt7530_set(priv, MT753X_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | 1351 UNU_FFP(BIT(port))); 1352 1353 /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on 1354 * the MT7988 SoC. Trapped frames will be forwarded to the CPU port that 1355 * is affine to the inbound user port. 1356 */ 1357 if (priv->id == ID_MT7531 || priv->id == ID_MT7988 || 1358 priv->id == ID_EN7581 || priv->id == ID_AN7583) 1359 mt7530_set(priv, MT7531_CFC, MT7531_CPU_PMAP(BIT(port))); 1360 1361 /* CPU port gets connected to all user ports of 1362 * the switch. 1363 */ 1364 mt7530_write(priv, MT7530_PCR_P(port), 1365 PCR_MATRIX(dsa_user_ports(priv->ds))); 1366 1367 /* Set to fallback mode for independent VLAN learning */ 1368 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1369 MT7530_PORT_FALLBACK_MODE); 1370 } 1371 1372 static int 1373 mt7530_port_enable(struct dsa_switch *ds, int port, 1374 struct phy_device *phy) 1375 { 1376 struct dsa_port *dp = dsa_to_port(ds, port); 1377 struct mt7530_priv *priv = ds->priv; 1378 1379 mutex_lock(&priv->reg_mutex); 1380 1381 /* Allow the user port gets connected to the cpu port and also 1382 * restore the port matrix if the port is the member of a certain 1383 * bridge. 1384 */ 1385 if (dsa_port_is_user(dp)) { 1386 struct dsa_port *cpu_dp = dp->cpu_dp; 1387 1388 priv->ports[port].pm |= PCR_MATRIX(BIT(cpu_dp->index)); 1389 } 1390 priv->ports[port].enable = true; 1391 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1392 priv->ports[port].pm); 1393 1394 mutex_unlock(&priv->reg_mutex); 1395 1396 if (priv->id != ID_MT7530 && priv->id != ID_MT7621) 1397 return 0; 1398 1399 if (port == 5) 1400 mt7530_clear(priv, MT753X_MTRAP, MT7530_P5_DIS); 1401 else if (port == 6) 1402 mt7530_clear(priv, MT753X_MTRAP, MT7530_P6_DIS); 1403 1404 return 0; 1405 } 1406 1407 static void 1408 mt7530_port_disable(struct dsa_switch *ds, int port) 1409 { 1410 struct mt7530_priv *priv = ds->priv; 1411 1412 mutex_lock(&priv->reg_mutex); 1413 1414 /* Clear up all port matrix which could be restored in the next 1415 * enablement for the port. 1416 */ 1417 priv->ports[port].enable = false; 1418 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1419 PCR_MATRIX_CLR); 1420 1421 mutex_unlock(&priv->reg_mutex); 1422 1423 if (priv->id != ID_MT7530 && priv->id != ID_MT7621) 1424 return; 1425 1426 /* Do not set MT7530_P5_DIS when port 5 is being used for PHY muxing. */ 1427 if (port == 5 && priv->p5_mode == GMAC5) 1428 mt7530_set(priv, MT753X_MTRAP, MT7530_P5_DIS); 1429 else if (port == 6) 1430 mt7530_set(priv, MT753X_MTRAP, MT7530_P6_DIS); 1431 } 1432 1433 static int 1434 mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1435 { 1436 struct mt7530_priv *priv = ds->priv; 1437 int length; 1438 u32 val; 1439 1440 /* When a new MTU is set, DSA always set the CPU port's MTU to the 1441 * largest MTU of the user ports. Because the switch only has a global 1442 * RX length register, only allowing CPU port here is enough. 1443 */ 1444 if (!dsa_is_cpu_port(ds, port)) 1445 return 0; 1446 1447 mt7530_mutex_lock(priv); 1448 1449 val = mt7530_mii_read(priv, MT7530_GMACCR); 1450 val &= ~MAX_RX_PKT_LEN_MASK; 1451 1452 /* RX length also includes Ethernet header, MTK tag, and FCS length */ 1453 length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN; 1454 if (length <= 1522) { 1455 val |= MAX_RX_PKT_LEN_1522; 1456 } else if (length <= 1536) { 1457 val |= MAX_RX_PKT_LEN_1536; 1458 } else if (length <= 1552) { 1459 val |= MAX_RX_PKT_LEN_1552; 1460 } else { 1461 val &= ~MAX_RX_JUMBO_MASK; 1462 val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024)); 1463 val |= MAX_RX_PKT_LEN_JUMBO; 1464 } 1465 1466 mt7530_mii_write(priv, MT7530_GMACCR, val); 1467 1468 mt7530_mutex_unlock(priv); 1469 1470 return 0; 1471 } 1472 1473 static int 1474 mt7530_port_max_mtu(struct dsa_switch *ds, int port) 1475 { 1476 return MT7530_MAX_MTU; 1477 } 1478 1479 static void 1480 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1481 { 1482 struct mt7530_priv *priv = ds->priv; 1483 u32 stp_state; 1484 1485 switch (state) { 1486 case BR_STATE_DISABLED: 1487 stp_state = MT7530_STP_DISABLED; 1488 break; 1489 case BR_STATE_BLOCKING: 1490 stp_state = MT7530_STP_BLOCKING; 1491 break; 1492 case BR_STATE_LISTENING: 1493 stp_state = MT7530_STP_LISTENING; 1494 break; 1495 case BR_STATE_LEARNING: 1496 stp_state = MT7530_STP_LEARNING; 1497 break; 1498 case BR_STATE_FORWARDING: 1499 default: 1500 stp_state = MT7530_STP_FORWARDING; 1501 break; 1502 } 1503 1504 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK(FID_BRIDGED), 1505 FID_PST(FID_BRIDGED, stp_state)); 1506 } 1507 1508 static void mt7530_update_port_member(struct mt7530_priv *priv, int port, 1509 const struct net_device *bridge_dev, 1510 bool join) __must_hold(&priv->reg_mutex) 1511 { 1512 struct dsa_port *dp = dsa_to_port(priv->ds, port), *other_dp; 1513 struct mt7530_port *p = &priv->ports[port], *other_p; 1514 struct dsa_port *cpu_dp = dp->cpu_dp; 1515 u32 port_bitmap = BIT(cpu_dp->index); 1516 int other_port; 1517 bool isolated; 1518 1519 dsa_switch_for_each_user_port(other_dp, priv->ds) { 1520 other_port = other_dp->index; 1521 other_p = &priv->ports[other_port]; 1522 1523 if (dp == other_dp) 1524 continue; 1525 1526 /* Add/remove this port to/from the port matrix of the other 1527 * ports in the same bridge. If the port is disabled, port 1528 * matrix is kept and not being setup until the port becomes 1529 * enabled. 1530 */ 1531 if (!dsa_port_offloads_bridge_dev(other_dp, bridge_dev)) 1532 continue; 1533 1534 isolated = p->isolated && other_p->isolated; 1535 1536 if (join && !isolated) { 1537 other_p->pm |= PCR_MATRIX(BIT(port)); 1538 port_bitmap |= BIT(other_port); 1539 } else { 1540 other_p->pm &= ~PCR_MATRIX(BIT(port)); 1541 } 1542 1543 if (other_p->enable) 1544 mt7530_rmw(priv, MT7530_PCR_P(other_port), 1545 PCR_MATRIX_MASK, other_p->pm); 1546 } 1547 1548 /* Add/remove the all other ports to this port matrix. For !join 1549 * (leaving the bridge), only the CPU port will remain in the port matrix 1550 * of this port. 1551 */ 1552 p->pm = PCR_MATRIX(port_bitmap); 1553 if (priv->ports[port].enable) 1554 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, p->pm); 1555 } 1556 1557 static int 1558 mt7530_port_pre_bridge_flags(struct dsa_switch *ds, int port, 1559 struct switchdev_brport_flags flags, 1560 struct netlink_ext_ack *extack) 1561 { 1562 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 1563 BR_BCAST_FLOOD | BR_ISOLATED)) 1564 return -EINVAL; 1565 1566 return 0; 1567 } 1568 1569 static int 1570 mt7530_port_bridge_flags(struct dsa_switch *ds, int port, 1571 struct switchdev_brport_flags flags, 1572 struct netlink_ext_ack *extack) 1573 { 1574 struct mt7530_priv *priv = ds->priv; 1575 1576 if (flags.mask & BR_LEARNING) 1577 mt7530_rmw(priv, MT7530_PSC_P(port), SA_DIS, 1578 flags.val & BR_LEARNING ? 0 : SA_DIS); 1579 1580 if (flags.mask & BR_FLOOD) 1581 mt7530_rmw(priv, MT753X_MFC, UNU_FFP(BIT(port)), 1582 flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0); 1583 1584 if (flags.mask & BR_MCAST_FLOOD) 1585 mt7530_rmw(priv, MT753X_MFC, UNM_FFP(BIT(port)), 1586 flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0); 1587 1588 if (flags.mask & BR_BCAST_FLOOD) 1589 mt7530_rmw(priv, MT753X_MFC, BC_FFP(BIT(port)), 1590 flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0); 1591 1592 if (flags.mask & BR_ISOLATED) { 1593 struct dsa_port *dp = dsa_to_port(ds, port); 1594 struct net_device *bridge_dev = dsa_port_bridge_dev_get(dp); 1595 1596 priv->ports[port].isolated = !!(flags.val & BR_ISOLATED); 1597 1598 mutex_lock(&priv->reg_mutex); 1599 mt7530_update_port_member(priv, port, bridge_dev, true); 1600 mutex_unlock(&priv->reg_mutex); 1601 } 1602 1603 return 0; 1604 } 1605 1606 static int 1607 mt7530_port_bridge_join(struct dsa_switch *ds, int port, 1608 struct dsa_bridge bridge, bool *tx_fwd_offload, 1609 struct netlink_ext_ack *extack) 1610 { 1611 struct mt7530_priv *priv = ds->priv; 1612 1613 mutex_lock(&priv->reg_mutex); 1614 1615 mt7530_update_port_member(priv, port, bridge.dev, true); 1616 1617 /* Set to fallback mode for independent VLAN learning */ 1618 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1619 MT7530_PORT_FALLBACK_MODE); 1620 1621 mutex_unlock(&priv->reg_mutex); 1622 1623 return 0; 1624 } 1625 1626 static int 1627 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid) 1628 { 1629 struct mt7530_dummy_poll p; 1630 u32 val; 1631 int ret; 1632 1633 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid; 1634 mt7530_write(priv, MT7530_VTCR, val); 1635 1636 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR); 1637 ret = readx_poll_timeout(_mt7530_read, &p, val, 1638 !(val & VTCR_BUSY), 20, 20000); 1639 if (ret < 0) { 1640 dev_err(priv->dev, "poll timeout\n"); 1641 return ret; 1642 } 1643 1644 val = mt7530_read(priv, MT7530_VTCR); 1645 if (val & VTCR_INVALID) { 1646 dev_err(priv->dev, "read VTCR invalid\n"); 1647 return -EINVAL; 1648 } 1649 1650 return 0; 1651 } 1652 1653 static int 1654 mt7530_setup_vlan0(struct mt7530_priv *priv) 1655 { 1656 u32 val; 1657 1658 /* Validate the entry with independent learning, keep the original 1659 * ingress tag attribute. 1660 */ 1661 val = IVL_MAC | EG_CON | PORT_MEM(MT7530_ALL_MEMBERS) | FID(FID_BRIDGED) | 1662 VLAN_VALID; 1663 mt7530_write(priv, MT7530_VAWD1, val); 1664 mt7530_write(priv, MT7530_VAWD2, 0); 1665 1666 return mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, 0); 1667 } 1668 1669 static void 1670 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) 1671 { 1672 struct mt7530_priv *priv = ds->priv; 1673 bool all_user_ports_removed = true; 1674 int i; 1675 1676 /* This is called after .port_bridge_leave when leaving a VLAN-aware 1677 * bridge. Don't set standalone ports to fallback mode. 1678 */ 1679 if (dsa_port_bridge_dev_get(dsa_to_port(ds, port))) 1680 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1681 MT7530_PORT_FALLBACK_MODE); 1682 1683 mt7530_rmw(priv, MT7530_PVC_P(port), 1684 VLAN_ATTR_MASK | PVC_EG_TAG_MASK | ACC_FRM_MASK, 1685 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) | 1686 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT) | 1687 MT7530_VLAN_ACC_ALL); 1688 1689 /* Set PVID to 0 */ 1690 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1691 G0_PORT_VID_DEF); 1692 1693 for (i = 0; i < priv->ds->num_ports; i++) { 1694 if (i == port) 1695 continue; 1696 if (dsa_is_user_port(ds, i) && 1697 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { 1698 all_user_ports_removed = false; 1699 break; 1700 } 1701 } 1702 1703 /* CPU port also does the same thing until all user ports belonging to 1704 * the CPU port get out of VLAN filtering mode. 1705 */ 1706 if (all_user_ports_removed) { 1707 mutex_lock(&priv->reg_mutex); 1708 mt7530_setup_vlan0(priv); 1709 mutex_unlock(&priv->reg_mutex); 1710 } 1711 } 1712 1713 static void 1714 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port) 1715 { 1716 struct mt7530_priv *priv = ds->priv; 1717 1718 /* Trapped into security mode allows packet forwarding through VLAN 1719 * table lookup. 1720 */ 1721 if (dsa_is_user_port(ds, port)) { 1722 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1723 MT7530_PORT_SECURITY_MODE); 1724 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1725 G0_PORT_VID(priv->ports[port].pvid)); 1726 1727 /* Only accept tagged frames if PVID is not set */ 1728 if (!priv->ports[port].pvid) 1729 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1730 MT7530_VLAN_ACC_TAGGED); 1731 1732 /* Set the port as a user port which is to be able to recognize 1733 * VID from incoming packets before fetching entry within the 1734 * VLAN table. 1735 */ 1736 mt7530_rmw(priv, MT7530_PVC_P(port), 1737 VLAN_ATTR_MASK | PVC_EG_TAG_MASK, 1738 VLAN_ATTR(MT7530_VLAN_USER) | 1739 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED)); 1740 } else { 1741 /* Also set CPU ports to the "user" VLAN port attribute, to 1742 * allow VLAN classification, but keep the EG_TAG attribute as 1743 * "consistent" (i.o.w. don't change its value) for packets 1744 * received by the switch from the CPU, so that tagged packets 1745 * are forwarded to user ports as tagged, and untagged as 1746 * untagged. 1747 */ 1748 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK, 1749 VLAN_ATTR(MT7530_VLAN_USER)); 1750 } 1751 } 1752 1753 static void 1754 mt7530_port_bridge_leave(struct dsa_switch *ds, int port, 1755 struct dsa_bridge bridge) 1756 { 1757 struct mt7530_priv *priv = ds->priv; 1758 1759 mutex_lock(&priv->reg_mutex); 1760 1761 mt7530_update_port_member(priv, port, bridge.dev, false); 1762 1763 /* When a port is removed from the bridge, the port would be set up 1764 * back to the default as is at initial boot which is a VLAN-unaware 1765 * port. 1766 */ 1767 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1768 MT7530_PORT_MATRIX_MODE); 1769 1770 mutex_unlock(&priv->reg_mutex); 1771 } 1772 1773 static int 1774 mt7530_port_fdb_add(struct dsa_switch *ds, int port, 1775 const unsigned char *addr, u16 vid, 1776 struct dsa_db db) 1777 { 1778 struct mt7530_priv *priv = ds->priv; 1779 int ret; 1780 u8 port_mask = BIT(port); 1781 1782 mutex_lock(&priv->reg_mutex); 1783 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1784 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1785 mutex_unlock(&priv->reg_mutex); 1786 1787 return ret; 1788 } 1789 1790 static int 1791 mt7530_port_fdb_del(struct dsa_switch *ds, int port, 1792 const unsigned char *addr, u16 vid, 1793 struct dsa_db db) 1794 { 1795 struct mt7530_priv *priv = ds->priv; 1796 int ret; 1797 u8 port_mask = BIT(port); 1798 1799 mutex_lock(&priv->reg_mutex); 1800 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); 1801 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1802 mutex_unlock(&priv->reg_mutex); 1803 1804 return ret; 1805 } 1806 1807 static int 1808 mt7530_port_fdb_dump(struct dsa_switch *ds, int port, 1809 dsa_fdb_dump_cb_t *cb, void *data) 1810 { 1811 struct mt7530_priv *priv = ds->priv; 1812 struct mt7530_fdb _fdb = { 0 }; 1813 int cnt = MT7530_NUM_FDB_RECORDS; 1814 int ret = 0; 1815 u32 rsp = 0; 1816 1817 mutex_lock(&priv->reg_mutex); 1818 1819 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp); 1820 if (ret < 0) 1821 goto err; 1822 1823 do { 1824 if (rsp & ATC_SRCH_HIT) { 1825 mt7530_fdb_read(priv, &_fdb); 1826 if (_fdb.port_mask & BIT(port)) { 1827 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, 1828 data); 1829 if (ret < 0) 1830 break; 1831 } 1832 } 1833 } while (--cnt && 1834 !(rsp & ATC_SRCH_END) && 1835 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp)); 1836 err: 1837 mutex_unlock(&priv->reg_mutex); 1838 1839 return 0; 1840 } 1841 1842 static int 1843 mt7530_port_mdb_add(struct dsa_switch *ds, int port, 1844 const struct switchdev_obj_port_mdb *mdb, 1845 struct dsa_db db) 1846 { 1847 struct mt7530_priv *priv = ds->priv; 1848 const u8 *addr = mdb->addr; 1849 u16 vid = mdb->vid; 1850 u8 port_mask = 0; 1851 int ret; 1852 1853 mutex_lock(&priv->reg_mutex); 1854 1855 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1856 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1857 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1858 & PORT_MAP_MASK; 1859 1860 port_mask |= BIT(port); 1861 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1862 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1863 1864 mutex_unlock(&priv->reg_mutex); 1865 1866 return ret; 1867 } 1868 1869 static int 1870 mt7530_port_mdb_del(struct dsa_switch *ds, int port, 1871 const struct switchdev_obj_port_mdb *mdb, 1872 struct dsa_db db) 1873 { 1874 struct mt7530_priv *priv = ds->priv; 1875 const u8 *addr = mdb->addr; 1876 u16 vid = mdb->vid; 1877 u8 port_mask = 0; 1878 int ret; 1879 1880 mutex_lock(&priv->reg_mutex); 1881 1882 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1883 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1884 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1885 & PORT_MAP_MASK; 1886 1887 port_mask &= ~BIT(port); 1888 mt7530_fdb_write(priv, vid, port_mask, addr, -1, 1889 port_mask ? STATIC_ENT : STATIC_EMP); 1890 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1891 1892 mutex_unlock(&priv->reg_mutex); 1893 1894 return ret; 1895 } 1896 1897 static int 1898 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, 1899 struct netlink_ext_ack *extack) 1900 { 1901 struct dsa_port *dp = dsa_to_port(ds, port); 1902 struct dsa_port *cpu_dp = dp->cpu_dp; 1903 1904 if (vlan_filtering) { 1905 /* The port is being kept as VLAN-unaware port when bridge is 1906 * set up with vlan_filtering not being set, Otherwise, the 1907 * port and the corresponding CPU port is required the setup 1908 * for becoming a VLAN-aware port. 1909 */ 1910 mt7530_port_set_vlan_aware(ds, port); 1911 mt7530_port_set_vlan_aware(ds, cpu_dp->index); 1912 } else { 1913 mt7530_port_set_vlan_unaware(ds, port); 1914 } 1915 1916 return 0; 1917 } 1918 1919 static void 1920 mt7530_hw_vlan_add(struct mt7530_priv *priv, 1921 struct mt7530_hw_vlan_entry *entry) 1922 { 1923 struct dsa_port *dp = dsa_to_port(priv->ds, entry->port); 1924 u8 new_members; 1925 u32 val; 1926 1927 new_members = entry->old_members | BIT(entry->port); 1928 1929 /* Validate the entry with independent learning, create egress tag per 1930 * VLAN and joining the port as one of the port members. 1931 */ 1932 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | FID(FID_BRIDGED) | 1933 VLAN_VALID; 1934 mt7530_write(priv, MT7530_VAWD1, val); 1935 1936 /* Decide whether adding tag or not for those outgoing packets from the 1937 * port inside the VLAN. 1938 * CPU port is always taken as a tagged port for serving more than one 1939 * VLANs across and also being applied with egress type stack mode for 1940 * that VLAN tags would be appended after hardware special tag used as 1941 * DSA tag. 1942 */ 1943 if (dsa_port_is_cpu(dp)) 1944 val = MT7530_VLAN_EGRESS_STACK; 1945 else if (entry->untagged) 1946 val = MT7530_VLAN_EGRESS_UNTAG; 1947 else 1948 val = MT7530_VLAN_EGRESS_TAG; 1949 mt7530_rmw(priv, MT7530_VAWD2, 1950 ETAG_CTRL_P_MASK(entry->port), 1951 ETAG_CTRL_P(entry->port, val)); 1952 } 1953 1954 static void 1955 mt7530_hw_vlan_del(struct mt7530_priv *priv, 1956 struct mt7530_hw_vlan_entry *entry) 1957 { 1958 u8 new_members; 1959 u32 val; 1960 1961 new_members = entry->old_members & ~BIT(entry->port); 1962 1963 val = mt7530_read(priv, MT7530_VAWD1); 1964 if (!(val & VLAN_VALID)) { 1965 dev_err(priv->dev, 1966 "Cannot be deleted due to invalid entry\n"); 1967 return; 1968 } 1969 1970 if (new_members) { 1971 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | 1972 VLAN_VALID; 1973 mt7530_write(priv, MT7530_VAWD1, val); 1974 } else { 1975 mt7530_write(priv, MT7530_VAWD1, 0); 1976 mt7530_write(priv, MT7530_VAWD2, 0); 1977 } 1978 } 1979 1980 static void 1981 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid, 1982 struct mt7530_hw_vlan_entry *entry, 1983 mt7530_vlan_op vlan_op) 1984 { 1985 u32 val; 1986 1987 /* Fetch entry */ 1988 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid); 1989 1990 val = mt7530_read(priv, MT7530_VAWD1); 1991 1992 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; 1993 1994 /* Manipulate entry */ 1995 vlan_op(priv, entry); 1996 1997 /* Flush result to hardware */ 1998 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid); 1999 } 2000 2001 static int 2002 mt7530_port_vlan_add(struct dsa_switch *ds, int port, 2003 const struct switchdev_obj_port_vlan *vlan, 2004 struct netlink_ext_ack *extack) 2005 { 2006 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 2007 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 2008 struct mt7530_hw_vlan_entry new_entry; 2009 struct mt7530_priv *priv = ds->priv; 2010 2011 mutex_lock(&priv->reg_mutex); 2012 2013 /* VID 0 is managed exclusively by mt7530_setup_vlan0() for 2014 * VLAN-unaware bridge operation. Don't let the bridge overwrite 2015 * its EG_CON flag with VTAG_EN and corrupt PORT_MEM. 2016 */ 2017 if (vlan->vid == 0) 2018 goto skip_vlan_table; 2019 2020 mt7530_hw_vlan_entry_init(&new_entry, port, untagged); 2021 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add); 2022 2023 skip_vlan_table: 2024 2025 if (pvid) { 2026 priv->ports[port].pvid = vlan->vid; 2027 2028 /* Accept all frames if PVID is set */ 2029 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 2030 MT7530_VLAN_ACC_ALL); 2031 2032 /* Only configure PVID if VLAN filtering is enabled */ 2033 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 2034 mt7530_rmw(priv, MT7530_PPBV1_P(port), 2035 G0_PORT_VID_MASK, 2036 G0_PORT_VID(vlan->vid)); 2037 } else if (vlan->vid && priv->ports[port].pvid == vlan->vid) { 2038 /* This VLAN is overwritten without PVID, so unset it */ 2039 priv->ports[port].pvid = G0_PORT_VID_DEF; 2040 2041 /* Only accept tagged frames if the port is VLAN-aware */ 2042 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 2043 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 2044 MT7530_VLAN_ACC_TAGGED); 2045 2046 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 2047 G0_PORT_VID_DEF); 2048 } 2049 2050 mutex_unlock(&priv->reg_mutex); 2051 2052 return 0; 2053 } 2054 2055 static int 2056 mt7530_port_vlan_del(struct dsa_switch *ds, int port, 2057 const struct switchdev_obj_port_vlan *vlan) 2058 { 2059 struct mt7530_hw_vlan_entry target_entry; 2060 struct mt7530_priv *priv = ds->priv; 2061 2062 mutex_lock(&priv->reg_mutex); 2063 2064 /* VID 0 is managed exclusively by mt7530_setup_vlan0(). */ 2065 if (vlan->vid == 0) 2066 goto skip_vlan_table; 2067 2068 mt7530_hw_vlan_entry_init(&target_entry, port, 0); 2069 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry, 2070 mt7530_hw_vlan_del); 2071 2072 skip_vlan_table: 2073 /* PVID is being restored to the default whenever the PVID port 2074 * is being removed from the VLAN. 2075 */ 2076 if (priv->ports[port].pvid == vlan->vid) { 2077 priv->ports[port].pvid = G0_PORT_VID_DEF; 2078 2079 /* Only accept tagged frames if the port is VLAN-aware */ 2080 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 2081 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 2082 MT7530_VLAN_ACC_TAGGED); 2083 2084 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 2085 G0_PORT_VID_DEF); 2086 } 2087 2088 2089 mutex_unlock(&priv->reg_mutex); 2090 2091 return 0; 2092 } 2093 2094 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port, 2095 struct dsa_mall_mirror_tc_entry *mirror, 2096 bool ingress, struct netlink_ext_ack *extack) 2097 { 2098 struct mt7530_priv *priv = ds->priv; 2099 int monitor_port; 2100 u32 val; 2101 2102 /* Check for existent entry */ 2103 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) 2104 return -EEXIST; 2105 2106 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 2107 2108 /* MT7530 only supports one monitor port */ 2109 monitor_port = MT753X_MIRROR_PORT_GET(priv->id, val); 2110 if (val & MT753X_MIRROR_EN(priv->id) && 2111 monitor_port != mirror->to_local_port) 2112 return -EEXIST; 2113 2114 val |= MT753X_MIRROR_EN(priv->id); 2115 val &= ~MT753X_MIRROR_PORT_MASK(priv->id); 2116 val |= MT753X_MIRROR_PORT_SET(priv->id, mirror->to_local_port); 2117 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 2118 2119 val = mt7530_read(priv, MT7530_PCR_P(port)); 2120 if (ingress) { 2121 val |= PORT_RX_MIR; 2122 priv->mirror_rx |= BIT(port); 2123 } else { 2124 val |= PORT_TX_MIR; 2125 priv->mirror_tx |= BIT(port); 2126 } 2127 mt7530_write(priv, MT7530_PCR_P(port), val); 2128 2129 return 0; 2130 } 2131 2132 static void mt753x_port_mirror_del(struct dsa_switch *ds, int port, 2133 struct dsa_mall_mirror_tc_entry *mirror) 2134 { 2135 struct mt7530_priv *priv = ds->priv; 2136 u32 val; 2137 2138 val = mt7530_read(priv, MT7530_PCR_P(port)); 2139 if (mirror->ingress) { 2140 val &= ~PORT_RX_MIR; 2141 priv->mirror_rx &= ~BIT(port); 2142 } else { 2143 val &= ~PORT_TX_MIR; 2144 priv->mirror_tx &= ~BIT(port); 2145 } 2146 mt7530_write(priv, MT7530_PCR_P(port), val); 2147 2148 if (!priv->mirror_rx && !priv->mirror_tx) { 2149 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 2150 val &= ~MT753X_MIRROR_EN(priv->id); 2151 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 2152 } 2153 } 2154 2155 static enum dsa_tag_protocol 2156 mtk_get_tag_protocol(struct dsa_switch *ds, int port, 2157 enum dsa_tag_protocol mp) 2158 { 2159 return DSA_TAG_PROTO_MTK; 2160 } 2161 2162 #ifdef CONFIG_GPIOLIB 2163 static inline u32 2164 mt7530_gpio_to_bit(unsigned int offset) 2165 { 2166 /* Map GPIO offset to register bit 2167 * [ 2: 0] port 0 LED 0..2 as GPIO 0..2 2168 * [ 6: 4] port 1 LED 0..2 as GPIO 3..5 2169 * [10: 8] port 2 LED 0..2 as GPIO 6..8 2170 * [14:12] port 3 LED 0..2 as GPIO 9..11 2171 * [18:16] port 4 LED 0..2 as GPIO 12..14 2172 */ 2173 return BIT(offset + offset / 3); 2174 } 2175 2176 static int 2177 mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset) 2178 { 2179 struct mt7530_priv *priv = gpiochip_get_data(gc); 2180 u32 bit = mt7530_gpio_to_bit(offset); 2181 2182 return !!(mt7530_read(priv, MT7530_LED_GPIO_DATA) & bit); 2183 } 2184 2185 static int 2186 mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 2187 { 2188 struct mt7530_priv *priv = gpiochip_get_data(gc); 2189 u32 bit = mt7530_gpio_to_bit(offset); 2190 2191 if (value) 2192 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 2193 else 2194 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 2195 2196 return 0; 2197 } 2198 2199 static int 2200 mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 2201 { 2202 struct mt7530_priv *priv = gpiochip_get_data(gc); 2203 u32 bit = mt7530_gpio_to_bit(offset); 2204 2205 return (mt7530_read(priv, MT7530_LED_GPIO_DIR) & bit) ? 2206 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 2207 } 2208 2209 static int 2210 mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset) 2211 { 2212 struct mt7530_priv *priv = gpiochip_get_data(gc); 2213 u32 bit = mt7530_gpio_to_bit(offset); 2214 2215 mt7530_clear(priv, MT7530_LED_GPIO_OE, bit); 2216 mt7530_clear(priv, MT7530_LED_GPIO_DIR, bit); 2217 2218 return 0; 2219 } 2220 2221 static int 2222 mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value) 2223 { 2224 struct mt7530_priv *priv = gpiochip_get_data(gc); 2225 u32 bit = mt7530_gpio_to_bit(offset); 2226 2227 mt7530_set(priv, MT7530_LED_GPIO_DIR, bit); 2228 2229 if (value) 2230 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 2231 else 2232 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 2233 2234 mt7530_set(priv, MT7530_LED_GPIO_OE, bit); 2235 2236 return 0; 2237 } 2238 2239 static int 2240 mt7530_setup_gpio(struct mt7530_priv *priv) 2241 { 2242 struct device *dev = priv->dev; 2243 struct gpio_chip *gc; 2244 2245 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 2246 if (!gc) 2247 return -ENOMEM; 2248 2249 mt7530_write(priv, MT7530_LED_GPIO_OE, 0); 2250 mt7530_write(priv, MT7530_LED_GPIO_DIR, 0); 2251 mt7530_write(priv, MT7530_LED_IO_MODE, 0); 2252 2253 gc->label = "mt7530"; 2254 gc->parent = dev; 2255 gc->owner = THIS_MODULE; 2256 gc->get_direction = mt7530_gpio_get_direction; 2257 gc->direction_input = mt7530_gpio_direction_input; 2258 gc->direction_output = mt7530_gpio_direction_output; 2259 gc->get = mt7530_gpio_get; 2260 gc->set = mt7530_gpio_set; 2261 gc->base = -1; 2262 gc->ngpio = 15; 2263 gc->can_sleep = true; 2264 2265 return devm_gpiochip_add_data(dev, gc, priv); 2266 } 2267 #endif /* CONFIG_GPIOLIB */ 2268 2269 static void 2270 mt7530_setup_mdio_irq(struct mt7530_priv *priv) 2271 { 2272 struct dsa_switch *ds = priv->ds; 2273 int p; 2274 2275 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2276 if (BIT(p) & ds->phys_mii_mask) { 2277 unsigned int irq; 2278 2279 irq = irq_create_mapping(priv->irq_domain, p); 2280 ds->user_mii_bus->irq[p] = irq; 2281 } 2282 } 2283 } 2284 2285 static const struct regmap_irq mt7530_irqs[] = { 2286 REGMAP_IRQ_REG_LINE(0, 32), /* PHY0_LC */ 2287 REGMAP_IRQ_REG_LINE(1, 32), /* PHY1_LC */ 2288 REGMAP_IRQ_REG_LINE(2, 32), /* PHY2_LC */ 2289 REGMAP_IRQ_REG_LINE(3, 32), /* PHY3_LC */ 2290 REGMAP_IRQ_REG_LINE(4, 32), /* PHY4_LC */ 2291 REGMAP_IRQ_REG_LINE(5, 32), /* PHY5_LC */ 2292 REGMAP_IRQ_REG_LINE(6, 32), /* PHY6_LC */ 2293 REGMAP_IRQ_REG_LINE(16, 32), /* MAC_PC */ 2294 REGMAP_IRQ_REG_LINE(17, 32), /* BMU */ 2295 REGMAP_IRQ_REG_LINE(18, 32), /* MIB */ 2296 REGMAP_IRQ_REG_LINE(22, 32), /* ARL_COL_FULL_COL */ 2297 REGMAP_IRQ_REG_LINE(23, 32), /* ARL_COL_FULL */ 2298 REGMAP_IRQ_REG_LINE(24, 32), /* ARL_TBL_ERR */ 2299 REGMAP_IRQ_REG_LINE(25, 32), /* ARL_PKT_QERR */ 2300 REGMAP_IRQ_REG_LINE(26, 32), /* ARL_EQ_ERR */ 2301 REGMAP_IRQ_REG_LINE(27, 32), /* ARL_PKT_BC */ 2302 REGMAP_IRQ_REG_LINE(28, 32), /* ARL_SEC_IG1X */ 2303 REGMAP_IRQ_REG_LINE(29, 32), /* ARL_SEC_VLAN */ 2304 REGMAP_IRQ_REG_LINE(30, 32), /* ARL_SEC_TAG */ 2305 REGMAP_IRQ_REG_LINE(31, 32), /* ACL */ 2306 }; 2307 2308 static const struct regmap_irq_chip mt7530_regmap_irq_chip = { 2309 .name = KBUILD_MODNAME, 2310 .status_base = MT7530_SYS_INT_STS, 2311 .unmask_base = MT7530_SYS_INT_EN, 2312 .ack_base = MT7530_SYS_INT_STS, 2313 .init_ack_masked = true, 2314 .irqs = mt7530_irqs, 2315 .num_irqs = ARRAY_SIZE(mt7530_irqs), 2316 .num_regs = 1, 2317 }; 2318 2319 static int 2320 mt7530_setup_irq(struct mt7530_priv *priv) 2321 { 2322 struct regmap_irq_chip_data *irq_data; 2323 struct device *dev = priv->dev; 2324 struct device_node *np = dev->of_node; 2325 int irq, ret; 2326 2327 if (!of_property_read_bool(np, "interrupt-controller")) { 2328 dev_info(dev, "no interrupt support\n"); 2329 return 0; 2330 } 2331 2332 irq = of_irq_get(np, 0); 2333 if (irq <= 0) { 2334 dev_err(dev, "failed to get parent IRQ: %d\n", irq); 2335 return irq ? : -EINVAL; 2336 } 2337 2338 /* This register must be set for MT7530 to properly fire interrupts */ 2339 if (priv->id == ID_MT7530 || priv->id == ID_MT7621) 2340 mt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL); 2341 2342 ret = devm_regmap_add_irq_chip_fwnode(dev, dev_fwnode(dev), 2343 priv->regmap, irq, 2344 IRQF_ONESHOT, 2345 0, &mt7530_regmap_irq_chip, 2346 &irq_data); 2347 if (ret) 2348 return ret; 2349 2350 priv->irq_domain = regmap_irq_get_domain(irq_data); 2351 2352 return 0; 2353 } 2354 2355 static void 2356 mt7530_free_mdio_irq(struct mt7530_priv *priv) 2357 { 2358 int p; 2359 2360 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2361 if (BIT(p) & priv->ds->phys_mii_mask) { 2362 unsigned int irq; 2363 2364 irq = irq_find_mapping(priv->irq_domain, p); 2365 irq_dispose_mapping(irq); 2366 } 2367 } 2368 } 2369 2370 static int 2371 mt7530_setup_mdio(struct mt7530_priv *priv) 2372 { 2373 struct device_node *mnp, *np = priv->dev->of_node; 2374 struct dsa_switch *ds = priv->ds; 2375 struct device *dev = priv->dev; 2376 struct mii_bus *bus; 2377 static int idx; 2378 int ret = 0; 2379 2380 mnp = of_get_child_by_name(np, "mdio"); 2381 2382 if (mnp && !of_device_is_available(mnp)) 2383 goto out; 2384 2385 bus = devm_mdiobus_alloc(dev); 2386 if (!bus) { 2387 ret = -ENOMEM; 2388 goto out; 2389 } 2390 2391 if (!mnp) 2392 ds->user_mii_bus = bus; 2393 2394 bus->priv = priv; 2395 bus->name = KBUILD_MODNAME "-mii"; 2396 snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++); 2397 bus->read = mt753x_phy_read_c22; 2398 bus->write = mt753x_phy_write_c22; 2399 bus->read_c45 = mt753x_phy_read_c45; 2400 bus->write_c45 = mt753x_phy_write_c45; 2401 bus->parent = dev; 2402 bus->phy_mask = ~ds->phys_mii_mask; 2403 2404 if (priv->irq_domain && !mnp) 2405 mt7530_setup_mdio_irq(priv); 2406 2407 ret = devm_of_mdiobus_register(dev, bus, mnp); 2408 if (ret) { 2409 dev_err(dev, "failed to register MDIO bus: %d\n", ret); 2410 if (priv->irq_domain && !mnp) 2411 mt7530_free_mdio_irq(priv); 2412 } 2413 2414 out: 2415 of_node_put(mnp); 2416 return ret; 2417 } 2418 2419 static int 2420 mt7530_setup(struct dsa_switch *ds) 2421 { 2422 struct mt7530_priv *priv = ds->priv; 2423 struct device_node *dn = NULL; 2424 struct device_node *phy_node; 2425 struct device_node *mac_np; 2426 struct mt7530_dummy_poll p; 2427 phy_interface_t interface; 2428 struct dsa_port *cpu_dp; 2429 u32 id, val; 2430 int ret, i; 2431 2432 /* The parent node of conduit netdev which holds the common system 2433 * controller also is the container for two GMACs nodes representing 2434 * as two netdev instances. 2435 */ 2436 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 2437 dn = cpu_dp->conduit->dev.of_node->parent; 2438 /* It doesn't matter which CPU port is found first, 2439 * their conduits should share the same parent OF node 2440 */ 2441 break; 2442 } 2443 2444 if (!dn) { 2445 dev_err(ds->dev, "parent OF node of DSA conduit not found"); 2446 return -EINVAL; 2447 } 2448 2449 ds->assisted_learning_on_cpu_port = true; 2450 ds->untag_vlan_aware_bridge_pvid = true; 2451 ds->mtu_enforcement_ingress = true; 2452 ds->ageing_time_min = 2 * 1000; 2453 ds->ageing_time_max = (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1) * 1000; 2454 2455 if (priv->id == ID_MT7530) { 2456 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); 2457 ret = regulator_enable(priv->core_pwr); 2458 if (ret < 0) { 2459 dev_err(priv->dev, 2460 "Failed to enable core power: %d\n", ret); 2461 return ret; 2462 } 2463 2464 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); 2465 ret = regulator_enable(priv->io_pwr); 2466 if (ret < 0) { 2467 dev_err(priv->dev, "Failed to enable io pwr: %d\n", 2468 ret); 2469 return ret; 2470 } 2471 } 2472 2473 /* Reset whole chip through gpio pin or memory-mapped registers for 2474 * different type of hardware 2475 */ 2476 if (priv->mcm) { 2477 reset_control_assert(priv->rstc); 2478 usleep_range(5000, 5100); 2479 reset_control_deassert(priv->rstc); 2480 } else { 2481 gpiod_set_value_cansleep(priv->reset, 0); 2482 usleep_range(5000, 5100); 2483 gpiod_set_value_cansleep(priv->reset, 1); 2484 } 2485 2486 /* Waiting for MT7530 got to stable */ 2487 INIT_MT7530_DUMMY_POLL(&p, priv, MT753X_TRAP); 2488 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2489 20, 1000000); 2490 if (ret < 0) { 2491 dev_err(priv->dev, "reset timeout\n"); 2492 return ret; 2493 } 2494 2495 id = mt7530_read(priv, MT7530_CREV); 2496 id >>= CHIP_NAME_SHIFT; 2497 if (id != MT7530_ID) { 2498 dev_err(priv->dev, "chip %x can't be supported\n", id); 2499 return -ENODEV; 2500 } 2501 2502 if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_20MHZ) { 2503 dev_err(priv->dev, 2504 "MT7530 with a 20MHz XTAL is not supported!\n"); 2505 return -EINVAL; 2506 } 2507 2508 /* Reset the switch through internal reset */ 2509 mt7530_write(priv, MT7530_SYS_CTRL, 2510 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2511 SYS_CTRL_REG_RST); 2512 2513 /* Lower Tx driving for TRGMII path */ 2514 for (i = 0; i < NUM_TRGMII_CTRL; i++) 2515 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), 2516 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 2517 2518 for (i = 0; i < NUM_TRGMII_CTRL; i++) 2519 mt7530_rmw(priv, MT7530_TRGMII_RD(i), 2520 RD_TAP_MASK, RD_TAP(16)); 2521 2522 /* Allow modifying the trap and directly access PHY registers via the 2523 * MDIO bus the switch is on. 2524 */ 2525 mt7530_rmw(priv, MT753X_MTRAP, MT7530_CHG_TRAP | 2526 MT7530_PHY_INDIRECT_ACCESS, MT7530_CHG_TRAP); 2527 2528 if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_40MHZ) 2529 mt7530_pll_setup(priv); 2530 2531 mt753x_trap_frames(priv); 2532 2533 /* Enable and reset MIB counters */ 2534 mt7530_mib_reset(ds); 2535 2536 for (i = 0; i < priv->ds->num_ports; i++) { 2537 /* Clear link settings and enable force mode to force link down 2538 * on all ports until they're enabled later. 2539 */ 2540 mt7530_rmw(priv, MT753X_PMCR_P(i), 2541 PMCR_LINK_SETTINGS_MASK | 2542 MT753X_FORCE_MODE(priv->id), 2543 MT753X_FORCE_MODE(priv->id)); 2544 2545 /* Disable forwarding by default on all ports */ 2546 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2547 PCR_MATRIX_CLR); 2548 2549 /* Disable learning by default on all ports */ 2550 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2551 2552 if (dsa_is_cpu_port(ds, i)) { 2553 mt753x_cpu_port_enable(ds, i); 2554 } else { 2555 mt7530_port_disable(ds, i); 2556 2557 /* Set default PVID to 0 on all user ports */ 2558 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2559 G0_PORT_VID_DEF); 2560 } 2561 /* Enable consistent egress tag */ 2562 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2563 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2564 } 2565 2566 /* Allow mirroring frames received on the local port (monitor port). */ 2567 mt7530_set(priv, MT753X_AGC, LOCAL_EN); 2568 2569 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2570 ret = mt7530_setup_vlan0(priv); 2571 if (ret) 2572 return ret; 2573 2574 /* Check for PHY muxing on port 5 */ 2575 if (dsa_is_unused_port(ds, 5)) { 2576 /* Scan the ethernet nodes. Look for GMAC1, lookup the used PHY. 2577 * Set priv->p5_mode to the appropriate value if PHY muxing is 2578 * detected. 2579 */ 2580 for_each_child_of_node(dn, mac_np) { 2581 if (!of_device_is_compatible(mac_np, 2582 "mediatek,eth-mac")) 2583 continue; 2584 2585 ret = of_property_read_u32(mac_np, "reg", &id); 2586 if (ret < 0 || id != 1) 2587 continue; 2588 2589 phy_node = of_parse_phandle(mac_np, "phy-handle", 0); 2590 if (!phy_node) 2591 continue; 2592 2593 if (phy_node->parent == priv->dev->of_node->parent || 2594 phy_node->parent->parent == priv->dev->of_node) { 2595 ret = of_get_phy_mode(mac_np, &interface); 2596 if (ret && ret != -ENODEV) { 2597 of_node_put(mac_np); 2598 of_node_put(phy_node); 2599 return ret; 2600 } 2601 id = of_mdio_parse_addr(ds->dev, phy_node); 2602 if (id == 0) 2603 priv->p5_mode = MUX_PHY_P0; 2604 if (id == 4) 2605 priv->p5_mode = MUX_PHY_P4; 2606 } 2607 of_node_put(mac_np); 2608 of_node_put(phy_node); 2609 break; 2610 } 2611 2612 if (priv->p5_mode == MUX_PHY_P0 || 2613 priv->p5_mode == MUX_PHY_P4) { 2614 mt7530_clear(priv, MT753X_MTRAP, MT7530_P5_DIS); 2615 mt7530_setup_port5(ds, interface); 2616 } 2617 } 2618 2619 #ifdef CONFIG_GPIOLIB 2620 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) { 2621 ret = mt7530_setup_gpio(priv); 2622 if (ret) 2623 return ret; 2624 } 2625 #endif /* CONFIG_GPIOLIB */ 2626 2627 /* Flush the FDB table */ 2628 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2629 if (ret < 0) 2630 return ret; 2631 2632 return 0; 2633 } 2634 2635 static int 2636 mt7531_setup_common(struct dsa_switch *ds) 2637 { 2638 struct mt7530_priv *priv = ds->priv; 2639 int ret, i; 2640 2641 ds->assisted_learning_on_cpu_port = true; 2642 ds->untag_vlan_aware_bridge_pvid = true; 2643 ds->mtu_enforcement_ingress = true; 2644 ds->ageing_time_min = 2 * 1000; 2645 ds->ageing_time_max = (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1) * 1000; 2646 2647 mt753x_trap_frames(priv); 2648 2649 /* Enable and reset MIB counters */ 2650 mt7530_mib_reset(ds); 2651 2652 /* Disable flooding on all ports */ 2653 mt7530_clear(priv, MT753X_MFC, BC_FFP_MASK | UNM_FFP_MASK | 2654 UNU_FFP_MASK); 2655 2656 for (i = 0; i < priv->ds->num_ports; i++) { 2657 /* Clear link settings and enable force mode to force link down 2658 * on all ports until they're enabled later. 2659 */ 2660 mt7530_rmw(priv, MT753X_PMCR_P(i), 2661 PMCR_LINK_SETTINGS_MASK | 2662 MT753X_FORCE_MODE(priv->id), 2663 MT753X_FORCE_MODE(priv->id)); 2664 2665 /* Disable forwarding by default on all ports */ 2666 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2667 PCR_MATRIX_CLR); 2668 2669 /* Disable learning by default on all ports */ 2670 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2671 2672 mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR); 2673 2674 if (dsa_is_cpu_port(ds, i)) { 2675 mt753x_cpu_port_enable(ds, i); 2676 } else { 2677 mt7530_port_disable(ds, i); 2678 2679 /* Set default PVID to 0 on all user ports */ 2680 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2681 G0_PORT_VID_DEF); 2682 } 2683 2684 /* Enable consistent egress tag */ 2685 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2686 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2687 } 2688 2689 /* Allow mirroring frames received on the local port (monitor port). */ 2690 mt7530_set(priv, MT753X_AGC, LOCAL_EN); 2691 2692 /* Enable Special Tag for rx frames */ 2693 if (priv->id == ID_EN7581 || priv->id == ID_AN7583) 2694 mt7530_write(priv, MT753X_CPORT_SPTAG_CFG, 2695 CPORT_SW2FE_STAG_EN | CPORT_FE2SW_STAG_EN); 2696 2697 /* Flush the FDB table */ 2698 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2699 if (ret < 0) 2700 return ret; 2701 2702 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2703 return mt7530_setup_vlan0(priv); 2704 } 2705 2706 static int 2707 mt7531_setup(struct dsa_switch *ds) 2708 { 2709 struct mt7530_priv *priv = ds->priv; 2710 struct mt7530_dummy_poll p; 2711 u32 val, id; 2712 int ret, i; 2713 2714 /* Reset whole chip through gpio pin or memory-mapped registers for 2715 * different type of hardware 2716 */ 2717 if (priv->mcm) { 2718 reset_control_assert(priv->rstc); 2719 usleep_range(5000, 5100); 2720 reset_control_deassert(priv->rstc); 2721 } else { 2722 gpiod_set_value_cansleep(priv->reset, 0); 2723 usleep_range(5000, 5100); 2724 gpiod_set_value_cansleep(priv->reset, 1); 2725 } 2726 2727 /* Waiting for MT7530 got to stable */ 2728 INIT_MT7530_DUMMY_POLL(&p, priv, MT753X_TRAP); 2729 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2730 20, 1000000); 2731 if (ret < 0) { 2732 dev_err(priv->dev, "reset timeout\n"); 2733 return ret; 2734 } 2735 2736 id = mt7530_read(priv, MT7531_CREV); 2737 id >>= CHIP_NAME_SHIFT; 2738 2739 if (id != MT7531_ID) { 2740 dev_err(priv->dev, "chip %x can't be supported\n", id); 2741 return -ENODEV; 2742 } 2743 2744 /* MT7531AE has got two SGMII units. One for port 5, one for port 6. 2745 * MT7531BE has got only one SGMII unit which is for port 6. 2746 */ 2747 val = mt7530_read(priv, MT7531_TOP_SIG_SR); 2748 priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN); 2749 2750 /* Force link down on all ports before internal reset */ 2751 for (i = 0; i < priv->ds->num_ports; i++) 2752 mt7530_write(priv, MT753X_PMCR_P(i), MT7531_FORCE_MODE_LNK); 2753 2754 /* Reset the switch through internal reset */ 2755 mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_SW_RST | SYS_CTRL_REG_RST); 2756 2757 if (!priv->p5_sgmii) { 2758 mt7531_pll_setup(priv); 2759 } else { 2760 /* Unlike MT7531BE, the GPIO 6-12 pins are not used for RGMII on 2761 * MT7531AE. Set the GPIO 11-12 pins to function as MDC and MDIO 2762 * to expose the MDIO bus of the switch. 2763 */ 2764 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK, 2765 MT7531_EXT_P_MDC_11); 2766 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK, 2767 MT7531_EXT_P_MDIO_12); 2768 } 2769 2770 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, 2771 MT7531_GPIO0_INTERRUPT); 2772 2773 /* Enable Energy-Efficient Ethernet (EEE) and PHY core PLL, since 2774 * phy_device has not yet been created provided for 2775 * phy_[read,write]_mmd_indirect is called, we provide our own 2776 * mt7531_ind_mmd_phy_[read,write] to complete this function. 2777 */ 2778 val = mt7531_ind_c45_phy_read(priv, 2779 MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 2780 MDIO_MMD_VEND2, CORE_PLL_GROUP4); 2781 val |= MT7531_RG_SYSPLL_DMY2 | MT7531_PHY_PLL_BYPASS_MODE; 2782 val &= ~MT7531_PHY_PLL_OFF; 2783 mt7531_ind_c45_phy_write(priv, 2784 MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 2785 MDIO_MMD_VEND2, CORE_PLL_GROUP4, val); 2786 2787 /* Disable EEE advertisement on the switch PHYs. */ 2788 for (i = MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr); 2789 i < MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr) + MT7530_NUM_PHYS; 2790 i++) { 2791 mt7531_ind_c45_phy_write(priv, i, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 2792 0); 2793 } 2794 2795 ret = mt7531_setup_common(ds); 2796 if (ret) 2797 return ret; 2798 2799 return 0; 2800 } 2801 2802 static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port, 2803 struct phylink_config *config) 2804 { 2805 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; 2806 2807 switch (port) { 2808 /* Ports which are connected to switch PHYs. There is no MII pinout. */ 2809 case 0 ... 4: 2810 __set_bit(PHY_INTERFACE_MODE_GMII, 2811 config->supported_interfaces); 2812 break; 2813 2814 /* Port 5 supports rgmii with delays, mii, and gmii. */ 2815 case 5: 2816 phy_interface_set_rgmii(config->supported_interfaces); 2817 __set_bit(PHY_INTERFACE_MODE_MII, 2818 config->supported_interfaces); 2819 __set_bit(PHY_INTERFACE_MODE_GMII, 2820 config->supported_interfaces); 2821 break; 2822 2823 /* Port 6 supports rgmii and trgmii. */ 2824 case 6: 2825 __set_bit(PHY_INTERFACE_MODE_RGMII, 2826 config->supported_interfaces); 2827 __set_bit(PHY_INTERFACE_MODE_TRGMII, 2828 config->supported_interfaces); 2829 break; 2830 } 2831 } 2832 2833 static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port, 2834 struct phylink_config *config) 2835 { 2836 struct mt7530_priv *priv = ds->priv; 2837 2838 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; 2839 2840 switch (port) { 2841 /* Ports which are connected to switch PHYs. There is no MII pinout. */ 2842 case 0 ... 4: 2843 __set_bit(PHY_INTERFACE_MODE_GMII, 2844 config->supported_interfaces); 2845 break; 2846 2847 /* Port 5 supports rgmii with delays on MT7531BE, sgmii/802.3z on 2848 * MT7531AE. 2849 */ 2850 case 5: 2851 if (!priv->p5_sgmii) { 2852 phy_interface_set_rgmii(config->supported_interfaces); 2853 break; 2854 } 2855 fallthrough; 2856 2857 /* Port 6 supports sgmii/802.3z. */ 2858 case 6: 2859 __set_bit(PHY_INTERFACE_MODE_SGMII, 2860 config->supported_interfaces); 2861 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 2862 config->supported_interfaces); 2863 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 2864 config->supported_interfaces); 2865 2866 config->mac_capabilities |= MAC_2500FD; 2867 break; 2868 } 2869 } 2870 2871 static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port, 2872 struct phylink_config *config) 2873 { 2874 switch (port) { 2875 /* Ports which are connected to switch PHYs. There is no MII pinout. */ 2876 case 0 ... 3: 2877 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2878 config->supported_interfaces); 2879 2880 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; 2881 break; 2882 2883 /* Port 6 is connected to SoC's XGMII MAC. There is no MII pinout. */ 2884 case 6: 2885 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2886 config->supported_interfaces); 2887 2888 config->mac_capabilities |= MAC_10000FD; 2889 break; 2890 } 2891 } 2892 2893 static void en7581_mac_port_get_caps(struct dsa_switch *ds, int port, 2894 struct phylink_config *config) 2895 { 2896 switch (port) { 2897 /* Ports which are connected to switch PHYs. There is no MII pinout. */ 2898 case 0 ... 4: 2899 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2900 config->supported_interfaces); 2901 2902 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; 2903 break; 2904 2905 /* Port 6 is connected to SoC's XGMII MAC. There is no MII pinout. */ 2906 case 6: 2907 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2908 config->supported_interfaces); 2909 2910 config->mac_capabilities |= MAC_10000FD; 2911 break; 2912 } 2913 } 2914 2915 static void 2916 mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2917 phy_interface_t interface) 2918 { 2919 struct mt7530_priv *priv = ds->priv; 2920 2921 if (port == 5) 2922 mt7530_setup_port5(priv->ds, interface); 2923 else if (port == 6) 2924 mt7530_setup_port6(priv->ds, interface); 2925 } 2926 2927 static void mt7531_rgmii_setup(struct mt7530_priv *priv, 2928 phy_interface_t interface, 2929 struct phy_device *phydev) 2930 { 2931 u32 val; 2932 2933 val = mt7530_read(priv, MT7531_CLKGEN_CTRL); 2934 val |= GP_CLK_EN; 2935 val &= ~GP_MODE_MASK; 2936 val |= GP_MODE(MT7531_GP_MODE_RGMII); 2937 val &= ~CLK_SKEW_IN_MASK; 2938 val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG); 2939 val &= ~CLK_SKEW_OUT_MASK; 2940 val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG); 2941 val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY; 2942 2943 /* Do not adjust rgmii delay when vendor phy driver presents. */ 2944 if (!phydev || phy_driver_is_genphy(phydev)) { 2945 val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY); 2946 switch (interface) { 2947 case PHY_INTERFACE_MODE_RGMII: 2948 val |= TXCLK_NO_REVERSE; 2949 val |= RXCLK_NO_DELAY; 2950 break; 2951 case PHY_INTERFACE_MODE_RGMII_RXID: 2952 val |= TXCLK_NO_REVERSE; 2953 break; 2954 case PHY_INTERFACE_MODE_RGMII_TXID: 2955 val |= RXCLK_NO_DELAY; 2956 break; 2957 case PHY_INTERFACE_MODE_RGMII_ID: 2958 break; 2959 default: 2960 break; 2961 } 2962 } 2963 2964 mt7530_write(priv, MT7531_CLKGEN_CTRL, val); 2965 } 2966 2967 static void 2968 mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2969 phy_interface_t interface) 2970 { 2971 struct mt7530_priv *priv = ds->priv; 2972 struct phy_device *phydev; 2973 struct dsa_port *dp; 2974 2975 if (phy_interface_mode_is_rgmii(interface)) { 2976 dp = dsa_to_port(ds, port); 2977 phydev = dp->user->phydev; 2978 mt7531_rgmii_setup(priv, interface, phydev); 2979 } 2980 } 2981 2982 static struct phylink_pcs * 2983 mt753x_phylink_mac_select_pcs(struct phylink_config *config, 2984 phy_interface_t interface) 2985 { 2986 struct dsa_port *dp = dsa_phylink_to_port(config); 2987 struct mt7530_priv *priv = dp->ds->priv; 2988 2989 switch (interface) { 2990 case PHY_INTERFACE_MODE_TRGMII: 2991 return &priv->pcs[dp->index].pcs; 2992 case PHY_INTERFACE_MODE_SGMII: 2993 case PHY_INTERFACE_MODE_1000BASEX: 2994 case PHY_INTERFACE_MODE_2500BASEX: 2995 return priv->ports[dp->index].sgmii_pcs; 2996 default: 2997 return NULL; 2998 } 2999 } 3000 3001 static void 3002 mt753x_phylink_mac_config(struct phylink_config *config, unsigned int mode, 3003 const struct phylink_link_state *state) 3004 { 3005 struct dsa_port *dp = dsa_phylink_to_port(config); 3006 struct dsa_switch *ds = dp->ds; 3007 struct mt7530_priv *priv; 3008 int port = dp->index; 3009 3010 priv = ds->priv; 3011 3012 if ((port == 5 || port == 6) && priv->info->mac_port_config) 3013 priv->info->mac_port_config(ds, port, mode, state->interface); 3014 3015 /* Are we connected to external phy */ 3016 if (port == 5 && dsa_is_user_port(ds, 5)) 3017 mt7530_set(priv, MT753X_PMCR_P(port), PMCR_EXT_PHY); 3018 } 3019 3020 static void mt753x_phylink_mac_link_down(struct phylink_config *config, 3021 unsigned int mode, 3022 phy_interface_t interface) 3023 { 3024 struct dsa_port *dp = dsa_phylink_to_port(config); 3025 struct mt7530_priv *priv = dp->ds->priv; 3026 3027 mt7530_clear(priv, MT753X_PMCR_P(dp->index), PMCR_LINK_SETTINGS_MASK); 3028 } 3029 3030 static void mt753x_phylink_mac_link_up(struct phylink_config *config, 3031 struct phy_device *phydev, 3032 unsigned int mode, 3033 phy_interface_t interface, 3034 int speed, int duplex, 3035 bool tx_pause, bool rx_pause) 3036 { 3037 struct dsa_port *dp = dsa_phylink_to_port(config); 3038 struct mt7530_priv *priv = dp->ds->priv; 3039 u32 mcr; 3040 3041 mcr = PMCR_MAC_RX_EN | PMCR_MAC_TX_EN | PMCR_FORCE_LNK; 3042 3043 switch (speed) { 3044 case SPEED_1000: 3045 case SPEED_2500: 3046 case SPEED_10000: 3047 mcr |= PMCR_FORCE_SPEED_1000; 3048 break; 3049 case SPEED_100: 3050 mcr |= PMCR_FORCE_SPEED_100; 3051 break; 3052 } 3053 if (duplex == DUPLEX_FULL) { 3054 mcr |= PMCR_FORCE_FDX; 3055 if (tx_pause) 3056 mcr |= PMCR_FORCE_TX_FC_EN; 3057 if (rx_pause) 3058 mcr |= PMCR_FORCE_RX_FC_EN; 3059 } 3060 3061 mt7530_set(priv, MT753X_PMCR_P(dp->index), mcr); 3062 } 3063 3064 static void mt753x_phylink_mac_disable_tx_lpi(struct phylink_config *config) 3065 { 3066 struct dsa_port *dp = dsa_phylink_to_port(config); 3067 struct mt7530_priv *priv = dp->ds->priv; 3068 3069 mt7530_clear(priv, MT753X_PMCR_P(dp->index), 3070 PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100); 3071 } 3072 3073 static int mt753x_phylink_mac_enable_tx_lpi(struct phylink_config *config, 3074 u32 timer, bool tx_clock_stop) 3075 { 3076 struct dsa_port *dp = dsa_phylink_to_port(config); 3077 struct mt7530_priv *priv = dp->ds->priv; 3078 u32 val; 3079 3080 /* If the timer is zero, then set LPI_MODE_EN, which allows the 3081 * system to enter LPI mode immediately rather than waiting for 3082 * the LPI threshold. 3083 */ 3084 if (!timer) 3085 val = LPI_MODE_EN; 3086 else if (FIELD_FIT(LPI_THRESH_MASK, timer)) 3087 val = FIELD_PREP(LPI_THRESH_MASK, timer); 3088 else 3089 val = LPI_THRESH_MASK; 3090 3091 mt7530_rmw(priv, MT753X_PMEEECR_P(dp->index), 3092 LPI_THRESH_MASK | LPI_MODE_EN, val); 3093 3094 mt7530_set(priv, MT753X_PMCR_P(dp->index), 3095 PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100); 3096 3097 return 0; 3098 } 3099 3100 static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port, 3101 struct phylink_config *config) 3102 { 3103 struct mt7530_priv *priv = ds->priv; 3104 u32 eeecr; 3105 3106 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE; 3107 3108 config->lpi_capabilities = MAC_100FD | MAC_1000FD | MAC_2500FD; 3109 3110 eeecr = mt7530_read(priv, MT753X_PMEEECR_P(port)); 3111 /* tx_lpi_timer should be in microseconds. The time units for 3112 * LPI threshold are unspecified. 3113 */ 3114 config->lpi_timer_default = FIELD_GET(LPI_THRESH_MASK, eeecr); 3115 3116 priv->info->mac_port_get_caps(ds, port, config); 3117 } 3118 3119 static int mt753x_pcs_validate(struct phylink_pcs *pcs, 3120 unsigned long *supported, 3121 const struct phylink_link_state *state) 3122 { 3123 /* Autonegotiation is not supported in TRGMII nor 802.3z modes */ 3124 if (state->interface == PHY_INTERFACE_MODE_TRGMII || 3125 phy_interface_mode_is_8023z(state->interface)) 3126 phylink_clear(supported, Autoneg); 3127 3128 return 0; 3129 } 3130 3131 static void mt7530_pcs_get_state(struct phylink_pcs *pcs, unsigned int neg_mode, 3132 struct phylink_link_state *state) 3133 { 3134 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; 3135 int port = pcs_to_mt753x_pcs(pcs)->port; 3136 u32 pmsr; 3137 3138 pmsr = mt7530_read(priv, MT7530_PMSR_P(port)); 3139 3140 state->link = (pmsr & PMSR_LINK); 3141 state->an_complete = state->link; 3142 state->duplex = !!(pmsr & PMSR_DPX); 3143 3144 switch (pmsr & PMSR_SPEED_MASK) { 3145 case PMSR_SPEED_10: 3146 state->speed = SPEED_10; 3147 break; 3148 case PMSR_SPEED_100: 3149 state->speed = SPEED_100; 3150 break; 3151 case PMSR_SPEED_1000: 3152 state->speed = SPEED_1000; 3153 break; 3154 default: 3155 state->speed = SPEED_UNKNOWN; 3156 break; 3157 } 3158 3159 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX); 3160 if (pmsr & PMSR_RX_FC) 3161 state->pause |= MLO_PAUSE_RX; 3162 if (pmsr & PMSR_TX_FC) 3163 state->pause |= MLO_PAUSE_TX; 3164 } 3165 3166 static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode, 3167 phy_interface_t interface, 3168 const unsigned long *advertising, 3169 bool permit_pause_to_mac) 3170 { 3171 return 0; 3172 } 3173 3174 static void mt7530_pcs_an_restart(struct phylink_pcs *pcs) 3175 { 3176 } 3177 3178 static const struct phylink_pcs_ops mt7530_pcs_ops = { 3179 .pcs_validate = mt753x_pcs_validate, 3180 .pcs_get_state = mt7530_pcs_get_state, 3181 .pcs_config = mt753x_pcs_config, 3182 .pcs_an_restart = mt7530_pcs_an_restart, 3183 }; 3184 3185 static int 3186 mt753x_setup(struct dsa_switch *ds) 3187 { 3188 struct mt7530_priv *priv = ds->priv; 3189 int ret = priv->info->sw_setup(ds); 3190 int i; 3191 3192 if (ret) 3193 return ret; 3194 3195 ret = mt7530_setup_irq(priv); 3196 if (ret) 3197 return ret; 3198 3199 ret = mt7530_setup_mdio(priv); 3200 if (ret) 3201 return ret; 3202 3203 /* Initialise the PCS devices */ 3204 for (i = 0; i < priv->ds->num_ports; i++) { 3205 priv->pcs[i].pcs.ops = priv->info->pcs_ops; 3206 priv->pcs[i].priv = priv; 3207 priv->pcs[i].port = i; 3208 } 3209 3210 if (priv->create_sgmii) 3211 ret = priv->create_sgmii(priv); 3212 3213 if (ret && priv->irq_domain) 3214 mt7530_free_mdio_irq(priv); 3215 3216 if (!ret && priv->bus) { 3217 mt7530_stats_refresh(priv); 3218 schedule_delayed_work(&priv->stats_work, 3219 MT7530_STATS_POLL_INTERVAL); 3220 } 3221 3222 return ret; 3223 } 3224 3225 static void 3226 mt753x_teardown(struct dsa_switch *ds) 3227 { 3228 struct mt7530_priv *priv = ds->priv; 3229 3230 if (priv->bus) 3231 cancel_delayed_work_sync(&priv->stats_work); 3232 } 3233 3234 static int mt753x_set_mac_eee(struct dsa_switch *ds, int port, 3235 struct ethtool_keee *e) 3236 { 3237 if (e->tx_lpi_timer > 0xFFF) 3238 return -EINVAL; 3239 3240 return 0; 3241 } 3242 3243 static void 3244 mt753x_conduit_state_change(struct dsa_switch *ds, 3245 const struct net_device *conduit, 3246 bool operational) 3247 { 3248 struct dsa_port *cpu_dp = conduit->dsa_ptr; 3249 struct mt7530_priv *priv = ds->priv; 3250 int val = 0; 3251 u8 mask; 3252 3253 /* Set the CPU port to trap frames to for MT7530. Trapped frames will be 3254 * forwarded to the numerically smallest CPU port whose conduit 3255 * interface is up. 3256 */ 3257 if (priv->id != ID_MT7530 && priv->id != ID_MT7621) 3258 return; 3259 3260 mask = BIT(cpu_dp->index); 3261 3262 if (operational) 3263 priv->active_cpu_ports |= mask; 3264 else 3265 priv->active_cpu_ports &= ~mask; 3266 3267 if (priv->active_cpu_ports) { 3268 val = MT7530_CPU_EN | 3269 MT7530_CPU_PORT(__ffs(priv->active_cpu_ports)); 3270 } 3271 3272 mt7530_rmw(priv, MT753X_MFC, MT7530_CPU_EN | MT7530_CPU_PORT_MASK, val); 3273 } 3274 3275 static int mt753x_tc_setup_qdisc_tbf(struct dsa_switch *ds, int port, 3276 struct tc_tbf_qopt_offload *qopt) 3277 { 3278 struct tc_tbf_qopt_offload_replace_params *p = &qopt->replace_params; 3279 struct mt7530_priv *priv = ds->priv; 3280 u32 rate = 0; 3281 3282 switch (qopt->command) { 3283 case TC_TBF_REPLACE: 3284 rate = div_u64(p->rate.rate_bytes_ps, 1000) << 3; /* kbps */ 3285 fallthrough; 3286 case TC_TBF_DESTROY: { 3287 u32 val, tick; 3288 3289 mt7530_rmw(priv, MT753X_GERLCR, EGR_BC_MASK, 3290 EGR_BC_CRC_IPG_PREAMBLE); 3291 3292 /* if rate is greater than 10Mbps tick is 1/32 ms, 3293 * 1ms otherwise 3294 */ 3295 tick = rate > 10000 ? 2 : 7; 3296 val = FIELD_PREP(ERLCR_CIR_MASK, (rate >> 5)) | 3297 FIELD_PREP(ERLCR_EN_MASK, !!rate) | 3298 FIELD_PREP(ERLCR_EXP_MASK, tick) | 3299 ERLCR_TBF_MODE_MASK | 3300 FIELD_PREP(ERLCR_MANT_MASK, 0xf); 3301 mt7530_write(priv, MT753X_ERLCR_P(port), val); 3302 break; 3303 } 3304 default: 3305 return -EOPNOTSUPP; 3306 } 3307 3308 return 0; 3309 } 3310 3311 static int mt753x_setup_tc(struct dsa_switch *ds, int port, 3312 enum tc_setup_type type, void *type_data) 3313 { 3314 switch (type) { 3315 case TC_SETUP_QDISC_TBF: 3316 return mt753x_tc_setup_qdisc_tbf(ds, port, type_data); 3317 default: 3318 return -EOPNOTSUPP; 3319 } 3320 } 3321 3322 static int mt7988_setup(struct dsa_switch *ds) 3323 { 3324 struct mt7530_priv *priv = ds->priv; 3325 3326 /* Reset the switch */ 3327 reset_control_assert(priv->rstc); 3328 usleep_range(20, 50); 3329 reset_control_deassert(priv->rstc); 3330 usleep_range(20, 50); 3331 3332 /* AN7583 require additional tweak to CONN_CFG */ 3333 if (priv->id == ID_AN7583) 3334 mt7530_rmw(priv, AN7583_GEPHY_CONN_CFG, 3335 AN7583_CSR_DPHY_CKIN_SEL | 3336 AN7583_CSR_PHY_CORE_REG_CLK_SEL | 3337 AN7583_CSR_ETHER_AFE_PWD, 3338 AN7583_CSR_DPHY_CKIN_SEL | 3339 AN7583_CSR_PHY_CORE_REG_CLK_SEL | 3340 FIELD_PREP(AN7583_CSR_ETHER_AFE_PWD, 0)); 3341 3342 /* Reset the switch PHYs */ 3343 mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_PHY_RST); 3344 3345 return mt7531_setup_common(ds); 3346 } 3347 3348 static const struct dsa_switch_ops mt7530_switch_ops = { 3349 .get_tag_protocol = mtk_get_tag_protocol, 3350 .setup = mt753x_setup, 3351 .teardown = mt753x_teardown, 3352 .preferred_default_local_cpu_port = mt753x_preferred_default_local_cpu_port, 3353 .get_strings = mt7530_get_strings, 3354 .get_ethtool_stats = mt7530_get_ethtool_stats, 3355 .get_sset_count = mt7530_get_sset_count, 3356 .get_eth_mac_stats = mt7530_get_eth_mac_stats, 3357 .get_rmon_stats = mt7530_get_rmon_stats, 3358 .get_eth_ctrl_stats = mt7530_get_eth_ctrl_stats, 3359 .get_stats64 = mt7530_get_stats64, 3360 .set_ageing_time = mt7530_set_ageing_time, 3361 .port_enable = mt7530_port_enable, 3362 .port_disable = mt7530_port_disable, 3363 .port_change_mtu = mt7530_port_change_mtu, 3364 .port_max_mtu = mt7530_port_max_mtu, 3365 .port_stp_state_set = mt7530_stp_state_set, 3366 .port_pre_bridge_flags = mt7530_port_pre_bridge_flags, 3367 .port_bridge_flags = mt7530_port_bridge_flags, 3368 .port_bridge_join = mt7530_port_bridge_join, 3369 .port_bridge_leave = mt7530_port_bridge_leave, 3370 .port_fdb_add = mt7530_port_fdb_add, 3371 .port_fdb_del = mt7530_port_fdb_del, 3372 .port_fdb_dump = mt7530_port_fdb_dump, 3373 .port_mdb_add = mt7530_port_mdb_add, 3374 .port_mdb_del = mt7530_port_mdb_del, 3375 .port_vlan_filtering = mt7530_port_vlan_filtering, 3376 .port_vlan_add = mt7530_port_vlan_add, 3377 .port_vlan_del = mt7530_port_vlan_del, 3378 .port_mirror_add = mt753x_port_mirror_add, 3379 .port_mirror_del = mt753x_port_mirror_del, 3380 .phylink_get_caps = mt753x_phylink_get_caps, 3381 .support_eee = dsa_supports_eee, 3382 .set_mac_eee = mt753x_set_mac_eee, 3383 .conduit_state_change = mt753x_conduit_state_change, 3384 .port_setup_tc = mt753x_setup_tc, 3385 .port_hsr_join = dsa_port_simple_hsr_join, 3386 .port_hsr_leave = dsa_port_simple_hsr_leave, 3387 }; 3388 3389 static const struct phylink_mac_ops mt753x_phylink_mac_ops = { 3390 .mac_select_pcs = mt753x_phylink_mac_select_pcs, 3391 .mac_config = mt753x_phylink_mac_config, 3392 .mac_link_down = mt753x_phylink_mac_link_down, 3393 .mac_link_up = mt753x_phylink_mac_link_up, 3394 .mac_disable_tx_lpi = mt753x_phylink_mac_disable_tx_lpi, 3395 .mac_enable_tx_lpi = mt753x_phylink_mac_enable_tx_lpi, 3396 }; 3397 3398 const struct mt753x_info mt753x_table[] = { 3399 [ID_MT7621] = { 3400 .id = ID_MT7621, 3401 .pcs_ops = &mt7530_pcs_ops, 3402 .sw_setup = mt7530_setup, 3403 .phy_read_c22 = mt7530_phy_read_c22, 3404 .phy_write_c22 = mt7530_phy_write_c22, 3405 .phy_read_c45 = mt7530_phy_read_c45, 3406 .phy_write_c45 = mt7530_phy_write_c45, 3407 .mac_port_get_caps = mt7530_mac_port_get_caps, 3408 .mac_port_config = mt7530_mac_config, 3409 }, 3410 [ID_MT7530] = { 3411 .id = ID_MT7530, 3412 .pcs_ops = &mt7530_pcs_ops, 3413 .sw_setup = mt7530_setup, 3414 .phy_read_c22 = mt7530_phy_read_c22, 3415 .phy_write_c22 = mt7530_phy_write_c22, 3416 .phy_read_c45 = mt7530_phy_read_c45, 3417 .phy_write_c45 = mt7530_phy_write_c45, 3418 .mac_port_get_caps = mt7530_mac_port_get_caps, 3419 .mac_port_config = mt7530_mac_config, 3420 }, 3421 [ID_MT7531] = { 3422 .id = ID_MT7531, 3423 .pcs_ops = &mt7530_pcs_ops, 3424 .sw_setup = mt7531_setup, 3425 .phy_read_c22 = mt7531_ind_c22_phy_read, 3426 .phy_write_c22 = mt7531_ind_c22_phy_write, 3427 .phy_read_c45 = mt7531_ind_c45_phy_read, 3428 .phy_write_c45 = mt7531_ind_c45_phy_write, 3429 .mac_port_get_caps = mt7531_mac_port_get_caps, 3430 .mac_port_config = mt7531_mac_config, 3431 }, 3432 [ID_MT7988] = { 3433 .id = ID_MT7988, 3434 .pcs_ops = &mt7530_pcs_ops, 3435 .sw_setup = mt7988_setup, 3436 .phy_read_c22 = mt7531_ind_c22_phy_read, 3437 .phy_write_c22 = mt7531_ind_c22_phy_write, 3438 .phy_read_c45 = mt7531_ind_c45_phy_read, 3439 .phy_write_c45 = mt7531_ind_c45_phy_write, 3440 .mac_port_get_caps = mt7988_mac_port_get_caps, 3441 }, 3442 [ID_EN7581] = { 3443 .id = ID_EN7581, 3444 .pcs_ops = &mt7530_pcs_ops, 3445 .sw_setup = mt7988_setup, 3446 .phy_read_c22 = mt7531_ind_c22_phy_read, 3447 .phy_write_c22 = mt7531_ind_c22_phy_write, 3448 .phy_read_c45 = mt7531_ind_c45_phy_read, 3449 .phy_write_c45 = mt7531_ind_c45_phy_write, 3450 .mac_port_get_caps = en7581_mac_port_get_caps, 3451 }, 3452 [ID_AN7583] = { 3453 .id = ID_AN7583, 3454 .pcs_ops = &mt7530_pcs_ops, 3455 .sw_setup = mt7988_setup, 3456 .phy_read_c22 = mt7531_ind_c22_phy_read, 3457 .phy_write_c22 = mt7531_ind_c22_phy_write, 3458 .phy_read_c45 = mt7531_ind_c45_phy_read, 3459 .phy_write_c45 = mt7531_ind_c45_phy_write, 3460 .mac_port_get_caps = en7581_mac_port_get_caps, 3461 }, 3462 }; 3463 EXPORT_SYMBOL_GPL(mt753x_table); 3464 3465 int 3466 mt7530_probe_common(struct mt7530_priv *priv) 3467 { 3468 struct device *dev = priv->dev; 3469 3470 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL); 3471 if (!priv->ds) 3472 return -ENOMEM; 3473 3474 priv->ds->dev = dev; 3475 priv->ds->num_ports = MT7530_NUM_PORTS; 3476 3477 /* Get the hardware identifier from the devicetree node. 3478 * We will need it for some of the clock and regulator setup. 3479 */ 3480 priv->info = of_device_get_match_data(dev); 3481 if (!priv->info) 3482 return -EINVAL; 3483 3484 priv->id = priv->info->id; 3485 priv->dev = dev; 3486 priv->ds->priv = priv; 3487 priv->ds->ops = &mt7530_switch_ops; 3488 priv->ds->phylink_mac_ops = &mt753x_phylink_mac_ops; 3489 mutex_init(&priv->reg_mutex); 3490 spin_lock_init(&priv->stats_lock); 3491 INIT_DELAYED_WORK(&priv->stats_work, mt7530_stats_poll); 3492 3493 dev_set_drvdata(dev, priv); 3494 3495 return 0; 3496 } 3497 EXPORT_SYMBOL_GPL(mt7530_probe_common); 3498 3499 void 3500 mt7530_remove_common(struct mt7530_priv *priv) 3501 { 3502 if (priv->irq_domain) 3503 mt7530_free_mdio_irq(priv); 3504 3505 dsa_unregister_switch(priv->ds); 3506 3507 mutex_destroy(&priv->reg_mutex); 3508 } 3509 EXPORT_SYMBOL_GPL(mt7530_remove_common); 3510 3511 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 3512 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch"); 3513 MODULE_LICENSE("GPL"); 3514