xref: /linux/drivers/mmc/host/toshsd.h (revision a5eb8bbd66ccf9f169419f9652544aec771b7c57)
1*a5eb8bbdSOndrej Zary /*
2*a5eb8bbdSOndrej Zary  *  Toshiba PCI Secure Digital Host Controller Interface driver
3*a5eb8bbdSOndrej Zary  *
4*a5eb8bbdSOndrej Zary  *  Copyright (C) 2014 Ondrej Zary
5*a5eb8bbdSOndrej Zary  *  Copyright (C) 2007 Richard Betts, All Rights Reserved.
6*a5eb8bbdSOndrej Zary  *
7*a5eb8bbdSOndrej Zary  *      Based on asic3_mmc.c Copyright (c) 2005 SDG Systems, LLC
8*a5eb8bbdSOndrej Zary  *
9*a5eb8bbdSOndrej Zary  * This program is free software; you can redistribute it and/or modify
10*a5eb8bbdSOndrej Zary  * it under the terms of the GNU General Public License as published by
11*a5eb8bbdSOndrej Zary  * the Free Software Foundation; either version 2 of the License, or (at
12*a5eb8bbdSOndrej Zary  * your option) any later version.
13*a5eb8bbdSOndrej Zary  */
14*a5eb8bbdSOndrej Zary 
15*a5eb8bbdSOndrej Zary #define HCLK	33000000	/* 33 MHz (PCI clock) */
16*a5eb8bbdSOndrej Zary 
17*a5eb8bbdSOndrej Zary #define SD_PCICFG_CLKSTOP	0x40	/* 0x1f = clock controller, 0 = stop */
18*a5eb8bbdSOndrej Zary #define SD_PCICFG_GATEDCLK	0x41	/* Gated clock */
19*a5eb8bbdSOndrej Zary #define SD_PCICFG_CLKMODE	0x42	/* Control clock of SD controller */
20*a5eb8bbdSOndrej Zary #define SD_PCICFG_PINSTATUS	0x44	/* R/O: read status of SD pins */
21*a5eb8bbdSOndrej Zary #define SD_PCICFG_POWER1	0x48
22*a5eb8bbdSOndrej Zary #define SD_PCICFG_POWER2	0x49
23*a5eb8bbdSOndrej Zary #define SD_PCICFG_POWER3	0x4a
24*a5eb8bbdSOndrej Zary #define SD_PCICFG_CARDDETECT	0x4c
25*a5eb8bbdSOndrej Zary #define SD_PCICFG_SLOTS		0x50	/* R/O: define support slot number */
26*a5eb8bbdSOndrej Zary #define SD_PCICFG_EXTGATECLK1	0xf0	/* Could be used for gated clock */
27*a5eb8bbdSOndrej Zary #define SD_PCICFG_EXTGATECLK2	0xf1	/* Could be used for gated clock */
28*a5eb8bbdSOndrej Zary #define SD_PCICFG_EXTGATECLK3	0xf9	/* Bit 1: double buffer/single buffer */
29*a5eb8bbdSOndrej Zary #define SD_PCICFG_SDLED_ENABLE1	0xfa
30*a5eb8bbdSOndrej Zary #define SD_PCICFG_SDLED_ENABLE2	0xfe
31*a5eb8bbdSOndrej Zary 
32*a5eb8bbdSOndrej Zary #define SD_PCICFG_CLKMODE_DIV_DISABLE	BIT(0)
33*a5eb8bbdSOndrej Zary #define SD_PCICFG_CLKSTOP_ENABLE_ALL	0x1f
34*a5eb8bbdSOndrej Zary #define SD_PCICFG_LED_ENABLE1_START	0x12
35*a5eb8bbdSOndrej Zary #define SD_PCICFG_LED_ENABLE2_START	0x80
36*a5eb8bbdSOndrej Zary 
37*a5eb8bbdSOndrej Zary #define SD_PCICFG_PWR1_33V	0x08	/* Set for 3.3 volts */
38*a5eb8bbdSOndrej Zary #define SD_PCICFG_PWR1_OFF	0x00	/* Turn off power */
39*a5eb8bbdSOndrej Zary #define SD_PCICFG_PWR2_AUTO	0x02
40*a5eb8bbdSOndrej Zary 
41*a5eb8bbdSOndrej Zary #define SD_CMD			0x00	/* also for SDIO */
42*a5eb8bbdSOndrej Zary #define SD_ARG0			0x04	/* also for SDIO */
43*a5eb8bbdSOndrej Zary #define SD_ARG1			0x06	/* also for SDIO */
44*a5eb8bbdSOndrej Zary #define SD_STOPINTERNAL		0x08
45*a5eb8bbdSOndrej Zary #define SD_BLOCKCOUNT		0x0a	/* also for SDIO */
46*a5eb8bbdSOndrej Zary #define SD_RESPONSE0		0x0c	/* also for SDIO */
47*a5eb8bbdSOndrej Zary #define SD_RESPONSE1		0x0e	/* also for SDIO */
48*a5eb8bbdSOndrej Zary #define SD_RESPONSE2		0x10	/* also for SDIO */
49*a5eb8bbdSOndrej Zary #define SD_RESPONSE3		0x12	/* also for SDIO */
50*a5eb8bbdSOndrej Zary #define SD_RESPONSE4		0x14	/* also for SDIO */
51*a5eb8bbdSOndrej Zary #define SD_RESPONSE5		0x16	/* also for SDIO */
52*a5eb8bbdSOndrej Zary #define SD_RESPONSE6		0x18	/* also for SDIO */
53*a5eb8bbdSOndrej Zary #define SD_RESPONSE7		0x1a	/* also for SDIO */
54*a5eb8bbdSOndrej Zary #define SD_CARDSTATUS		0x1c	/* also for SDIO */
55*a5eb8bbdSOndrej Zary #define SD_BUFFERCTRL		0x1e	/* also for SDIO */
56*a5eb8bbdSOndrej Zary #define SD_INTMASKCARD		0x20	/* also for SDIO */
57*a5eb8bbdSOndrej Zary #define SD_INTMASKBUFFER	0x22	/* also for SDIO */
58*a5eb8bbdSOndrej Zary #define SD_CARDCLOCKCTRL	0x24
59*a5eb8bbdSOndrej Zary #define SD_CARDXFERDATALEN	0x26	/* also for SDIO */
60*a5eb8bbdSOndrej Zary #define SD_CARDOPTIONSETUP	0x28	/* also for SDIO */
61*a5eb8bbdSOndrej Zary #define SD_ERRORSTATUS0		0x2c	/* also for SDIO */
62*a5eb8bbdSOndrej Zary #define SD_ERRORSTATUS1		0x2e	/* also for SDIO */
63*a5eb8bbdSOndrej Zary #define SD_DATAPORT		0x30	/* also for SDIO */
64*a5eb8bbdSOndrej Zary #define SD_TRANSACTIONCTRL	0x34	/* also for SDIO */
65*a5eb8bbdSOndrej Zary #define SD_SOFTWARERESET	0xe0	/* also for SDIO */
66*a5eb8bbdSOndrej Zary 
67*a5eb8bbdSOndrej Zary /* registers above marked "also for SDIO" and all SDIO registers below can be
68*a5eb8bbdSOndrej Zary  * accessed at SDIO_BASE + reg address */
69*a5eb8bbdSOndrej Zary #define SDIO_BASE	 0x100
70*a5eb8bbdSOndrej Zary 
71*a5eb8bbdSOndrej Zary #define SDIO_CARDPORTSEL	0x02
72*a5eb8bbdSOndrej Zary #define SDIO_CARDINTCTRL	0x36
73*a5eb8bbdSOndrej Zary #define SDIO_CLOCKNWAITCTRL	0x38
74*a5eb8bbdSOndrej Zary #define SDIO_HOSTINFORMATION	0x3a
75*a5eb8bbdSOndrej Zary #define SDIO_ERRORCTRL		0x3c
76*a5eb8bbdSOndrej Zary #define SDIO_LEDCTRL		0x3e
77*a5eb8bbdSOndrej Zary 
78*a5eb8bbdSOndrej Zary #define SD_TRANSCTL_SET		BIT(8)
79*a5eb8bbdSOndrej Zary 
80*a5eb8bbdSOndrej Zary #define SD_CARDCLK_DIV_DISABLE	BIT(15)
81*a5eb8bbdSOndrej Zary #define SD_CARDCLK_ENABLE_CLOCK	BIT(8)
82*a5eb8bbdSOndrej Zary #define SD_CARDCLK_CLK_DIV_512	BIT(7)
83*a5eb8bbdSOndrej Zary #define SD_CARDCLK_CLK_DIV_256	BIT(6)
84*a5eb8bbdSOndrej Zary #define SD_CARDCLK_CLK_DIV_128	BIT(5)
85*a5eb8bbdSOndrej Zary #define SD_CARDCLK_CLK_DIV_64	BIT(4)
86*a5eb8bbdSOndrej Zary #define SD_CARDCLK_CLK_DIV_32	BIT(3)
87*a5eb8bbdSOndrej Zary #define SD_CARDCLK_CLK_DIV_16	BIT(2)
88*a5eb8bbdSOndrej Zary #define SD_CARDCLK_CLK_DIV_8	BIT(1)
89*a5eb8bbdSOndrej Zary #define SD_CARDCLK_CLK_DIV_4	BIT(0)
90*a5eb8bbdSOndrej Zary #define SD_CARDCLK_CLK_DIV_2	0
91*a5eb8bbdSOndrej Zary 
92*a5eb8bbdSOndrej Zary #define SD_CARDOPT_REQUIRED		0x000e
93*a5eb8bbdSOndrej Zary #define SD_CARDOPT_DATA_RESP_TIMEOUT(x)	(((x) & 0x0f) << 4) /* 4 bits */
94*a5eb8bbdSOndrej Zary #define SD_CARDOPT_C2_MODULE_ABSENT	BIT(14)
95*a5eb8bbdSOndrej Zary #define SD_CARDOPT_DATA_XFR_WIDTH_1	(1 << 15)
96*a5eb8bbdSOndrej Zary #define SD_CARDOPT_DATA_XFR_WIDTH_4	(0 << 15)
97*a5eb8bbdSOndrej Zary 
98*a5eb8bbdSOndrej Zary #define SD_CMD_TYPE_CMD			(0 << 6)
99*a5eb8bbdSOndrej Zary #define SD_CMD_TYPE_ACMD		(1 << 6)
100*a5eb8bbdSOndrej Zary #define SD_CMD_TYPE_AUTHEN		(2 << 6)
101*a5eb8bbdSOndrej Zary #define SD_CMD_RESP_TYPE_NONE		(3 << 8)
102*a5eb8bbdSOndrej Zary #define SD_CMD_RESP_TYPE_EXT_R1		(4 << 8)
103*a5eb8bbdSOndrej Zary #define SD_CMD_RESP_TYPE_EXT_R1B	(5 << 8)
104*a5eb8bbdSOndrej Zary #define SD_CMD_RESP_TYPE_EXT_R2		(6 << 8)
105*a5eb8bbdSOndrej Zary #define SD_CMD_RESP_TYPE_EXT_R3		(7 << 8)
106*a5eb8bbdSOndrej Zary #define SD_CMD_RESP_TYPE_EXT_R6		(4 << 8)
107*a5eb8bbdSOndrej Zary #define SD_CMD_RESP_TYPE_EXT_R7		(4 << 8)
108*a5eb8bbdSOndrej Zary #define SD_CMD_DATA_PRESENT		BIT(11)
109*a5eb8bbdSOndrej Zary #define SD_CMD_TRANSFER_READ		BIT(12)
110*a5eb8bbdSOndrej Zary #define SD_CMD_MULTI_BLOCK		BIT(13)
111*a5eb8bbdSOndrej Zary #define SD_CMD_SECURITY_CMD		BIT(14)
112*a5eb8bbdSOndrej Zary 
113*a5eb8bbdSOndrej Zary #define SD_STOPINT_ISSUE_CMD12		BIT(0)
114*a5eb8bbdSOndrej Zary #define SD_STOPINT_AUTO_ISSUE_CMD12	BIT(8)
115*a5eb8bbdSOndrej Zary 
116*a5eb8bbdSOndrej Zary #define SD_CARD_RESP_END	BIT(0)
117*a5eb8bbdSOndrej Zary #define SD_CARD_RW_END		BIT(2)
118*a5eb8bbdSOndrej Zary #define SD_CARD_CARD_REMOVED_0	BIT(3)
119*a5eb8bbdSOndrej Zary #define SD_CARD_CARD_INSERTED_0	BIT(4)
120*a5eb8bbdSOndrej Zary #define SD_CARD_PRESENT_0	BIT(5)
121*a5eb8bbdSOndrej Zary #define SD_CARD_UNK6		BIT(6)
122*a5eb8bbdSOndrej Zary #define SD_CARD_WRITE_PROTECT	BIT(7)
123*a5eb8bbdSOndrej Zary #define SD_CARD_CARD_REMOVED_3	BIT(8)
124*a5eb8bbdSOndrej Zary #define SD_CARD_CARD_INSERTED_3	BIT(9)
125*a5eb8bbdSOndrej Zary #define SD_CARD_PRESENT_3	BIT(10)
126*a5eb8bbdSOndrej Zary 
127*a5eb8bbdSOndrej Zary #define SD_BUF_CMD_INDEX_ERR	BIT(16)
128*a5eb8bbdSOndrej Zary #define SD_BUF_CRC_ERR		BIT(17)
129*a5eb8bbdSOndrej Zary #define SD_BUF_STOP_BIT_END_ERR	BIT(18)
130*a5eb8bbdSOndrej Zary #define SD_BUF_DATA_TIMEOUT	BIT(19)
131*a5eb8bbdSOndrej Zary #define SD_BUF_OVERFLOW		BIT(20)
132*a5eb8bbdSOndrej Zary #define SD_BUF_UNDERFLOW	BIT(21)
133*a5eb8bbdSOndrej Zary #define SD_BUF_CMD_TIMEOUT	BIT(22)
134*a5eb8bbdSOndrej Zary #define SD_BUF_UNK7		BIT(23)
135*a5eb8bbdSOndrej Zary #define SD_BUF_READ_ENABLE	BIT(24)
136*a5eb8bbdSOndrej Zary #define SD_BUF_WRITE_ENABLE	BIT(25)
137*a5eb8bbdSOndrej Zary #define SD_BUF_ILLEGAL_FUNCTION	BIT(29)
138*a5eb8bbdSOndrej Zary #define SD_BUF_CMD_BUSY		BIT(30)
139*a5eb8bbdSOndrej Zary #define SD_BUF_ILLEGAL_ACCESS	BIT(31)
140*a5eb8bbdSOndrej Zary 
141*a5eb8bbdSOndrej Zary #define SD_ERR0_RESP_CMD_ERR			BIT(0)
142*a5eb8bbdSOndrej Zary #define SD_ERR0_RESP_NON_CMD12_END_BIT_ERR	BIT(2)
143*a5eb8bbdSOndrej Zary #define SD_ERR0_RESP_CMD12_END_BIT_ERR		BIT(3)
144*a5eb8bbdSOndrej Zary #define SD_ERR0_READ_DATA_END_BIT_ERR		BIT(4)
145*a5eb8bbdSOndrej Zary #define SD_ERR0_WRITE_CRC_STATUS_END_BIT_ERR	BIT(5)
146*a5eb8bbdSOndrej Zary #define SD_ERR0_RESP_NON_CMD12_CRC_ERR		BIT(8)
147*a5eb8bbdSOndrej Zary #define SD_ERR0_RESP_CMD12_CRC_ERR		BIT(9)
148*a5eb8bbdSOndrej Zary #define SD_ERR0_READ_DATA_CRC_ERR		BIT(10)
149*a5eb8bbdSOndrej Zary #define SD_ERR0_WRITE_CMD_CRC_ERR		BIT(11)
150*a5eb8bbdSOndrej Zary 
151*a5eb8bbdSOndrej Zary #define SD_ERR1_NO_CMD_RESP		BIT(16)
152*a5eb8bbdSOndrej Zary #define SD_ERR1_TIMEOUT_READ_DATA	BIT(20)
153*a5eb8bbdSOndrej Zary #define SD_ERR1_TIMEOUT_CRS_STATUS	BIT(21)
154*a5eb8bbdSOndrej Zary #define SD_ERR1_TIMEOUT_CRC_BUSY	BIT(22)
155*a5eb8bbdSOndrej Zary 
156*a5eb8bbdSOndrej Zary #define IRQ_DONT_CARE_BITS (SD_CARD_PRESENT_3 \
157*a5eb8bbdSOndrej Zary 	| SD_CARD_WRITE_PROTECT \
158*a5eb8bbdSOndrej Zary 	| SD_CARD_UNK6 \
159*a5eb8bbdSOndrej Zary 	| SD_CARD_PRESENT_0 \
160*a5eb8bbdSOndrej Zary 	| SD_BUF_UNK7 \
161*a5eb8bbdSOndrej Zary 	| SD_BUF_CMD_BUSY)
162*a5eb8bbdSOndrej Zary 
163*a5eb8bbdSOndrej Zary struct toshsd_host {
164*a5eb8bbdSOndrej Zary 	struct pci_dev *pdev;
165*a5eb8bbdSOndrej Zary 	struct mmc_host *mmc;
166*a5eb8bbdSOndrej Zary 
167*a5eb8bbdSOndrej Zary 	spinlock_t lock;
168*a5eb8bbdSOndrej Zary 
169*a5eb8bbdSOndrej Zary 	struct mmc_request *mrq;/* Current request */
170*a5eb8bbdSOndrej Zary 	struct mmc_command *cmd;/* Current command */
171*a5eb8bbdSOndrej Zary 	struct mmc_data *data;	/* Current data request */
172*a5eb8bbdSOndrej Zary 
173*a5eb8bbdSOndrej Zary 	struct sg_mapping_iter sg_miter; /* for PIO */
174*a5eb8bbdSOndrej Zary 
175*a5eb8bbdSOndrej Zary 	void __iomem *ioaddr; /* mapped address */
176*a5eb8bbdSOndrej Zary };
177