1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014-2015 MediaTek Inc. 4 * Author: Chaotian.Jing <chaotian.jing@mediatek.com> 5 */ 6 7 #include <linux/module.h> 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/ioport.h> 12 #include <linux/irq.h> 13 #include <linux/of_address.h> 14 #include <linux/of_device.h> 15 #include <linux/of_irq.h> 16 #include <linux/of_gpio.h> 17 #include <linux/pinctrl/consumer.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/regulator/consumer.h> 22 #include <linux/slab.h> 23 #include <linux/spinlock.h> 24 #include <linux/interrupt.h> 25 #include <linux/reset.h> 26 27 #include <linux/mmc/card.h> 28 #include <linux/mmc/core.h> 29 #include <linux/mmc/host.h> 30 #include <linux/mmc/mmc.h> 31 #include <linux/mmc/sd.h> 32 #include <linux/mmc/sdio.h> 33 #include <linux/mmc/slot-gpio.h> 34 35 #include "cqhci.h" 36 37 #define MAX_BD_NUM 1024 38 #define MSDC_NR_CLOCKS 3 39 40 /*--------------------------------------------------------------------------*/ 41 /* Common Definition */ 42 /*--------------------------------------------------------------------------*/ 43 #define MSDC_BUS_1BITS 0x0 44 #define MSDC_BUS_4BITS 0x1 45 #define MSDC_BUS_8BITS 0x2 46 47 #define MSDC_BURST_64B 0x6 48 49 /*--------------------------------------------------------------------------*/ 50 /* Register Offset */ 51 /*--------------------------------------------------------------------------*/ 52 #define MSDC_CFG 0x0 53 #define MSDC_IOCON 0x04 54 #define MSDC_PS 0x08 55 #define MSDC_INT 0x0c 56 #define MSDC_INTEN 0x10 57 #define MSDC_FIFOCS 0x14 58 #define SDC_CFG 0x30 59 #define SDC_CMD 0x34 60 #define SDC_ARG 0x38 61 #define SDC_STS 0x3c 62 #define SDC_RESP0 0x40 63 #define SDC_RESP1 0x44 64 #define SDC_RESP2 0x48 65 #define SDC_RESP3 0x4c 66 #define SDC_BLK_NUM 0x50 67 #define SDC_ADV_CFG0 0x64 68 #define EMMC_IOCON 0x7c 69 #define SDC_ACMD_RESP 0x80 70 #define DMA_SA_H4BIT 0x8c 71 #define MSDC_DMA_SA 0x90 72 #define MSDC_DMA_CTRL 0x98 73 #define MSDC_DMA_CFG 0x9c 74 #define MSDC_PATCH_BIT 0xb0 75 #define MSDC_PATCH_BIT1 0xb4 76 #define MSDC_PATCH_BIT2 0xb8 77 #define MSDC_PAD_TUNE 0xec 78 #define MSDC_PAD_TUNE0 0xf0 79 #define PAD_DS_TUNE 0x188 80 #define PAD_CMD_TUNE 0x18c 81 #define EMMC51_CFG0 0x204 82 #define EMMC50_CFG0 0x208 83 #define EMMC50_CFG1 0x20c 84 #define EMMC50_CFG3 0x220 85 #define SDC_FIFO_CFG 0x228 86 #define CQHCI_SETTING 0x7fc 87 88 /*--------------------------------------------------------------------------*/ 89 /* Top Pad Register Offset */ 90 /*--------------------------------------------------------------------------*/ 91 #define EMMC_TOP_CONTROL 0x00 92 #define EMMC_TOP_CMD 0x04 93 #define EMMC50_PAD_DS_TUNE 0x0c 94 95 /*--------------------------------------------------------------------------*/ 96 /* Register Mask */ 97 /*--------------------------------------------------------------------------*/ 98 99 /* MSDC_CFG mask */ 100 #define MSDC_CFG_MODE (0x1 << 0) /* RW */ 101 #define MSDC_CFG_CKPDN (0x1 << 1) /* RW */ 102 #define MSDC_CFG_RST (0x1 << 2) /* RW */ 103 #define MSDC_CFG_PIO (0x1 << 3) /* RW */ 104 #define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */ 105 #define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */ 106 #define MSDC_CFG_BV18PSS (0x1 << 6) /* R */ 107 #define MSDC_CFG_CKSTB (0x1 << 7) /* R */ 108 #define MSDC_CFG_CKDIV (0xff << 8) /* RW */ 109 #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */ 110 #define MSDC_CFG_HS400_CK_MODE (0x1 << 18) /* RW */ 111 #define MSDC_CFG_HS400_CK_MODE_EXTRA (0x1 << 22) /* RW */ 112 #define MSDC_CFG_CKDIV_EXTRA (0xfff << 8) /* RW */ 113 #define MSDC_CFG_CKMOD_EXTRA (0x3 << 20) /* RW */ 114 115 /* MSDC_IOCON mask */ 116 #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */ 117 #define MSDC_IOCON_RSPL (0x1 << 1) /* RW */ 118 #define MSDC_IOCON_DSPL (0x1 << 2) /* RW */ 119 #define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */ 120 #define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */ 121 #define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */ 122 #define MSDC_IOCON_W_DSPL (0x1 << 8) /* RW */ 123 #define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */ 124 #define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */ 125 #define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */ 126 #define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */ 127 #define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */ 128 #define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */ 129 #define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */ 130 #define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */ 131 #define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */ 132 133 /* MSDC_PS mask */ 134 #define MSDC_PS_CDEN (0x1 << 0) /* RW */ 135 #define MSDC_PS_CDSTS (0x1 << 1) /* R */ 136 #define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */ 137 #define MSDC_PS_DAT (0xff << 16) /* R */ 138 #define MSDC_PS_DATA1 (0x1 << 17) /* R */ 139 #define MSDC_PS_CMD (0x1 << 24) /* R */ 140 #define MSDC_PS_WP (0x1 << 31) /* R */ 141 142 /* MSDC_INT mask */ 143 #define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */ 144 #define MSDC_INT_CDSC (0x1 << 1) /* W1C */ 145 #define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */ 146 #define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */ 147 #define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */ 148 #define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */ 149 #define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */ 150 #define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */ 151 #define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */ 152 #define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */ 153 #define MSDC_INT_CSTA (0x1 << 11) /* R */ 154 #define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */ 155 #define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */ 156 #define MSDC_INT_DATTMO (0x1 << 14) /* W1C */ 157 #define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */ 158 #define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */ 159 #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */ 160 #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */ 161 #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */ 162 #define MSDC_INT_CMDQ (0x1 << 28) /* W1C */ 163 164 /* MSDC_INTEN mask */ 165 #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */ 166 #define MSDC_INTEN_CDSC (0x1 << 1) /* RW */ 167 #define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */ 168 #define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */ 169 #define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */ 170 #define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */ 171 #define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */ 172 #define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */ 173 #define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */ 174 #define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */ 175 #define MSDC_INTEN_CSTA (0x1 << 11) /* RW */ 176 #define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */ 177 #define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */ 178 #define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */ 179 #define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */ 180 #define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */ 181 #define MSDC_INTEN_DMA_BDCSERR (0x1 << 17) /* RW */ 182 #define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18) /* RW */ 183 #define MSDC_INTEN_DMA_PROTECT (0x1 << 19) /* RW */ 184 185 /* MSDC_FIFOCS mask */ 186 #define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */ 187 #define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */ 188 #define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */ 189 190 /* SDC_CFG mask */ 191 #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */ 192 #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */ 193 #define SDC_CFG_WRDTOC (0x1fff << 2) /* RW */ 194 #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */ 195 #define SDC_CFG_SDIO (0x1 << 19) /* RW */ 196 #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */ 197 #define SDC_CFG_INTATGAP (0x1 << 21) /* RW */ 198 #define SDC_CFG_DTOC (0xff << 24) /* RW */ 199 200 /* SDC_STS mask */ 201 #define SDC_STS_SDCBUSY (0x1 << 0) /* RW */ 202 #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */ 203 #define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */ 204 205 #define SDC_DAT1_IRQ_TRIGGER (0x1 << 19) /* RW */ 206 /* SDC_ADV_CFG0 mask */ 207 #define SDC_RX_ENHANCE_EN (0x1 << 20) /* RW */ 208 209 /* DMA_SA_H4BIT mask */ 210 #define DMA_ADDR_HIGH_4BIT (0xf << 0) /* RW */ 211 212 /* MSDC_DMA_CTRL mask */ 213 #define MSDC_DMA_CTRL_START (0x1 << 0) /* W */ 214 #define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */ 215 #define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */ 216 #define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */ 217 #define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */ 218 #define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */ 219 220 /* MSDC_DMA_CFG mask */ 221 #define MSDC_DMA_CFG_STS (0x1 << 0) /* R */ 222 #define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */ 223 #define MSDC_DMA_CFG_AHBHPROT2 (0x2 << 8) /* RW */ 224 #define MSDC_DMA_CFG_ACTIVEEN (0x2 << 12) /* RW */ 225 #define MSDC_DMA_CFG_CS12B16B (0x1 << 16) /* RW */ 226 227 /* MSDC_PATCH_BIT mask */ 228 #define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */ 229 #define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7) 230 #define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10) 231 #define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */ 232 #define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */ 233 #define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */ 234 #define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */ 235 #define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */ 236 #define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */ 237 #define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */ 238 #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */ 239 #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ 240 241 #define MSDC_PATCH_BIT1_CMDTA (0x7 << 3) /* RW */ 242 #define MSDC_PB1_BUSY_CHECK_SEL (0x1 << 7) /* RW */ 243 #define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */ 244 245 #define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */ 246 #define MSDC_PATCH_BIT2_CFGCRCSTS (0x1 << 28) /* RW */ 247 #define MSDC_PB2_SUPPORT_64G (0x1 << 1) /* RW */ 248 #define MSDC_PB2_RESPWAIT (0x3 << 2) /* RW */ 249 #define MSDC_PB2_RESPSTSENSEL (0x7 << 16) /* RW */ 250 #define MSDC_PB2_CRCSTSENSEL (0x7 << 29) /* RW */ 251 252 #define MSDC_PAD_TUNE_DATWRDLY (0x1f << 0) /* RW */ 253 #define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */ 254 #define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */ 255 #define MSDC_PAD_TUNE_CMDRRDLY (0x1f << 22) /* RW */ 256 #define MSDC_PAD_TUNE_CLKTDLY (0x1f << 27) /* RW */ 257 #define MSDC_PAD_TUNE_RXDLYSEL (0x1 << 15) /* RW */ 258 #define MSDC_PAD_TUNE_RD_SEL (0x1 << 13) /* RW */ 259 #define MSDC_PAD_TUNE_CMD_SEL (0x1 << 21) /* RW */ 260 261 #define PAD_DS_TUNE_DLY1 (0x1f << 2) /* RW */ 262 #define PAD_DS_TUNE_DLY2 (0x1f << 7) /* RW */ 263 #define PAD_DS_TUNE_DLY3 (0x1f << 12) /* RW */ 264 265 #define PAD_CMD_TUNE_RX_DLY3 (0x1f << 1) /* RW */ 266 267 /* EMMC51_CFG0 mask */ 268 #define CMDQ_RDAT_CNT (0x3ff << 12) /* RW */ 269 270 #define EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0) /* RW */ 271 #define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */ 272 #define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */ 273 #define EMMC50_CFG_CMD_RESP_SEL (0x1 << 9) /* RW */ 274 275 /* EMMC50_CFG1 mask */ 276 #define EMMC50_CFG1_DS_CFG (0x1 << 28) /* RW */ 277 278 #define EMMC50_CFG3_OUTS_WR (0x1f << 0) /* RW */ 279 280 #define SDC_FIFO_CFG_WRVALIDSEL (0x1 << 24) /* RW */ 281 #define SDC_FIFO_CFG_RDVALIDSEL (0x1 << 25) /* RW */ 282 283 /* CQHCI_SETTING */ 284 #define CQHCI_RD_CMD_WND_SEL (0x1 << 14) /* RW */ 285 #define CQHCI_WR_CMD_WND_SEL (0x1 << 15) /* RW */ 286 287 /* EMMC_TOP_CONTROL mask */ 288 #define PAD_RXDLY_SEL (0x1 << 0) /* RW */ 289 #define DELAY_EN (0x1 << 1) /* RW */ 290 #define PAD_DAT_RD_RXDLY2 (0x1f << 2) /* RW */ 291 #define PAD_DAT_RD_RXDLY (0x1f << 7) /* RW */ 292 #define PAD_DAT_RD_RXDLY2_SEL (0x1 << 12) /* RW */ 293 #define PAD_DAT_RD_RXDLY_SEL (0x1 << 13) /* RW */ 294 #define DATA_K_VALUE_SEL (0x1 << 14) /* RW */ 295 #define SDC_RX_ENH_EN (0x1 << 15) /* TW */ 296 297 /* EMMC_TOP_CMD mask */ 298 #define PAD_CMD_RXDLY2 (0x1f << 0) /* RW */ 299 #define PAD_CMD_RXDLY (0x1f << 5) /* RW */ 300 #define PAD_CMD_RD_RXDLY2_SEL (0x1 << 10) /* RW */ 301 #define PAD_CMD_RD_RXDLY_SEL (0x1 << 11) /* RW */ 302 #define PAD_CMD_TX_DLY (0x1f << 12) /* RW */ 303 304 #define REQ_CMD_EIO (0x1 << 0) 305 #define REQ_CMD_TMO (0x1 << 1) 306 #define REQ_DAT_ERR (0x1 << 2) 307 #define REQ_STOP_EIO (0x1 << 3) 308 #define REQ_STOP_TMO (0x1 << 4) 309 #define REQ_CMD_BUSY (0x1 << 5) 310 311 #define MSDC_PREPARE_FLAG (0x1 << 0) 312 #define MSDC_ASYNC_FLAG (0x1 << 1) 313 #define MSDC_MMAP_FLAG (0x1 << 2) 314 315 #define MTK_MMC_AUTOSUSPEND_DELAY 50 316 #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */ 317 #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */ 318 319 #define DEFAULT_DEBOUNCE (8) /* 8 cycles CD debounce */ 320 321 #define PAD_DELAY_MAX 32 /* PAD delay cells */ 322 /*--------------------------------------------------------------------------*/ 323 /* Descriptor Structure */ 324 /*--------------------------------------------------------------------------*/ 325 struct mt_gpdma_desc { 326 u32 gpd_info; 327 #define GPDMA_DESC_HWO (0x1 << 0) 328 #define GPDMA_DESC_BDP (0x1 << 1) 329 #define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 330 #define GPDMA_DESC_INT (0x1 << 16) 331 #define GPDMA_DESC_NEXT_H4 (0xf << 24) 332 #define GPDMA_DESC_PTR_H4 (0xf << 28) 333 u32 next; 334 u32 ptr; 335 u32 gpd_data_len; 336 #define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 337 #define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */ 338 u32 arg; 339 u32 blknum; 340 u32 cmd; 341 }; 342 343 struct mt_bdma_desc { 344 u32 bd_info; 345 #define BDMA_DESC_EOL (0x1 << 0) 346 #define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 347 #define BDMA_DESC_BLKPAD (0x1 << 17) 348 #define BDMA_DESC_DWPAD (0x1 << 18) 349 #define BDMA_DESC_NEXT_H4 (0xf << 24) 350 #define BDMA_DESC_PTR_H4 (0xf << 28) 351 u32 next; 352 u32 ptr; 353 u32 bd_data_len; 354 #define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 355 #define BDMA_DESC_BUFLEN_EXT (0xffffff) /* bit0 ~ bit23 */ 356 }; 357 358 struct msdc_dma { 359 struct scatterlist *sg; /* I/O scatter list */ 360 struct mt_gpdma_desc *gpd; /* pointer to gpd array */ 361 struct mt_bdma_desc *bd; /* pointer to bd array */ 362 dma_addr_t gpd_addr; /* the physical address of gpd array */ 363 dma_addr_t bd_addr; /* the physical address of bd array */ 364 }; 365 366 struct msdc_save_para { 367 u32 msdc_cfg; 368 u32 iocon; 369 u32 sdc_cfg; 370 u32 pad_tune; 371 u32 patch_bit0; 372 u32 patch_bit1; 373 u32 patch_bit2; 374 u32 pad_ds_tune; 375 u32 pad_cmd_tune; 376 u32 emmc50_cfg0; 377 u32 emmc50_cfg3; 378 u32 sdc_fifo_cfg; 379 u32 emmc_top_control; 380 u32 emmc_top_cmd; 381 u32 emmc50_pad_ds_tune; 382 }; 383 384 struct mtk_mmc_compatible { 385 u8 clk_div_bits; 386 bool recheck_sdio_irq; 387 bool hs400_tune; /* only used for MT8173 */ 388 u32 pad_tune_reg; 389 bool async_fifo; 390 bool data_tune; 391 bool busy_check; 392 bool stop_clk_fix; 393 bool enhance_rx; 394 bool support_64g; 395 bool use_internal_cd; 396 }; 397 398 struct msdc_tune_para { 399 u32 iocon; 400 u32 pad_tune; 401 u32 pad_cmd_tune; 402 u32 emmc_top_control; 403 u32 emmc_top_cmd; 404 }; 405 406 struct msdc_delay_phase { 407 u8 maxlen; 408 u8 start; 409 u8 final_phase; 410 }; 411 412 struct msdc_host { 413 struct device *dev; 414 const struct mtk_mmc_compatible *dev_comp; 415 int cmd_rsp; 416 417 spinlock_t lock; 418 struct mmc_request *mrq; 419 struct mmc_command *cmd; 420 struct mmc_data *data; 421 int error; 422 423 void __iomem *base; /* host base address */ 424 void __iomem *top_base; /* host top register base address */ 425 426 struct msdc_dma dma; /* dma channel */ 427 u64 dma_mask; 428 429 u32 timeout_ns; /* data timeout ns */ 430 u32 timeout_clks; /* data timeout clks */ 431 432 struct pinctrl *pinctrl; 433 struct pinctrl_state *pins_default; 434 struct pinctrl_state *pins_uhs; 435 struct delayed_work req_timeout; 436 int irq; /* host interrupt */ 437 struct reset_control *reset; 438 439 struct clk *src_clk; /* msdc source clock */ 440 struct clk *h_clk; /* msdc h_clk */ 441 struct clk *bus_clk; /* bus clock which used to access register */ 442 struct clk *src_clk_cg; /* msdc source clock control gate */ 443 struct clk *sys_clk_cg; /* msdc subsys clock control gate */ 444 struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS]; 445 u32 mclk; /* mmc subsystem clock frequency */ 446 u32 src_clk_freq; /* source clock frequency */ 447 unsigned char timing; 448 bool vqmmc_enabled; 449 u32 latch_ck; 450 u32 hs400_ds_delay; 451 u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */ 452 u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */ 453 bool hs400_cmd_resp_sel_rising; 454 /* cmd response sample selection for HS400 */ 455 bool hs400_mode; /* current eMMC will run at hs400 mode */ 456 bool internal_cd; /* Use internal card-detect logic */ 457 bool cqhci; /* support eMMC hw cmdq */ 458 struct msdc_save_para save_para; /* used when gate HCLK */ 459 struct msdc_tune_para def_tune_para; /* default tune setting */ 460 struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */ 461 struct cqhci_host *cq_host; 462 }; 463 464 static const struct mtk_mmc_compatible mt8135_compat = { 465 .clk_div_bits = 8, 466 .recheck_sdio_irq = true, 467 .hs400_tune = false, 468 .pad_tune_reg = MSDC_PAD_TUNE, 469 .async_fifo = false, 470 .data_tune = false, 471 .busy_check = false, 472 .stop_clk_fix = false, 473 .enhance_rx = false, 474 .support_64g = false, 475 }; 476 477 static const struct mtk_mmc_compatible mt8173_compat = { 478 .clk_div_bits = 8, 479 .recheck_sdio_irq = true, 480 .hs400_tune = true, 481 .pad_tune_reg = MSDC_PAD_TUNE, 482 .async_fifo = false, 483 .data_tune = false, 484 .busy_check = false, 485 .stop_clk_fix = false, 486 .enhance_rx = false, 487 .support_64g = false, 488 }; 489 490 static const struct mtk_mmc_compatible mt8183_compat = { 491 .clk_div_bits = 12, 492 .recheck_sdio_irq = false, 493 .hs400_tune = false, 494 .pad_tune_reg = MSDC_PAD_TUNE0, 495 .async_fifo = true, 496 .data_tune = true, 497 .busy_check = true, 498 .stop_clk_fix = true, 499 .enhance_rx = true, 500 .support_64g = true, 501 }; 502 503 static const struct mtk_mmc_compatible mt2701_compat = { 504 .clk_div_bits = 12, 505 .recheck_sdio_irq = true, 506 .hs400_tune = false, 507 .pad_tune_reg = MSDC_PAD_TUNE0, 508 .async_fifo = true, 509 .data_tune = true, 510 .busy_check = false, 511 .stop_clk_fix = false, 512 .enhance_rx = false, 513 .support_64g = false, 514 }; 515 516 static const struct mtk_mmc_compatible mt2712_compat = { 517 .clk_div_bits = 12, 518 .recheck_sdio_irq = false, 519 .hs400_tune = false, 520 .pad_tune_reg = MSDC_PAD_TUNE0, 521 .async_fifo = true, 522 .data_tune = true, 523 .busy_check = true, 524 .stop_clk_fix = true, 525 .enhance_rx = true, 526 .support_64g = true, 527 }; 528 529 static const struct mtk_mmc_compatible mt7622_compat = { 530 .clk_div_bits = 12, 531 .recheck_sdio_irq = true, 532 .hs400_tune = false, 533 .pad_tune_reg = MSDC_PAD_TUNE0, 534 .async_fifo = true, 535 .data_tune = true, 536 .busy_check = true, 537 .stop_clk_fix = true, 538 .enhance_rx = true, 539 .support_64g = false, 540 }; 541 542 static const struct mtk_mmc_compatible mt8516_compat = { 543 .clk_div_bits = 12, 544 .recheck_sdio_irq = true, 545 .hs400_tune = false, 546 .pad_tune_reg = MSDC_PAD_TUNE0, 547 .async_fifo = true, 548 .data_tune = true, 549 .busy_check = true, 550 .stop_clk_fix = true, 551 }; 552 553 static const struct mtk_mmc_compatible mt7620_compat = { 554 .clk_div_bits = 8, 555 .recheck_sdio_irq = true, 556 .hs400_tune = false, 557 .pad_tune_reg = MSDC_PAD_TUNE, 558 .async_fifo = false, 559 .data_tune = false, 560 .busy_check = false, 561 .stop_clk_fix = false, 562 .enhance_rx = false, 563 .use_internal_cd = true, 564 }; 565 566 static const struct mtk_mmc_compatible mt6779_compat = { 567 .clk_div_bits = 12, 568 .recheck_sdio_irq = false, 569 .hs400_tune = false, 570 .pad_tune_reg = MSDC_PAD_TUNE0, 571 .async_fifo = true, 572 .data_tune = true, 573 .busy_check = true, 574 .stop_clk_fix = true, 575 .enhance_rx = true, 576 .support_64g = true, 577 }; 578 579 static const struct of_device_id msdc_of_ids[] = { 580 { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, 581 { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, 582 { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat}, 583 { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat}, 584 { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat}, 585 { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, 586 { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat}, 587 { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat}, 588 { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat}, 589 {} 590 }; 591 MODULE_DEVICE_TABLE(of, msdc_of_ids); 592 593 static void sdr_set_bits(void __iomem *reg, u32 bs) 594 { 595 u32 val = readl(reg); 596 597 val |= bs; 598 writel(val, reg); 599 } 600 601 static void sdr_clr_bits(void __iomem *reg, u32 bs) 602 { 603 u32 val = readl(reg); 604 605 val &= ~bs; 606 writel(val, reg); 607 } 608 609 static void sdr_set_field(void __iomem *reg, u32 field, u32 val) 610 { 611 unsigned int tv = readl(reg); 612 613 tv &= ~field; 614 tv |= ((val) << (ffs((unsigned int)field) - 1)); 615 writel(tv, reg); 616 } 617 618 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val) 619 { 620 unsigned int tv = readl(reg); 621 622 *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); 623 } 624 625 static void msdc_reset_hw(struct msdc_host *host) 626 { 627 u32 val; 628 629 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); 630 while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST) 631 cpu_relax(); 632 633 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); 634 while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR) 635 cpu_relax(); 636 637 val = readl(host->base + MSDC_INT); 638 writel(val, host->base + MSDC_INT); 639 } 640 641 static void msdc_cmd_next(struct msdc_host *host, 642 struct mmc_request *mrq, struct mmc_command *cmd); 643 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb); 644 645 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR | 646 MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY | 647 MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO; 648 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | 649 MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR | 650 MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT; 651 652 static u8 msdc_dma_calcs(u8 *buf, u32 len) 653 { 654 u32 i, sum = 0; 655 656 for (i = 0; i < len; i++) 657 sum += buf[i]; 658 return 0xff - (u8) sum; 659 } 660 661 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma, 662 struct mmc_data *data) 663 { 664 unsigned int j, dma_len; 665 dma_addr_t dma_address; 666 u32 dma_ctrl; 667 struct scatterlist *sg; 668 struct mt_gpdma_desc *gpd; 669 struct mt_bdma_desc *bd; 670 671 sg = data->sg; 672 673 gpd = dma->gpd; 674 bd = dma->bd; 675 676 /* modify gpd */ 677 gpd->gpd_info |= GPDMA_DESC_HWO; 678 gpd->gpd_info |= GPDMA_DESC_BDP; 679 /* need to clear first. use these bits to calc checksum */ 680 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM; 681 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8; 682 683 /* modify bd */ 684 for_each_sg(data->sg, sg, data->sg_count, j) { 685 dma_address = sg_dma_address(sg); 686 dma_len = sg_dma_len(sg); 687 688 /* init bd */ 689 bd[j].bd_info &= ~BDMA_DESC_BLKPAD; 690 bd[j].bd_info &= ~BDMA_DESC_DWPAD; 691 bd[j].ptr = lower_32_bits(dma_address); 692 if (host->dev_comp->support_64g) { 693 bd[j].bd_info &= ~BDMA_DESC_PTR_H4; 694 bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf) 695 << 28; 696 } 697 698 if (host->dev_comp->support_64g) { 699 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN_EXT; 700 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN_EXT); 701 } else { 702 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN; 703 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN); 704 } 705 706 if (j == data->sg_count - 1) /* the last bd */ 707 bd[j].bd_info |= BDMA_DESC_EOL; 708 else 709 bd[j].bd_info &= ~BDMA_DESC_EOL; 710 711 /* checksume need to clear first */ 712 bd[j].bd_info &= ~BDMA_DESC_CHECKSUM; 713 bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8; 714 } 715 716 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); 717 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); 718 dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE); 719 dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8); 720 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); 721 if (host->dev_comp->support_64g) 722 sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT, 723 upper_32_bits(dma->gpd_addr) & 0xf); 724 writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA); 725 } 726 727 static void msdc_prepare_data(struct msdc_host *host, struct mmc_data *data) 728 { 729 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) { 730 data->host_cookie |= MSDC_PREPARE_FLAG; 731 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len, 732 mmc_get_dma_dir(data)); 733 } 734 } 735 736 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_data *data) 737 { 738 if (data->host_cookie & MSDC_ASYNC_FLAG) 739 return; 740 741 if (data->host_cookie & MSDC_PREPARE_FLAG) { 742 dma_unmap_sg(host->dev, data->sg, data->sg_len, 743 mmc_get_dma_dir(data)); 744 data->host_cookie &= ~MSDC_PREPARE_FLAG; 745 } 746 } 747 748 static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks) 749 { 750 struct mmc_host *mmc = mmc_from_priv(host); 751 u64 timeout, clk_ns; 752 u32 mode = 0; 753 754 if (mmc->actual_clock == 0) { 755 timeout = 0; 756 } else { 757 clk_ns = 1000000000ULL; 758 do_div(clk_ns, mmc->actual_clock); 759 timeout = ns + clk_ns - 1; 760 do_div(timeout, clk_ns); 761 timeout += clks; 762 /* in 1048576 sclk cycle unit */ 763 timeout = DIV_ROUND_UP(timeout, (0x1 << 20)); 764 if (host->dev_comp->clk_div_bits == 8) 765 sdr_get_field(host->base + MSDC_CFG, 766 MSDC_CFG_CKMOD, &mode); 767 else 768 sdr_get_field(host->base + MSDC_CFG, 769 MSDC_CFG_CKMOD_EXTRA, &mode); 770 /*DDR mode will double the clk cycles for data timeout */ 771 timeout = mode >= 2 ? timeout * 2 : timeout; 772 timeout = timeout > 1 ? timeout - 1 : 0; 773 } 774 return timeout; 775 } 776 777 /* clock control primitives */ 778 static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks) 779 { 780 u64 timeout; 781 782 host->timeout_ns = ns; 783 host->timeout_clks = clks; 784 785 timeout = msdc_timeout_cal(host, ns, clks); 786 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 787 (u32)(timeout > 255 ? 255 : timeout)); 788 } 789 790 static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks) 791 { 792 u64 timeout; 793 794 timeout = msdc_timeout_cal(host, ns, clks); 795 sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC, 796 (u32)(timeout > 8191 ? 8191 : timeout)); 797 } 798 799 static void msdc_gate_clock(struct msdc_host *host) 800 { 801 clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks); 802 clk_disable_unprepare(host->src_clk_cg); 803 clk_disable_unprepare(host->src_clk); 804 clk_disable_unprepare(host->bus_clk); 805 clk_disable_unprepare(host->h_clk); 806 } 807 808 static void msdc_ungate_clock(struct msdc_host *host) 809 { 810 int ret; 811 812 clk_prepare_enable(host->h_clk); 813 clk_prepare_enable(host->bus_clk); 814 clk_prepare_enable(host->src_clk); 815 clk_prepare_enable(host->src_clk_cg); 816 ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks); 817 if (ret) { 818 dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n"); 819 return; 820 } 821 822 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 823 cpu_relax(); 824 } 825 826 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) 827 { 828 struct mmc_host *mmc = mmc_from_priv(host); 829 u32 mode; 830 u32 flags; 831 u32 div; 832 u32 sclk; 833 u32 tune_reg = host->dev_comp->pad_tune_reg; 834 835 if (!hz) { 836 dev_dbg(host->dev, "set mclk to 0\n"); 837 host->mclk = 0; 838 mmc->actual_clock = 0; 839 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 840 return; 841 } 842 843 flags = readl(host->base + MSDC_INTEN); 844 sdr_clr_bits(host->base + MSDC_INTEN, flags); 845 if (host->dev_comp->clk_div_bits == 8) 846 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); 847 else 848 sdr_clr_bits(host->base + MSDC_CFG, 849 MSDC_CFG_HS400_CK_MODE_EXTRA); 850 if (timing == MMC_TIMING_UHS_DDR50 || 851 timing == MMC_TIMING_MMC_DDR52 || 852 timing == MMC_TIMING_MMC_HS400) { 853 if (timing == MMC_TIMING_MMC_HS400) 854 mode = 0x3; 855 else 856 mode = 0x2; /* ddr mode and use divisor */ 857 858 if (hz >= (host->src_clk_freq >> 2)) { 859 div = 0; /* mean div = 1/4 */ 860 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ 861 } else { 862 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 863 sclk = (host->src_clk_freq >> 2) / div; 864 div = (div >> 1); 865 } 866 867 if (timing == MMC_TIMING_MMC_HS400 && 868 hz >= (host->src_clk_freq >> 1)) { 869 if (host->dev_comp->clk_div_bits == 8) 870 sdr_set_bits(host->base + MSDC_CFG, 871 MSDC_CFG_HS400_CK_MODE); 872 else 873 sdr_set_bits(host->base + MSDC_CFG, 874 MSDC_CFG_HS400_CK_MODE_EXTRA); 875 sclk = host->src_clk_freq >> 1; 876 div = 0; /* div is ignore when bit18 is set */ 877 } 878 } else if (hz >= host->src_clk_freq) { 879 mode = 0x1; /* no divisor */ 880 div = 0; 881 sclk = host->src_clk_freq; 882 } else { 883 mode = 0x0; /* use divisor */ 884 if (hz >= (host->src_clk_freq >> 1)) { 885 div = 0; /* mean div = 1/2 */ 886 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ 887 } else { 888 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 889 sclk = (host->src_clk_freq >> 2) / div; 890 } 891 } 892 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 893 /* 894 * As src_clk/HCLK use the same bit to gate/ungate, 895 * So if want to only gate src_clk, need gate its parent(mux). 896 */ 897 if (host->src_clk_cg) 898 clk_disable_unprepare(host->src_clk_cg); 899 else 900 clk_disable_unprepare(clk_get_parent(host->src_clk)); 901 if (host->dev_comp->clk_div_bits == 8) 902 sdr_set_field(host->base + MSDC_CFG, 903 MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, 904 (mode << 8) | div); 905 else 906 sdr_set_field(host->base + MSDC_CFG, 907 MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA, 908 (mode << 12) | div); 909 if (host->src_clk_cg) 910 clk_prepare_enable(host->src_clk_cg); 911 else 912 clk_prepare_enable(clk_get_parent(host->src_clk)); 913 914 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 915 cpu_relax(); 916 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 917 mmc->actual_clock = sclk; 918 host->mclk = hz; 919 host->timing = timing; 920 /* need because clk changed. */ 921 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); 922 sdr_set_bits(host->base + MSDC_INTEN, flags); 923 924 /* 925 * mmc_select_hs400() will drop to 50Mhz and High speed mode, 926 * tune result of hs200/200Mhz is not suitable for 50Mhz 927 */ 928 if (mmc->actual_clock <= 52000000) { 929 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON); 930 if (host->top_base) { 931 writel(host->def_tune_para.emmc_top_control, 932 host->top_base + EMMC_TOP_CONTROL); 933 writel(host->def_tune_para.emmc_top_cmd, 934 host->top_base + EMMC_TOP_CMD); 935 } else { 936 writel(host->def_tune_para.pad_tune, 937 host->base + tune_reg); 938 } 939 } else { 940 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON); 941 writel(host->saved_tune_para.pad_cmd_tune, 942 host->base + PAD_CMD_TUNE); 943 if (host->top_base) { 944 writel(host->saved_tune_para.emmc_top_control, 945 host->top_base + EMMC_TOP_CONTROL); 946 writel(host->saved_tune_para.emmc_top_cmd, 947 host->top_base + EMMC_TOP_CMD); 948 } else { 949 writel(host->saved_tune_para.pad_tune, 950 host->base + tune_reg); 951 } 952 } 953 954 if (timing == MMC_TIMING_MMC_HS400 && 955 host->dev_comp->hs400_tune) 956 sdr_set_field(host->base + tune_reg, 957 MSDC_PAD_TUNE_CMDRRDLY, 958 host->hs400_cmd_int_delay); 959 dev_dbg(host->dev, "sclk: %d, timing: %d\n", mmc->actual_clock, 960 timing); 961 } 962 963 static inline u32 msdc_cmd_find_resp(struct msdc_host *host, 964 struct mmc_request *mrq, struct mmc_command *cmd) 965 { 966 u32 resp; 967 968 switch (mmc_resp_type(cmd)) { 969 /* Actually, R1, R5, R6, R7 are the same */ 970 case MMC_RSP_R1: 971 resp = 0x1; 972 break; 973 case MMC_RSP_R1B: 974 resp = 0x7; 975 break; 976 case MMC_RSP_R2: 977 resp = 0x2; 978 break; 979 case MMC_RSP_R3: 980 resp = 0x3; 981 break; 982 case MMC_RSP_NONE: 983 default: 984 resp = 0x0; 985 break; 986 } 987 988 return resp; 989 } 990 991 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host, 992 struct mmc_request *mrq, struct mmc_command *cmd) 993 { 994 struct mmc_host *mmc = mmc_from_priv(host); 995 /* rawcmd : 996 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 | 997 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode 998 */ 999 u32 opcode = cmd->opcode; 1000 u32 resp = msdc_cmd_find_resp(host, mrq, cmd); 1001 u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7); 1002 1003 host->cmd_rsp = resp; 1004 1005 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) || 1006 opcode == MMC_STOP_TRANSMISSION) 1007 rawcmd |= (0x1 << 14); 1008 else if (opcode == SD_SWITCH_VOLTAGE) 1009 rawcmd |= (0x1 << 30); 1010 else if (opcode == SD_APP_SEND_SCR || 1011 opcode == SD_APP_SEND_NUM_WR_BLKS || 1012 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 1013 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 1014 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC)) 1015 rawcmd |= (0x1 << 11); 1016 1017 if (cmd->data) { 1018 struct mmc_data *data = cmd->data; 1019 1020 if (mmc_op_multi(opcode)) { 1021 if (mmc_card_mmc(mmc->card) && mrq->sbc && 1022 !(mrq->sbc->arg & 0xFFFF0000)) 1023 rawcmd |= 0x2 << 28; /* AutoCMD23 */ 1024 } 1025 1026 rawcmd |= ((data->blksz & 0xFFF) << 16); 1027 if (data->flags & MMC_DATA_WRITE) 1028 rawcmd |= (0x1 << 13); 1029 if (data->blocks > 1) 1030 rawcmd |= (0x2 << 11); 1031 else 1032 rawcmd |= (0x1 << 11); 1033 /* Always use dma mode */ 1034 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); 1035 1036 if (host->timeout_ns != data->timeout_ns || 1037 host->timeout_clks != data->timeout_clks) 1038 msdc_set_timeout(host, data->timeout_ns, 1039 data->timeout_clks); 1040 1041 writel(data->blocks, host->base + SDC_BLK_NUM); 1042 } 1043 return rawcmd; 1044 } 1045 1046 static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq, 1047 struct mmc_command *cmd, struct mmc_data *data) 1048 { 1049 bool read; 1050 1051 WARN_ON(host->data); 1052 host->data = data; 1053 read = data->flags & MMC_DATA_READ; 1054 1055 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 1056 msdc_dma_setup(host, &host->dma, data); 1057 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); 1058 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); 1059 dev_dbg(host->dev, "DMA start\n"); 1060 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", 1061 __func__, cmd->opcode, data->blocks, read); 1062 } 1063 1064 static int msdc_auto_cmd_done(struct msdc_host *host, int events, 1065 struct mmc_command *cmd) 1066 { 1067 u32 *rsp = cmd->resp; 1068 1069 rsp[0] = readl(host->base + SDC_ACMD_RESP); 1070 1071 if (events & MSDC_INT_ACMDRDY) { 1072 cmd->error = 0; 1073 } else { 1074 msdc_reset_hw(host); 1075 if (events & MSDC_INT_ACMDCRCERR) { 1076 cmd->error = -EILSEQ; 1077 host->error |= REQ_STOP_EIO; 1078 } else if (events & MSDC_INT_ACMDTMO) { 1079 cmd->error = -ETIMEDOUT; 1080 host->error |= REQ_STOP_TMO; 1081 } 1082 dev_err(host->dev, 1083 "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n", 1084 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); 1085 } 1086 return cmd->error; 1087 } 1088 1089 /* 1090 * msdc_recheck_sdio_irq - recheck whether the SDIO irq is lost 1091 * 1092 * Host controller may lost interrupt in some special case. 1093 * Add SDIO irq recheck mechanism to make sure all interrupts 1094 * can be processed immediately 1095 */ 1096 static void msdc_recheck_sdio_irq(struct msdc_host *host) 1097 { 1098 struct mmc_host *mmc = mmc_from_priv(host); 1099 u32 reg_int, reg_inten, reg_ps; 1100 1101 if (mmc->caps & MMC_CAP_SDIO_IRQ) { 1102 reg_inten = readl(host->base + MSDC_INTEN); 1103 if (reg_inten & MSDC_INTEN_SDIOIRQ) { 1104 reg_int = readl(host->base + MSDC_INT); 1105 reg_ps = readl(host->base + MSDC_PS); 1106 if (!(reg_int & MSDC_INT_SDIOIRQ || 1107 reg_ps & MSDC_PS_DATA1)) { 1108 __msdc_enable_sdio_irq(host, 0); 1109 sdio_signal_irq(mmc); 1110 } 1111 } 1112 } 1113 } 1114 1115 static void msdc_track_cmd_data(struct msdc_host *host, 1116 struct mmc_command *cmd, struct mmc_data *data) 1117 { 1118 if (host->error) 1119 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", 1120 __func__, cmd->opcode, cmd->arg, host->error); 1121 } 1122 1123 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq) 1124 { 1125 unsigned long flags; 1126 1127 /* 1128 * No need check the return value of cancel_delayed_work, as only ONE 1129 * path will go here! 1130 */ 1131 cancel_delayed_work(&host->req_timeout); 1132 1133 spin_lock_irqsave(&host->lock, flags); 1134 host->mrq = NULL; 1135 spin_unlock_irqrestore(&host->lock, flags); 1136 1137 msdc_track_cmd_data(host, mrq->cmd, mrq->data); 1138 if (mrq->data) 1139 msdc_unprepare_data(host, mrq->data); 1140 if (host->error) 1141 msdc_reset_hw(host); 1142 mmc_request_done(mmc_from_priv(host), mrq); 1143 if (host->dev_comp->recheck_sdio_irq) 1144 msdc_recheck_sdio_irq(host); 1145 } 1146 1147 /* returns true if command is fully handled; returns false otherwise */ 1148 static bool msdc_cmd_done(struct msdc_host *host, int events, 1149 struct mmc_request *mrq, struct mmc_command *cmd) 1150 { 1151 bool done = false; 1152 bool sbc_error; 1153 unsigned long flags; 1154 u32 *rsp; 1155 1156 if (mrq->sbc && cmd == mrq->cmd && 1157 (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR 1158 | MSDC_INT_ACMDTMO))) 1159 msdc_auto_cmd_done(host, events, mrq->sbc); 1160 1161 sbc_error = mrq->sbc && mrq->sbc->error; 1162 1163 if (!sbc_error && !(events & (MSDC_INT_CMDRDY 1164 | MSDC_INT_RSPCRCERR 1165 | MSDC_INT_CMDTMO))) 1166 return done; 1167 1168 spin_lock_irqsave(&host->lock, flags); 1169 done = !host->cmd; 1170 host->cmd = NULL; 1171 spin_unlock_irqrestore(&host->lock, flags); 1172 1173 if (done) 1174 return true; 1175 rsp = cmd->resp; 1176 1177 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask); 1178 1179 if (cmd->flags & MMC_RSP_PRESENT) { 1180 if (cmd->flags & MMC_RSP_136) { 1181 rsp[0] = readl(host->base + SDC_RESP3); 1182 rsp[1] = readl(host->base + SDC_RESP2); 1183 rsp[2] = readl(host->base + SDC_RESP1); 1184 rsp[3] = readl(host->base + SDC_RESP0); 1185 } else { 1186 rsp[0] = readl(host->base + SDC_RESP0); 1187 } 1188 } 1189 1190 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) { 1191 if (events & MSDC_INT_CMDTMO || 1192 (cmd->opcode != MMC_SEND_TUNING_BLOCK && 1193 cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)) 1194 /* 1195 * should not clear fifo/interrupt as the tune data 1196 * may have alreay come when cmd19/cmd21 gets response 1197 * CRC error. 1198 */ 1199 msdc_reset_hw(host); 1200 if (events & MSDC_INT_RSPCRCERR) { 1201 cmd->error = -EILSEQ; 1202 host->error |= REQ_CMD_EIO; 1203 } else if (events & MSDC_INT_CMDTMO) { 1204 cmd->error = -ETIMEDOUT; 1205 host->error |= REQ_CMD_TMO; 1206 } 1207 } 1208 if (cmd->error) 1209 dev_dbg(host->dev, 1210 "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n", 1211 __func__, cmd->opcode, cmd->arg, rsp[0], 1212 cmd->error); 1213 1214 msdc_cmd_next(host, mrq, cmd); 1215 return true; 1216 } 1217 1218 /* It is the core layer's responsibility to ensure card status 1219 * is correct before issue a request. but host design do below 1220 * checks recommended. 1221 */ 1222 static inline bool msdc_cmd_is_ready(struct msdc_host *host, 1223 struct mmc_request *mrq, struct mmc_command *cmd) 1224 { 1225 /* The max busy time we can endure is 20ms */ 1226 unsigned long tmo = jiffies + msecs_to_jiffies(20); 1227 1228 while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) && 1229 time_before(jiffies, tmo)) 1230 cpu_relax(); 1231 if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) { 1232 dev_err(host->dev, "CMD bus busy detected\n"); 1233 host->error |= REQ_CMD_BUSY; 1234 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 1235 return false; 1236 } 1237 1238 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) { 1239 tmo = jiffies + msecs_to_jiffies(20); 1240 /* R1B or with data, should check SDCBUSY */ 1241 while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) && 1242 time_before(jiffies, tmo)) 1243 cpu_relax(); 1244 if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) { 1245 dev_err(host->dev, "Controller busy detected\n"); 1246 host->error |= REQ_CMD_BUSY; 1247 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 1248 return false; 1249 } 1250 } 1251 return true; 1252 } 1253 1254 static void msdc_start_command(struct msdc_host *host, 1255 struct mmc_request *mrq, struct mmc_command *cmd) 1256 { 1257 u32 rawcmd; 1258 unsigned long flags; 1259 1260 WARN_ON(host->cmd); 1261 host->cmd = cmd; 1262 1263 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 1264 if (!msdc_cmd_is_ready(host, mrq, cmd)) 1265 return; 1266 1267 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || 1268 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { 1269 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); 1270 msdc_reset_hw(host); 1271 } 1272 1273 cmd->error = 0; 1274 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd); 1275 1276 spin_lock_irqsave(&host->lock, flags); 1277 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask); 1278 spin_unlock_irqrestore(&host->lock, flags); 1279 1280 writel(cmd->arg, host->base + SDC_ARG); 1281 writel(rawcmd, host->base + SDC_CMD); 1282 } 1283 1284 static void msdc_cmd_next(struct msdc_host *host, 1285 struct mmc_request *mrq, struct mmc_command *cmd) 1286 { 1287 if ((cmd->error && 1288 !(cmd->error == -EILSEQ && 1289 (cmd->opcode == MMC_SEND_TUNING_BLOCK || 1290 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) || 1291 (mrq->sbc && mrq->sbc->error)) 1292 msdc_request_done(host, mrq); 1293 else if (cmd == mrq->sbc) 1294 msdc_start_command(host, mrq, mrq->cmd); 1295 else if (!cmd->data) 1296 msdc_request_done(host, mrq); 1297 else 1298 msdc_start_data(host, mrq, cmd, cmd->data); 1299 } 1300 1301 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq) 1302 { 1303 struct msdc_host *host = mmc_priv(mmc); 1304 1305 host->error = 0; 1306 WARN_ON(host->mrq); 1307 host->mrq = mrq; 1308 1309 if (mrq->data) 1310 msdc_prepare_data(host, mrq->data); 1311 1312 /* if SBC is required, we have HW option and SW option. 1313 * if HW option is enabled, and SBC does not have "special" flags, 1314 * use HW option, otherwise use SW option 1315 */ 1316 if (mrq->sbc && (!mmc_card_mmc(mmc->card) || 1317 (mrq->sbc->arg & 0xFFFF0000))) 1318 msdc_start_command(host, mrq, mrq->sbc); 1319 else 1320 msdc_start_command(host, mrq, mrq->cmd); 1321 } 1322 1323 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 1324 { 1325 struct msdc_host *host = mmc_priv(mmc); 1326 struct mmc_data *data = mrq->data; 1327 1328 if (!data) 1329 return; 1330 1331 msdc_prepare_data(host, data); 1332 data->host_cookie |= MSDC_ASYNC_FLAG; 1333 } 1334 1335 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 1336 int err) 1337 { 1338 struct msdc_host *host = mmc_priv(mmc); 1339 struct mmc_data *data = mrq->data; 1340 1341 if (!data) 1342 return; 1343 1344 if (data->host_cookie) { 1345 data->host_cookie &= ~MSDC_ASYNC_FLAG; 1346 msdc_unprepare_data(host, data); 1347 } 1348 } 1349 1350 static void msdc_data_xfer_next(struct msdc_host *host, 1351 struct mmc_request *mrq, struct mmc_data *data) 1352 { 1353 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error && 1354 !mrq->sbc) 1355 msdc_start_command(host, mrq, mrq->stop); 1356 else 1357 msdc_request_done(host, mrq); 1358 } 1359 1360 static bool msdc_data_xfer_done(struct msdc_host *host, u32 events, 1361 struct mmc_request *mrq, struct mmc_data *data) 1362 { 1363 struct mmc_command *stop; 1364 unsigned long flags; 1365 bool done; 1366 unsigned int check_data = events & 1367 (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO 1368 | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR 1369 | MSDC_INT_DMA_PROTECT); 1370 1371 spin_lock_irqsave(&host->lock, flags); 1372 done = !host->data; 1373 if (check_data) 1374 host->data = NULL; 1375 spin_unlock_irqrestore(&host->lock, flags); 1376 1377 if (done) 1378 return true; 1379 stop = data->stop; 1380 1381 if (check_data || (stop && stop->error)) { 1382 dev_dbg(host->dev, "DMA status: 0x%8X\n", 1383 readl(host->base + MSDC_DMA_CFG)); 1384 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 1385 1); 1386 while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS) 1387 cpu_relax(); 1388 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); 1389 dev_dbg(host->dev, "DMA stop\n"); 1390 1391 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) { 1392 data->bytes_xfered = data->blocks * data->blksz; 1393 } else { 1394 dev_dbg(host->dev, "interrupt events: %x\n", events); 1395 msdc_reset_hw(host); 1396 host->error |= REQ_DAT_ERR; 1397 data->bytes_xfered = 0; 1398 1399 if (events & MSDC_INT_DATTMO) 1400 data->error = -ETIMEDOUT; 1401 else if (events & MSDC_INT_DATCRCERR) 1402 data->error = -EILSEQ; 1403 1404 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d", 1405 __func__, mrq->cmd->opcode, data->blocks); 1406 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n", 1407 (int)data->error, data->bytes_xfered); 1408 } 1409 1410 msdc_data_xfer_next(host, mrq, data); 1411 done = true; 1412 } 1413 return done; 1414 } 1415 1416 static void msdc_set_buswidth(struct msdc_host *host, u32 width) 1417 { 1418 u32 val = readl(host->base + SDC_CFG); 1419 1420 val &= ~SDC_CFG_BUSWIDTH; 1421 1422 switch (width) { 1423 default: 1424 case MMC_BUS_WIDTH_1: 1425 val |= (MSDC_BUS_1BITS << 16); 1426 break; 1427 case MMC_BUS_WIDTH_4: 1428 val |= (MSDC_BUS_4BITS << 16); 1429 break; 1430 case MMC_BUS_WIDTH_8: 1431 val |= (MSDC_BUS_8BITS << 16); 1432 break; 1433 } 1434 1435 writel(val, host->base + SDC_CFG); 1436 dev_dbg(host->dev, "Bus Width = %d", width); 1437 } 1438 1439 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios) 1440 { 1441 struct msdc_host *host = mmc_priv(mmc); 1442 int ret; 1443 1444 if (!IS_ERR(mmc->supply.vqmmc)) { 1445 if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 && 1446 ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) { 1447 dev_err(host->dev, "Unsupported signal voltage!\n"); 1448 return -EINVAL; 1449 } 1450 1451 ret = mmc_regulator_set_vqmmc(mmc, ios); 1452 if (ret < 0) { 1453 dev_dbg(host->dev, "Regulator set error %d (%d)\n", 1454 ret, ios->signal_voltage); 1455 return ret; 1456 } 1457 1458 /* Apply different pinctrl settings for different signal voltage */ 1459 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 1460 pinctrl_select_state(host->pinctrl, host->pins_uhs); 1461 else 1462 pinctrl_select_state(host->pinctrl, host->pins_default); 1463 } 1464 return 0; 1465 } 1466 1467 static int msdc_card_busy(struct mmc_host *mmc) 1468 { 1469 struct msdc_host *host = mmc_priv(mmc); 1470 u32 status = readl(host->base + MSDC_PS); 1471 1472 /* only check if data0 is low */ 1473 return !(status & BIT(16)); 1474 } 1475 1476 static void msdc_request_timeout(struct work_struct *work) 1477 { 1478 struct msdc_host *host = container_of(work, struct msdc_host, 1479 req_timeout.work); 1480 1481 /* simulate HW timeout status */ 1482 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); 1483 if (host->mrq) { 1484 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, 1485 host->mrq, host->mrq->cmd->opcode); 1486 if (host->cmd) { 1487 dev_err(host->dev, "%s: aborting cmd=%d\n", 1488 __func__, host->cmd->opcode); 1489 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, 1490 host->cmd); 1491 } else if (host->data) { 1492 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", 1493 __func__, host->mrq->cmd->opcode, 1494 host->data->blocks); 1495 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, 1496 host->data); 1497 } 1498 } 1499 } 1500 1501 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb) 1502 { 1503 if (enb) { 1504 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 1505 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1506 if (host->dev_comp->recheck_sdio_irq) 1507 msdc_recheck_sdio_irq(host); 1508 } else { 1509 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 1510 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1511 } 1512 } 1513 1514 static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb) 1515 { 1516 unsigned long flags; 1517 struct msdc_host *host = mmc_priv(mmc); 1518 1519 spin_lock_irqsave(&host->lock, flags); 1520 __msdc_enable_sdio_irq(host, enb); 1521 spin_unlock_irqrestore(&host->lock, flags); 1522 1523 if (enb) 1524 pm_runtime_get_noresume(host->dev); 1525 else 1526 pm_runtime_put_noidle(host->dev); 1527 } 1528 1529 static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts) 1530 { 1531 struct mmc_host *mmc = mmc_from_priv(host); 1532 int cmd_err = 0, dat_err = 0; 1533 1534 if (intsts & MSDC_INT_RSPCRCERR) { 1535 cmd_err = -EILSEQ; 1536 dev_err(host->dev, "%s: CMD CRC ERR", __func__); 1537 } else if (intsts & MSDC_INT_CMDTMO) { 1538 cmd_err = -ETIMEDOUT; 1539 dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__); 1540 } 1541 1542 if (intsts & MSDC_INT_DATCRCERR) { 1543 dat_err = -EILSEQ; 1544 dev_err(host->dev, "%s: DATA CRC ERR", __func__); 1545 } else if (intsts & MSDC_INT_DATTMO) { 1546 dat_err = -ETIMEDOUT; 1547 dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__); 1548 } 1549 1550 if (cmd_err || dat_err) { 1551 dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x", 1552 cmd_err, dat_err, intsts); 1553 } 1554 1555 return cqhci_irq(mmc, 0, cmd_err, dat_err); 1556 } 1557 1558 static irqreturn_t msdc_irq(int irq, void *dev_id) 1559 { 1560 struct msdc_host *host = (struct msdc_host *) dev_id; 1561 struct mmc_host *mmc = mmc_from_priv(host); 1562 1563 while (true) { 1564 struct mmc_request *mrq; 1565 struct mmc_command *cmd; 1566 struct mmc_data *data; 1567 u32 events, event_mask; 1568 1569 spin_lock(&host->lock); 1570 events = readl(host->base + MSDC_INT); 1571 event_mask = readl(host->base + MSDC_INTEN); 1572 if ((events & event_mask) & MSDC_INT_SDIOIRQ) 1573 __msdc_enable_sdio_irq(host, 0); 1574 /* clear interrupts */ 1575 writel(events & event_mask, host->base + MSDC_INT); 1576 1577 mrq = host->mrq; 1578 cmd = host->cmd; 1579 data = host->data; 1580 spin_unlock(&host->lock); 1581 1582 if ((events & event_mask) & MSDC_INT_SDIOIRQ) 1583 sdio_signal_irq(mmc); 1584 1585 if ((events & event_mask) & MSDC_INT_CDSC) { 1586 if (host->internal_cd) 1587 mmc_detect_change(mmc, msecs_to_jiffies(20)); 1588 events &= ~MSDC_INT_CDSC; 1589 } 1590 1591 if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ))) 1592 break; 1593 1594 if ((mmc->caps2 & MMC_CAP2_CQE) && 1595 (events & MSDC_INT_CMDQ)) { 1596 msdc_cmdq_irq(host, events); 1597 /* clear interrupts */ 1598 writel(events, host->base + MSDC_INT); 1599 return IRQ_HANDLED; 1600 } 1601 1602 if (!mrq) { 1603 dev_err(host->dev, 1604 "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", 1605 __func__, events, event_mask); 1606 WARN_ON(1); 1607 break; 1608 } 1609 1610 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); 1611 1612 if (cmd) 1613 msdc_cmd_done(host, events, mrq, cmd); 1614 else if (data) 1615 msdc_data_xfer_done(host, events, mrq, data); 1616 } 1617 1618 return IRQ_HANDLED; 1619 } 1620 1621 static void msdc_init_hw(struct msdc_host *host) 1622 { 1623 u32 val; 1624 u32 tune_reg = host->dev_comp->pad_tune_reg; 1625 1626 if (host->reset) { 1627 reset_control_assert(host->reset); 1628 usleep_range(10, 50); 1629 reset_control_deassert(host->reset); 1630 } 1631 1632 /* Configure to MMC/SD mode, clock free running */ 1633 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); 1634 1635 /* Reset */ 1636 msdc_reset_hw(host); 1637 1638 /* Disable and clear all interrupts */ 1639 writel(0, host->base + MSDC_INTEN); 1640 val = readl(host->base + MSDC_INT); 1641 writel(val, host->base + MSDC_INT); 1642 1643 /* Configure card detection */ 1644 if (host->internal_cd) { 1645 sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE, 1646 DEFAULT_DEBOUNCE); 1647 sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1648 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); 1649 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1650 } else { 1651 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1652 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1653 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); 1654 } 1655 1656 if (host->top_base) { 1657 writel(0, host->top_base + EMMC_TOP_CONTROL); 1658 writel(0, host->top_base + EMMC_TOP_CMD); 1659 } else { 1660 writel(0, host->base + tune_reg); 1661 } 1662 writel(0, host->base + MSDC_IOCON); 1663 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0); 1664 writel(0x403c0046, host->base + MSDC_PATCH_BIT); 1665 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); 1666 writel(0xffff4089, host->base + MSDC_PATCH_BIT1); 1667 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); 1668 1669 if (host->dev_comp->stop_clk_fix) { 1670 sdr_set_field(host->base + MSDC_PATCH_BIT1, 1671 MSDC_PATCH_BIT1_STOP_DLY, 3); 1672 sdr_clr_bits(host->base + SDC_FIFO_CFG, 1673 SDC_FIFO_CFG_WRVALIDSEL); 1674 sdr_clr_bits(host->base + SDC_FIFO_CFG, 1675 SDC_FIFO_CFG_RDVALIDSEL); 1676 } 1677 1678 if (host->dev_comp->busy_check) 1679 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, (1 << 7)); 1680 1681 if (host->dev_comp->async_fifo) { 1682 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1683 MSDC_PB2_RESPWAIT, 3); 1684 if (host->dev_comp->enhance_rx) { 1685 if (host->top_base) 1686 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1687 SDC_RX_ENH_EN); 1688 else 1689 sdr_set_bits(host->base + SDC_ADV_CFG0, 1690 SDC_RX_ENHANCE_EN); 1691 } else { 1692 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1693 MSDC_PB2_RESPSTSENSEL, 2); 1694 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1695 MSDC_PB2_CRCSTSENSEL, 2); 1696 } 1697 /* use async fifo, then no need tune internal delay */ 1698 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, 1699 MSDC_PATCH_BIT2_CFGRESP); 1700 sdr_set_bits(host->base + MSDC_PATCH_BIT2, 1701 MSDC_PATCH_BIT2_CFGCRCSTS); 1702 } 1703 1704 if (host->dev_comp->support_64g) 1705 sdr_set_bits(host->base + MSDC_PATCH_BIT2, 1706 MSDC_PB2_SUPPORT_64G); 1707 if (host->dev_comp->data_tune) { 1708 if (host->top_base) { 1709 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1710 PAD_DAT_RD_RXDLY_SEL); 1711 sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL, 1712 DATA_K_VALUE_SEL); 1713 sdr_set_bits(host->top_base + EMMC_TOP_CMD, 1714 PAD_CMD_RD_RXDLY_SEL); 1715 } else { 1716 sdr_set_bits(host->base + tune_reg, 1717 MSDC_PAD_TUNE_RD_SEL | 1718 MSDC_PAD_TUNE_CMD_SEL); 1719 } 1720 } else { 1721 /* choose clock tune */ 1722 if (host->top_base) 1723 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1724 PAD_RXDLY_SEL); 1725 else 1726 sdr_set_bits(host->base + tune_reg, 1727 MSDC_PAD_TUNE_RXDLYSEL); 1728 } 1729 1730 /* Configure to enable SDIO mode. 1731 * it's must otherwise sdio cmd5 failed 1732 */ 1733 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); 1734 1735 /* Config SDIO device detect interrupt function */ 1736 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1737 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); 1738 1739 /* Configure to default data timeout */ 1740 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); 1741 1742 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON); 1743 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 1744 if (host->top_base) { 1745 host->def_tune_para.emmc_top_control = 1746 readl(host->top_base + EMMC_TOP_CONTROL); 1747 host->def_tune_para.emmc_top_cmd = 1748 readl(host->top_base + EMMC_TOP_CMD); 1749 host->saved_tune_para.emmc_top_control = 1750 readl(host->top_base + EMMC_TOP_CONTROL); 1751 host->saved_tune_para.emmc_top_cmd = 1752 readl(host->top_base + EMMC_TOP_CMD); 1753 } else { 1754 host->def_tune_para.pad_tune = readl(host->base + tune_reg); 1755 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 1756 } 1757 dev_dbg(host->dev, "init hardware done!"); 1758 } 1759 1760 static void msdc_deinit_hw(struct msdc_host *host) 1761 { 1762 u32 val; 1763 1764 if (host->internal_cd) { 1765 /* Disabled card-detect */ 1766 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1767 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1768 } 1769 1770 /* Disable and clear all interrupts */ 1771 writel(0, host->base + MSDC_INTEN); 1772 1773 val = readl(host->base + MSDC_INT); 1774 writel(val, host->base + MSDC_INT); 1775 } 1776 1777 /* init gpd and bd list in msdc_drv_probe */ 1778 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma) 1779 { 1780 struct mt_gpdma_desc *gpd = dma->gpd; 1781 struct mt_bdma_desc *bd = dma->bd; 1782 dma_addr_t dma_addr; 1783 int i; 1784 1785 memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2); 1786 1787 dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc); 1788 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */ 1789 /* gpd->next is must set for desc DMA 1790 * That's why must alloc 2 gpd structure. 1791 */ 1792 gpd->next = lower_32_bits(dma_addr); 1793 if (host->dev_comp->support_64g) 1794 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 1795 1796 dma_addr = dma->bd_addr; 1797 gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */ 1798 if (host->dev_comp->support_64g) 1799 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28; 1800 1801 memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM); 1802 for (i = 0; i < (MAX_BD_NUM - 1); i++) { 1803 dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1); 1804 bd[i].next = lower_32_bits(dma_addr); 1805 if (host->dev_comp->support_64g) 1806 bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 1807 } 1808 } 1809 1810 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1811 { 1812 struct msdc_host *host = mmc_priv(mmc); 1813 int ret; 1814 1815 msdc_set_buswidth(host, ios->bus_width); 1816 1817 /* Suspend/Resume will do power off/on */ 1818 switch (ios->power_mode) { 1819 case MMC_POWER_UP: 1820 if (!IS_ERR(mmc->supply.vmmc)) { 1821 msdc_init_hw(host); 1822 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 1823 ios->vdd); 1824 if (ret) { 1825 dev_err(host->dev, "Failed to set vmmc power!\n"); 1826 return; 1827 } 1828 } 1829 break; 1830 case MMC_POWER_ON: 1831 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1832 ret = regulator_enable(mmc->supply.vqmmc); 1833 if (ret) 1834 dev_err(host->dev, "Failed to set vqmmc power!\n"); 1835 else 1836 host->vqmmc_enabled = true; 1837 } 1838 break; 1839 case MMC_POWER_OFF: 1840 if (!IS_ERR(mmc->supply.vmmc)) 1841 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1842 1843 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1844 regulator_disable(mmc->supply.vqmmc); 1845 host->vqmmc_enabled = false; 1846 } 1847 break; 1848 default: 1849 break; 1850 } 1851 1852 if (host->mclk != ios->clock || host->timing != ios->timing) 1853 msdc_set_mclk(host, ios->timing, ios->clock); 1854 } 1855 1856 static u32 test_delay_bit(u32 delay, u32 bit) 1857 { 1858 bit %= PAD_DELAY_MAX; 1859 return delay & (1 << bit); 1860 } 1861 1862 static int get_delay_len(u32 delay, u32 start_bit) 1863 { 1864 int i; 1865 1866 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) { 1867 if (test_delay_bit(delay, start_bit + i) == 0) 1868 return i; 1869 } 1870 return PAD_DELAY_MAX - start_bit; 1871 } 1872 1873 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay) 1874 { 1875 int start = 0, len = 0; 1876 int start_final = 0, len_final = 0; 1877 u8 final_phase = 0xff; 1878 struct msdc_delay_phase delay_phase = { 0, }; 1879 1880 if (delay == 0) { 1881 dev_err(host->dev, "phase error: [map:%x]\n", delay); 1882 delay_phase.final_phase = final_phase; 1883 return delay_phase; 1884 } 1885 1886 while (start < PAD_DELAY_MAX) { 1887 len = get_delay_len(delay, start); 1888 if (len_final < len) { 1889 start_final = start; 1890 len_final = len; 1891 } 1892 start += len ? len : 1; 1893 if (len >= 12 && start_final < 4) 1894 break; 1895 } 1896 1897 /* The rule is that to find the smallest delay cell */ 1898 if (start_final == 0) 1899 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX; 1900 else 1901 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX; 1902 dev_info(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n", 1903 delay, len_final, final_phase); 1904 1905 delay_phase.maxlen = len_final; 1906 delay_phase.start = start_final; 1907 delay_phase.final_phase = final_phase; 1908 return delay_phase; 1909 } 1910 1911 static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value) 1912 { 1913 u32 tune_reg = host->dev_comp->pad_tune_reg; 1914 1915 if (host->top_base) 1916 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY, 1917 value); 1918 else 1919 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, 1920 value); 1921 } 1922 1923 static inline void msdc_set_data_delay(struct msdc_host *host, u32 value) 1924 { 1925 u32 tune_reg = host->dev_comp->pad_tune_reg; 1926 1927 if (host->top_base) 1928 sdr_set_field(host->top_base + EMMC_TOP_CONTROL, 1929 PAD_DAT_RD_RXDLY, value); 1930 else 1931 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, 1932 value); 1933 } 1934 1935 static int msdc_tune_response(struct mmc_host *mmc, u32 opcode) 1936 { 1937 struct msdc_host *host = mmc_priv(mmc); 1938 u32 rise_delay = 0, fall_delay = 0; 1939 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 1940 struct msdc_delay_phase internal_delay_phase; 1941 u8 final_delay, final_maxlen; 1942 u32 internal_delay = 0; 1943 u32 tune_reg = host->dev_comp->pad_tune_reg; 1944 int cmd_err; 1945 int i, j; 1946 1947 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 1948 mmc->ios.timing == MMC_TIMING_UHS_SDR104) 1949 sdr_set_field(host->base + tune_reg, 1950 MSDC_PAD_TUNE_CMDRRDLY, 1951 host->hs200_cmd_int_delay); 1952 1953 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1954 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 1955 msdc_set_cmd_delay(host, i); 1956 /* 1957 * Using the same parameters, it may sometimes pass the test, 1958 * but sometimes it may fail. To make sure the parameters are 1959 * more stable, we test each set of parameters 3 times. 1960 */ 1961 for (j = 0; j < 3; j++) { 1962 mmc_send_tuning(mmc, opcode, &cmd_err); 1963 if (!cmd_err) { 1964 rise_delay |= (1 << i); 1965 } else { 1966 rise_delay &= ~(1 << i); 1967 break; 1968 } 1969 } 1970 } 1971 final_rise_delay = get_best_delay(host, rise_delay); 1972 /* if rising edge has enough margin, then do not scan falling edge */ 1973 if (final_rise_delay.maxlen >= 12 || 1974 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 1975 goto skip_fall; 1976 1977 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1978 for (i = 0; i < PAD_DELAY_MAX; i++) { 1979 msdc_set_cmd_delay(host, i); 1980 /* 1981 * Using the same parameters, it may sometimes pass the test, 1982 * but sometimes it may fail. To make sure the parameters are 1983 * more stable, we test each set of parameters 3 times. 1984 */ 1985 for (j = 0; j < 3; j++) { 1986 mmc_send_tuning(mmc, opcode, &cmd_err); 1987 if (!cmd_err) { 1988 fall_delay |= (1 << i); 1989 } else { 1990 fall_delay &= ~(1 << i); 1991 break; 1992 } 1993 } 1994 } 1995 final_fall_delay = get_best_delay(host, fall_delay); 1996 1997 skip_fall: 1998 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 1999 if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4) 2000 final_maxlen = final_fall_delay.maxlen; 2001 if (final_maxlen == final_rise_delay.maxlen) { 2002 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2003 final_delay = final_rise_delay.final_phase; 2004 } else { 2005 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2006 final_delay = final_fall_delay.final_phase; 2007 } 2008 msdc_set_cmd_delay(host, final_delay); 2009 2010 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay) 2011 goto skip_internal; 2012 2013 for (i = 0; i < PAD_DELAY_MAX; i++) { 2014 sdr_set_field(host->base + tune_reg, 2015 MSDC_PAD_TUNE_CMDRRDLY, i); 2016 mmc_send_tuning(mmc, opcode, &cmd_err); 2017 if (!cmd_err) 2018 internal_delay |= (1 << i); 2019 } 2020 dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay); 2021 internal_delay_phase = get_best_delay(host, internal_delay); 2022 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY, 2023 internal_delay_phase.final_phase); 2024 skip_internal: 2025 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 2026 return final_delay == 0xff ? -EIO : 0; 2027 } 2028 2029 static int hs400_tune_response(struct mmc_host *mmc, u32 opcode) 2030 { 2031 struct msdc_host *host = mmc_priv(mmc); 2032 u32 cmd_delay = 0; 2033 struct msdc_delay_phase final_cmd_delay = { 0,}; 2034 u8 final_delay; 2035 int cmd_err; 2036 int i, j; 2037 2038 /* select EMMC50 PAD CMD tune */ 2039 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0)); 2040 sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2); 2041 2042 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 2043 mmc->ios.timing == MMC_TIMING_UHS_SDR104) 2044 sdr_set_field(host->base + MSDC_PAD_TUNE, 2045 MSDC_PAD_TUNE_CMDRRDLY, 2046 host->hs200_cmd_int_delay); 2047 2048 if (host->hs400_cmd_resp_sel_rising) 2049 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2050 else 2051 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2052 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2053 sdr_set_field(host->base + PAD_CMD_TUNE, 2054 PAD_CMD_TUNE_RX_DLY3, i); 2055 /* 2056 * Using the same parameters, it may sometimes pass the test, 2057 * but sometimes it may fail. To make sure the parameters are 2058 * more stable, we test each set of parameters 3 times. 2059 */ 2060 for (j = 0; j < 3; j++) { 2061 mmc_send_tuning(mmc, opcode, &cmd_err); 2062 if (!cmd_err) { 2063 cmd_delay |= (1 << i); 2064 } else { 2065 cmd_delay &= ~(1 << i); 2066 break; 2067 } 2068 } 2069 } 2070 final_cmd_delay = get_best_delay(host, cmd_delay); 2071 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3, 2072 final_cmd_delay.final_phase); 2073 final_delay = final_cmd_delay.final_phase; 2074 2075 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 2076 return final_delay == 0xff ? -EIO : 0; 2077 } 2078 2079 static int msdc_tune_data(struct mmc_host *mmc, u32 opcode) 2080 { 2081 struct msdc_host *host = mmc_priv(mmc); 2082 u32 rise_delay = 0, fall_delay = 0; 2083 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 2084 u8 final_delay, final_maxlen; 2085 int i, ret; 2086 2087 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 2088 host->latch_ck); 2089 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2090 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2091 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2092 msdc_set_data_delay(host, i); 2093 ret = mmc_send_tuning(mmc, opcode, NULL); 2094 if (!ret) 2095 rise_delay |= (1 << i); 2096 } 2097 final_rise_delay = get_best_delay(host, rise_delay); 2098 /* if rising edge has enough margin, then do not scan falling edge */ 2099 if (final_rise_delay.maxlen >= 12 || 2100 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 2101 goto skip_fall; 2102 2103 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2104 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2105 for (i = 0; i < PAD_DELAY_MAX; i++) { 2106 msdc_set_data_delay(host, i); 2107 ret = mmc_send_tuning(mmc, opcode, NULL); 2108 if (!ret) 2109 fall_delay |= (1 << i); 2110 } 2111 final_fall_delay = get_best_delay(host, fall_delay); 2112 2113 skip_fall: 2114 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 2115 if (final_maxlen == final_rise_delay.maxlen) { 2116 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2117 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2118 final_delay = final_rise_delay.final_phase; 2119 } else { 2120 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2121 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2122 final_delay = final_fall_delay.final_phase; 2123 } 2124 msdc_set_data_delay(host, final_delay); 2125 2126 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay); 2127 return final_delay == 0xff ? -EIO : 0; 2128 } 2129 2130 /* 2131 * MSDC IP which supports data tune + async fifo can do CMD/DAT tune 2132 * together, which can save the tuning time. 2133 */ 2134 static int msdc_tune_together(struct mmc_host *mmc, u32 opcode) 2135 { 2136 struct msdc_host *host = mmc_priv(mmc); 2137 u32 rise_delay = 0, fall_delay = 0; 2138 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 2139 u8 final_delay, final_maxlen; 2140 int i, ret; 2141 2142 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 2143 host->latch_ck); 2144 2145 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2146 sdr_clr_bits(host->base + MSDC_IOCON, 2147 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2148 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2149 msdc_set_cmd_delay(host, i); 2150 msdc_set_data_delay(host, i); 2151 ret = mmc_send_tuning(mmc, opcode, NULL); 2152 if (!ret) 2153 rise_delay |= (1 << i); 2154 } 2155 final_rise_delay = get_best_delay(host, rise_delay); 2156 /* if rising edge has enough margin, then do not scan falling edge */ 2157 if (final_rise_delay.maxlen >= 12 || 2158 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 2159 goto skip_fall; 2160 2161 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2162 sdr_set_bits(host->base + MSDC_IOCON, 2163 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2164 for (i = 0; i < PAD_DELAY_MAX; i++) { 2165 msdc_set_cmd_delay(host, i); 2166 msdc_set_data_delay(host, i); 2167 ret = mmc_send_tuning(mmc, opcode, NULL); 2168 if (!ret) 2169 fall_delay |= (1 << i); 2170 } 2171 final_fall_delay = get_best_delay(host, fall_delay); 2172 2173 skip_fall: 2174 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 2175 if (final_maxlen == final_rise_delay.maxlen) { 2176 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2177 sdr_clr_bits(host->base + MSDC_IOCON, 2178 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2179 final_delay = final_rise_delay.final_phase; 2180 } else { 2181 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2182 sdr_set_bits(host->base + MSDC_IOCON, 2183 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2184 final_delay = final_fall_delay.final_phase; 2185 } 2186 2187 msdc_set_cmd_delay(host, final_delay); 2188 msdc_set_data_delay(host, final_delay); 2189 2190 dev_dbg(host->dev, "Final pad delay: %x\n", final_delay); 2191 return final_delay == 0xff ? -EIO : 0; 2192 } 2193 2194 static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode) 2195 { 2196 struct msdc_host *host = mmc_priv(mmc); 2197 int ret; 2198 u32 tune_reg = host->dev_comp->pad_tune_reg; 2199 2200 if (host->dev_comp->data_tune && host->dev_comp->async_fifo) { 2201 ret = msdc_tune_together(mmc, opcode); 2202 if (host->hs400_mode) { 2203 sdr_clr_bits(host->base + MSDC_IOCON, 2204 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2205 msdc_set_data_delay(host, 0); 2206 } 2207 goto tune_done; 2208 } 2209 if (host->hs400_mode && 2210 host->dev_comp->hs400_tune) 2211 ret = hs400_tune_response(mmc, opcode); 2212 else 2213 ret = msdc_tune_response(mmc, opcode); 2214 if (ret == -EIO) { 2215 dev_err(host->dev, "Tune response fail!\n"); 2216 return ret; 2217 } 2218 if (host->hs400_mode == false) { 2219 ret = msdc_tune_data(mmc, opcode); 2220 if (ret == -EIO) 2221 dev_err(host->dev, "Tune data fail!\n"); 2222 } 2223 2224 tune_done: 2225 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 2226 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 2227 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 2228 if (host->top_base) { 2229 host->saved_tune_para.emmc_top_control = readl(host->top_base + 2230 EMMC_TOP_CONTROL); 2231 host->saved_tune_para.emmc_top_cmd = readl(host->top_base + 2232 EMMC_TOP_CMD); 2233 } 2234 return ret; 2235 } 2236 2237 static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 2238 { 2239 struct msdc_host *host = mmc_priv(mmc); 2240 host->hs400_mode = true; 2241 2242 if (host->top_base) 2243 writel(host->hs400_ds_delay, 2244 host->top_base + EMMC50_PAD_DS_TUNE); 2245 else 2246 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); 2247 /* hs400 mode must set it to 0 */ 2248 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS); 2249 /* to improve read performance, set outstanding to 2 */ 2250 sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2); 2251 2252 return 0; 2253 } 2254 2255 static void msdc_hw_reset(struct mmc_host *mmc) 2256 { 2257 struct msdc_host *host = mmc_priv(mmc); 2258 2259 sdr_set_bits(host->base + EMMC_IOCON, 1); 2260 udelay(10); /* 10us is enough */ 2261 sdr_clr_bits(host->base + EMMC_IOCON, 1); 2262 } 2263 2264 static void msdc_ack_sdio_irq(struct mmc_host *mmc) 2265 { 2266 unsigned long flags; 2267 struct msdc_host *host = mmc_priv(mmc); 2268 2269 spin_lock_irqsave(&host->lock, flags); 2270 __msdc_enable_sdio_irq(host, 1); 2271 spin_unlock_irqrestore(&host->lock, flags); 2272 } 2273 2274 static int msdc_get_cd(struct mmc_host *mmc) 2275 { 2276 struct msdc_host *host = mmc_priv(mmc); 2277 int val; 2278 2279 if (mmc->caps & MMC_CAP_NONREMOVABLE) 2280 return 1; 2281 2282 if (!host->internal_cd) 2283 return mmc_gpio_get_cd(mmc); 2284 2285 val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS; 2286 if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH) 2287 return !!val; 2288 else 2289 return !val; 2290 } 2291 2292 static void msdc_hs400_enhanced_strobe(struct mmc_host *mmc, 2293 struct mmc_ios *ios) 2294 { 2295 struct msdc_host *host = mmc_priv(mmc); 2296 2297 if (ios->enhanced_strobe) { 2298 msdc_prepare_hs400_tuning(mmc, ios); 2299 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 1); 2300 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 1); 2301 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 1); 2302 2303 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL); 2304 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL); 2305 sdr_clr_bits(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT); 2306 } else { 2307 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 0); 2308 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 0); 2309 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 0); 2310 2311 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL); 2312 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL); 2313 sdr_set_field(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT, 0xb4); 2314 } 2315 } 2316 2317 static void msdc_cqe_enable(struct mmc_host *mmc) 2318 { 2319 struct msdc_host *host = mmc_priv(mmc); 2320 2321 /* enable cmdq irq */ 2322 writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN); 2323 /* enable busy check */ 2324 sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); 2325 /* default write data / busy timeout 20s */ 2326 msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0); 2327 /* default read data timeout 1s */ 2328 msdc_set_timeout(host, 1000000000ULL, 0); 2329 } 2330 2331 static void msdc_cqe_disable(struct mmc_host *mmc, bool recovery) 2332 { 2333 struct msdc_host *host = mmc_priv(mmc); 2334 2335 /* disable cmdq irq */ 2336 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ); 2337 /* disable busy check */ 2338 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); 2339 2340 if (recovery) { 2341 sdr_set_field(host->base + MSDC_DMA_CTRL, 2342 MSDC_DMA_CTRL_STOP, 1); 2343 msdc_reset_hw(host); 2344 } 2345 } 2346 2347 static void msdc_cqe_pre_enable(struct mmc_host *mmc) 2348 { 2349 struct cqhci_host *cq_host = mmc->cqe_private; 2350 u32 reg; 2351 2352 reg = cqhci_readl(cq_host, CQHCI_CFG); 2353 reg |= CQHCI_ENABLE; 2354 cqhci_writel(cq_host, reg, CQHCI_CFG); 2355 } 2356 2357 static void msdc_cqe_post_disable(struct mmc_host *mmc) 2358 { 2359 struct cqhci_host *cq_host = mmc->cqe_private; 2360 u32 reg; 2361 2362 reg = cqhci_readl(cq_host, CQHCI_CFG); 2363 reg &= ~CQHCI_ENABLE; 2364 cqhci_writel(cq_host, reg, CQHCI_CFG); 2365 } 2366 2367 static const struct mmc_host_ops mt_msdc_ops = { 2368 .post_req = msdc_post_req, 2369 .pre_req = msdc_pre_req, 2370 .request = msdc_ops_request, 2371 .set_ios = msdc_ops_set_ios, 2372 .get_ro = mmc_gpio_get_ro, 2373 .get_cd = msdc_get_cd, 2374 .hs400_enhanced_strobe = msdc_hs400_enhanced_strobe, 2375 .enable_sdio_irq = msdc_enable_sdio_irq, 2376 .ack_sdio_irq = msdc_ack_sdio_irq, 2377 .start_signal_voltage_switch = msdc_ops_switch_volt, 2378 .card_busy = msdc_card_busy, 2379 .execute_tuning = msdc_execute_tuning, 2380 .prepare_hs400_tuning = msdc_prepare_hs400_tuning, 2381 .hw_reset = msdc_hw_reset, 2382 }; 2383 2384 static const struct cqhci_host_ops msdc_cmdq_ops = { 2385 .enable = msdc_cqe_enable, 2386 .disable = msdc_cqe_disable, 2387 .pre_enable = msdc_cqe_pre_enable, 2388 .post_disable = msdc_cqe_post_disable, 2389 }; 2390 2391 static void msdc_of_property_parse(struct platform_device *pdev, 2392 struct msdc_host *host) 2393 { 2394 of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck", 2395 &host->latch_ck); 2396 2397 of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay", 2398 &host->hs400_ds_delay); 2399 2400 of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay", 2401 &host->hs200_cmd_int_delay); 2402 2403 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay", 2404 &host->hs400_cmd_int_delay); 2405 2406 if (of_property_read_bool(pdev->dev.of_node, 2407 "mediatek,hs400-cmd-resp-sel-rising")) 2408 host->hs400_cmd_resp_sel_rising = true; 2409 else 2410 host->hs400_cmd_resp_sel_rising = false; 2411 2412 if (of_property_read_bool(pdev->dev.of_node, 2413 "supports-cqe")) 2414 host->cqhci = true; 2415 else 2416 host->cqhci = false; 2417 } 2418 2419 static int msdc_of_clock_parse(struct platform_device *pdev, 2420 struct msdc_host *host) 2421 { 2422 int ret; 2423 2424 host->src_clk = devm_clk_get(&pdev->dev, "source"); 2425 if (IS_ERR(host->src_clk)) 2426 return PTR_ERR(host->src_clk); 2427 2428 host->h_clk = devm_clk_get(&pdev->dev, "hclk"); 2429 if (IS_ERR(host->h_clk)) 2430 return PTR_ERR(host->h_clk); 2431 2432 host->bus_clk = devm_clk_get_optional(&pdev->dev, "bus_clk"); 2433 if (IS_ERR(host->bus_clk)) 2434 host->bus_clk = NULL; 2435 2436 /*source clock control gate is optional clock*/ 2437 host->src_clk_cg = devm_clk_get_optional(&pdev->dev, "source_cg"); 2438 if (IS_ERR(host->src_clk_cg)) 2439 host->src_clk_cg = NULL; 2440 2441 host->sys_clk_cg = devm_clk_get_optional(&pdev->dev, "sys_cg"); 2442 if (IS_ERR(host->sys_clk_cg)) 2443 host->sys_clk_cg = NULL; 2444 2445 /* If present, always enable for this clock gate */ 2446 clk_prepare_enable(host->sys_clk_cg); 2447 2448 host->bulk_clks[0].id = "pclk_cg"; 2449 host->bulk_clks[1].id = "axi_cg"; 2450 host->bulk_clks[2].id = "ahb_cg"; 2451 ret = devm_clk_bulk_get_optional(&pdev->dev, MSDC_NR_CLOCKS, 2452 host->bulk_clks); 2453 if (ret) { 2454 dev_err(&pdev->dev, "Cannot get pclk/axi/ahb clock gates\n"); 2455 return ret; 2456 } 2457 2458 return 0; 2459 } 2460 2461 static int msdc_drv_probe(struct platform_device *pdev) 2462 { 2463 struct mmc_host *mmc; 2464 struct msdc_host *host; 2465 struct resource *res; 2466 int ret; 2467 2468 if (!pdev->dev.of_node) { 2469 dev_err(&pdev->dev, "No DT found\n"); 2470 return -EINVAL; 2471 } 2472 2473 /* Allocate MMC host for this device */ 2474 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev); 2475 if (!mmc) 2476 return -ENOMEM; 2477 2478 host = mmc_priv(mmc); 2479 ret = mmc_of_parse(mmc); 2480 if (ret) 2481 goto host_free; 2482 2483 host->base = devm_platform_ioremap_resource(pdev, 0); 2484 if (IS_ERR(host->base)) { 2485 ret = PTR_ERR(host->base); 2486 goto host_free; 2487 } 2488 2489 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2490 if (res) { 2491 host->top_base = devm_ioremap_resource(&pdev->dev, res); 2492 if (IS_ERR(host->top_base)) 2493 host->top_base = NULL; 2494 } 2495 2496 ret = mmc_regulator_get_supply(mmc); 2497 if (ret) 2498 goto host_free; 2499 2500 ret = msdc_of_clock_parse(pdev, host); 2501 if (ret) 2502 goto host_free; 2503 2504 host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev, 2505 "hrst"); 2506 if (IS_ERR(host->reset)) { 2507 ret = PTR_ERR(host->reset); 2508 goto host_free; 2509 } 2510 2511 host->irq = platform_get_irq(pdev, 0); 2512 if (host->irq < 0) { 2513 ret = -EINVAL; 2514 goto host_free; 2515 } 2516 2517 host->pinctrl = devm_pinctrl_get(&pdev->dev); 2518 if (IS_ERR(host->pinctrl)) { 2519 ret = PTR_ERR(host->pinctrl); 2520 dev_err(&pdev->dev, "Cannot find pinctrl!\n"); 2521 goto host_free; 2522 } 2523 2524 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); 2525 if (IS_ERR(host->pins_default)) { 2526 ret = PTR_ERR(host->pins_default); 2527 dev_err(&pdev->dev, "Cannot find pinctrl default!\n"); 2528 goto host_free; 2529 } 2530 2531 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); 2532 if (IS_ERR(host->pins_uhs)) { 2533 ret = PTR_ERR(host->pins_uhs); 2534 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); 2535 goto host_free; 2536 } 2537 2538 msdc_of_property_parse(pdev, host); 2539 2540 host->dev = &pdev->dev; 2541 host->dev_comp = of_device_get_match_data(&pdev->dev); 2542 host->src_clk_freq = clk_get_rate(host->src_clk); 2543 /* Set host parameters to mmc */ 2544 mmc->ops = &mt_msdc_ops; 2545 if (host->dev_comp->clk_div_bits == 8) 2546 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255); 2547 else 2548 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095); 2549 2550 if (!(mmc->caps & MMC_CAP_NONREMOVABLE) && 2551 !mmc_can_gpio_cd(mmc) && 2552 host->dev_comp->use_internal_cd) { 2553 /* 2554 * Is removable but no GPIO declared, so 2555 * use internal functionality. 2556 */ 2557 host->internal_cd = true; 2558 } 2559 2560 if (mmc->caps & MMC_CAP_SDIO_IRQ) 2561 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 2562 2563 mmc->caps |= MMC_CAP_CMD23; 2564 if (host->cqhci) 2565 mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 2566 /* MMC core transfer sizes tunable parameters */ 2567 mmc->max_segs = MAX_BD_NUM; 2568 if (host->dev_comp->support_64g) 2569 mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT; 2570 else 2571 mmc->max_seg_size = BDMA_DESC_BUFLEN; 2572 mmc->max_blk_size = 2048; 2573 mmc->max_req_size = 512 * 1024; 2574 mmc->max_blk_count = mmc->max_req_size / 512; 2575 if (host->dev_comp->support_64g) 2576 host->dma_mask = DMA_BIT_MASK(36); 2577 else 2578 host->dma_mask = DMA_BIT_MASK(32); 2579 mmc_dev(mmc)->dma_mask = &host->dma_mask; 2580 2581 if (mmc->caps2 & MMC_CAP2_CQE) { 2582 host->cq_host = devm_kzalloc(mmc->parent, 2583 sizeof(*host->cq_host), 2584 GFP_KERNEL); 2585 if (!host->cq_host) { 2586 ret = -ENOMEM; 2587 goto host_free; 2588 } 2589 host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 2590 host->cq_host->mmio = host->base + 0x800; 2591 host->cq_host->ops = &msdc_cmdq_ops; 2592 ret = cqhci_init(host->cq_host, mmc, true); 2593 if (ret) 2594 goto host_free; 2595 mmc->max_segs = 128; 2596 /* cqhci 16bit length */ 2597 /* 0 size, means 65536 so we don't have to -1 here */ 2598 mmc->max_seg_size = 64 * 1024; 2599 } 2600 2601 host->timeout_clks = 3 * 1048576; 2602 host->dma.gpd = dma_alloc_coherent(&pdev->dev, 2603 2 * sizeof(struct mt_gpdma_desc), 2604 &host->dma.gpd_addr, GFP_KERNEL); 2605 host->dma.bd = dma_alloc_coherent(&pdev->dev, 2606 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2607 &host->dma.bd_addr, GFP_KERNEL); 2608 if (!host->dma.gpd || !host->dma.bd) { 2609 ret = -ENOMEM; 2610 goto release_mem; 2611 } 2612 msdc_init_gpd_bd(host, &host->dma); 2613 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); 2614 spin_lock_init(&host->lock); 2615 2616 platform_set_drvdata(pdev, mmc); 2617 msdc_ungate_clock(host); 2618 msdc_init_hw(host); 2619 2620 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, 2621 IRQF_TRIGGER_NONE, pdev->name, host); 2622 if (ret) 2623 goto release; 2624 2625 pm_runtime_set_active(host->dev); 2626 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); 2627 pm_runtime_use_autosuspend(host->dev); 2628 pm_runtime_enable(host->dev); 2629 ret = mmc_add_host(mmc); 2630 2631 if (ret) 2632 goto end; 2633 2634 return 0; 2635 end: 2636 pm_runtime_disable(host->dev); 2637 release: 2638 platform_set_drvdata(pdev, NULL); 2639 msdc_deinit_hw(host); 2640 msdc_gate_clock(host); 2641 release_mem: 2642 if (host->dma.gpd) 2643 dma_free_coherent(&pdev->dev, 2644 2 * sizeof(struct mt_gpdma_desc), 2645 host->dma.gpd, host->dma.gpd_addr); 2646 if (host->dma.bd) 2647 dma_free_coherent(&pdev->dev, 2648 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2649 host->dma.bd, host->dma.bd_addr); 2650 host_free: 2651 mmc_free_host(mmc); 2652 2653 return ret; 2654 } 2655 2656 static int msdc_drv_remove(struct platform_device *pdev) 2657 { 2658 struct mmc_host *mmc; 2659 struct msdc_host *host; 2660 2661 mmc = platform_get_drvdata(pdev); 2662 host = mmc_priv(mmc); 2663 2664 pm_runtime_get_sync(host->dev); 2665 2666 platform_set_drvdata(pdev, NULL); 2667 mmc_remove_host(mmc); 2668 msdc_deinit_hw(host); 2669 msdc_gate_clock(host); 2670 2671 pm_runtime_disable(host->dev); 2672 pm_runtime_put_noidle(host->dev); 2673 dma_free_coherent(&pdev->dev, 2674 2 * sizeof(struct mt_gpdma_desc), 2675 host->dma.gpd, host->dma.gpd_addr); 2676 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2677 host->dma.bd, host->dma.bd_addr); 2678 2679 mmc_free_host(mmc); 2680 2681 return 0; 2682 } 2683 2684 static void msdc_save_reg(struct msdc_host *host) 2685 { 2686 u32 tune_reg = host->dev_comp->pad_tune_reg; 2687 2688 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); 2689 host->save_para.iocon = readl(host->base + MSDC_IOCON); 2690 host->save_para.sdc_cfg = readl(host->base + SDC_CFG); 2691 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); 2692 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); 2693 host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2); 2694 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); 2695 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 2696 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); 2697 host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3); 2698 host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG); 2699 if (host->top_base) { 2700 host->save_para.emmc_top_control = 2701 readl(host->top_base + EMMC_TOP_CONTROL); 2702 host->save_para.emmc_top_cmd = 2703 readl(host->top_base + EMMC_TOP_CMD); 2704 host->save_para.emmc50_pad_ds_tune = 2705 readl(host->top_base + EMMC50_PAD_DS_TUNE); 2706 } else { 2707 host->save_para.pad_tune = readl(host->base + tune_reg); 2708 } 2709 } 2710 2711 static void msdc_restore_reg(struct msdc_host *host) 2712 { 2713 struct mmc_host *mmc = mmc_from_priv(host); 2714 u32 tune_reg = host->dev_comp->pad_tune_reg; 2715 2716 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); 2717 writel(host->save_para.iocon, host->base + MSDC_IOCON); 2718 writel(host->save_para.sdc_cfg, host->base + SDC_CFG); 2719 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); 2720 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); 2721 writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2); 2722 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); 2723 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE); 2724 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); 2725 writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3); 2726 writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG); 2727 if (host->top_base) { 2728 writel(host->save_para.emmc_top_control, 2729 host->top_base + EMMC_TOP_CONTROL); 2730 writel(host->save_para.emmc_top_cmd, 2731 host->top_base + EMMC_TOP_CMD); 2732 writel(host->save_para.emmc50_pad_ds_tune, 2733 host->top_base + EMMC50_PAD_DS_TUNE); 2734 } else { 2735 writel(host->save_para.pad_tune, host->base + tune_reg); 2736 } 2737 2738 if (sdio_irq_claimed(mmc)) 2739 __msdc_enable_sdio_irq(host, 1); 2740 } 2741 2742 static int __maybe_unused msdc_runtime_suspend(struct device *dev) 2743 { 2744 struct mmc_host *mmc = dev_get_drvdata(dev); 2745 struct msdc_host *host = mmc_priv(mmc); 2746 2747 msdc_save_reg(host); 2748 msdc_gate_clock(host); 2749 return 0; 2750 } 2751 2752 static int __maybe_unused msdc_runtime_resume(struct device *dev) 2753 { 2754 struct mmc_host *mmc = dev_get_drvdata(dev); 2755 struct msdc_host *host = mmc_priv(mmc); 2756 2757 msdc_ungate_clock(host); 2758 msdc_restore_reg(host); 2759 return 0; 2760 } 2761 2762 static int __maybe_unused msdc_suspend(struct device *dev) 2763 { 2764 struct mmc_host *mmc = dev_get_drvdata(dev); 2765 int ret; 2766 2767 if (mmc->caps2 & MMC_CAP2_CQE) { 2768 ret = cqhci_suspend(mmc); 2769 if (ret) 2770 return ret; 2771 } 2772 2773 return pm_runtime_force_suspend(dev); 2774 } 2775 2776 static int __maybe_unused msdc_resume(struct device *dev) 2777 { 2778 return pm_runtime_force_resume(dev); 2779 } 2780 2781 static const struct dev_pm_ops msdc_dev_pm_ops = { 2782 SET_SYSTEM_SLEEP_PM_OPS(msdc_suspend, msdc_resume) 2783 SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL) 2784 }; 2785 2786 static struct platform_driver mt_msdc_driver = { 2787 .probe = msdc_drv_probe, 2788 .remove = msdc_drv_remove, 2789 .driver = { 2790 .name = "mtk-msdc", 2791 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 2792 .of_match_table = msdc_of_ids, 2793 .pm = &msdc_dev_pm_ops, 2794 }, 2795 }; 2796 2797 module_platform_driver(mt_msdc_driver); 2798 MODULE_LICENSE("GPL v2"); 2799 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver"); 2800