1 /* 2 * 3 * Intel Management Engine Interface (Intel MEI) Linux driver 4 * Copyright (c) 2003-2012, Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 */ 16 #include <linux/module.h> 17 #include <linux/moduleparam.h> 18 #include <linux/kernel.h> 19 #include <linux/device.h> 20 #include <linux/fs.h> 21 #include <linux/errno.h> 22 #include <linux/types.h> 23 #include <linux/fcntl.h> 24 #include <linux/aio.h> 25 #include <linux/pci.h> 26 #include <linux/poll.h> 27 #include <linux/ioctl.h> 28 #include <linux/cdev.h> 29 #include <linux/sched.h> 30 #include <linux/uuid.h> 31 #include <linux/compat.h> 32 #include <linux/jiffies.h> 33 #include <linux/interrupt.h> 34 #include <linux/miscdevice.h> 35 36 #include <linux/mei.h> 37 38 #include "mei_dev.h" 39 #include "client.h" 40 #include "hw-me-regs.h" 41 #include "hw-me.h" 42 43 /* mei_pci_tbl - PCI Device ID Table */ 44 static const struct pci_device_id mei_me_pci_tbl[] = { 45 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82946GZ)}, 46 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82G35)}, 47 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82Q965)}, 48 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82G965)}, 49 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82GM965)}, 50 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82GME965)}, 51 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_82Q35)}, 52 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_82G33)}, 53 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_82Q33)}, 54 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_82X38)}, 55 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_3200)}, 56 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_6)}, 57 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_7)}, 58 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_8)}, 59 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_9)}, 60 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_10)}, 61 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9M_1)}, 62 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9M_2)}, 63 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9M_3)}, 64 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9M_4)}, 65 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH10_1)}, 66 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH10_2)}, 67 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH10_3)}, 68 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH10_4)}, 69 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_IBXPK_1)}, 70 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_IBXPK_2)}, 71 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_CPT_1)}, 72 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_PBG_1)}, 73 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_PPT_1)}, 74 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_PPT_2)}, 75 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_PPT_3)}, 76 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_LPT_H)}, 77 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_LPT_W)}, 78 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_LPT_LP)}, 79 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_LPT_HR)}, 80 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_WPT_LP)}, 81 82 /* required last entry */ 83 {0, } 84 }; 85 86 MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl); 87 88 /** 89 * mei_quirk_probe - probe for devices that doesn't valid ME interface 90 * 91 * @pdev: PCI device structure 92 * @ent: entry into pci_device_table 93 * 94 * returns true if ME Interface is valid, false otherwise 95 */ 96 static bool mei_me_quirk_probe(struct pci_dev *pdev, 97 const struct pci_device_id *ent) 98 { 99 u32 reg; 100 if (ent->device == MEI_DEV_ID_PBG_1) { 101 pci_read_config_dword(pdev, 0x48, ®); 102 /* make sure that bit 9 is up and bit 10 is down */ 103 if ((reg & 0x600) == 0x200) { 104 dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n"); 105 return false; 106 } 107 } 108 return true; 109 } 110 /** 111 * mei_probe - Device Initialization Routine 112 * 113 * @pdev: PCI device structure 114 * @ent: entry in kcs_pci_tbl 115 * 116 * returns 0 on success, <0 on failure. 117 */ 118 static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 119 { 120 struct mei_device *dev; 121 struct mei_me_hw *hw; 122 int err; 123 124 125 if (!mei_me_quirk_probe(pdev, ent)) { 126 err = -ENODEV; 127 goto end; 128 } 129 130 /* enable pci dev */ 131 err = pci_enable_device(pdev); 132 if (err) { 133 dev_err(&pdev->dev, "failed to enable pci device.\n"); 134 goto end; 135 } 136 /* set PCI host mastering */ 137 pci_set_master(pdev); 138 /* pci request regions for mei driver */ 139 err = pci_request_regions(pdev, KBUILD_MODNAME); 140 if (err) { 141 dev_err(&pdev->dev, "failed to get pci regions.\n"); 142 goto disable_device; 143 } 144 145 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) || 146 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) { 147 148 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 149 if (err) 150 err = dma_set_coherent_mask(&pdev->dev, 151 DMA_BIT_MASK(32)); 152 } 153 if (err) { 154 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n"); 155 goto release_regions; 156 } 157 158 159 /* allocates and initializes the mei dev structure */ 160 dev = mei_me_dev_init(pdev); 161 if (!dev) { 162 err = -ENOMEM; 163 goto release_regions; 164 } 165 hw = to_me_hw(dev); 166 /* mapping IO device memory */ 167 hw->mem_addr = pci_iomap(pdev, 0, 0); 168 if (!hw->mem_addr) { 169 dev_err(&pdev->dev, "mapping I/O device memory failure.\n"); 170 err = -ENOMEM; 171 goto free_device; 172 } 173 pci_enable_msi(pdev); 174 175 /* request and enable interrupt */ 176 if (pci_dev_msi_enabled(pdev)) 177 err = request_threaded_irq(pdev->irq, 178 NULL, 179 mei_me_irq_thread_handler, 180 IRQF_ONESHOT, KBUILD_MODNAME, dev); 181 else 182 err = request_threaded_irq(pdev->irq, 183 mei_me_irq_quick_handler, 184 mei_me_irq_thread_handler, 185 IRQF_SHARED, KBUILD_MODNAME, dev); 186 187 if (err) { 188 dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n", 189 pdev->irq); 190 goto disable_msi; 191 } 192 193 if (mei_start(dev)) { 194 dev_err(&pdev->dev, "init hw failure.\n"); 195 err = -ENODEV; 196 goto release_irq; 197 } 198 199 err = mei_register(dev); 200 if (err) 201 goto release_irq; 202 203 pci_set_drvdata(pdev, dev); 204 205 schedule_delayed_work(&dev->timer_work, HZ); 206 207 dev_dbg(&pdev->dev, "initialization successful.\n"); 208 209 return 0; 210 211 release_irq: 212 mei_cancel_work(dev); 213 mei_disable_interrupts(dev); 214 free_irq(pdev->irq, dev); 215 disable_msi: 216 pci_disable_msi(pdev); 217 pci_iounmap(pdev, hw->mem_addr); 218 free_device: 219 kfree(dev); 220 release_regions: 221 pci_release_regions(pdev); 222 disable_device: 223 pci_disable_device(pdev); 224 end: 225 dev_err(&pdev->dev, "initialization failed.\n"); 226 return err; 227 } 228 229 /** 230 * mei_remove - Device Removal Routine 231 * 232 * @pdev: PCI device structure 233 * 234 * mei_remove is called by the PCI subsystem to alert the driver 235 * that it should release a PCI device. 236 */ 237 static void mei_me_remove(struct pci_dev *pdev) 238 { 239 struct mei_device *dev; 240 struct mei_me_hw *hw; 241 242 dev = pci_get_drvdata(pdev); 243 if (!dev) 244 return; 245 246 hw = to_me_hw(dev); 247 248 249 dev_dbg(&pdev->dev, "stop\n"); 250 mei_stop(dev); 251 252 /* disable interrupts */ 253 mei_disable_interrupts(dev); 254 255 free_irq(pdev->irq, dev); 256 pci_disable_msi(pdev); 257 258 if (hw->mem_addr) 259 pci_iounmap(pdev, hw->mem_addr); 260 261 mei_deregister(dev); 262 263 kfree(dev); 264 265 pci_release_regions(pdev); 266 pci_disable_device(pdev); 267 268 269 } 270 #ifdef CONFIG_PM_SLEEP 271 static int mei_me_pci_suspend(struct device *device) 272 { 273 struct pci_dev *pdev = to_pci_dev(device); 274 struct mei_device *dev = pci_get_drvdata(pdev); 275 276 if (!dev) 277 return -ENODEV; 278 279 dev_dbg(&pdev->dev, "suspend\n"); 280 281 mei_stop(dev); 282 283 mei_disable_interrupts(dev); 284 285 free_irq(pdev->irq, dev); 286 pci_disable_msi(pdev); 287 288 return 0; 289 } 290 291 static int mei_me_pci_resume(struct device *device) 292 { 293 struct pci_dev *pdev = to_pci_dev(device); 294 struct mei_device *dev; 295 int err; 296 297 dev = pci_get_drvdata(pdev); 298 if (!dev) 299 return -ENODEV; 300 301 pci_enable_msi(pdev); 302 303 /* request and enable interrupt */ 304 if (pci_dev_msi_enabled(pdev)) 305 err = request_threaded_irq(pdev->irq, 306 NULL, 307 mei_me_irq_thread_handler, 308 IRQF_ONESHOT, KBUILD_MODNAME, dev); 309 else 310 err = request_threaded_irq(pdev->irq, 311 mei_me_irq_quick_handler, 312 mei_me_irq_thread_handler, 313 IRQF_SHARED, KBUILD_MODNAME, dev); 314 315 if (err) { 316 dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n", 317 pdev->irq); 318 return err; 319 } 320 321 err = mei_restart(dev); 322 if (err) 323 return err; 324 325 /* Start timer if stopped in suspend */ 326 schedule_delayed_work(&dev->timer_work, HZ); 327 328 return 0; 329 } 330 331 static SIMPLE_DEV_PM_OPS(mei_me_pm_ops, mei_me_pci_suspend, mei_me_pci_resume); 332 #define MEI_ME_PM_OPS (&mei_me_pm_ops) 333 #else 334 #define MEI_ME_PM_OPS NULL 335 #endif /* CONFIG_PM_SLEEP */ 336 /* 337 * PCI driver structure 338 */ 339 static struct pci_driver mei_me_driver = { 340 .name = KBUILD_MODNAME, 341 .id_table = mei_me_pci_tbl, 342 .probe = mei_me_probe, 343 .remove = mei_me_remove, 344 .shutdown = mei_me_remove, 345 .driver.pm = MEI_ME_PM_OPS, 346 }; 347 348 module_pci_driver(mei_me_driver); 349 350 MODULE_AUTHOR("Intel Corporation"); 351 MODULE_DESCRIPTION("Intel(R) Management Engine Interface"); 352 MODULE_LICENSE("GPL v2"); 353