1*2874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
2e0a3389aSMark Brown /*
3e0a3389aSMark Brown * wm8350-irq.c -- IRQ support for Wolfson WM8350
4e0a3389aSMark Brown *
5e0a3389aSMark Brown * Copyright 2007, 2008, 2009 Wolfson Microelectronics PLC.
6e0a3389aSMark Brown *
7e0a3389aSMark Brown * Author: Liam Girdwood, Mark Brown
8e0a3389aSMark Brown */
9e0a3389aSMark Brown
10e0a3389aSMark Brown #include <linux/kernel.h>
11e0a3389aSMark Brown #include <linux/module.h>
12e0a3389aSMark Brown #include <linux/bug.h>
13e0a3389aSMark Brown #include <linux/device.h>
14e0a3389aSMark Brown #include <linux/interrupt.h>
15760e4518SMark Brown #include <linux/irq.h>
16e0a3389aSMark Brown
17e0a3389aSMark Brown #include <linux/mfd/wm8350/core.h>
18e0a3389aSMark Brown #include <linux/mfd/wm8350/audio.h>
19e0a3389aSMark Brown #include <linux/mfd/wm8350/comparator.h>
20e0a3389aSMark Brown #include <linux/mfd/wm8350/gpio.h>
21e0a3389aSMark Brown #include <linux/mfd/wm8350/pmic.h>
22e0a3389aSMark Brown #include <linux/mfd/wm8350/rtc.h>
23e0a3389aSMark Brown #include <linux/mfd/wm8350/supply.h>
24e0a3389aSMark Brown #include <linux/mfd/wm8350/wdt.h>
25e0a3389aSMark Brown
260c7229f9SMark Brown #define WM8350_INT_OFFSET_1 0
270c7229f9SMark Brown #define WM8350_INT_OFFSET_2 1
280c7229f9SMark Brown #define WM8350_POWER_UP_INT_OFFSET 2
290c7229f9SMark Brown #define WM8350_UNDER_VOLTAGE_INT_OFFSET 3
300c7229f9SMark Brown #define WM8350_OVER_CURRENT_INT_OFFSET 4
310c7229f9SMark Brown #define WM8350_GPIO_INT_OFFSET 5
320c7229f9SMark Brown #define WM8350_COMPARATOR_INT_OFFSET 6
330c7229f9SMark Brown
340c7229f9SMark Brown struct wm8350_irq_data {
350c7229f9SMark Brown int primary;
360c7229f9SMark Brown int reg;
370c7229f9SMark Brown int mask;
380c7229f9SMark Brown int primary_only;
390c7229f9SMark Brown };
400c7229f9SMark Brown
410c7229f9SMark Brown static struct wm8350_irq_data wm8350_irqs[] = {
420c7229f9SMark Brown [WM8350_IRQ_OC_LS] = {
430c7229f9SMark Brown .primary = WM8350_OC_INT,
440c7229f9SMark Brown .reg = WM8350_OVER_CURRENT_INT_OFFSET,
450c7229f9SMark Brown .mask = WM8350_OC_LS_EINT,
460c7229f9SMark Brown .primary_only = 1,
470c7229f9SMark Brown },
480c7229f9SMark Brown [WM8350_IRQ_UV_DC1] = {
490c7229f9SMark Brown .primary = WM8350_UV_INT,
500c7229f9SMark Brown .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET,
510c7229f9SMark Brown .mask = WM8350_UV_DC1_EINT,
520c7229f9SMark Brown },
530c7229f9SMark Brown [WM8350_IRQ_UV_DC2] = {
540c7229f9SMark Brown .primary = WM8350_UV_INT,
550c7229f9SMark Brown .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET,
560c7229f9SMark Brown .mask = WM8350_UV_DC2_EINT,
570c7229f9SMark Brown },
580c7229f9SMark Brown [WM8350_IRQ_UV_DC3] = {
590c7229f9SMark Brown .primary = WM8350_UV_INT,
600c7229f9SMark Brown .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET,
610c7229f9SMark Brown .mask = WM8350_UV_DC3_EINT,
620c7229f9SMark Brown },
630c7229f9SMark Brown [WM8350_IRQ_UV_DC4] = {
640c7229f9SMark Brown .primary = WM8350_UV_INT,
650c7229f9SMark Brown .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET,
660c7229f9SMark Brown .mask = WM8350_UV_DC4_EINT,
670c7229f9SMark Brown },
680c7229f9SMark Brown [WM8350_IRQ_UV_DC5] = {
690c7229f9SMark Brown .primary = WM8350_UV_INT,
700c7229f9SMark Brown .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET,
710c7229f9SMark Brown .mask = WM8350_UV_DC5_EINT,
720c7229f9SMark Brown },
730c7229f9SMark Brown [WM8350_IRQ_UV_DC6] = {
740c7229f9SMark Brown .primary = WM8350_UV_INT,
750c7229f9SMark Brown .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET,
760c7229f9SMark Brown .mask = WM8350_UV_DC6_EINT,
770c7229f9SMark Brown },
780c7229f9SMark Brown [WM8350_IRQ_UV_LDO1] = {
790c7229f9SMark Brown .primary = WM8350_UV_INT,
800c7229f9SMark Brown .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET,
810c7229f9SMark Brown .mask = WM8350_UV_LDO1_EINT,
820c7229f9SMark Brown },
830c7229f9SMark Brown [WM8350_IRQ_UV_LDO2] = {
840c7229f9SMark Brown .primary = WM8350_UV_INT,
850c7229f9SMark Brown .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET,
860c7229f9SMark Brown .mask = WM8350_UV_LDO2_EINT,
870c7229f9SMark Brown },
880c7229f9SMark Brown [WM8350_IRQ_UV_LDO3] = {
890c7229f9SMark Brown .primary = WM8350_UV_INT,
900c7229f9SMark Brown .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET,
910c7229f9SMark Brown .mask = WM8350_UV_LDO3_EINT,
920c7229f9SMark Brown },
930c7229f9SMark Brown [WM8350_IRQ_UV_LDO4] = {
940c7229f9SMark Brown .primary = WM8350_UV_INT,
950c7229f9SMark Brown .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET,
960c7229f9SMark Brown .mask = WM8350_UV_LDO4_EINT,
970c7229f9SMark Brown },
980c7229f9SMark Brown [WM8350_IRQ_CHG_BAT_HOT] = {
990c7229f9SMark Brown .primary = WM8350_CHG_INT,
1000c7229f9SMark Brown .reg = WM8350_INT_OFFSET_1,
1010c7229f9SMark Brown .mask = WM8350_CHG_BAT_HOT_EINT,
1020c7229f9SMark Brown },
1030c7229f9SMark Brown [WM8350_IRQ_CHG_BAT_COLD] = {
1040c7229f9SMark Brown .primary = WM8350_CHG_INT,
1050c7229f9SMark Brown .reg = WM8350_INT_OFFSET_1,
1060c7229f9SMark Brown .mask = WM8350_CHG_BAT_COLD_EINT,
1070c7229f9SMark Brown },
1080c7229f9SMark Brown [WM8350_IRQ_CHG_BAT_FAIL] = {
1090c7229f9SMark Brown .primary = WM8350_CHG_INT,
1100c7229f9SMark Brown .reg = WM8350_INT_OFFSET_1,
1110c7229f9SMark Brown .mask = WM8350_CHG_BAT_FAIL_EINT,
1120c7229f9SMark Brown },
1130c7229f9SMark Brown [WM8350_IRQ_CHG_TO] = {
1140c7229f9SMark Brown .primary = WM8350_CHG_INT,
1150c7229f9SMark Brown .reg = WM8350_INT_OFFSET_1,
1160c7229f9SMark Brown .mask = WM8350_CHG_TO_EINT,
1170c7229f9SMark Brown },
1180c7229f9SMark Brown [WM8350_IRQ_CHG_END] = {
1190c7229f9SMark Brown .primary = WM8350_CHG_INT,
1200c7229f9SMark Brown .reg = WM8350_INT_OFFSET_1,
1210c7229f9SMark Brown .mask = WM8350_CHG_END_EINT,
1220c7229f9SMark Brown },
1230c7229f9SMark Brown [WM8350_IRQ_CHG_START] = {
1240c7229f9SMark Brown .primary = WM8350_CHG_INT,
1250c7229f9SMark Brown .reg = WM8350_INT_OFFSET_1,
1260c7229f9SMark Brown .mask = WM8350_CHG_START_EINT,
1270c7229f9SMark Brown },
1280c7229f9SMark Brown [WM8350_IRQ_CHG_FAST_RDY] = {
1290c7229f9SMark Brown .primary = WM8350_CHG_INT,
1300c7229f9SMark Brown .reg = WM8350_INT_OFFSET_1,
1310c7229f9SMark Brown .mask = WM8350_CHG_FAST_RDY_EINT,
1320c7229f9SMark Brown },
1330c7229f9SMark Brown [WM8350_IRQ_CHG_VBATT_LT_3P9] = {
1340c7229f9SMark Brown .primary = WM8350_CHG_INT,
1350c7229f9SMark Brown .reg = WM8350_INT_OFFSET_1,
1360c7229f9SMark Brown .mask = WM8350_CHG_VBATT_LT_3P9_EINT,
1370c7229f9SMark Brown },
1380c7229f9SMark Brown [WM8350_IRQ_CHG_VBATT_LT_3P1] = {
1390c7229f9SMark Brown .primary = WM8350_CHG_INT,
1400c7229f9SMark Brown .reg = WM8350_INT_OFFSET_1,
1410c7229f9SMark Brown .mask = WM8350_CHG_VBATT_LT_3P1_EINT,
1420c7229f9SMark Brown },
1430c7229f9SMark Brown [WM8350_IRQ_CHG_VBATT_LT_2P85] = {
1440c7229f9SMark Brown .primary = WM8350_CHG_INT,
1450c7229f9SMark Brown .reg = WM8350_INT_OFFSET_1,
1460c7229f9SMark Brown .mask = WM8350_CHG_VBATT_LT_2P85_EINT,
1470c7229f9SMark Brown },
1480c7229f9SMark Brown [WM8350_IRQ_RTC_ALM] = {
1490c7229f9SMark Brown .primary = WM8350_RTC_INT,
1500c7229f9SMark Brown .reg = WM8350_INT_OFFSET_1,
1510c7229f9SMark Brown .mask = WM8350_RTC_ALM_EINT,
1520c7229f9SMark Brown },
1530c7229f9SMark Brown [WM8350_IRQ_RTC_SEC] = {
1540c7229f9SMark Brown .primary = WM8350_RTC_INT,
1550c7229f9SMark Brown .reg = WM8350_INT_OFFSET_1,
1560c7229f9SMark Brown .mask = WM8350_RTC_SEC_EINT,
1570c7229f9SMark Brown },
1580c7229f9SMark Brown [WM8350_IRQ_RTC_PER] = {
1590c7229f9SMark Brown .primary = WM8350_RTC_INT,
1600c7229f9SMark Brown .reg = WM8350_INT_OFFSET_1,
1610c7229f9SMark Brown .mask = WM8350_RTC_PER_EINT,
1620c7229f9SMark Brown },
1630c7229f9SMark Brown [WM8350_IRQ_CS1] = {
1640c7229f9SMark Brown .primary = WM8350_CS_INT,
1650c7229f9SMark Brown .reg = WM8350_INT_OFFSET_2,
1660c7229f9SMark Brown .mask = WM8350_CS1_EINT,
1670c7229f9SMark Brown },
1680c7229f9SMark Brown [WM8350_IRQ_CS2] = {
1690c7229f9SMark Brown .primary = WM8350_CS_INT,
1700c7229f9SMark Brown .reg = WM8350_INT_OFFSET_2,
1710c7229f9SMark Brown .mask = WM8350_CS2_EINT,
1720c7229f9SMark Brown },
1730c7229f9SMark Brown [WM8350_IRQ_SYS_HYST_COMP_FAIL] = {
1740c7229f9SMark Brown .primary = WM8350_SYS_INT,
1750c7229f9SMark Brown .reg = WM8350_INT_OFFSET_2,
1760c7229f9SMark Brown .mask = WM8350_SYS_HYST_COMP_FAIL_EINT,
1770c7229f9SMark Brown },
1780c7229f9SMark Brown [WM8350_IRQ_SYS_CHIP_GT115] = {
1790c7229f9SMark Brown .primary = WM8350_SYS_INT,
1800c7229f9SMark Brown .reg = WM8350_INT_OFFSET_2,
1810c7229f9SMark Brown .mask = WM8350_SYS_CHIP_GT115_EINT,
1820c7229f9SMark Brown },
1830c7229f9SMark Brown [WM8350_IRQ_SYS_CHIP_GT140] = {
1840c7229f9SMark Brown .primary = WM8350_SYS_INT,
1850c7229f9SMark Brown .reg = WM8350_INT_OFFSET_2,
1860c7229f9SMark Brown .mask = WM8350_SYS_CHIP_GT140_EINT,
1870c7229f9SMark Brown },
1880c7229f9SMark Brown [WM8350_IRQ_SYS_WDOG_TO] = {
1890c7229f9SMark Brown .primary = WM8350_SYS_INT,
1900c7229f9SMark Brown .reg = WM8350_INT_OFFSET_2,
1910c7229f9SMark Brown .mask = WM8350_SYS_WDOG_TO_EINT,
1920c7229f9SMark Brown },
1930c7229f9SMark Brown [WM8350_IRQ_AUXADC_DATARDY] = {
1940c7229f9SMark Brown .primary = WM8350_AUXADC_INT,
1950c7229f9SMark Brown .reg = WM8350_INT_OFFSET_2,
1960c7229f9SMark Brown .mask = WM8350_AUXADC_DATARDY_EINT,
1970c7229f9SMark Brown },
1980c7229f9SMark Brown [WM8350_IRQ_AUXADC_DCOMP4] = {
1990c7229f9SMark Brown .primary = WM8350_AUXADC_INT,
2000c7229f9SMark Brown .reg = WM8350_INT_OFFSET_2,
2010c7229f9SMark Brown .mask = WM8350_AUXADC_DCOMP4_EINT,
2020c7229f9SMark Brown },
2030c7229f9SMark Brown [WM8350_IRQ_AUXADC_DCOMP3] = {
2040c7229f9SMark Brown .primary = WM8350_AUXADC_INT,
2050c7229f9SMark Brown .reg = WM8350_INT_OFFSET_2,
2060c7229f9SMark Brown .mask = WM8350_AUXADC_DCOMP3_EINT,
2070c7229f9SMark Brown },
2080c7229f9SMark Brown [WM8350_IRQ_AUXADC_DCOMP2] = {
2090c7229f9SMark Brown .primary = WM8350_AUXADC_INT,
2100c7229f9SMark Brown .reg = WM8350_INT_OFFSET_2,
2110c7229f9SMark Brown .mask = WM8350_AUXADC_DCOMP2_EINT,
2120c7229f9SMark Brown },
2130c7229f9SMark Brown [WM8350_IRQ_AUXADC_DCOMP1] = {
2140c7229f9SMark Brown .primary = WM8350_AUXADC_INT,
2150c7229f9SMark Brown .reg = WM8350_INT_OFFSET_2,
2160c7229f9SMark Brown .mask = WM8350_AUXADC_DCOMP1_EINT,
2170c7229f9SMark Brown },
2180c7229f9SMark Brown [WM8350_IRQ_USB_LIMIT] = {
2190c7229f9SMark Brown .primary = WM8350_USB_INT,
2200c7229f9SMark Brown .reg = WM8350_INT_OFFSET_2,
2210c7229f9SMark Brown .mask = WM8350_USB_LIMIT_EINT,
2220c7229f9SMark Brown .primary_only = 1,
2230c7229f9SMark Brown },
2240c7229f9SMark Brown [WM8350_IRQ_WKUP_OFF_STATE] = {
2250c7229f9SMark Brown .primary = WM8350_WKUP_INT,
2260c7229f9SMark Brown .reg = WM8350_COMPARATOR_INT_OFFSET,
2270c7229f9SMark Brown .mask = WM8350_WKUP_OFF_STATE_EINT,
2280c7229f9SMark Brown },
2290c7229f9SMark Brown [WM8350_IRQ_WKUP_HIB_STATE] = {
2300c7229f9SMark Brown .primary = WM8350_WKUP_INT,
2310c7229f9SMark Brown .reg = WM8350_COMPARATOR_INT_OFFSET,
2320c7229f9SMark Brown .mask = WM8350_WKUP_HIB_STATE_EINT,
2330c7229f9SMark Brown },
2340c7229f9SMark Brown [WM8350_IRQ_WKUP_CONV_FAULT] = {
2350c7229f9SMark Brown .primary = WM8350_WKUP_INT,
2360c7229f9SMark Brown .reg = WM8350_COMPARATOR_INT_OFFSET,
2370c7229f9SMark Brown .mask = WM8350_WKUP_CONV_FAULT_EINT,
2380c7229f9SMark Brown },
2390c7229f9SMark Brown [WM8350_IRQ_WKUP_WDOG_RST] = {
2400c7229f9SMark Brown .primary = WM8350_WKUP_INT,
2410c7229f9SMark Brown .reg = WM8350_COMPARATOR_INT_OFFSET,
2420c7229f9SMark Brown .mask = WM8350_WKUP_WDOG_RST_EINT,
2430c7229f9SMark Brown },
2440c7229f9SMark Brown [WM8350_IRQ_WKUP_GP_PWR_ON] = {
2450c7229f9SMark Brown .primary = WM8350_WKUP_INT,
2460c7229f9SMark Brown .reg = WM8350_COMPARATOR_INT_OFFSET,
2470c7229f9SMark Brown .mask = WM8350_WKUP_GP_PWR_ON_EINT,
2480c7229f9SMark Brown },
2490c7229f9SMark Brown [WM8350_IRQ_WKUP_ONKEY] = {
2500c7229f9SMark Brown .primary = WM8350_WKUP_INT,
2510c7229f9SMark Brown .reg = WM8350_COMPARATOR_INT_OFFSET,
2520c7229f9SMark Brown .mask = WM8350_WKUP_ONKEY_EINT,
2530c7229f9SMark Brown },
2540c7229f9SMark Brown [WM8350_IRQ_WKUP_GP_WAKEUP] = {
2550c7229f9SMark Brown .primary = WM8350_WKUP_INT,
2560c7229f9SMark Brown .reg = WM8350_COMPARATOR_INT_OFFSET,
2570c7229f9SMark Brown .mask = WM8350_WKUP_GP_WAKEUP_EINT,
2580c7229f9SMark Brown },
2590c7229f9SMark Brown [WM8350_IRQ_CODEC_JCK_DET_L] = {
2600c7229f9SMark Brown .primary = WM8350_CODEC_INT,
2610c7229f9SMark Brown .reg = WM8350_COMPARATOR_INT_OFFSET,
2620c7229f9SMark Brown .mask = WM8350_CODEC_JCK_DET_L_EINT,
2630c7229f9SMark Brown },
2640c7229f9SMark Brown [WM8350_IRQ_CODEC_JCK_DET_R] = {
2650c7229f9SMark Brown .primary = WM8350_CODEC_INT,
2660c7229f9SMark Brown .reg = WM8350_COMPARATOR_INT_OFFSET,
2670c7229f9SMark Brown .mask = WM8350_CODEC_JCK_DET_R_EINT,
2680c7229f9SMark Brown },
2690c7229f9SMark Brown [WM8350_IRQ_CODEC_MICSCD] = {
2700c7229f9SMark Brown .primary = WM8350_CODEC_INT,
2710c7229f9SMark Brown .reg = WM8350_COMPARATOR_INT_OFFSET,
2720c7229f9SMark Brown .mask = WM8350_CODEC_MICSCD_EINT,
2730c7229f9SMark Brown },
2740c7229f9SMark Brown [WM8350_IRQ_CODEC_MICD] = {
2750c7229f9SMark Brown .primary = WM8350_CODEC_INT,
2760c7229f9SMark Brown .reg = WM8350_COMPARATOR_INT_OFFSET,
2770c7229f9SMark Brown .mask = WM8350_CODEC_MICD_EINT,
2780c7229f9SMark Brown },
2790c7229f9SMark Brown [WM8350_IRQ_EXT_USB_FB] = {
2800c7229f9SMark Brown .primary = WM8350_EXT_INT,
2810c7229f9SMark Brown .reg = WM8350_COMPARATOR_INT_OFFSET,
2820c7229f9SMark Brown .mask = WM8350_EXT_USB_FB_EINT,
2830c7229f9SMark Brown },
2840c7229f9SMark Brown [WM8350_IRQ_EXT_WALL_FB] = {
2850c7229f9SMark Brown .primary = WM8350_EXT_INT,
2860c7229f9SMark Brown .reg = WM8350_COMPARATOR_INT_OFFSET,
2870c7229f9SMark Brown .mask = WM8350_EXT_WALL_FB_EINT,
2880c7229f9SMark Brown },
2890c7229f9SMark Brown [WM8350_IRQ_EXT_BAT_FB] = {
2900c7229f9SMark Brown .primary = WM8350_EXT_INT,
2910c7229f9SMark Brown .reg = WM8350_COMPARATOR_INT_OFFSET,
2920c7229f9SMark Brown .mask = WM8350_EXT_BAT_FB_EINT,
2930c7229f9SMark Brown },
2940c7229f9SMark Brown [WM8350_IRQ_GPIO(0)] = {
2950c7229f9SMark Brown .primary = WM8350_GP_INT,
2960c7229f9SMark Brown .reg = WM8350_GPIO_INT_OFFSET,
2970c7229f9SMark Brown .mask = WM8350_GP0_EINT,
2980c7229f9SMark Brown },
2990c7229f9SMark Brown [WM8350_IRQ_GPIO(1)] = {
3000c7229f9SMark Brown .primary = WM8350_GP_INT,
3010c7229f9SMark Brown .reg = WM8350_GPIO_INT_OFFSET,
3020c7229f9SMark Brown .mask = WM8350_GP1_EINT,
3030c7229f9SMark Brown },
3040c7229f9SMark Brown [WM8350_IRQ_GPIO(2)] = {
3050c7229f9SMark Brown .primary = WM8350_GP_INT,
3060c7229f9SMark Brown .reg = WM8350_GPIO_INT_OFFSET,
3070c7229f9SMark Brown .mask = WM8350_GP2_EINT,
3080c7229f9SMark Brown },
3090c7229f9SMark Brown [WM8350_IRQ_GPIO(3)] = {
3100c7229f9SMark Brown .primary = WM8350_GP_INT,
3110c7229f9SMark Brown .reg = WM8350_GPIO_INT_OFFSET,
3120c7229f9SMark Brown .mask = WM8350_GP3_EINT,
3130c7229f9SMark Brown },
3140c7229f9SMark Brown [WM8350_IRQ_GPIO(4)] = {
3150c7229f9SMark Brown .primary = WM8350_GP_INT,
3160c7229f9SMark Brown .reg = WM8350_GPIO_INT_OFFSET,
3170c7229f9SMark Brown .mask = WM8350_GP4_EINT,
3180c7229f9SMark Brown },
3190c7229f9SMark Brown [WM8350_IRQ_GPIO(5)] = {
3200c7229f9SMark Brown .primary = WM8350_GP_INT,
3210c7229f9SMark Brown .reg = WM8350_GPIO_INT_OFFSET,
3220c7229f9SMark Brown .mask = WM8350_GP5_EINT,
3230c7229f9SMark Brown },
3240c7229f9SMark Brown [WM8350_IRQ_GPIO(6)] = {
3250c7229f9SMark Brown .primary = WM8350_GP_INT,
3260c7229f9SMark Brown .reg = WM8350_GPIO_INT_OFFSET,
3270c7229f9SMark Brown .mask = WM8350_GP6_EINT,
3280c7229f9SMark Brown },
3290c7229f9SMark Brown [WM8350_IRQ_GPIO(7)] = {
3300c7229f9SMark Brown .primary = WM8350_GP_INT,
3310c7229f9SMark Brown .reg = WM8350_GPIO_INT_OFFSET,
3320c7229f9SMark Brown .mask = WM8350_GP7_EINT,
3330c7229f9SMark Brown },
3340c7229f9SMark Brown [WM8350_IRQ_GPIO(8)] = {
3350c7229f9SMark Brown .primary = WM8350_GP_INT,
3360c7229f9SMark Brown .reg = WM8350_GPIO_INT_OFFSET,
3370c7229f9SMark Brown .mask = WM8350_GP8_EINT,
3380c7229f9SMark Brown },
3390c7229f9SMark Brown [WM8350_IRQ_GPIO(9)] = {
3400c7229f9SMark Brown .primary = WM8350_GP_INT,
3410c7229f9SMark Brown .reg = WM8350_GPIO_INT_OFFSET,
3420c7229f9SMark Brown .mask = WM8350_GP9_EINT,
3430c7229f9SMark Brown },
3440c7229f9SMark Brown [WM8350_IRQ_GPIO(10)] = {
3450c7229f9SMark Brown .primary = WM8350_GP_INT,
3460c7229f9SMark Brown .reg = WM8350_GPIO_INT_OFFSET,
3470c7229f9SMark Brown .mask = WM8350_GP10_EINT,
3480c7229f9SMark Brown },
3490c7229f9SMark Brown [WM8350_IRQ_GPIO(11)] = {
3500c7229f9SMark Brown .primary = WM8350_GP_INT,
3510c7229f9SMark Brown .reg = WM8350_GPIO_INT_OFFSET,
3520c7229f9SMark Brown .mask = WM8350_GP11_EINT,
3530c7229f9SMark Brown },
3540c7229f9SMark Brown [WM8350_IRQ_GPIO(12)] = {
3550c7229f9SMark Brown .primary = WM8350_GP_INT,
3560c7229f9SMark Brown .reg = WM8350_GPIO_INT_OFFSET,
3570c7229f9SMark Brown .mask = WM8350_GP12_EINT,
3580c7229f9SMark Brown },
3590c7229f9SMark Brown };
3600c7229f9SMark Brown
irq_to_wm8350_irq(struct wm8350 * wm8350,int irq)361760e4518SMark Brown static inline struct wm8350_irq_data *irq_to_wm8350_irq(struct wm8350 *wm8350,
362760e4518SMark Brown int irq)
363e0a3389aSMark Brown {
364760e4518SMark Brown return &wm8350_irqs[irq - wm8350->irq_base];
365e0a3389aSMark Brown }
366e0a3389aSMark Brown
367e0a3389aSMark Brown /*
368e0a3389aSMark Brown * This is a threaded IRQ handler so can access I2C/SPI. Since all
369e0a3389aSMark Brown * interrupts are clear on read the IRQ line will be reasserted and
370e0a3389aSMark Brown * the physical IRQ will be handled again if another interrupt is
371e0a3389aSMark Brown * asserted while we run - in the normal course of events this is a
372760e4518SMark Brown * rare occurrence so we save I2C/SPI reads. We're also assuming that
373760e4518SMark Brown * it's rare to get lots of interrupts firing simultaneously so try to
374760e4518SMark Brown * minimise I/O.
375e0a3389aSMark Brown */
wm8350_irq(int irq,void * irq_data)3760c7229f9SMark Brown static irqreturn_t wm8350_irq(int irq, void *irq_data)
377e0a3389aSMark Brown {
3780c7229f9SMark Brown struct wm8350 *wm8350 = irq_data;
3790c7229f9SMark Brown u16 level_one;
3800c7229f9SMark Brown u16 sub_reg[WM8350_NUM_IRQ_REGS];
3810c7229f9SMark Brown int read_done[WM8350_NUM_IRQ_REGS];
3820c7229f9SMark Brown struct wm8350_irq_data *data;
3830c7229f9SMark Brown int i;
384e0a3389aSMark Brown
385e0a3389aSMark Brown level_one = wm8350_reg_read(wm8350, WM8350_SYSTEM_INTERRUPTS)
386e0a3389aSMark Brown & ~wm8350_reg_read(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK);
387e0a3389aSMark Brown
3880c7229f9SMark Brown if (!level_one)
3890c7229f9SMark Brown return IRQ_NONE;
390e0a3389aSMark Brown
3910c7229f9SMark Brown memset(&read_done, 0, sizeof(read_done));
392e0a3389aSMark Brown
3930c7229f9SMark Brown for (i = 0; i < ARRAY_SIZE(wm8350_irqs); i++) {
3940c7229f9SMark Brown data = &wm8350_irqs[i];
3950c7229f9SMark Brown
3960c7229f9SMark Brown if (!(level_one & data->primary))
3970c7229f9SMark Brown continue;
3980c7229f9SMark Brown
3990c7229f9SMark Brown if (!read_done[data->reg]) {
4000c7229f9SMark Brown sub_reg[data->reg] =
4010c7229f9SMark Brown wm8350_reg_read(wm8350, WM8350_INT_STATUS_1 +
4020c7229f9SMark Brown data->reg);
403760e4518SMark Brown sub_reg[data->reg] &= ~wm8350->irq_masks[data->reg];
4040c7229f9SMark Brown read_done[data->reg] = 1;
405e0a3389aSMark Brown }
406e0a3389aSMark Brown
4070c7229f9SMark Brown if (sub_reg[data->reg] & data->mask)
408760e4518SMark Brown handle_nested_irq(wm8350->irq_base + i);
409e0a3389aSMark Brown }
410e0a3389aSMark Brown
411e0a3389aSMark Brown return IRQ_HANDLED;
412e0a3389aSMark Brown }
413e0a3389aSMark Brown
wm8350_irq_lock(struct irq_data * data)414fdcc475bSMark Brown static void wm8350_irq_lock(struct irq_data *data)
415e0a3389aSMark Brown {
41625a947f8SMark Brown struct wm8350 *wm8350 = irq_data_get_irq_chip_data(data);
417e0a3389aSMark Brown
418760e4518SMark Brown mutex_lock(&wm8350->irq_lock);
419e0a3389aSMark Brown }
420e0a3389aSMark Brown
wm8350_irq_sync_unlock(struct irq_data * data)421fdcc475bSMark Brown static void wm8350_irq_sync_unlock(struct irq_data *data)
422e0a3389aSMark Brown {
42325a947f8SMark Brown struct wm8350 *wm8350 = irq_data_get_irq_chip_data(data);
424760e4518SMark Brown int i;
425e0a3389aSMark Brown
426760e4518SMark Brown for (i = 0; i < ARRAY_SIZE(wm8350->irq_masks); i++) {
427760e4518SMark Brown /* If there's been a change in the mask write it back
428760e4518SMark Brown * to the hardware. */
4297fdb5d32SMark Brown WARN_ON(regmap_update_bits(wm8350->regmap,
430760e4518SMark Brown WM8350_INT_STATUS_1_MASK + i,
4317fdb5d32SMark Brown 0xffff, wm8350->irq_masks[i]));
432e0a3389aSMark Brown }
433e0a3389aSMark Brown
434760e4518SMark Brown mutex_unlock(&wm8350->irq_lock);
435760e4518SMark Brown }
436760e4518SMark Brown
wm8350_irq_enable(struct irq_data * data)437fdcc475bSMark Brown static void wm8350_irq_enable(struct irq_data *data)
438e0a3389aSMark Brown {
43925a947f8SMark Brown struct wm8350 *wm8350 = irq_data_get_irq_chip_data(data);
440fdcc475bSMark Brown struct wm8350_irq_data *irq_data = irq_to_wm8350_irq(wm8350,
441fdcc475bSMark Brown data->irq);
442e0a3389aSMark Brown
443760e4518SMark Brown wm8350->irq_masks[irq_data->reg] &= ~irq_data->mask;
444e0a3389aSMark Brown }
445760e4518SMark Brown
wm8350_irq_disable(struct irq_data * data)446fdcc475bSMark Brown static void wm8350_irq_disable(struct irq_data *data)
447760e4518SMark Brown {
44825a947f8SMark Brown struct wm8350 *wm8350 = irq_data_get_irq_chip_data(data);
449fdcc475bSMark Brown struct wm8350_irq_data *irq_data = irq_to_wm8350_irq(wm8350,
450fdcc475bSMark Brown data->irq);
451760e4518SMark Brown
452760e4518SMark Brown wm8350->irq_masks[irq_data->reg] |= irq_data->mask;
453760e4518SMark Brown }
454760e4518SMark Brown
455760e4518SMark Brown static struct irq_chip wm8350_irq_chip = {
456760e4518SMark Brown .name = "wm8350",
457fdcc475bSMark Brown .irq_bus_lock = wm8350_irq_lock,
458fdcc475bSMark Brown .irq_bus_sync_unlock = wm8350_irq_sync_unlock,
459fdcc475bSMark Brown .irq_disable = wm8350_irq_disable,
460fdcc475bSMark Brown .irq_enable = wm8350_irq_enable,
461760e4518SMark Brown };
462e0a3389aSMark Brown
wm8350_irq_init(struct wm8350 * wm8350,int irq,struct wm8350_platform_data * pdata)463e0a3389aSMark Brown int wm8350_irq_init(struct wm8350 *wm8350, int irq,
464e0a3389aSMark Brown struct wm8350_platform_data *pdata)
465e0a3389aSMark Brown {
466760e4518SMark Brown int ret, cur_irq, i;
467e0a3389aSMark Brown int flags = IRQF_ONESHOT;
468d1738aefSSascha Hauer int irq_base = -1;
469e0a3389aSMark Brown
470e0a3389aSMark Brown if (!irq) {
471760e4518SMark Brown dev_warn(wm8350->dev, "No interrupt support, no core IRQ\n");
472760e4518SMark Brown return 0;
473e0a3389aSMark Brown }
474e0a3389aSMark Brown
475760e4518SMark Brown /* Mask top level interrupts */
476e0a3389aSMark Brown wm8350_reg_write(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK, 0xFFFF);
477e0a3389aSMark Brown
478760e4518SMark Brown /* Mask all individual interrupts by default and cache the
479760e4518SMark Brown * masks. We read the masks back since there are unwritable
480760e4518SMark Brown * bits in the mask registers. */
481760e4518SMark Brown for (i = 0; i < ARRAY_SIZE(wm8350->irq_masks); i++) {
482760e4518SMark Brown wm8350_reg_write(wm8350, WM8350_INT_STATUS_1_MASK + i,
483760e4518SMark Brown 0xFFFF);
484760e4518SMark Brown wm8350->irq_masks[i] =
485760e4518SMark Brown wm8350_reg_read(wm8350,
486760e4518SMark Brown WM8350_INT_STATUS_1_MASK + i);
487760e4518SMark Brown }
488760e4518SMark Brown
489760e4518SMark Brown mutex_init(&wm8350->irq_lock);
490e0a3389aSMark Brown wm8350->chip_irq = irq;
491e0a3389aSMark Brown
492d1738aefSSascha Hauer if (pdata && pdata->irq_base > 0)
493d1738aefSSascha Hauer irq_base = pdata->irq_base;
494d1738aefSSascha Hauer
495ebb37dcaSLee Jones wm8350->irq_base =
496ebb37dcaSLee Jones irq_alloc_descs(irq_base, 0, ARRAY_SIZE(wm8350_irqs), 0);
497d1738aefSSascha Hauer if (wm8350->irq_base < 0) {
498d1738aefSSascha Hauer dev_warn(wm8350->dev, "Allocating irqs failed with %d\n",
499d1738aefSSascha Hauer wm8350->irq_base);
500d1738aefSSascha Hauer return 0;
501d1738aefSSascha Hauer }
502d1738aefSSascha Hauer
503d1738aefSSascha Hauer if (pdata && pdata->irq_high) {
504e0a3389aSMark Brown flags |= IRQF_TRIGGER_HIGH;
505e0a3389aSMark Brown
506e0a3389aSMark Brown wm8350_set_bits(wm8350, WM8350_SYSTEM_CONTROL_1,
507e0a3389aSMark Brown WM8350_IRQ_POL);
508e0a3389aSMark Brown } else {
509e0a3389aSMark Brown flags |= IRQF_TRIGGER_LOW;
510e0a3389aSMark Brown
511e0a3389aSMark Brown wm8350_clear_bits(wm8350, WM8350_SYSTEM_CONTROL_1,
512e0a3389aSMark Brown WM8350_IRQ_POL);
513e0a3389aSMark Brown }
514e0a3389aSMark Brown
515760e4518SMark Brown /* Register with genirq */
516760e4518SMark Brown for (cur_irq = wm8350->irq_base;
517760e4518SMark Brown cur_irq < ARRAY_SIZE(wm8350_irqs) + wm8350->irq_base;
518760e4518SMark Brown cur_irq++) {
519d5bb1221SThomas Gleixner irq_set_chip_data(cur_irq, wm8350);
520d5bb1221SThomas Gleixner irq_set_chip_and_handler(cur_irq, &wm8350_irq_chip,
521760e4518SMark Brown handle_edge_irq);
522d5bb1221SThomas Gleixner irq_set_nested_thread(cur_irq, 1);
523760e4518SMark Brown
5249bd09f34SRob Herring irq_clear_status_flags(cur_irq, IRQ_NOREQUEST | IRQ_NOPROBE);
525760e4518SMark Brown }
526760e4518SMark Brown
527e0a3389aSMark Brown ret = request_threaded_irq(irq, NULL, wm8350_irq, flags,
528e0a3389aSMark Brown "wm8350", wm8350);
529e0a3389aSMark Brown if (ret != 0)
530e0a3389aSMark Brown dev_err(wm8350->dev, "Failed to request IRQ: %d\n", ret);
531e0a3389aSMark Brown
532760e4518SMark Brown /* Allow interrupts to fire */
533760e4518SMark Brown wm8350_reg_write(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK, 0);
534760e4518SMark Brown
535e0a3389aSMark Brown return ret;
536e0a3389aSMark Brown }
537e0a3389aSMark Brown
wm8350_irq_exit(struct wm8350 * wm8350)538e0a3389aSMark Brown int wm8350_irq_exit(struct wm8350 *wm8350)
539e0a3389aSMark Brown {
540e0a3389aSMark Brown free_irq(wm8350->chip_irq, wm8350);
541e0a3389aSMark Brown return 0;
542e0a3389aSMark Brown }
543