196e5da7cSDmitry Osipenko // SPDX-License-Identifier: GPL-2.0 296e5da7cSDmitry Osipenko /* 396e5da7cSDmitry Osipenko * Tegra20 External Memory Controller driver 496e5da7cSDmitry Osipenko * 596e5da7cSDmitry Osipenko * Author: Dmitry Osipenko <digetx@gmail.com> 696e5da7cSDmitry Osipenko */ 796e5da7cSDmitry Osipenko 896e5da7cSDmitry Osipenko #include <linux/clk.h> 977ab499dSDmitry Osipenko #include <linux/clk/tegra.h> 108209eefaSThierry Reding #include <linux/debugfs.h> 1196e5da7cSDmitry Osipenko #include <linux/err.h> 12d5ef16baSDmitry Osipenko #include <linux/interconnect-provider.h> 1396e5da7cSDmitry Osipenko #include <linux/interrupt.h> 14d039cf28SDmitry Osipenko #include <linux/io.h> 15adbcec88SDmitry Osipenko #include <linux/iopoll.h> 1696e5da7cSDmitry Osipenko #include <linux/kernel.h> 1796e5da7cSDmitry Osipenko #include <linux/module.h> 18d5ef16baSDmitry Osipenko #include <linux/mutex.h> 1996e5da7cSDmitry Osipenko #include <linux/of.h> 2096e5da7cSDmitry Osipenko #include <linux/platform_device.h> 21d5ef16baSDmitry Osipenko #include <linux/pm_opp.h> 22d5ef16baSDmitry Osipenko #include <linux/slab.h> 2396e5da7cSDmitry Osipenko #include <linux/sort.h> 2496e5da7cSDmitry Osipenko #include <linux/types.h> 2596e5da7cSDmitry Osipenko 26d5ef16baSDmitry Osipenko #include <soc/tegra/common.h> 2796e5da7cSDmitry Osipenko #include <soc/tegra/fuse.h> 2896e5da7cSDmitry Osipenko 29d5ef16baSDmitry Osipenko #include "mc.h" 30d5ef16baSDmitry Osipenko 3196e5da7cSDmitry Osipenko #define EMC_INTSTATUS 0x000 3296e5da7cSDmitry Osipenko #define EMC_INTMASK 0x004 33c72396f9SDmitry Osipenko #define EMC_DBG 0x008 3496e5da7cSDmitry Osipenko #define EMC_TIMING_CONTROL 0x028 3596e5da7cSDmitry Osipenko #define EMC_RC 0x02c 3696e5da7cSDmitry Osipenko #define EMC_RFC 0x030 3796e5da7cSDmitry Osipenko #define EMC_RAS 0x034 3896e5da7cSDmitry Osipenko #define EMC_RP 0x038 3996e5da7cSDmitry Osipenko #define EMC_R2W 0x03c 4096e5da7cSDmitry Osipenko #define EMC_W2R 0x040 4196e5da7cSDmitry Osipenko #define EMC_R2P 0x044 4296e5da7cSDmitry Osipenko #define EMC_W2P 0x048 4396e5da7cSDmitry Osipenko #define EMC_RD_RCD 0x04c 4496e5da7cSDmitry Osipenko #define EMC_WR_RCD 0x050 4596e5da7cSDmitry Osipenko #define EMC_RRD 0x054 4696e5da7cSDmitry Osipenko #define EMC_REXT 0x058 4796e5da7cSDmitry Osipenko #define EMC_WDV 0x05c 4896e5da7cSDmitry Osipenko #define EMC_QUSE 0x060 4996e5da7cSDmitry Osipenko #define EMC_QRST 0x064 5096e5da7cSDmitry Osipenko #define EMC_QSAFE 0x068 5196e5da7cSDmitry Osipenko #define EMC_RDV 0x06c 5296e5da7cSDmitry Osipenko #define EMC_REFRESH 0x070 5396e5da7cSDmitry Osipenko #define EMC_BURST_REFRESH_NUM 0x074 5496e5da7cSDmitry Osipenko #define EMC_PDEX2WR 0x078 5596e5da7cSDmitry Osipenko #define EMC_PDEX2RD 0x07c 5696e5da7cSDmitry Osipenko #define EMC_PCHG2PDEN 0x080 5796e5da7cSDmitry Osipenko #define EMC_ACT2PDEN 0x084 5896e5da7cSDmitry Osipenko #define EMC_AR2PDEN 0x088 5996e5da7cSDmitry Osipenko #define EMC_RW2PDEN 0x08c 6096e5da7cSDmitry Osipenko #define EMC_TXSR 0x090 6196e5da7cSDmitry Osipenko #define EMC_TCKE 0x094 6296e5da7cSDmitry Osipenko #define EMC_TFAW 0x098 6396e5da7cSDmitry Osipenko #define EMC_TRPAB 0x09c 6496e5da7cSDmitry Osipenko #define EMC_TCLKSTABLE 0x0a0 6596e5da7cSDmitry Osipenko #define EMC_TCLKSTOP 0x0a4 6696e5da7cSDmitry Osipenko #define EMC_TREFBW 0x0a8 6796e5da7cSDmitry Osipenko #define EMC_QUSE_EXTRA 0x0ac 6896e5da7cSDmitry Osipenko #define EMC_ODT_WRITE 0x0b0 6996e5da7cSDmitry Osipenko #define EMC_ODT_READ 0x0b4 7096e5da7cSDmitry Osipenko #define EMC_FBIO_CFG5 0x104 7196e5da7cSDmitry Osipenko #define EMC_FBIO_CFG6 0x114 72d5ef16baSDmitry Osipenko #define EMC_STAT_CONTROL 0x160 73d5ef16baSDmitry Osipenko #define EMC_STAT_LLMC_CONTROL 0x178 74d5ef16baSDmitry Osipenko #define EMC_STAT_PWR_CLOCK_LIMIT 0x198 75d5ef16baSDmitry Osipenko #define EMC_STAT_PWR_CLOCKS 0x19c 76d5ef16baSDmitry Osipenko #define EMC_STAT_PWR_COUNT 0x1a0 7796e5da7cSDmitry Osipenko #define EMC_AUTO_CAL_INTERVAL 0x2a8 7896e5da7cSDmitry Osipenko #define EMC_CFG_2 0x2b8 7996e5da7cSDmitry Osipenko #define EMC_CFG_DIG_DLL 0x2bc 8096e5da7cSDmitry Osipenko #define EMC_DLL_XFORM_DQS 0x2c0 8196e5da7cSDmitry Osipenko #define EMC_DLL_XFORM_QUSE 0x2c4 8296e5da7cSDmitry Osipenko #define EMC_ZCAL_REF_CNT 0x2e0 8396e5da7cSDmitry Osipenko #define EMC_ZCAL_WAIT_CNT 0x2e4 8496e5da7cSDmitry Osipenko #define EMC_CFG_CLKTRIM_0 0x2d0 8596e5da7cSDmitry Osipenko #define EMC_CFG_CLKTRIM_1 0x2d4 8696e5da7cSDmitry Osipenko #define EMC_CFG_CLKTRIM_2 0x2d8 8796e5da7cSDmitry Osipenko 8896e5da7cSDmitry Osipenko #define EMC_CLKCHANGE_REQ_ENABLE BIT(0) 8996e5da7cSDmitry Osipenko #define EMC_CLKCHANGE_PD_ENABLE BIT(1) 9096e5da7cSDmitry Osipenko #define EMC_CLKCHANGE_SR_ENABLE BIT(2) 9196e5da7cSDmitry Osipenko 9296e5da7cSDmitry Osipenko #define EMC_TIMING_UPDATE BIT(0) 9396e5da7cSDmitry Osipenko 9496e5da7cSDmitry Osipenko #define EMC_REFRESH_OVERFLOW_INT BIT(3) 9596e5da7cSDmitry Osipenko #define EMC_CLKCHANGE_COMPLETE_INT BIT(4) 9696e5da7cSDmitry Osipenko 97c72396f9SDmitry Osipenko #define EMC_DBG_READ_MUX_ASSEMBLY BIT(0) 98c72396f9SDmitry Osipenko #define EMC_DBG_WRITE_MUX_ACTIVE BIT(1) 99c72396f9SDmitry Osipenko #define EMC_DBG_FORCE_UPDATE BIT(2) 100c72396f9SDmitry Osipenko #define EMC_DBG_READ_DQM_CTRL BIT(9) 101c72396f9SDmitry Osipenko #define EMC_DBG_CFG_PRIORITY BIT(24) 102c72396f9SDmitry Osipenko 103d5ef16baSDmitry Osipenko #define EMC_FBIO_CFG5_DRAM_WIDTH_X16 BIT(4) 104d5ef16baSDmitry Osipenko 10596e5da7cSDmitry Osipenko static const u16 emc_timing_registers[] = { 10696e5da7cSDmitry Osipenko EMC_RC, 10796e5da7cSDmitry Osipenko EMC_RFC, 10896e5da7cSDmitry Osipenko EMC_RAS, 10996e5da7cSDmitry Osipenko EMC_RP, 11096e5da7cSDmitry Osipenko EMC_R2W, 11196e5da7cSDmitry Osipenko EMC_W2R, 11296e5da7cSDmitry Osipenko EMC_R2P, 11396e5da7cSDmitry Osipenko EMC_W2P, 11496e5da7cSDmitry Osipenko EMC_RD_RCD, 11596e5da7cSDmitry Osipenko EMC_WR_RCD, 11696e5da7cSDmitry Osipenko EMC_RRD, 11796e5da7cSDmitry Osipenko EMC_REXT, 11896e5da7cSDmitry Osipenko EMC_WDV, 11996e5da7cSDmitry Osipenko EMC_QUSE, 12096e5da7cSDmitry Osipenko EMC_QRST, 12196e5da7cSDmitry Osipenko EMC_QSAFE, 12296e5da7cSDmitry Osipenko EMC_RDV, 12396e5da7cSDmitry Osipenko EMC_REFRESH, 12496e5da7cSDmitry Osipenko EMC_BURST_REFRESH_NUM, 12596e5da7cSDmitry Osipenko EMC_PDEX2WR, 12696e5da7cSDmitry Osipenko EMC_PDEX2RD, 12796e5da7cSDmitry Osipenko EMC_PCHG2PDEN, 12896e5da7cSDmitry Osipenko EMC_ACT2PDEN, 12996e5da7cSDmitry Osipenko EMC_AR2PDEN, 13096e5da7cSDmitry Osipenko EMC_RW2PDEN, 13196e5da7cSDmitry Osipenko EMC_TXSR, 13296e5da7cSDmitry Osipenko EMC_TCKE, 13396e5da7cSDmitry Osipenko EMC_TFAW, 13496e5da7cSDmitry Osipenko EMC_TRPAB, 13596e5da7cSDmitry Osipenko EMC_TCLKSTABLE, 13696e5da7cSDmitry Osipenko EMC_TCLKSTOP, 13796e5da7cSDmitry Osipenko EMC_TREFBW, 13896e5da7cSDmitry Osipenko EMC_QUSE_EXTRA, 13996e5da7cSDmitry Osipenko EMC_FBIO_CFG6, 14096e5da7cSDmitry Osipenko EMC_ODT_WRITE, 14196e5da7cSDmitry Osipenko EMC_ODT_READ, 14296e5da7cSDmitry Osipenko EMC_FBIO_CFG5, 14396e5da7cSDmitry Osipenko EMC_CFG_DIG_DLL, 14496e5da7cSDmitry Osipenko EMC_DLL_XFORM_DQS, 14596e5da7cSDmitry Osipenko EMC_DLL_XFORM_QUSE, 14696e5da7cSDmitry Osipenko EMC_ZCAL_REF_CNT, 14796e5da7cSDmitry Osipenko EMC_ZCAL_WAIT_CNT, 14896e5da7cSDmitry Osipenko EMC_AUTO_CAL_INTERVAL, 14996e5da7cSDmitry Osipenko EMC_CFG_CLKTRIM_0, 15096e5da7cSDmitry Osipenko EMC_CFG_CLKTRIM_1, 15196e5da7cSDmitry Osipenko EMC_CFG_CLKTRIM_2, 15296e5da7cSDmitry Osipenko }; 15396e5da7cSDmitry Osipenko 15496e5da7cSDmitry Osipenko struct emc_timing { 15596e5da7cSDmitry Osipenko unsigned long rate; 15696e5da7cSDmitry Osipenko u32 data[ARRAY_SIZE(emc_timing_registers)]; 15796e5da7cSDmitry Osipenko }; 15896e5da7cSDmitry Osipenko 159d5ef16baSDmitry Osipenko enum emc_rate_request_type { 160d5ef16baSDmitry Osipenko EMC_RATE_DEBUG, 161d5ef16baSDmitry Osipenko EMC_RATE_ICC, 162d5ef16baSDmitry Osipenko EMC_RATE_TYPE_MAX, 163d5ef16baSDmitry Osipenko }; 164d5ef16baSDmitry Osipenko 165d5ef16baSDmitry Osipenko struct emc_rate_request { 166d5ef16baSDmitry Osipenko unsigned long min_rate; 167d5ef16baSDmitry Osipenko unsigned long max_rate; 168d5ef16baSDmitry Osipenko }; 169d5ef16baSDmitry Osipenko 17096e5da7cSDmitry Osipenko struct tegra_emc { 17196e5da7cSDmitry Osipenko struct device *dev; 172d5ef16baSDmitry Osipenko struct tegra_mc *mc; 173d5ef16baSDmitry Osipenko struct icc_provider provider; 17496e5da7cSDmitry Osipenko struct notifier_block clk_nb; 17596e5da7cSDmitry Osipenko struct clk *clk; 17696e5da7cSDmitry Osipenko void __iomem *regs; 177d5ef16baSDmitry Osipenko unsigned int dram_bus_width; 17896e5da7cSDmitry Osipenko 17996e5da7cSDmitry Osipenko struct emc_timing *timings; 18096e5da7cSDmitry Osipenko unsigned int num_timings; 1818209eefaSThierry Reding 1828209eefaSThierry Reding struct { 1838209eefaSThierry Reding struct dentry *root; 1848209eefaSThierry Reding unsigned long min_rate; 1858209eefaSThierry Reding unsigned long max_rate; 1868209eefaSThierry Reding } debugfs; 187d5ef16baSDmitry Osipenko 188d5ef16baSDmitry Osipenko /* 189d5ef16baSDmitry Osipenko * There are multiple sources in the EMC driver which could request 190d5ef16baSDmitry Osipenko * a min/max clock rate, these rates are contained in this array. 191d5ef16baSDmitry Osipenko */ 192d5ef16baSDmitry Osipenko struct emc_rate_request requested_rate[EMC_RATE_TYPE_MAX]; 193d5ef16baSDmitry Osipenko 194d5ef16baSDmitry Osipenko /* protect shared rate-change code path */ 195d5ef16baSDmitry Osipenko struct mutex rate_lock; 19696e5da7cSDmitry Osipenko }; 19796e5da7cSDmitry Osipenko 19896e5da7cSDmitry Osipenko static irqreturn_t tegra_emc_isr(int irq, void *data) 19996e5da7cSDmitry Osipenko { 20096e5da7cSDmitry Osipenko struct tegra_emc *emc = data; 201adbcec88SDmitry Osipenko u32 intmask = EMC_REFRESH_OVERFLOW_INT; 20296e5da7cSDmitry Osipenko u32 status; 20396e5da7cSDmitry Osipenko 20496e5da7cSDmitry Osipenko status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; 20596e5da7cSDmitry Osipenko if (!status) 20696e5da7cSDmitry Osipenko return IRQ_NONE; 20796e5da7cSDmitry Osipenko 20896e5da7cSDmitry Osipenko /* notify about HW problem */ 20996e5da7cSDmitry Osipenko if (status & EMC_REFRESH_OVERFLOW_INT) 21096e5da7cSDmitry Osipenko dev_err_ratelimited(emc->dev, 21196e5da7cSDmitry Osipenko "refresh request overflow timeout\n"); 21296e5da7cSDmitry Osipenko 21396e5da7cSDmitry Osipenko /* clear interrupts */ 21496e5da7cSDmitry Osipenko writel_relaxed(status, emc->regs + EMC_INTSTATUS); 21596e5da7cSDmitry Osipenko 21696e5da7cSDmitry Osipenko return IRQ_HANDLED; 21796e5da7cSDmitry Osipenko } 21896e5da7cSDmitry Osipenko 21996e5da7cSDmitry Osipenko static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc, 22096e5da7cSDmitry Osipenko unsigned long rate) 22196e5da7cSDmitry Osipenko { 22296e5da7cSDmitry Osipenko struct emc_timing *timing = NULL; 22396e5da7cSDmitry Osipenko unsigned int i; 22496e5da7cSDmitry Osipenko 22596e5da7cSDmitry Osipenko for (i = 0; i < emc->num_timings; i++) { 22696e5da7cSDmitry Osipenko if (emc->timings[i].rate >= rate) { 22796e5da7cSDmitry Osipenko timing = &emc->timings[i]; 22896e5da7cSDmitry Osipenko break; 22996e5da7cSDmitry Osipenko } 23096e5da7cSDmitry Osipenko } 23196e5da7cSDmitry Osipenko 23296e5da7cSDmitry Osipenko if (!timing) { 23396e5da7cSDmitry Osipenko dev_err(emc->dev, "no timing for rate %lu\n", rate); 23496e5da7cSDmitry Osipenko return NULL; 23596e5da7cSDmitry Osipenko } 23696e5da7cSDmitry Osipenko 23796e5da7cSDmitry Osipenko return timing; 23896e5da7cSDmitry Osipenko } 23996e5da7cSDmitry Osipenko 24096e5da7cSDmitry Osipenko static int emc_prepare_timing_change(struct tegra_emc *emc, unsigned long rate) 24196e5da7cSDmitry Osipenko { 24296e5da7cSDmitry Osipenko struct emc_timing *timing = tegra_emc_find_timing(emc, rate); 24396e5da7cSDmitry Osipenko unsigned int i; 24496e5da7cSDmitry Osipenko 24596e5da7cSDmitry Osipenko if (!timing) 24696e5da7cSDmitry Osipenko return -EINVAL; 24796e5da7cSDmitry Osipenko 24896e5da7cSDmitry Osipenko dev_dbg(emc->dev, "%s: using timing rate %lu for requested rate %lu\n", 24996e5da7cSDmitry Osipenko __func__, timing->rate, rate); 25096e5da7cSDmitry Osipenko 25196e5da7cSDmitry Osipenko /* program shadow registers */ 25296e5da7cSDmitry Osipenko for (i = 0; i < ARRAY_SIZE(timing->data); i++) 25396e5da7cSDmitry Osipenko writel_relaxed(timing->data[i], 25496e5da7cSDmitry Osipenko emc->regs + emc_timing_registers[i]); 25596e5da7cSDmitry Osipenko 25696e5da7cSDmitry Osipenko /* wait until programming has settled */ 25796e5da7cSDmitry Osipenko readl_relaxed(emc->regs + emc_timing_registers[i - 1]); 25896e5da7cSDmitry Osipenko 25996e5da7cSDmitry Osipenko return 0; 26096e5da7cSDmitry Osipenko } 26196e5da7cSDmitry Osipenko 26296e5da7cSDmitry Osipenko static int emc_complete_timing_change(struct tegra_emc *emc, bool flush) 26396e5da7cSDmitry Osipenko { 264adbcec88SDmitry Osipenko int err; 265adbcec88SDmitry Osipenko u32 v; 26696e5da7cSDmitry Osipenko 26796e5da7cSDmitry Osipenko dev_dbg(emc->dev, "%s: flush %d\n", __func__, flush); 26896e5da7cSDmitry Osipenko 26996e5da7cSDmitry Osipenko if (flush) { 27096e5da7cSDmitry Osipenko /* manually initiate memory timing update */ 27196e5da7cSDmitry Osipenko writel_relaxed(EMC_TIMING_UPDATE, 27296e5da7cSDmitry Osipenko emc->regs + EMC_TIMING_CONTROL); 27396e5da7cSDmitry Osipenko return 0; 27496e5da7cSDmitry Osipenko } 27596e5da7cSDmitry Osipenko 276adbcec88SDmitry Osipenko err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, v, 277adbcec88SDmitry Osipenko v & EMC_CLKCHANGE_COMPLETE_INT, 278adbcec88SDmitry Osipenko 1, 100); 279adbcec88SDmitry Osipenko if (err) { 280adbcec88SDmitry Osipenko dev_err(emc->dev, "emc-car handshake timeout: %d\n", err); 281adbcec88SDmitry Osipenko return err; 28296e5da7cSDmitry Osipenko } 28396e5da7cSDmitry Osipenko 28496e5da7cSDmitry Osipenko return 0; 28596e5da7cSDmitry Osipenko } 28696e5da7cSDmitry Osipenko 28796e5da7cSDmitry Osipenko static int tegra_emc_clk_change_notify(struct notifier_block *nb, 28896e5da7cSDmitry Osipenko unsigned long msg, void *data) 28996e5da7cSDmitry Osipenko { 29096e5da7cSDmitry Osipenko struct tegra_emc *emc = container_of(nb, struct tegra_emc, clk_nb); 29196e5da7cSDmitry Osipenko struct clk_notifier_data *cnd = data; 29296e5da7cSDmitry Osipenko int err; 29396e5da7cSDmitry Osipenko 29496e5da7cSDmitry Osipenko switch (msg) { 29596e5da7cSDmitry Osipenko case PRE_RATE_CHANGE: 29696e5da7cSDmitry Osipenko err = emc_prepare_timing_change(emc, cnd->new_rate); 29796e5da7cSDmitry Osipenko break; 29896e5da7cSDmitry Osipenko 29996e5da7cSDmitry Osipenko case ABORT_RATE_CHANGE: 30096e5da7cSDmitry Osipenko err = emc_prepare_timing_change(emc, cnd->old_rate); 30196e5da7cSDmitry Osipenko if (err) 30296e5da7cSDmitry Osipenko break; 30396e5da7cSDmitry Osipenko 30496e5da7cSDmitry Osipenko err = emc_complete_timing_change(emc, true); 30596e5da7cSDmitry Osipenko break; 30696e5da7cSDmitry Osipenko 30796e5da7cSDmitry Osipenko case POST_RATE_CHANGE: 30896e5da7cSDmitry Osipenko err = emc_complete_timing_change(emc, false); 30996e5da7cSDmitry Osipenko break; 31096e5da7cSDmitry Osipenko 31196e5da7cSDmitry Osipenko default: 31296e5da7cSDmitry Osipenko return NOTIFY_DONE; 31396e5da7cSDmitry Osipenko } 31496e5da7cSDmitry Osipenko 31596e5da7cSDmitry Osipenko return notifier_from_errno(err); 31696e5da7cSDmitry Osipenko } 31796e5da7cSDmitry Osipenko 31896e5da7cSDmitry Osipenko static int load_one_timing_from_dt(struct tegra_emc *emc, 31996e5da7cSDmitry Osipenko struct emc_timing *timing, 32096e5da7cSDmitry Osipenko struct device_node *node) 32196e5da7cSDmitry Osipenko { 32296e5da7cSDmitry Osipenko u32 rate; 32396e5da7cSDmitry Osipenko int err; 32496e5da7cSDmitry Osipenko 32596e5da7cSDmitry Osipenko if (!of_device_is_compatible(node, "nvidia,tegra20-emc-table")) { 32696e5da7cSDmitry Osipenko dev_err(emc->dev, "incompatible DT node: %pOF\n", node); 32796e5da7cSDmitry Osipenko return -EINVAL; 32896e5da7cSDmitry Osipenko } 32996e5da7cSDmitry Osipenko 33096e5da7cSDmitry Osipenko err = of_property_read_u32(node, "clock-frequency", &rate); 33196e5da7cSDmitry Osipenko if (err) { 33296e5da7cSDmitry Osipenko dev_err(emc->dev, "timing %pOF: failed to read rate: %d\n", 33396e5da7cSDmitry Osipenko node, err); 33496e5da7cSDmitry Osipenko return err; 33596e5da7cSDmitry Osipenko } 33696e5da7cSDmitry Osipenko 33796e5da7cSDmitry Osipenko err = of_property_read_u32_array(node, "nvidia,emc-registers", 33896e5da7cSDmitry Osipenko timing->data, 33996e5da7cSDmitry Osipenko ARRAY_SIZE(emc_timing_registers)); 34096e5da7cSDmitry Osipenko if (err) { 34196e5da7cSDmitry Osipenko dev_err(emc->dev, 34296e5da7cSDmitry Osipenko "timing %pOF: failed to read emc timing data: %d\n", 34396e5da7cSDmitry Osipenko node, err); 34496e5da7cSDmitry Osipenko return err; 34596e5da7cSDmitry Osipenko } 34696e5da7cSDmitry Osipenko 34796e5da7cSDmitry Osipenko /* 34896e5da7cSDmitry Osipenko * The EMC clock rate is twice the bus rate, and the bus rate is 34996e5da7cSDmitry Osipenko * measured in kHz. 35096e5da7cSDmitry Osipenko */ 35196e5da7cSDmitry Osipenko timing->rate = rate * 2 * 1000; 35296e5da7cSDmitry Osipenko 35396e5da7cSDmitry Osipenko dev_dbg(emc->dev, "%s: %pOF: EMC rate %lu\n", 35496e5da7cSDmitry Osipenko __func__, node, timing->rate); 35596e5da7cSDmitry Osipenko 35696e5da7cSDmitry Osipenko return 0; 35796e5da7cSDmitry Osipenko } 35896e5da7cSDmitry Osipenko 35996e5da7cSDmitry Osipenko static int cmp_timings(const void *_a, const void *_b) 36096e5da7cSDmitry Osipenko { 36196e5da7cSDmitry Osipenko const struct emc_timing *a = _a; 36296e5da7cSDmitry Osipenko const struct emc_timing *b = _b; 36396e5da7cSDmitry Osipenko 36496e5da7cSDmitry Osipenko if (a->rate < b->rate) 36596e5da7cSDmitry Osipenko return -1; 36696e5da7cSDmitry Osipenko 36796e5da7cSDmitry Osipenko if (a->rate > b->rate) 36896e5da7cSDmitry Osipenko return 1; 36996e5da7cSDmitry Osipenko 37096e5da7cSDmitry Osipenko return 0; 37196e5da7cSDmitry Osipenko } 37296e5da7cSDmitry Osipenko 37396e5da7cSDmitry Osipenko static int tegra_emc_load_timings_from_dt(struct tegra_emc *emc, 37496e5da7cSDmitry Osipenko struct device_node *node) 37596e5da7cSDmitry Osipenko { 37696e5da7cSDmitry Osipenko struct device_node *child; 37796e5da7cSDmitry Osipenko struct emc_timing *timing; 37896e5da7cSDmitry Osipenko int child_count; 37996e5da7cSDmitry Osipenko int err; 38096e5da7cSDmitry Osipenko 38196e5da7cSDmitry Osipenko child_count = of_get_child_count(node); 38296e5da7cSDmitry Osipenko if (!child_count) { 38396e5da7cSDmitry Osipenko dev_err(emc->dev, "no memory timings in DT node: %pOF\n", node); 38496e5da7cSDmitry Osipenko return -EINVAL; 38596e5da7cSDmitry Osipenko } 38696e5da7cSDmitry Osipenko 38796e5da7cSDmitry Osipenko emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing), 38896e5da7cSDmitry Osipenko GFP_KERNEL); 38996e5da7cSDmitry Osipenko if (!emc->timings) 39096e5da7cSDmitry Osipenko return -ENOMEM; 39196e5da7cSDmitry Osipenko 39296e5da7cSDmitry Osipenko emc->num_timings = child_count; 39396e5da7cSDmitry Osipenko timing = emc->timings; 39496e5da7cSDmitry Osipenko 39596e5da7cSDmitry Osipenko for_each_child_of_node(node, child) { 39696e5da7cSDmitry Osipenko err = load_one_timing_from_dt(emc, timing++, child); 39796e5da7cSDmitry Osipenko if (err) { 39896e5da7cSDmitry Osipenko of_node_put(child); 39996e5da7cSDmitry Osipenko return err; 40096e5da7cSDmitry Osipenko } 40196e5da7cSDmitry Osipenko } 40296e5da7cSDmitry Osipenko 40396e5da7cSDmitry Osipenko sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings, 40496e5da7cSDmitry Osipenko NULL); 40596e5da7cSDmitry Osipenko 406f541efaaSDmitry Osipenko dev_info(emc->dev, 407f541efaaSDmitry Osipenko "got %u timings for RAM code %u (min %luMHz max %luMHz)\n", 408f541efaaSDmitry Osipenko emc->num_timings, 409f541efaaSDmitry Osipenko tegra_read_ram_code(), 410f541efaaSDmitry Osipenko emc->timings[0].rate / 1000000, 411f541efaaSDmitry Osipenko emc->timings[emc->num_timings - 1].rate / 1000000); 412f541efaaSDmitry Osipenko 41396e5da7cSDmitry Osipenko return 0; 41496e5da7cSDmitry Osipenko } 41596e5da7cSDmitry Osipenko 41696e5da7cSDmitry Osipenko static struct device_node * 41796e5da7cSDmitry Osipenko tegra_emc_find_node_by_ram_code(struct device *dev) 41896e5da7cSDmitry Osipenko { 41996e5da7cSDmitry Osipenko struct device_node *np; 42096e5da7cSDmitry Osipenko u32 value, ram_code; 42196e5da7cSDmitry Osipenko int err; 42296e5da7cSDmitry Osipenko 423fa4794ffSDmitry Osipenko if (of_get_child_count(dev->of_node) == 0) { 424fa4794ffSDmitry Osipenko dev_info(dev, "device-tree doesn't have memory timings\n"); 425fa4794ffSDmitry Osipenko return NULL; 426fa4794ffSDmitry Osipenko } 427fa4794ffSDmitry Osipenko 42896e5da7cSDmitry Osipenko if (!of_property_read_bool(dev->of_node, "nvidia,use-ram-code")) 42996e5da7cSDmitry Osipenko return of_node_get(dev->of_node); 43096e5da7cSDmitry Osipenko 43196e5da7cSDmitry Osipenko ram_code = tegra_read_ram_code(); 43296e5da7cSDmitry Osipenko 43396e5da7cSDmitry Osipenko for (np = of_find_node_by_name(dev->of_node, "emc-tables"); np; 43496e5da7cSDmitry Osipenko np = of_find_node_by_name(np, "emc-tables")) { 43596e5da7cSDmitry Osipenko err = of_property_read_u32(np, "nvidia,ram-code", &value); 43696e5da7cSDmitry Osipenko if (err || value != ram_code) { 43796e5da7cSDmitry Osipenko of_node_put(np); 43896e5da7cSDmitry Osipenko continue; 43996e5da7cSDmitry Osipenko } 44096e5da7cSDmitry Osipenko 44196e5da7cSDmitry Osipenko return np; 44296e5da7cSDmitry Osipenko } 44396e5da7cSDmitry Osipenko 44496e5da7cSDmitry Osipenko dev_err(dev, "no memory timings for RAM code %u found in device tree\n", 44596e5da7cSDmitry Osipenko ram_code); 44696e5da7cSDmitry Osipenko 44796e5da7cSDmitry Osipenko return NULL; 44896e5da7cSDmitry Osipenko } 44996e5da7cSDmitry Osipenko 45096e5da7cSDmitry Osipenko static int emc_setup_hw(struct tegra_emc *emc) 45196e5da7cSDmitry Osipenko { 452adbcec88SDmitry Osipenko u32 intmask = EMC_REFRESH_OVERFLOW_INT; 453d5ef16baSDmitry Osipenko u32 emc_cfg, emc_dbg, emc_fbio; 45496e5da7cSDmitry Osipenko 45596e5da7cSDmitry Osipenko emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2); 45696e5da7cSDmitry Osipenko 45796e5da7cSDmitry Osipenko /* 45896e5da7cSDmitry Osipenko * Depending on a memory type, DRAM should enter either self-refresh 45996e5da7cSDmitry Osipenko * or power-down state on EMC clock change. 46096e5da7cSDmitry Osipenko */ 46196e5da7cSDmitry Osipenko if (!(emc_cfg & EMC_CLKCHANGE_PD_ENABLE) && 46296e5da7cSDmitry Osipenko !(emc_cfg & EMC_CLKCHANGE_SR_ENABLE)) { 46396e5da7cSDmitry Osipenko dev_err(emc->dev, 46496e5da7cSDmitry Osipenko "bootloader didn't specify DRAM auto-suspend mode\n"); 46596e5da7cSDmitry Osipenko return -EINVAL; 46696e5da7cSDmitry Osipenko } 46796e5da7cSDmitry Osipenko 46896e5da7cSDmitry Osipenko /* enable EMC and CAR to handshake on PLL divider/source changes */ 46996e5da7cSDmitry Osipenko emc_cfg |= EMC_CLKCHANGE_REQ_ENABLE; 47096e5da7cSDmitry Osipenko writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2); 47196e5da7cSDmitry Osipenko 47296e5da7cSDmitry Osipenko /* initialize interrupt */ 47396e5da7cSDmitry Osipenko writel_relaxed(intmask, emc->regs + EMC_INTMASK); 47496e5da7cSDmitry Osipenko writel_relaxed(intmask, emc->regs + EMC_INTSTATUS); 47596e5da7cSDmitry Osipenko 476c72396f9SDmitry Osipenko /* ensure that unwanted debug features are disabled */ 477c72396f9SDmitry Osipenko emc_dbg = readl_relaxed(emc->regs + EMC_DBG); 478c72396f9SDmitry Osipenko emc_dbg |= EMC_DBG_CFG_PRIORITY; 479c72396f9SDmitry Osipenko emc_dbg &= ~EMC_DBG_READ_MUX_ASSEMBLY; 480c72396f9SDmitry Osipenko emc_dbg &= ~EMC_DBG_WRITE_MUX_ACTIVE; 481c72396f9SDmitry Osipenko emc_dbg &= ~EMC_DBG_FORCE_UPDATE; 482c72396f9SDmitry Osipenko writel_relaxed(emc_dbg, emc->regs + EMC_DBG); 483c72396f9SDmitry Osipenko 484d5ef16baSDmitry Osipenko emc_fbio = readl_relaxed(emc->regs + EMC_FBIO_CFG5); 485d5ef16baSDmitry Osipenko 486d5ef16baSDmitry Osipenko if (emc_fbio & EMC_FBIO_CFG5_DRAM_WIDTH_X16) 487d5ef16baSDmitry Osipenko emc->dram_bus_width = 16; 488d5ef16baSDmitry Osipenko else 489d5ef16baSDmitry Osipenko emc->dram_bus_width = 32; 490d5ef16baSDmitry Osipenko 491d5ef16baSDmitry Osipenko dev_info(emc->dev, "%ubit DRAM bus\n", emc->dram_bus_width); 492d5ef16baSDmitry Osipenko 49396e5da7cSDmitry Osipenko return 0; 49496e5da7cSDmitry Osipenko } 49596e5da7cSDmitry Osipenko 49677ab499dSDmitry Osipenko static long emc_round_rate(unsigned long rate, 49777ab499dSDmitry Osipenko unsigned long min_rate, 49877ab499dSDmitry Osipenko unsigned long max_rate, 49977ab499dSDmitry Osipenko void *arg) 50077ab499dSDmitry Osipenko { 50177ab499dSDmitry Osipenko struct emc_timing *timing = NULL; 50277ab499dSDmitry Osipenko struct tegra_emc *emc = arg; 50377ab499dSDmitry Osipenko unsigned int i; 50477ab499dSDmitry Osipenko 505fa4794ffSDmitry Osipenko if (!emc->num_timings) 506fa4794ffSDmitry Osipenko return clk_get_rate(emc->clk); 507fa4794ffSDmitry Osipenko 50877ab499dSDmitry Osipenko min_rate = min(min_rate, emc->timings[emc->num_timings - 1].rate); 50977ab499dSDmitry Osipenko 51077ab499dSDmitry Osipenko for (i = 0; i < emc->num_timings; i++) { 51177ab499dSDmitry Osipenko if (emc->timings[i].rate < rate && i != emc->num_timings - 1) 51277ab499dSDmitry Osipenko continue; 51377ab499dSDmitry Osipenko 51477ab499dSDmitry Osipenko if (emc->timings[i].rate > max_rate) { 51577ab499dSDmitry Osipenko i = max(i, 1u) - 1; 51677ab499dSDmitry Osipenko 51777ab499dSDmitry Osipenko if (emc->timings[i].rate < min_rate) 51877ab499dSDmitry Osipenko break; 51977ab499dSDmitry Osipenko } 52077ab499dSDmitry Osipenko 52177ab499dSDmitry Osipenko if (emc->timings[i].rate < min_rate) 52277ab499dSDmitry Osipenko continue; 52377ab499dSDmitry Osipenko 52477ab499dSDmitry Osipenko timing = &emc->timings[i]; 52577ab499dSDmitry Osipenko break; 52677ab499dSDmitry Osipenko } 52777ab499dSDmitry Osipenko 52877ab499dSDmitry Osipenko if (!timing) { 52977ab499dSDmitry Osipenko dev_err(emc->dev, "no timing for rate %lu min %lu max %lu\n", 53077ab499dSDmitry Osipenko rate, min_rate, max_rate); 53177ab499dSDmitry Osipenko return -EINVAL; 53277ab499dSDmitry Osipenko } 53377ab499dSDmitry Osipenko 53477ab499dSDmitry Osipenko return timing->rate; 53577ab499dSDmitry Osipenko } 53677ab499dSDmitry Osipenko 537d5ef16baSDmitry Osipenko static void tegra_emc_rate_requests_init(struct tegra_emc *emc) 538d5ef16baSDmitry Osipenko { 539d5ef16baSDmitry Osipenko unsigned int i; 540d5ef16baSDmitry Osipenko 541d5ef16baSDmitry Osipenko for (i = 0; i < EMC_RATE_TYPE_MAX; i++) { 542d5ef16baSDmitry Osipenko emc->requested_rate[i].min_rate = 0; 543d5ef16baSDmitry Osipenko emc->requested_rate[i].max_rate = ULONG_MAX; 544d5ef16baSDmitry Osipenko } 545d5ef16baSDmitry Osipenko } 546d5ef16baSDmitry Osipenko 547d5ef16baSDmitry Osipenko static int emc_request_rate(struct tegra_emc *emc, 548d5ef16baSDmitry Osipenko unsigned long new_min_rate, 549d5ef16baSDmitry Osipenko unsigned long new_max_rate, 550d5ef16baSDmitry Osipenko enum emc_rate_request_type type) 551d5ef16baSDmitry Osipenko { 552d5ef16baSDmitry Osipenko struct emc_rate_request *req = emc->requested_rate; 553d5ef16baSDmitry Osipenko unsigned long min_rate = 0, max_rate = ULONG_MAX; 554d5ef16baSDmitry Osipenko unsigned int i; 555d5ef16baSDmitry Osipenko int err; 556d5ef16baSDmitry Osipenko 557d5ef16baSDmitry Osipenko /* select minimum and maximum rates among the requested rates */ 558d5ef16baSDmitry Osipenko for (i = 0; i < EMC_RATE_TYPE_MAX; i++, req++) { 559d5ef16baSDmitry Osipenko if (i == type) { 560d5ef16baSDmitry Osipenko min_rate = max(new_min_rate, min_rate); 561d5ef16baSDmitry Osipenko max_rate = min(new_max_rate, max_rate); 562d5ef16baSDmitry Osipenko } else { 563d5ef16baSDmitry Osipenko min_rate = max(req->min_rate, min_rate); 564d5ef16baSDmitry Osipenko max_rate = min(req->max_rate, max_rate); 565d5ef16baSDmitry Osipenko } 566d5ef16baSDmitry Osipenko } 567d5ef16baSDmitry Osipenko 568d5ef16baSDmitry Osipenko if (min_rate > max_rate) { 569d5ef16baSDmitry Osipenko dev_err_ratelimited(emc->dev, "%s: type %u: out of range: %lu %lu\n", 570d5ef16baSDmitry Osipenko __func__, type, min_rate, max_rate); 571d5ef16baSDmitry Osipenko return -ERANGE; 572d5ef16baSDmitry Osipenko } 573d5ef16baSDmitry Osipenko 574d5ef16baSDmitry Osipenko /* 575d5ef16baSDmitry Osipenko * EMC rate-changes should go via OPP API because it manages voltage 576d5ef16baSDmitry Osipenko * changes. 577d5ef16baSDmitry Osipenko */ 578d5ef16baSDmitry Osipenko err = dev_pm_opp_set_rate(emc->dev, min_rate); 579d5ef16baSDmitry Osipenko if (err) 580d5ef16baSDmitry Osipenko return err; 581d5ef16baSDmitry Osipenko 582d5ef16baSDmitry Osipenko emc->requested_rate[type].min_rate = new_min_rate; 583d5ef16baSDmitry Osipenko emc->requested_rate[type].max_rate = new_max_rate; 584d5ef16baSDmitry Osipenko 585d5ef16baSDmitry Osipenko return 0; 586d5ef16baSDmitry Osipenko } 587d5ef16baSDmitry Osipenko 588d5ef16baSDmitry Osipenko static int emc_set_min_rate(struct tegra_emc *emc, unsigned long rate, 589d5ef16baSDmitry Osipenko enum emc_rate_request_type type) 590d5ef16baSDmitry Osipenko { 591d5ef16baSDmitry Osipenko struct emc_rate_request *req = &emc->requested_rate[type]; 592d5ef16baSDmitry Osipenko int ret; 593d5ef16baSDmitry Osipenko 594d5ef16baSDmitry Osipenko mutex_lock(&emc->rate_lock); 595d5ef16baSDmitry Osipenko ret = emc_request_rate(emc, rate, req->max_rate, type); 596d5ef16baSDmitry Osipenko mutex_unlock(&emc->rate_lock); 597d5ef16baSDmitry Osipenko 598d5ef16baSDmitry Osipenko return ret; 599d5ef16baSDmitry Osipenko } 600d5ef16baSDmitry Osipenko 601d5ef16baSDmitry Osipenko static int emc_set_max_rate(struct tegra_emc *emc, unsigned long rate, 602d5ef16baSDmitry Osipenko enum emc_rate_request_type type) 603d5ef16baSDmitry Osipenko { 604d5ef16baSDmitry Osipenko struct emc_rate_request *req = &emc->requested_rate[type]; 605d5ef16baSDmitry Osipenko int ret; 606d5ef16baSDmitry Osipenko 607d5ef16baSDmitry Osipenko mutex_lock(&emc->rate_lock); 608d5ef16baSDmitry Osipenko ret = emc_request_rate(emc, req->min_rate, rate, type); 609d5ef16baSDmitry Osipenko mutex_unlock(&emc->rate_lock); 610d5ef16baSDmitry Osipenko 611d5ef16baSDmitry Osipenko return ret; 612d5ef16baSDmitry Osipenko } 613d5ef16baSDmitry Osipenko 6148209eefaSThierry Reding /* 6158209eefaSThierry Reding * debugfs interface 6168209eefaSThierry Reding * 6178209eefaSThierry Reding * The memory controller driver exposes some files in debugfs that can be used 6188209eefaSThierry Reding * to control the EMC frequency. The top-level directory can be found here: 6198209eefaSThierry Reding * 6208209eefaSThierry Reding * /sys/kernel/debug/emc 6218209eefaSThierry Reding * 6228209eefaSThierry Reding * It contains the following files: 6238209eefaSThierry Reding * 6248209eefaSThierry Reding * - available_rates: This file contains a list of valid, space-separated 6258209eefaSThierry Reding * EMC frequencies. 6268209eefaSThierry Reding * 6278209eefaSThierry Reding * - min_rate: Writing a value to this file sets the given frequency as the 6288209eefaSThierry Reding * floor of the permitted range. If this is higher than the currently 6298209eefaSThierry Reding * configured EMC frequency, this will cause the frequency to be 6308209eefaSThierry Reding * increased so that it stays within the valid range. 6318209eefaSThierry Reding * 6328209eefaSThierry Reding * - max_rate: Similarily to the min_rate file, writing a value to this file 6338209eefaSThierry Reding * sets the given frequency as the ceiling of the permitted range. If 6348209eefaSThierry Reding * the value is lower than the currently configured EMC frequency, this 6358209eefaSThierry Reding * will cause the frequency to be decreased so that it stays within the 6368209eefaSThierry Reding * valid range. 6378209eefaSThierry Reding */ 6388209eefaSThierry Reding 6398209eefaSThierry Reding static bool tegra_emc_validate_rate(struct tegra_emc *emc, unsigned long rate) 6408209eefaSThierry Reding { 6418209eefaSThierry Reding unsigned int i; 6428209eefaSThierry Reding 6438209eefaSThierry Reding for (i = 0; i < emc->num_timings; i++) 6448209eefaSThierry Reding if (rate == emc->timings[i].rate) 6458209eefaSThierry Reding return true; 6468209eefaSThierry Reding 6478209eefaSThierry Reding return false; 6488209eefaSThierry Reding } 6498209eefaSThierry Reding 6508209eefaSThierry Reding static int tegra_emc_debug_available_rates_show(struct seq_file *s, void *data) 6518209eefaSThierry Reding { 6528209eefaSThierry Reding struct tegra_emc *emc = s->private; 6538209eefaSThierry Reding const char *prefix = ""; 6548209eefaSThierry Reding unsigned int i; 6558209eefaSThierry Reding 6568209eefaSThierry Reding for (i = 0; i < emc->num_timings; i++) { 6578209eefaSThierry Reding seq_printf(s, "%s%lu", prefix, emc->timings[i].rate); 6588209eefaSThierry Reding prefix = " "; 6598209eefaSThierry Reding } 6608209eefaSThierry Reding 6618209eefaSThierry Reding seq_puts(s, "\n"); 6628209eefaSThierry Reding 6638209eefaSThierry Reding return 0; 6648209eefaSThierry Reding } 6658209eefaSThierry Reding 6668209eefaSThierry Reding static int tegra_emc_debug_available_rates_open(struct inode *inode, 6678209eefaSThierry Reding struct file *file) 6688209eefaSThierry Reding { 6698209eefaSThierry Reding return single_open(file, tegra_emc_debug_available_rates_show, 6708209eefaSThierry Reding inode->i_private); 6718209eefaSThierry Reding } 6728209eefaSThierry Reding 6738209eefaSThierry Reding static const struct file_operations tegra_emc_debug_available_rates_fops = { 6748209eefaSThierry Reding .open = tegra_emc_debug_available_rates_open, 6758209eefaSThierry Reding .read = seq_read, 6768209eefaSThierry Reding .llseek = seq_lseek, 6778209eefaSThierry Reding .release = single_release, 6788209eefaSThierry Reding }; 6798209eefaSThierry Reding 6808209eefaSThierry Reding static int tegra_emc_debug_min_rate_get(void *data, u64 *rate) 6818209eefaSThierry Reding { 6828209eefaSThierry Reding struct tegra_emc *emc = data; 6838209eefaSThierry Reding 6848209eefaSThierry Reding *rate = emc->debugfs.min_rate; 6858209eefaSThierry Reding 6868209eefaSThierry Reding return 0; 6878209eefaSThierry Reding } 6888209eefaSThierry Reding 6898209eefaSThierry Reding static int tegra_emc_debug_min_rate_set(void *data, u64 rate) 6908209eefaSThierry Reding { 6918209eefaSThierry Reding struct tegra_emc *emc = data; 6928209eefaSThierry Reding int err; 6938209eefaSThierry Reding 6948209eefaSThierry Reding if (!tegra_emc_validate_rate(emc, rate)) 6958209eefaSThierry Reding return -EINVAL; 6968209eefaSThierry Reding 697d5ef16baSDmitry Osipenko err = emc_set_min_rate(emc, rate, EMC_RATE_DEBUG); 6988209eefaSThierry Reding if (err < 0) 6998209eefaSThierry Reding return err; 7008209eefaSThierry Reding 7018209eefaSThierry Reding emc->debugfs.min_rate = rate; 7028209eefaSThierry Reding 7038209eefaSThierry Reding return 0; 7048209eefaSThierry Reding } 7058209eefaSThierry Reding 7068209eefaSThierry Reding DEFINE_SIMPLE_ATTRIBUTE(tegra_emc_debug_min_rate_fops, 7078209eefaSThierry Reding tegra_emc_debug_min_rate_get, 7088209eefaSThierry Reding tegra_emc_debug_min_rate_set, "%llu\n"); 7098209eefaSThierry Reding 7108209eefaSThierry Reding static int tegra_emc_debug_max_rate_get(void *data, u64 *rate) 7118209eefaSThierry Reding { 7128209eefaSThierry Reding struct tegra_emc *emc = data; 7138209eefaSThierry Reding 7148209eefaSThierry Reding *rate = emc->debugfs.max_rate; 7158209eefaSThierry Reding 7168209eefaSThierry Reding return 0; 7178209eefaSThierry Reding } 7188209eefaSThierry Reding 7198209eefaSThierry Reding static int tegra_emc_debug_max_rate_set(void *data, u64 rate) 7208209eefaSThierry Reding { 7218209eefaSThierry Reding struct tegra_emc *emc = data; 7228209eefaSThierry Reding int err; 7238209eefaSThierry Reding 7248209eefaSThierry Reding if (!tegra_emc_validate_rate(emc, rate)) 7258209eefaSThierry Reding return -EINVAL; 7268209eefaSThierry Reding 727d5ef16baSDmitry Osipenko err = emc_set_max_rate(emc, rate, EMC_RATE_DEBUG); 7288209eefaSThierry Reding if (err < 0) 7298209eefaSThierry Reding return err; 7308209eefaSThierry Reding 7318209eefaSThierry Reding emc->debugfs.max_rate = rate; 7328209eefaSThierry Reding 7338209eefaSThierry Reding return 0; 7348209eefaSThierry Reding } 7358209eefaSThierry Reding 7368209eefaSThierry Reding DEFINE_SIMPLE_ATTRIBUTE(tegra_emc_debug_max_rate_fops, 7378209eefaSThierry Reding tegra_emc_debug_max_rate_get, 7388209eefaSThierry Reding tegra_emc_debug_max_rate_set, "%llu\n"); 7398209eefaSThierry Reding 7408209eefaSThierry Reding static void tegra_emc_debugfs_init(struct tegra_emc *emc) 7418209eefaSThierry Reding { 7428209eefaSThierry Reding struct device *dev = emc->dev; 7438209eefaSThierry Reding unsigned int i; 7448209eefaSThierry Reding int err; 7458209eefaSThierry Reding 7468209eefaSThierry Reding emc->debugfs.min_rate = ULONG_MAX; 7478209eefaSThierry Reding emc->debugfs.max_rate = 0; 7488209eefaSThierry Reding 7498209eefaSThierry Reding for (i = 0; i < emc->num_timings; i++) { 7508209eefaSThierry Reding if (emc->timings[i].rate < emc->debugfs.min_rate) 7518209eefaSThierry Reding emc->debugfs.min_rate = emc->timings[i].rate; 7528209eefaSThierry Reding 7538209eefaSThierry Reding if (emc->timings[i].rate > emc->debugfs.max_rate) 7548209eefaSThierry Reding emc->debugfs.max_rate = emc->timings[i].rate; 7558209eefaSThierry Reding } 7568209eefaSThierry Reding 7572243af41SDmitry Osipenko if (!emc->num_timings) { 7582243af41SDmitry Osipenko emc->debugfs.min_rate = clk_get_rate(emc->clk); 7592243af41SDmitry Osipenko emc->debugfs.max_rate = emc->debugfs.min_rate; 7602243af41SDmitry Osipenko } 7612243af41SDmitry Osipenko 7628209eefaSThierry Reding err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate, 7638209eefaSThierry Reding emc->debugfs.max_rate); 7648209eefaSThierry Reding if (err < 0) { 7658209eefaSThierry Reding dev_err(dev, "failed to set rate range [%lu-%lu] for %pC\n", 7668209eefaSThierry Reding emc->debugfs.min_rate, emc->debugfs.max_rate, 7678209eefaSThierry Reding emc->clk); 7688209eefaSThierry Reding } 7698209eefaSThierry Reding 7708209eefaSThierry Reding emc->debugfs.root = debugfs_create_dir("emc", NULL); 7718209eefaSThierry Reding if (!emc->debugfs.root) { 7728209eefaSThierry Reding dev_err(emc->dev, "failed to create debugfs directory\n"); 7738209eefaSThierry Reding return; 7748209eefaSThierry Reding } 7758209eefaSThierry Reding 7766cc8823aSDmitry Osipenko debugfs_create_file("available_rates", 0444, emc->debugfs.root, 7778209eefaSThierry Reding emc, &tegra_emc_debug_available_rates_fops); 7786cc8823aSDmitry Osipenko debugfs_create_file("min_rate", 0644, emc->debugfs.root, 7798209eefaSThierry Reding emc, &tegra_emc_debug_min_rate_fops); 7806cc8823aSDmitry Osipenko debugfs_create_file("max_rate", 0644, emc->debugfs.root, 7818209eefaSThierry Reding emc, &tegra_emc_debug_max_rate_fops); 7828209eefaSThierry Reding } 7838209eefaSThierry Reding 784d5ef16baSDmitry Osipenko static inline struct tegra_emc * 785d5ef16baSDmitry Osipenko to_tegra_emc_provider(struct icc_provider *provider) 786d5ef16baSDmitry Osipenko { 787d5ef16baSDmitry Osipenko return container_of(provider, struct tegra_emc, provider); 788d5ef16baSDmitry Osipenko } 789d5ef16baSDmitry Osipenko 790d5ef16baSDmitry Osipenko static struct icc_node_data * 791d5ef16baSDmitry Osipenko emc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data) 792d5ef16baSDmitry Osipenko { 793d5ef16baSDmitry Osipenko struct icc_provider *provider = data; 794d5ef16baSDmitry Osipenko struct icc_node_data *ndata; 795d5ef16baSDmitry Osipenko struct icc_node *node; 796d5ef16baSDmitry Osipenko 797d5ef16baSDmitry Osipenko /* External Memory is the only possible ICC route */ 798d5ef16baSDmitry Osipenko list_for_each_entry(node, &provider->nodes, node_list) { 799d5ef16baSDmitry Osipenko if (node->id != TEGRA_ICC_EMEM) 800d5ef16baSDmitry Osipenko continue; 801d5ef16baSDmitry Osipenko 802d5ef16baSDmitry Osipenko ndata = kzalloc(sizeof(*ndata), GFP_KERNEL); 803d5ef16baSDmitry Osipenko if (!ndata) 804d5ef16baSDmitry Osipenko return ERR_PTR(-ENOMEM); 805d5ef16baSDmitry Osipenko 806d5ef16baSDmitry Osipenko /* 807d5ef16baSDmitry Osipenko * SRC and DST nodes should have matching TAG in order to have 808d5ef16baSDmitry Osipenko * it set by default for a requested path. 809d5ef16baSDmitry Osipenko */ 810d5ef16baSDmitry Osipenko ndata->tag = TEGRA_MC_ICC_TAG_ISO; 811d5ef16baSDmitry Osipenko ndata->node = node; 812d5ef16baSDmitry Osipenko 813d5ef16baSDmitry Osipenko return ndata; 814d5ef16baSDmitry Osipenko } 815d5ef16baSDmitry Osipenko 816d5ef16baSDmitry Osipenko return ERR_PTR(-EPROBE_DEFER); 817d5ef16baSDmitry Osipenko } 818d5ef16baSDmitry Osipenko 819d5ef16baSDmitry Osipenko static int emc_icc_set(struct icc_node *src, struct icc_node *dst) 820d5ef16baSDmitry Osipenko { 821d5ef16baSDmitry Osipenko struct tegra_emc *emc = to_tegra_emc_provider(dst->provider); 822d5ef16baSDmitry Osipenko unsigned long long peak_bw = icc_units_to_bps(dst->peak_bw); 823d5ef16baSDmitry Osipenko unsigned long long avg_bw = icc_units_to_bps(dst->avg_bw); 824d5ef16baSDmitry Osipenko unsigned long long rate = max(avg_bw, peak_bw); 825d5ef16baSDmitry Osipenko unsigned int dram_data_bus_width_bytes; 826d5ef16baSDmitry Osipenko int err; 827d5ef16baSDmitry Osipenko 828d5ef16baSDmitry Osipenko /* 829d5ef16baSDmitry Osipenko * Tegra20 EMC runs on x2 clock rate of SDRAM bus because DDR data 830d5ef16baSDmitry Osipenko * is sampled on both clock edges. This means that EMC clock rate 831d5ef16baSDmitry Osipenko * equals to the peak data-rate. 832d5ef16baSDmitry Osipenko */ 833d5ef16baSDmitry Osipenko dram_data_bus_width_bytes = emc->dram_bus_width / 8; 834d5ef16baSDmitry Osipenko do_div(rate, dram_data_bus_width_bytes); 835d5ef16baSDmitry Osipenko rate = min_t(u64, rate, U32_MAX); 836d5ef16baSDmitry Osipenko 837d5ef16baSDmitry Osipenko err = emc_set_min_rate(emc, rate, EMC_RATE_ICC); 838d5ef16baSDmitry Osipenko if (err) 839d5ef16baSDmitry Osipenko return err; 840d5ef16baSDmitry Osipenko 841d5ef16baSDmitry Osipenko return 0; 842d5ef16baSDmitry Osipenko } 843d5ef16baSDmitry Osipenko 844d5ef16baSDmitry Osipenko static int tegra_emc_interconnect_init(struct tegra_emc *emc) 845d5ef16baSDmitry Osipenko { 846d5ef16baSDmitry Osipenko const struct tegra_mc_soc *soc; 847d5ef16baSDmitry Osipenko struct icc_node *node; 848d5ef16baSDmitry Osipenko int err; 849d5ef16baSDmitry Osipenko 850d5ef16baSDmitry Osipenko emc->mc = devm_tegra_memory_controller_get(emc->dev); 851d5ef16baSDmitry Osipenko if (IS_ERR(emc->mc)) 852d5ef16baSDmitry Osipenko return PTR_ERR(emc->mc); 853d5ef16baSDmitry Osipenko 854d5ef16baSDmitry Osipenko soc = emc->mc->soc; 855d5ef16baSDmitry Osipenko 856d5ef16baSDmitry Osipenko emc->provider.dev = emc->dev; 857d5ef16baSDmitry Osipenko emc->provider.set = emc_icc_set; 858d5ef16baSDmitry Osipenko emc->provider.data = &emc->provider; 859d5ef16baSDmitry Osipenko emc->provider.aggregate = soc->icc_ops->aggregate; 860d5ef16baSDmitry Osipenko emc->provider.xlate_extended = emc_of_icc_xlate_extended; 861d5ef16baSDmitry Osipenko 862d5ef16baSDmitry Osipenko err = icc_provider_add(&emc->provider); 863d5ef16baSDmitry Osipenko if (err) 864d5ef16baSDmitry Osipenko goto err_msg; 865d5ef16baSDmitry Osipenko 866d5ef16baSDmitry Osipenko /* create External Memory Controller node */ 867d5ef16baSDmitry Osipenko node = icc_node_create(TEGRA_ICC_EMC); 868d5ef16baSDmitry Osipenko if (IS_ERR(node)) { 869d5ef16baSDmitry Osipenko err = PTR_ERR(node); 870d5ef16baSDmitry Osipenko goto del_provider; 871d5ef16baSDmitry Osipenko } 872d5ef16baSDmitry Osipenko 873d5ef16baSDmitry Osipenko node->name = "External Memory Controller"; 874d5ef16baSDmitry Osipenko icc_node_add(node, &emc->provider); 875d5ef16baSDmitry Osipenko 876d5ef16baSDmitry Osipenko /* link External Memory Controller to External Memory (DRAM) */ 877d5ef16baSDmitry Osipenko err = icc_link_create(node, TEGRA_ICC_EMEM); 878d5ef16baSDmitry Osipenko if (err) 879d5ef16baSDmitry Osipenko goto remove_nodes; 880d5ef16baSDmitry Osipenko 881d5ef16baSDmitry Osipenko /* create External Memory node */ 882d5ef16baSDmitry Osipenko node = icc_node_create(TEGRA_ICC_EMEM); 883d5ef16baSDmitry Osipenko if (IS_ERR(node)) { 884d5ef16baSDmitry Osipenko err = PTR_ERR(node); 885d5ef16baSDmitry Osipenko goto remove_nodes; 886d5ef16baSDmitry Osipenko } 887d5ef16baSDmitry Osipenko 888d5ef16baSDmitry Osipenko node->name = "External Memory (DRAM)"; 889d5ef16baSDmitry Osipenko icc_node_add(node, &emc->provider); 890d5ef16baSDmitry Osipenko 891d5ef16baSDmitry Osipenko return 0; 892d5ef16baSDmitry Osipenko 893d5ef16baSDmitry Osipenko remove_nodes: 894d5ef16baSDmitry Osipenko icc_nodes_remove(&emc->provider); 895d5ef16baSDmitry Osipenko del_provider: 896d5ef16baSDmitry Osipenko icc_provider_del(&emc->provider); 897d5ef16baSDmitry Osipenko err_msg: 898d5ef16baSDmitry Osipenko dev_err(emc->dev, "failed to initialize ICC: %d\n", err); 899d5ef16baSDmitry Osipenko 900d5ef16baSDmitry Osipenko return err; 901d5ef16baSDmitry Osipenko } 902d5ef16baSDmitry Osipenko 903d5ef16baSDmitry Osipenko static int tegra_emc_opp_table_init(struct tegra_emc *emc) 904d5ef16baSDmitry Osipenko { 905de47653bSDmitry Osipenko struct opp_table *reg_opp_table = NULL, *clk_opp_table; 906d5ef16baSDmitry Osipenko const char *rname = "core"; 907d5ef16baSDmitry Osipenko int err; 908d5ef16baSDmitry Osipenko 909d5ef16baSDmitry Osipenko /* 910d5ef16baSDmitry Osipenko * Legacy device-trees don't have OPP table and EMC driver isn't 911d5ef16baSDmitry Osipenko * useful in this case. 912d5ef16baSDmitry Osipenko */ 913d5ef16baSDmitry Osipenko if (!device_property_present(emc->dev, "operating-points-v2")) { 914d5ef16baSDmitry Osipenko dev_err(emc->dev, 915d5ef16baSDmitry Osipenko "OPP table not found, please update your device tree\n"); 916d5ef16baSDmitry Osipenko return -ENODEV; 917d5ef16baSDmitry Osipenko } 918d5ef16baSDmitry Osipenko 919d5ef16baSDmitry Osipenko /* voltage scaling is optional */ 920de47653bSDmitry Osipenko if (device_property_present(emc->dev, "core-supply")) { 921de47653bSDmitry Osipenko reg_opp_table = dev_pm_opp_set_regulators(emc->dev, &rname, 1); 922de47653bSDmitry Osipenko if (IS_ERR(reg_opp_table)) 923de47653bSDmitry Osipenko return dev_err_probe(emc->dev, PTR_ERR(reg_opp_table), 924de47653bSDmitry Osipenko "failed to set OPP regulator\n"); 925de47653bSDmitry Osipenko } 926d5ef16baSDmitry Osipenko 927de47653bSDmitry Osipenko clk_opp_table = dev_pm_opp_set_clkname(emc->dev, NULL); 928de47653bSDmitry Osipenko err = PTR_ERR_OR_ZERO(clk_opp_table); 929de47653bSDmitry Osipenko if (err) { 930de47653bSDmitry Osipenko dev_err(emc->dev, "failed to set OPP clk: %d\n", err); 931de47653bSDmitry Osipenko goto put_reg_table; 932de47653bSDmitry Osipenko } 933d5ef16baSDmitry Osipenko 934d5ef16baSDmitry Osipenko err = dev_pm_opp_of_add_table(emc->dev); 935d5ef16baSDmitry Osipenko if (err) { 936d5ef16baSDmitry Osipenko dev_err(emc->dev, "failed to add OPP table: %d\n", err); 937de47653bSDmitry Osipenko goto put_clk_table; 938d5ef16baSDmitry Osipenko } 939d5ef16baSDmitry Osipenko 940d5ef16baSDmitry Osipenko dev_info(emc->dev, "current clock rate %lu MHz\n", 941d5ef16baSDmitry Osipenko clk_get_rate(emc->clk) / 1000000); 942d5ef16baSDmitry Osipenko 943d5ef16baSDmitry Osipenko /* first dummy rate-set initializes voltage state */ 944d5ef16baSDmitry Osipenko err = dev_pm_opp_set_rate(emc->dev, clk_get_rate(emc->clk)); 945d5ef16baSDmitry Osipenko if (err) { 946d5ef16baSDmitry Osipenko dev_err(emc->dev, "failed to initialize OPP clock: %d\n", err); 947d5ef16baSDmitry Osipenko goto remove_table; 948d5ef16baSDmitry Osipenko } 949d5ef16baSDmitry Osipenko 950d5ef16baSDmitry Osipenko return 0; 951d5ef16baSDmitry Osipenko 952d5ef16baSDmitry Osipenko remove_table: 953d5ef16baSDmitry Osipenko dev_pm_opp_of_remove_table(emc->dev); 954de47653bSDmitry Osipenko put_clk_table: 955de47653bSDmitry Osipenko dev_pm_opp_put_clkname(clk_opp_table); 956de47653bSDmitry Osipenko put_reg_table: 957de47653bSDmitry Osipenko if (reg_opp_table) 958de47653bSDmitry Osipenko dev_pm_opp_put_regulators(reg_opp_table); 959d5ef16baSDmitry Osipenko 960d5ef16baSDmitry Osipenko return err; 961d5ef16baSDmitry Osipenko } 962d5ef16baSDmitry Osipenko 963cba3902bSDmitry Osipenko static void devm_tegra_emc_unset_callback(void *data) 964cba3902bSDmitry Osipenko { 965cba3902bSDmitry Osipenko tegra20_clk_set_emc_round_callback(NULL, NULL); 966cba3902bSDmitry Osipenko } 967cba3902bSDmitry Osipenko 968cba3902bSDmitry Osipenko static void devm_tegra_emc_unreg_clk_notifier(void *data) 969cba3902bSDmitry Osipenko { 970cba3902bSDmitry Osipenko struct tegra_emc *emc = data; 971cba3902bSDmitry Osipenko 972cba3902bSDmitry Osipenko clk_notifier_unregister(emc->clk, &emc->clk_nb); 973cba3902bSDmitry Osipenko } 974cba3902bSDmitry Osipenko 975cba3902bSDmitry Osipenko static int tegra_emc_init_clk(struct tegra_emc *emc) 976cba3902bSDmitry Osipenko { 977cba3902bSDmitry Osipenko int err; 978cba3902bSDmitry Osipenko 979cba3902bSDmitry Osipenko tegra20_clk_set_emc_round_callback(emc_round_rate, emc); 980cba3902bSDmitry Osipenko 981cba3902bSDmitry Osipenko err = devm_add_action_or_reset(emc->dev, devm_tegra_emc_unset_callback, 982cba3902bSDmitry Osipenko NULL); 983cba3902bSDmitry Osipenko if (err) 984cba3902bSDmitry Osipenko return err; 985cba3902bSDmitry Osipenko 986cba3902bSDmitry Osipenko emc->clk = devm_clk_get(emc->dev, NULL); 987cba3902bSDmitry Osipenko if (IS_ERR(emc->clk)) { 988cba3902bSDmitry Osipenko dev_err(emc->dev, "failed to get EMC clock: %pe\n", emc->clk); 989cba3902bSDmitry Osipenko return PTR_ERR(emc->clk); 990cba3902bSDmitry Osipenko } 991cba3902bSDmitry Osipenko 992cba3902bSDmitry Osipenko err = clk_notifier_register(emc->clk, &emc->clk_nb); 993cba3902bSDmitry Osipenko if (err) { 994cba3902bSDmitry Osipenko dev_err(emc->dev, "failed to register clk notifier: %d\n", err); 995cba3902bSDmitry Osipenko return err; 996cba3902bSDmitry Osipenko } 997cba3902bSDmitry Osipenko 998cba3902bSDmitry Osipenko err = devm_add_action_or_reset(emc->dev, 999cba3902bSDmitry Osipenko devm_tegra_emc_unreg_clk_notifier, emc); 1000cba3902bSDmitry Osipenko if (err) 1001cba3902bSDmitry Osipenko return err; 1002cba3902bSDmitry Osipenko 1003cba3902bSDmitry Osipenko return 0; 1004cba3902bSDmitry Osipenko } 1005cba3902bSDmitry Osipenko 100696e5da7cSDmitry Osipenko static int tegra_emc_probe(struct platform_device *pdev) 100796e5da7cSDmitry Osipenko { 100896e5da7cSDmitry Osipenko struct device_node *np; 100996e5da7cSDmitry Osipenko struct tegra_emc *emc; 101096e5da7cSDmitry Osipenko int irq, err; 101196e5da7cSDmitry Osipenko 101296e5da7cSDmitry Osipenko irq = platform_get_irq(pdev, 0); 101396e5da7cSDmitry Osipenko if (irq < 0) { 101496e5da7cSDmitry Osipenko dev_err(&pdev->dev, "please update your device tree\n"); 101596e5da7cSDmitry Osipenko return irq; 101696e5da7cSDmitry Osipenko } 101796e5da7cSDmitry Osipenko 101896e5da7cSDmitry Osipenko emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL); 1019fa4794ffSDmitry Osipenko if (!emc) 102096e5da7cSDmitry Osipenko return -ENOMEM; 102196e5da7cSDmitry Osipenko 1022d5ef16baSDmitry Osipenko mutex_init(&emc->rate_lock); 102396e5da7cSDmitry Osipenko emc->clk_nb.notifier_call = tegra_emc_clk_change_notify; 102496e5da7cSDmitry Osipenko emc->dev = &pdev->dev; 102596e5da7cSDmitry Osipenko 1026fa4794ffSDmitry Osipenko np = tegra_emc_find_node_by_ram_code(&pdev->dev); 1027fa4794ffSDmitry Osipenko if (np) { 102896e5da7cSDmitry Osipenko err = tegra_emc_load_timings_from_dt(emc, np); 102996e5da7cSDmitry Osipenko of_node_put(np); 103096e5da7cSDmitry Osipenko if (err) 103196e5da7cSDmitry Osipenko return err; 1032fa4794ffSDmitry Osipenko } 103396e5da7cSDmitry Osipenko 10344e84d0a6SDmitry Osipenko emc->regs = devm_platform_ioremap_resource(pdev, 0); 103596e5da7cSDmitry Osipenko if (IS_ERR(emc->regs)) 103696e5da7cSDmitry Osipenko return PTR_ERR(emc->regs); 103796e5da7cSDmitry Osipenko 103896e5da7cSDmitry Osipenko err = emc_setup_hw(emc); 103996e5da7cSDmitry Osipenko if (err) 104096e5da7cSDmitry Osipenko return err; 104196e5da7cSDmitry Osipenko 104296e5da7cSDmitry Osipenko err = devm_request_irq(&pdev->dev, irq, tegra_emc_isr, 0, 104396e5da7cSDmitry Osipenko dev_name(&pdev->dev), emc); 104496e5da7cSDmitry Osipenko if (err) { 1045*e09312feSDmitry Osipenko dev_err(&pdev->dev, "failed to request IRQ: %d\n", err); 104696e5da7cSDmitry Osipenko return err; 104796e5da7cSDmitry Osipenko } 104896e5da7cSDmitry Osipenko 1049cba3902bSDmitry Osipenko err = tegra_emc_init_clk(emc); 1050cba3902bSDmitry Osipenko if (err) 1051cba3902bSDmitry Osipenko return err; 105296e5da7cSDmitry Osipenko 1053d5ef16baSDmitry Osipenko err = tegra_emc_opp_table_init(emc); 1054d5ef16baSDmitry Osipenko if (err) 1055cba3902bSDmitry Osipenko return err; 1056d5ef16baSDmitry Osipenko 10578209eefaSThierry Reding platform_set_drvdata(pdev, emc); 1058d5ef16baSDmitry Osipenko tegra_emc_rate_requests_init(emc); 10598209eefaSThierry Reding tegra_emc_debugfs_init(emc); 1060d5ef16baSDmitry Osipenko tegra_emc_interconnect_init(emc); 10618209eefaSThierry Reding 10620260979bSDmitry Osipenko /* 10630260979bSDmitry Osipenko * Don't allow the kernel module to be unloaded. Unloading adds some 10640260979bSDmitry Osipenko * extra complexity which doesn't really worth the effort in a case of 10650260979bSDmitry Osipenko * this driver. 10660260979bSDmitry Osipenko */ 10670260979bSDmitry Osipenko try_module_get(THIS_MODULE); 10680260979bSDmitry Osipenko 106996e5da7cSDmitry Osipenko return 0; 107096e5da7cSDmitry Osipenko } 107196e5da7cSDmitry Osipenko 107296e5da7cSDmitry Osipenko static const struct of_device_id tegra_emc_of_match[] = { 107396e5da7cSDmitry Osipenko { .compatible = "nvidia,tegra20-emc", }, 107496e5da7cSDmitry Osipenko {}, 107596e5da7cSDmitry Osipenko }; 10760260979bSDmitry Osipenko MODULE_DEVICE_TABLE(of, tegra_emc_of_match); 107796e5da7cSDmitry Osipenko 107896e5da7cSDmitry Osipenko static struct platform_driver tegra_emc_driver = { 107996e5da7cSDmitry Osipenko .probe = tegra_emc_probe, 108096e5da7cSDmitry Osipenko .driver = { 108196e5da7cSDmitry Osipenko .name = "tegra20-emc", 108296e5da7cSDmitry Osipenko .of_match_table = tegra_emc_of_match, 108396e5da7cSDmitry Osipenko .suppress_bind_attrs = true, 1084d5ef16baSDmitry Osipenko .sync_state = icc_sync_state, 108596e5da7cSDmitry Osipenko }, 108696e5da7cSDmitry Osipenko }; 10870260979bSDmitry Osipenko module_platform_driver(tegra_emc_driver); 108896e5da7cSDmitry Osipenko 10890260979bSDmitry Osipenko MODULE_AUTHOR("Dmitry Osipenko <digetx@gmail.com>"); 10900260979bSDmitry Osipenko MODULE_DESCRIPTION("NVIDIA Tegra20 EMC driver"); 10910260979bSDmitry Osipenko MODULE_LICENSE("GPL v2"); 1092