1*a1e29404SDevarsh Thakkar /* SPDX-License-Identifier: GPL-2.0 */ 2*a1e29404SDevarsh Thakkar /* 3*a1e29404SDevarsh Thakkar * Imagination E5010 JPEG Encoder driver. 4*a1e29404SDevarsh Thakkar * 5*a1e29404SDevarsh Thakkar * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ 6*a1e29404SDevarsh Thakkar * 7*a1e29404SDevarsh Thakkar * Author: David Huang <d-huang@ti.com> 8*a1e29404SDevarsh Thakkar * Author: Devarsh Thakkar <devarsht@ti.com> 9*a1e29404SDevarsh Thakkar */ 10*a1e29404SDevarsh Thakkar 11*a1e29404SDevarsh Thakkar #ifndef _E5010_JPEG_ENC_HW_H 12*a1e29404SDevarsh Thakkar #define _E5010_JPEG_ENC_HW_H 13*a1e29404SDevarsh Thakkar 14*a1e29404SDevarsh Thakkar #include "e5010-core-regs.h" 15*a1e29404SDevarsh Thakkar #include "e5010-mmu-regs.h" 16*a1e29404SDevarsh Thakkar 17*a1e29404SDevarsh Thakkar int e5010_hw_enable_output_address_error_irq(void __iomem *core_offset, u32 enable); 18*a1e29404SDevarsh Thakkar int e5010_hw_enable_picture_done_irq(void __iomem *core_offset, u32 enable); 19*a1e29404SDevarsh Thakkar int e5010_hw_enable_auto_clock_gating(void __iomem *core_offset, u32 enable); 20*a1e29404SDevarsh Thakkar int e5010_hw_enable_manual_clock_gating(void __iomem *core_offset, u32 enable); 21*a1e29404SDevarsh Thakkar int e5010_hw_enable_crc_check(void __iomem *core_offset, u32 enable); 22*a1e29404SDevarsh Thakkar int e5010_hw_set_input_source_to_memory(void __iomem *core_offset, u32 set); 23*a1e29404SDevarsh Thakkar int e5010_hw_set_input_luma_addr(void __iomem *core_offset, u32 val); 24*a1e29404SDevarsh Thakkar int e5010_hw_set_input_chroma_addr(void __iomem *core_offset, u32 val); 25*a1e29404SDevarsh Thakkar int e5010_hw_set_output_base_addr(void __iomem *core_offset, u32 val); 26*a1e29404SDevarsh Thakkar int e5010_hw_get_output_size(void __iomem *core_offset); 27*a1e29404SDevarsh Thakkar int e5010_hw_set_horizontal_size(void __iomem *core_offset, u32 val); 28*a1e29404SDevarsh Thakkar int e5010_hw_set_vertical_size(void __iomem *core_offset, u32 val); 29*a1e29404SDevarsh Thakkar int e5010_hw_set_luma_stride(void __iomem *core_offset, u32 bytesperline); 30*a1e29404SDevarsh Thakkar int e5010_hw_set_chroma_stride(void __iomem *core_offset, u32 bytesperline); 31*a1e29404SDevarsh Thakkar int e5010_hw_set_input_subsampling(void __iomem *core_offset, u32 val); 32*a1e29404SDevarsh Thakkar int e5010_hw_set_chroma_order(void __iomem *core_offset, u32 val); 33*a1e29404SDevarsh Thakkar int e5010_hw_set_qpvalue(void __iomem *core_offset, u32 offset, u32 value); 34*a1e29404SDevarsh Thakkar void e5010_reset(struct device *dev, void __iomem *core_offset, void __iomem *mmu_offset); 35*a1e29404SDevarsh Thakkar void e5010_hw_set_output_max_size(void __iomem *core_offset, u32 val); 36*a1e29404SDevarsh Thakkar void e5010_hw_clear_picture_done(void __iomem *core_offset, u32 clear); 37*a1e29404SDevarsh Thakkar void e5010_hw_encode_start(void __iomem *core_offset, u32 start); 38*a1e29404SDevarsh Thakkar void e5010_hw_clear_output_error(void __iomem *core_offset, u32 clear); 39*a1e29404SDevarsh Thakkar void e5010_hw_bypass_mmu(void __iomem *mmu_base, u32 enable); 40*a1e29404SDevarsh Thakkar bool e5010_hw_pic_done_irq(void __iomem *core_base); 41*a1e29404SDevarsh Thakkar bool e5010_hw_output_address_irq(void __iomem *core_base); 42*a1e29404SDevarsh Thakkar #endif 43