1f2e3bd9aSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2cb7a01acSMauro Carvalho Chehab /* 3cb7a01acSMauro Carvalho Chehab * drivers/media/i2c/tvp514x_regs.h 4cb7a01acSMauro Carvalho Chehab * 5cb7a01acSMauro Carvalho Chehab * Copyright (C) 2008 Texas Instruments Inc 6cb7a01acSMauro Carvalho Chehab * Author: Vaibhav Hiremath <hvaibhav@ti.com> 7cb7a01acSMauro Carvalho Chehab * 8cb7a01acSMauro Carvalho Chehab * Contributors: 9cb7a01acSMauro Carvalho Chehab * Sivaraj R <sivaraj@ti.com> 10cb7a01acSMauro Carvalho Chehab * Brijesh R Jadav <brijesh.j@ti.com> 11cb7a01acSMauro Carvalho Chehab * Hardik Shah <hardik.shah@ti.com> 12cb7a01acSMauro Carvalho Chehab * Manjunath Hadli <mrh@ti.com> 13cb7a01acSMauro Carvalho Chehab * Karicheri Muralidharan <m-karicheri2@ti.com> 14cb7a01acSMauro Carvalho Chehab */ 15cb7a01acSMauro Carvalho Chehab 16cb7a01acSMauro Carvalho Chehab #ifndef _TVP514X_REGS_H 17cb7a01acSMauro Carvalho Chehab #define _TVP514X_REGS_H 18cb7a01acSMauro Carvalho Chehab 19cb7a01acSMauro Carvalho Chehab /* 20cb7a01acSMauro Carvalho Chehab * TVP5146/47 registers 21cb7a01acSMauro Carvalho Chehab */ 22cb7a01acSMauro Carvalho Chehab #define REG_INPUT_SEL (0x00) 23cb7a01acSMauro Carvalho Chehab #define REG_AFE_GAIN_CTRL (0x01) 24cb7a01acSMauro Carvalho Chehab #define REG_VIDEO_STD (0x02) 25cb7a01acSMauro Carvalho Chehab #define REG_OPERATION_MODE (0x03) 26cb7a01acSMauro Carvalho Chehab #define REG_AUTOSWITCH_MASK (0x04) 27cb7a01acSMauro Carvalho Chehab 28cb7a01acSMauro Carvalho Chehab #define REG_COLOR_KILLER (0x05) 29cb7a01acSMauro Carvalho Chehab #define REG_LUMA_CONTROL1 (0x06) 30cb7a01acSMauro Carvalho Chehab #define REG_LUMA_CONTROL2 (0x07) 31cb7a01acSMauro Carvalho Chehab #define REG_LUMA_CONTROL3 (0x08) 32cb7a01acSMauro Carvalho Chehab 33cb7a01acSMauro Carvalho Chehab #define REG_BRIGHTNESS (0x09) 34cb7a01acSMauro Carvalho Chehab #define REG_CONTRAST (0x0A) 35cb7a01acSMauro Carvalho Chehab #define REG_SATURATION (0x0B) 36cb7a01acSMauro Carvalho Chehab #define REG_HUE (0x0C) 37cb7a01acSMauro Carvalho Chehab 38cb7a01acSMauro Carvalho Chehab #define REG_CHROMA_CONTROL1 (0x0D) 39cb7a01acSMauro Carvalho Chehab #define REG_CHROMA_CONTROL2 (0x0E) 40cb7a01acSMauro Carvalho Chehab 41cb7a01acSMauro Carvalho Chehab /* 0x0F Reserved */ 42cb7a01acSMauro Carvalho Chehab 43cb7a01acSMauro Carvalho Chehab #define REG_COMP_PR_SATURATION (0x10) 44cb7a01acSMauro Carvalho Chehab #define REG_COMP_Y_CONTRAST (0x11) 45cb7a01acSMauro Carvalho Chehab #define REG_COMP_PB_SATURATION (0x12) 46cb7a01acSMauro Carvalho Chehab 47cb7a01acSMauro Carvalho Chehab /* 0x13 Reserved */ 48cb7a01acSMauro Carvalho Chehab 49cb7a01acSMauro Carvalho Chehab #define REG_COMP_Y_BRIGHTNESS (0x14) 50cb7a01acSMauro Carvalho Chehab 51cb7a01acSMauro Carvalho Chehab /* 0x15 Reserved */ 52cb7a01acSMauro Carvalho Chehab 53cb7a01acSMauro Carvalho Chehab #define REG_AVID_START_PIXEL_LSB (0x16) 54cb7a01acSMauro Carvalho Chehab #define REG_AVID_START_PIXEL_MSB (0x17) 55cb7a01acSMauro Carvalho Chehab #define REG_AVID_STOP_PIXEL_LSB (0x18) 56cb7a01acSMauro Carvalho Chehab #define REG_AVID_STOP_PIXEL_MSB (0x19) 57cb7a01acSMauro Carvalho Chehab 58cb7a01acSMauro Carvalho Chehab #define REG_HSYNC_START_PIXEL_LSB (0x1A) 59cb7a01acSMauro Carvalho Chehab #define REG_HSYNC_START_PIXEL_MSB (0x1B) 60cb7a01acSMauro Carvalho Chehab #define REG_HSYNC_STOP_PIXEL_LSB (0x1C) 61cb7a01acSMauro Carvalho Chehab #define REG_HSYNC_STOP_PIXEL_MSB (0x1D) 62cb7a01acSMauro Carvalho Chehab 63cb7a01acSMauro Carvalho Chehab #define REG_VSYNC_START_LINE_LSB (0x1E) 64cb7a01acSMauro Carvalho Chehab #define REG_VSYNC_START_LINE_MSB (0x1F) 65cb7a01acSMauro Carvalho Chehab #define REG_VSYNC_STOP_LINE_LSB (0x20) 66cb7a01acSMauro Carvalho Chehab #define REG_VSYNC_STOP_LINE_MSB (0x21) 67cb7a01acSMauro Carvalho Chehab 68cb7a01acSMauro Carvalho Chehab #define REG_VBLK_START_LINE_LSB (0x22) 69cb7a01acSMauro Carvalho Chehab #define REG_VBLK_START_LINE_MSB (0x23) 70cb7a01acSMauro Carvalho Chehab #define REG_VBLK_STOP_LINE_LSB (0x24) 71cb7a01acSMauro Carvalho Chehab #define REG_VBLK_STOP_LINE_MSB (0x25) 72cb7a01acSMauro Carvalho Chehab 73cb7a01acSMauro Carvalho Chehab /* 0x26 - 0x27 Reserved */ 74cb7a01acSMauro Carvalho Chehab 75cb7a01acSMauro Carvalho Chehab #define REG_FAST_SWTICH_CONTROL (0x28) 76cb7a01acSMauro Carvalho Chehab 77cb7a01acSMauro Carvalho Chehab /* 0x29 Reserved */ 78cb7a01acSMauro Carvalho Chehab 79cb7a01acSMauro Carvalho Chehab #define REG_FAST_SWTICH_SCART_DELAY (0x2A) 80cb7a01acSMauro Carvalho Chehab 81cb7a01acSMauro Carvalho Chehab /* 0x2B Reserved */ 82cb7a01acSMauro Carvalho Chehab 83cb7a01acSMauro Carvalho Chehab #define REG_SCART_DELAY (0x2C) 84cb7a01acSMauro Carvalho Chehab #define REG_CTI_DELAY (0x2D) 85cb7a01acSMauro Carvalho Chehab #define REG_CTI_CONTROL (0x2E) 86cb7a01acSMauro Carvalho Chehab 87cb7a01acSMauro Carvalho Chehab /* 0x2F - 0x31 Reserved */ 88cb7a01acSMauro Carvalho Chehab 89cb7a01acSMauro Carvalho Chehab #define REG_SYNC_CONTROL (0x32) 90cb7a01acSMauro Carvalho Chehab #define REG_OUTPUT_FORMATTER1 (0x33) 91cb7a01acSMauro Carvalho Chehab #define REG_OUTPUT_FORMATTER2 (0x34) 92cb7a01acSMauro Carvalho Chehab #define REG_OUTPUT_FORMATTER3 (0x35) 93cb7a01acSMauro Carvalho Chehab #define REG_OUTPUT_FORMATTER4 (0x36) 94cb7a01acSMauro Carvalho Chehab #define REG_OUTPUT_FORMATTER5 (0x37) 95cb7a01acSMauro Carvalho Chehab #define REG_OUTPUT_FORMATTER6 (0x38) 96cb7a01acSMauro Carvalho Chehab #define REG_CLEAR_LOST_LOCK (0x39) 97cb7a01acSMauro Carvalho Chehab 98cb7a01acSMauro Carvalho Chehab #define REG_STATUS1 (0x3A) 99cb7a01acSMauro Carvalho Chehab #define REG_STATUS2 (0x3B) 100cb7a01acSMauro Carvalho Chehab 101cb7a01acSMauro Carvalho Chehab #define REG_AGC_GAIN_STATUS_LSB (0x3C) 102cb7a01acSMauro Carvalho Chehab #define REG_AGC_GAIN_STATUS_MSB (0x3D) 103cb7a01acSMauro Carvalho Chehab 104cb7a01acSMauro Carvalho Chehab /* 0x3E Reserved */ 105cb7a01acSMauro Carvalho Chehab 106cb7a01acSMauro Carvalho Chehab #define REG_VIDEO_STD_STATUS (0x3F) 107cb7a01acSMauro Carvalho Chehab #define REG_GPIO_INPUT1 (0x40) 108cb7a01acSMauro Carvalho Chehab #define REG_GPIO_INPUT2 (0x41) 109cb7a01acSMauro Carvalho Chehab 110cb7a01acSMauro Carvalho Chehab /* 0x42 - 0x45 Reserved */ 111cb7a01acSMauro Carvalho Chehab 112cb7a01acSMauro Carvalho Chehab #define REG_AFE_COARSE_GAIN_CH1 (0x46) 113cb7a01acSMauro Carvalho Chehab #define REG_AFE_COARSE_GAIN_CH2 (0x47) 114cb7a01acSMauro Carvalho Chehab #define REG_AFE_COARSE_GAIN_CH3 (0x48) 115cb7a01acSMauro Carvalho Chehab #define REG_AFE_COARSE_GAIN_CH4 (0x49) 116cb7a01acSMauro Carvalho Chehab 117cb7a01acSMauro Carvalho Chehab #define REG_AFE_FINE_GAIN_PB_B_LSB (0x4A) 118cb7a01acSMauro Carvalho Chehab #define REG_AFE_FINE_GAIN_PB_B_MSB (0x4B) 119cb7a01acSMauro Carvalho Chehab #define REG_AFE_FINE_GAIN_Y_G_CHROMA_LSB (0x4C) 120cb7a01acSMauro Carvalho Chehab #define REG_AFE_FINE_GAIN_Y_G_CHROMA_MSB (0x4D) 121cb7a01acSMauro Carvalho Chehab #define REG_AFE_FINE_GAIN_PR_R_LSB (0x4E) 122cb7a01acSMauro Carvalho Chehab #define REG_AFE_FINE_GAIN_PR_R_MSB (0x4F) 123cb7a01acSMauro Carvalho Chehab #define REG_AFE_FINE_GAIN_CVBS_LUMA_LSB (0x50) 124cb7a01acSMauro Carvalho Chehab #define REG_AFE_FINE_GAIN_CVBS_LUMA_MSB (0x51) 125cb7a01acSMauro Carvalho Chehab 126cb7a01acSMauro Carvalho Chehab /* 0x52 - 0x68 Reserved */ 127cb7a01acSMauro Carvalho Chehab 128cb7a01acSMauro Carvalho Chehab #define REG_FBIT_VBIT_CONTROL1 (0x69) 129cb7a01acSMauro Carvalho Chehab 130cb7a01acSMauro Carvalho Chehab /* 0x6A - 0x6B Reserved */ 131cb7a01acSMauro Carvalho Chehab 132cb7a01acSMauro Carvalho Chehab #define REG_BACKEND_AGC_CONTROL (0x6C) 133cb7a01acSMauro Carvalho Chehab 134cb7a01acSMauro Carvalho Chehab /* 0x6D - 0x6E Reserved */ 135cb7a01acSMauro Carvalho Chehab 136cb7a01acSMauro Carvalho Chehab #define REG_AGC_DECREMENT_SPEED_CONTROL (0x6F) 137cb7a01acSMauro Carvalho Chehab #define REG_ROM_VERSION (0x70) 138cb7a01acSMauro Carvalho Chehab 139cb7a01acSMauro Carvalho Chehab /* 0x71 - 0x73 Reserved */ 140cb7a01acSMauro Carvalho Chehab 141cb7a01acSMauro Carvalho Chehab #define REG_AGC_WHITE_PEAK_PROCESSING (0x74) 142cb7a01acSMauro Carvalho Chehab #define REG_FBIT_VBIT_CONTROL2 (0x75) 143cb7a01acSMauro Carvalho Chehab #define REG_VCR_TRICK_MODE_CONTROL (0x76) 144cb7a01acSMauro Carvalho Chehab #define REG_HORIZONTAL_SHAKE_INCREMENT (0x77) 145cb7a01acSMauro Carvalho Chehab #define REG_AGC_INCREMENT_SPEED (0x78) 146cb7a01acSMauro Carvalho Chehab #define REG_AGC_INCREMENT_DELAY (0x79) 147cb7a01acSMauro Carvalho Chehab 148cb7a01acSMauro Carvalho Chehab /* 0x7A - 0x7F Reserved */ 149cb7a01acSMauro Carvalho Chehab 150cb7a01acSMauro Carvalho Chehab #define REG_CHIP_ID_MSB (0x80) 151cb7a01acSMauro Carvalho Chehab #define REG_CHIP_ID_LSB (0x81) 152cb7a01acSMauro Carvalho Chehab 153cb7a01acSMauro Carvalho Chehab /* 0x82 Reserved */ 154cb7a01acSMauro Carvalho Chehab 155cb7a01acSMauro Carvalho Chehab #define REG_CPLL_SPEED_CONTROL (0x83) 156cb7a01acSMauro Carvalho Chehab 157cb7a01acSMauro Carvalho Chehab /* 0x84 - 0x96 Reserved */ 158cb7a01acSMauro Carvalho Chehab 159cb7a01acSMauro Carvalho Chehab #define REG_STATUS_REQUEST (0x97) 160cb7a01acSMauro Carvalho Chehab 161cb7a01acSMauro Carvalho Chehab /* 0x98 - 0x99 Reserved */ 162cb7a01acSMauro Carvalho Chehab 163cb7a01acSMauro Carvalho Chehab #define REG_VERTICAL_LINE_COUNT_LSB (0x9A) 164cb7a01acSMauro Carvalho Chehab #define REG_VERTICAL_LINE_COUNT_MSB (0x9B) 165cb7a01acSMauro Carvalho Chehab 166cb7a01acSMauro Carvalho Chehab /* 0x9C - 0x9D Reserved */ 167cb7a01acSMauro Carvalho Chehab 168cb7a01acSMauro Carvalho Chehab #define REG_AGC_DECREMENT_DELAY (0x9E) 169cb7a01acSMauro Carvalho Chehab 170cb7a01acSMauro Carvalho Chehab /* 0x9F - 0xB0 Reserved */ 171cb7a01acSMauro Carvalho Chehab 172cb7a01acSMauro Carvalho Chehab #define REG_VDP_TTX_FILTER_1_MASK1 (0xB1) 173cb7a01acSMauro Carvalho Chehab #define REG_VDP_TTX_FILTER_1_MASK2 (0xB2) 174cb7a01acSMauro Carvalho Chehab #define REG_VDP_TTX_FILTER_1_MASK3 (0xB3) 175cb7a01acSMauro Carvalho Chehab #define REG_VDP_TTX_FILTER_1_MASK4 (0xB4) 176cb7a01acSMauro Carvalho Chehab #define REG_VDP_TTX_FILTER_1_MASK5 (0xB5) 177cb7a01acSMauro Carvalho Chehab #define REG_VDP_TTX_FILTER_2_MASK1 (0xB6) 178cb7a01acSMauro Carvalho Chehab #define REG_VDP_TTX_FILTER_2_MASK2 (0xB7) 179cb7a01acSMauro Carvalho Chehab #define REG_VDP_TTX_FILTER_2_MASK3 (0xB8) 180cb7a01acSMauro Carvalho Chehab #define REG_VDP_TTX_FILTER_2_MASK4 (0xB9) 181cb7a01acSMauro Carvalho Chehab #define REG_VDP_TTX_FILTER_2_MASK5 (0xBA) 182cb7a01acSMauro Carvalho Chehab #define REG_VDP_TTX_FILTER_CONTROL (0xBB) 183cb7a01acSMauro Carvalho Chehab #define REG_VDP_FIFO_WORD_COUNT (0xBC) 184cb7a01acSMauro Carvalho Chehab #define REG_VDP_FIFO_INTERRUPT_THRLD (0xBD) 185cb7a01acSMauro Carvalho Chehab 186cb7a01acSMauro Carvalho Chehab /* 0xBE Reserved */ 187cb7a01acSMauro Carvalho Chehab 188cb7a01acSMauro Carvalho Chehab #define REG_VDP_FIFO_RESET (0xBF) 189cb7a01acSMauro Carvalho Chehab #define REG_VDP_FIFO_OUTPUT_CONTROL (0xC0) 190cb7a01acSMauro Carvalho Chehab #define REG_VDP_LINE_NUMBER_INTERRUPT (0xC1) 191cb7a01acSMauro Carvalho Chehab #define REG_VDP_PIXEL_ALIGNMENT_LSB (0xC2) 192cb7a01acSMauro Carvalho Chehab #define REG_VDP_PIXEL_ALIGNMENT_MSB (0xC3) 193cb7a01acSMauro Carvalho Chehab 194cb7a01acSMauro Carvalho Chehab /* 0xC4 - 0xD5 Reserved */ 195cb7a01acSMauro Carvalho Chehab 196cb7a01acSMauro Carvalho Chehab #define REG_VDP_LINE_START (0xD6) 197cb7a01acSMauro Carvalho Chehab #define REG_VDP_LINE_STOP (0xD7) 198cb7a01acSMauro Carvalho Chehab #define REG_VDP_GLOBAL_LINE_MODE (0xD8) 199cb7a01acSMauro Carvalho Chehab #define REG_VDP_FULL_FIELD_ENABLE (0xD9) 200cb7a01acSMauro Carvalho Chehab #define REG_VDP_FULL_FIELD_MODE (0xDA) 201cb7a01acSMauro Carvalho Chehab 202cb7a01acSMauro Carvalho Chehab /* 0xDB - 0xDF Reserved */ 203cb7a01acSMauro Carvalho Chehab 204cb7a01acSMauro Carvalho Chehab #define REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR (0xE0) 205cb7a01acSMauro Carvalho Chehab #define REG_VBUS_DATA_ACCESS_VBUS_ADDR_INCR (0xE1) 206cb7a01acSMauro Carvalho Chehab #define REG_FIFO_READ_DATA (0xE2) 207cb7a01acSMauro Carvalho Chehab 208cb7a01acSMauro Carvalho Chehab /* 0xE3 - 0xE7 Reserved */ 209cb7a01acSMauro Carvalho Chehab 210cb7a01acSMauro Carvalho Chehab #define REG_VBUS_ADDRESS_ACCESS1 (0xE8) 211cb7a01acSMauro Carvalho Chehab #define REG_VBUS_ADDRESS_ACCESS2 (0xE9) 212cb7a01acSMauro Carvalho Chehab #define REG_VBUS_ADDRESS_ACCESS3 (0xEA) 213cb7a01acSMauro Carvalho Chehab 214cb7a01acSMauro Carvalho Chehab /* 0xEB - 0xEF Reserved */ 215cb7a01acSMauro Carvalho Chehab 216cb7a01acSMauro Carvalho Chehab #define REG_INTERRUPT_RAW_STATUS0 (0xF0) 217cb7a01acSMauro Carvalho Chehab #define REG_INTERRUPT_RAW_STATUS1 (0xF1) 218cb7a01acSMauro Carvalho Chehab #define REG_INTERRUPT_STATUS0 (0xF2) 219cb7a01acSMauro Carvalho Chehab #define REG_INTERRUPT_STATUS1 (0xF3) 220cb7a01acSMauro Carvalho Chehab #define REG_INTERRUPT_MASK0 (0xF4) 221cb7a01acSMauro Carvalho Chehab #define REG_INTERRUPT_MASK1 (0xF5) 222cb7a01acSMauro Carvalho Chehab #define REG_INTERRUPT_CLEAR0 (0xF6) 223cb7a01acSMauro Carvalho Chehab #define REG_INTERRUPT_CLEAR1 (0xF7) 224cb7a01acSMauro Carvalho Chehab 225cb7a01acSMauro Carvalho Chehab /* 0xF8 - 0xFF Reserved */ 226cb7a01acSMauro Carvalho Chehab 227cb7a01acSMauro Carvalho Chehab /* 228cb7a01acSMauro Carvalho Chehab * Mask and bit definitions of TVP5146/47 registers 229cb7a01acSMauro Carvalho Chehab */ 230cb7a01acSMauro Carvalho Chehab /* The ID values we are looking for */ 231cb7a01acSMauro Carvalho Chehab #define TVP514X_CHIP_ID_MSB (0x51) 232cb7a01acSMauro Carvalho Chehab #define TVP5146_CHIP_ID_LSB (0x46) 233cb7a01acSMauro Carvalho Chehab #define TVP5147_CHIP_ID_LSB (0x47) 234cb7a01acSMauro Carvalho Chehab 235cb7a01acSMauro Carvalho Chehab #define VIDEO_STD_MASK (0x07) 236cb7a01acSMauro Carvalho Chehab #define VIDEO_STD_AUTO_SWITCH_BIT (0x00) 237cb7a01acSMauro Carvalho Chehab #define VIDEO_STD_NTSC_MJ_BIT (0x01) 238cb7a01acSMauro Carvalho Chehab #define VIDEO_STD_PAL_BDGHIN_BIT (0x02) 239cb7a01acSMauro Carvalho Chehab #define VIDEO_STD_PAL_M_BIT (0x03) 240cb7a01acSMauro Carvalho Chehab #define VIDEO_STD_PAL_COMBINATION_N_BIT (0x04) 241cb7a01acSMauro Carvalho Chehab #define VIDEO_STD_NTSC_4_43_BIT (0x05) 242cb7a01acSMauro Carvalho Chehab #define VIDEO_STD_SECAM_BIT (0x06) 243cb7a01acSMauro Carvalho Chehab #define VIDEO_STD_PAL_60_BIT (0x07) 244cb7a01acSMauro Carvalho Chehab 245cb7a01acSMauro Carvalho Chehab /* 246cb7a01acSMauro Carvalho Chehab * Status bit 247cb7a01acSMauro Carvalho Chehab */ 248cb7a01acSMauro Carvalho Chehab #define STATUS_TV_VCR_BIT (1<<0) 249cb7a01acSMauro Carvalho Chehab #define STATUS_HORZ_SYNC_LOCK_BIT (1<<1) 250cb7a01acSMauro Carvalho Chehab #define STATUS_VIRT_SYNC_LOCK_BIT (1<<2) 251cb7a01acSMauro Carvalho Chehab #define STATUS_CLR_SUBCAR_LOCK_BIT (1<<3) 252cb7a01acSMauro Carvalho Chehab #define STATUS_LOST_LOCK_DETECT_BIT (1<<4) 253cb7a01acSMauro Carvalho Chehab #define STATUS_FEILD_RATE_BIT (1<<5) 254cb7a01acSMauro Carvalho Chehab #define STATUS_LINE_ALTERNATING_BIT (1<<6) 255cb7a01acSMauro Carvalho Chehab #define STATUS_PEAK_WHITE_DETECT_BIT (1<<7) 256cb7a01acSMauro Carvalho Chehab 257cb7a01acSMauro Carvalho Chehab /* Tokens for register write */ 258cb7a01acSMauro Carvalho Chehab #define TOK_WRITE (0) /* token for write operation */ 259cb7a01acSMauro Carvalho Chehab #define TOK_TERM (1) /* terminating token */ 260cb7a01acSMauro Carvalho Chehab #define TOK_DELAY (2) /* delay token for reg list */ 261cb7a01acSMauro Carvalho Chehab #define TOK_SKIP (3) /* token to skip a register */ 262cb7a01acSMauro Carvalho Chehab /** 263cb7a01acSMauro Carvalho Chehab * struct tvp514x_reg - Structure for TVP5146/47 register initialization values 264*a68a90b2SHans Verkuil * @token: Token: TOK_WRITE, TOK_TERM etc.. 265*a68a90b2SHans Verkuil * @reg: Register offset 266*a68a90b2SHans Verkuil * @val: Register Value for TOK_WRITE or delay in ms for TOK_DELAY 267cb7a01acSMauro Carvalho Chehab */ 268cb7a01acSMauro Carvalho Chehab struct tvp514x_reg { 269cb7a01acSMauro Carvalho Chehab u8 token; 270cb7a01acSMauro Carvalho Chehab u8 reg; 271cb7a01acSMauro Carvalho Chehab u32 val; 272cb7a01acSMauro Carvalho Chehab }; 273cb7a01acSMauro Carvalho Chehab 274cb7a01acSMauro Carvalho Chehab #endif /* ifndef _TVP514X_REGS_H */ 275