1*6058bb36SCarlo Caione /* 2*6058bb36SCarlo Caione * Allwinner A20/A31 SoCs NMI IRQ chip driver. 3*6058bb36SCarlo Caione * 4*6058bb36SCarlo Caione * Carlo Caione <carlo.caione@gmail.com> 5*6058bb36SCarlo Caione * 6*6058bb36SCarlo Caione * This file is licensed under the terms of the GNU General Public 7*6058bb36SCarlo Caione * License version 2. This program is licensed "as is" without any 8*6058bb36SCarlo Caione * warranty of any kind, whether express or implied. 9*6058bb36SCarlo Caione */ 10*6058bb36SCarlo Caione 11*6058bb36SCarlo Caione #include <linux/bitops.h> 12*6058bb36SCarlo Caione #include <linux/device.h> 13*6058bb36SCarlo Caione #include <linux/io.h> 14*6058bb36SCarlo Caione #include <linux/irq.h> 15*6058bb36SCarlo Caione #include <linux/interrupt.h> 16*6058bb36SCarlo Caione #include <linux/irqdomain.h> 17*6058bb36SCarlo Caione #include <linux/of_irq.h> 18*6058bb36SCarlo Caione #include <linux/of_address.h> 19*6058bb36SCarlo Caione #include <linux/of_platform.h> 20*6058bb36SCarlo Caione #include <linux/irqchip/chained_irq.h> 21*6058bb36SCarlo Caione #include "irqchip.h" 22*6058bb36SCarlo Caione 23*6058bb36SCarlo Caione #define SUNXI_NMI_SRC_TYPE_MASK 0x00000003 24*6058bb36SCarlo Caione 25*6058bb36SCarlo Caione enum { 26*6058bb36SCarlo Caione SUNXI_SRC_TYPE_LEVEL_LOW = 0, 27*6058bb36SCarlo Caione SUNXI_SRC_TYPE_EDGE_FALLING, 28*6058bb36SCarlo Caione SUNXI_SRC_TYPE_LEVEL_HIGH, 29*6058bb36SCarlo Caione SUNXI_SRC_TYPE_EDGE_RISING, 30*6058bb36SCarlo Caione }; 31*6058bb36SCarlo Caione 32*6058bb36SCarlo Caione struct sunxi_sc_nmi_reg_offs { 33*6058bb36SCarlo Caione u32 ctrl; 34*6058bb36SCarlo Caione u32 pend; 35*6058bb36SCarlo Caione u32 enable; 36*6058bb36SCarlo Caione }; 37*6058bb36SCarlo Caione 38*6058bb36SCarlo Caione static struct sunxi_sc_nmi_reg_offs sun7i_reg_offs = { 39*6058bb36SCarlo Caione .ctrl = 0x00, 40*6058bb36SCarlo Caione .pend = 0x04, 41*6058bb36SCarlo Caione .enable = 0x08, 42*6058bb36SCarlo Caione }; 43*6058bb36SCarlo Caione 44*6058bb36SCarlo Caione static struct sunxi_sc_nmi_reg_offs sun6i_reg_offs = { 45*6058bb36SCarlo Caione .ctrl = 0x00, 46*6058bb36SCarlo Caione .pend = 0x04, 47*6058bb36SCarlo Caione .enable = 0x34, 48*6058bb36SCarlo Caione }; 49*6058bb36SCarlo Caione 50*6058bb36SCarlo Caione static inline void sunxi_sc_nmi_write(struct irq_chip_generic *gc, u32 off, 51*6058bb36SCarlo Caione u32 val) 52*6058bb36SCarlo Caione { 53*6058bb36SCarlo Caione irq_reg_writel(val, gc->reg_base + off); 54*6058bb36SCarlo Caione } 55*6058bb36SCarlo Caione 56*6058bb36SCarlo Caione static inline u32 sunxi_sc_nmi_read(struct irq_chip_generic *gc, u32 off) 57*6058bb36SCarlo Caione { 58*6058bb36SCarlo Caione return irq_reg_readl(gc->reg_base + off); 59*6058bb36SCarlo Caione } 60*6058bb36SCarlo Caione 61*6058bb36SCarlo Caione static void sunxi_sc_nmi_handle_irq(unsigned int irq, struct irq_desc *desc) 62*6058bb36SCarlo Caione { 63*6058bb36SCarlo Caione struct irq_domain *domain = irq_desc_get_handler_data(desc); 64*6058bb36SCarlo Caione struct irq_chip *chip = irq_get_chip(irq); 65*6058bb36SCarlo Caione unsigned int virq = irq_find_mapping(domain, 0); 66*6058bb36SCarlo Caione 67*6058bb36SCarlo Caione chained_irq_enter(chip, desc); 68*6058bb36SCarlo Caione generic_handle_irq(virq); 69*6058bb36SCarlo Caione chained_irq_exit(chip, desc); 70*6058bb36SCarlo Caione } 71*6058bb36SCarlo Caione 72*6058bb36SCarlo Caione static int sunxi_sc_nmi_set_type(struct irq_data *data, unsigned int flow_type) 73*6058bb36SCarlo Caione { 74*6058bb36SCarlo Caione struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); 75*6058bb36SCarlo Caione struct irq_chip_type *ct = gc->chip_types; 76*6058bb36SCarlo Caione u32 src_type_reg; 77*6058bb36SCarlo Caione u32 ctrl_off = ct->regs.type; 78*6058bb36SCarlo Caione unsigned int src_type; 79*6058bb36SCarlo Caione unsigned int i; 80*6058bb36SCarlo Caione 81*6058bb36SCarlo Caione irq_gc_lock(gc); 82*6058bb36SCarlo Caione 83*6058bb36SCarlo Caione switch (flow_type & IRQF_TRIGGER_MASK) { 84*6058bb36SCarlo Caione case IRQ_TYPE_EDGE_FALLING: 85*6058bb36SCarlo Caione src_type = SUNXI_SRC_TYPE_EDGE_FALLING; 86*6058bb36SCarlo Caione break; 87*6058bb36SCarlo Caione case IRQ_TYPE_EDGE_RISING: 88*6058bb36SCarlo Caione src_type = SUNXI_SRC_TYPE_EDGE_RISING; 89*6058bb36SCarlo Caione break; 90*6058bb36SCarlo Caione case IRQ_TYPE_LEVEL_HIGH: 91*6058bb36SCarlo Caione src_type = SUNXI_SRC_TYPE_LEVEL_HIGH; 92*6058bb36SCarlo Caione break; 93*6058bb36SCarlo Caione case IRQ_TYPE_NONE: 94*6058bb36SCarlo Caione case IRQ_TYPE_LEVEL_LOW: 95*6058bb36SCarlo Caione src_type = SUNXI_SRC_TYPE_LEVEL_LOW; 96*6058bb36SCarlo Caione break; 97*6058bb36SCarlo Caione default: 98*6058bb36SCarlo Caione irq_gc_unlock(gc); 99*6058bb36SCarlo Caione pr_err("%s: Cannot assign multiple trigger modes to IRQ %d.\n", 100*6058bb36SCarlo Caione __func__, data->irq); 101*6058bb36SCarlo Caione return -EBADR; 102*6058bb36SCarlo Caione } 103*6058bb36SCarlo Caione 104*6058bb36SCarlo Caione irqd_set_trigger_type(data, flow_type); 105*6058bb36SCarlo Caione irq_setup_alt_chip(data, flow_type); 106*6058bb36SCarlo Caione 107*6058bb36SCarlo Caione for (i = 0; i <= gc->num_ct; i++, ct++) 108*6058bb36SCarlo Caione if (ct->type & flow_type) 109*6058bb36SCarlo Caione ctrl_off = ct->regs.type; 110*6058bb36SCarlo Caione 111*6058bb36SCarlo Caione src_type_reg = sunxi_sc_nmi_read(gc, ctrl_off); 112*6058bb36SCarlo Caione src_type_reg &= ~SUNXI_NMI_SRC_TYPE_MASK; 113*6058bb36SCarlo Caione src_type_reg |= src_type; 114*6058bb36SCarlo Caione sunxi_sc_nmi_write(gc, ctrl_off, src_type_reg); 115*6058bb36SCarlo Caione 116*6058bb36SCarlo Caione irq_gc_unlock(gc); 117*6058bb36SCarlo Caione 118*6058bb36SCarlo Caione return IRQ_SET_MASK_OK; 119*6058bb36SCarlo Caione } 120*6058bb36SCarlo Caione 121*6058bb36SCarlo Caione static int __init sunxi_sc_nmi_irq_init(struct device_node *node, 122*6058bb36SCarlo Caione struct sunxi_sc_nmi_reg_offs *reg_offs) 123*6058bb36SCarlo Caione { 124*6058bb36SCarlo Caione struct irq_domain *domain; 125*6058bb36SCarlo Caione struct irq_chip_generic *gc; 126*6058bb36SCarlo Caione unsigned int irq; 127*6058bb36SCarlo Caione unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; 128*6058bb36SCarlo Caione int ret; 129*6058bb36SCarlo Caione 130*6058bb36SCarlo Caione 131*6058bb36SCarlo Caione domain = irq_domain_add_linear(node, 1, &irq_generic_chip_ops, NULL); 132*6058bb36SCarlo Caione if (!domain) { 133*6058bb36SCarlo Caione pr_err("%s: Could not register interrupt domain.\n", node->name); 134*6058bb36SCarlo Caione return -ENOMEM; 135*6058bb36SCarlo Caione } 136*6058bb36SCarlo Caione 137*6058bb36SCarlo Caione ret = irq_alloc_domain_generic_chips(domain, 1, 2, node->name, 138*6058bb36SCarlo Caione handle_fasteoi_irq, clr, 0, 139*6058bb36SCarlo Caione IRQ_GC_INIT_MASK_CACHE); 140*6058bb36SCarlo Caione if (ret) { 141*6058bb36SCarlo Caione pr_err("%s: Could not allocate generic interrupt chip.\n", 142*6058bb36SCarlo Caione node->name); 143*6058bb36SCarlo Caione goto fail_irqd_remove; 144*6058bb36SCarlo Caione } 145*6058bb36SCarlo Caione 146*6058bb36SCarlo Caione irq = irq_of_parse_and_map(node, 0); 147*6058bb36SCarlo Caione if (irq <= 0) { 148*6058bb36SCarlo Caione pr_err("%s: unable to parse irq\n", node->name); 149*6058bb36SCarlo Caione ret = -EINVAL; 150*6058bb36SCarlo Caione goto fail_irqd_remove; 151*6058bb36SCarlo Caione } 152*6058bb36SCarlo Caione 153*6058bb36SCarlo Caione gc = irq_get_domain_generic_chip(domain, 0); 154*6058bb36SCarlo Caione gc->reg_base = of_iomap(node, 0); 155*6058bb36SCarlo Caione if (!gc->reg_base) { 156*6058bb36SCarlo Caione pr_err("%s: unable to map resource\n", node->name); 157*6058bb36SCarlo Caione ret = -ENOMEM; 158*6058bb36SCarlo Caione goto fail_irqd_remove; 159*6058bb36SCarlo Caione } 160*6058bb36SCarlo Caione 161*6058bb36SCarlo Caione gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK; 162*6058bb36SCarlo Caione gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; 163*6058bb36SCarlo Caione gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; 164*6058bb36SCarlo Caione gc->chip_types[0].chip.irq_eoi = irq_gc_ack_set_bit; 165*6058bb36SCarlo Caione gc->chip_types[0].chip.irq_set_type = sunxi_sc_nmi_set_type; 166*6058bb36SCarlo Caione gc->chip_types[0].chip.flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED; 167*6058bb36SCarlo Caione gc->chip_types[0].regs.ack = reg_offs->pend; 168*6058bb36SCarlo Caione gc->chip_types[0].regs.mask = reg_offs->enable; 169*6058bb36SCarlo Caione gc->chip_types[0].regs.type = reg_offs->ctrl; 170*6058bb36SCarlo Caione 171*6058bb36SCarlo Caione gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH; 172*6058bb36SCarlo Caione gc->chip_types[1].chip.name = gc->chip_types[0].chip.name; 173*6058bb36SCarlo Caione gc->chip_types[1].chip.irq_ack = irq_gc_ack_set_bit; 174*6058bb36SCarlo Caione gc->chip_types[1].chip.irq_mask = irq_gc_mask_clr_bit; 175*6058bb36SCarlo Caione gc->chip_types[1].chip.irq_unmask = irq_gc_mask_set_bit; 176*6058bb36SCarlo Caione gc->chip_types[1].chip.irq_set_type = sunxi_sc_nmi_set_type; 177*6058bb36SCarlo Caione gc->chip_types[1].regs.ack = reg_offs->pend; 178*6058bb36SCarlo Caione gc->chip_types[1].regs.mask = reg_offs->enable; 179*6058bb36SCarlo Caione gc->chip_types[1].regs.type = reg_offs->ctrl; 180*6058bb36SCarlo Caione gc->chip_types[1].handler = handle_edge_irq; 181*6058bb36SCarlo Caione 182*6058bb36SCarlo Caione irq_set_handler_data(irq, domain); 183*6058bb36SCarlo Caione irq_set_chained_handler(irq, sunxi_sc_nmi_handle_irq); 184*6058bb36SCarlo Caione 185*6058bb36SCarlo Caione sunxi_sc_nmi_write(gc, reg_offs->enable, 0); 186*6058bb36SCarlo Caione sunxi_sc_nmi_write(gc, reg_offs->pend, 0x1); 187*6058bb36SCarlo Caione 188*6058bb36SCarlo Caione return 0; 189*6058bb36SCarlo Caione 190*6058bb36SCarlo Caione fail_irqd_remove: 191*6058bb36SCarlo Caione irq_domain_remove(domain); 192*6058bb36SCarlo Caione 193*6058bb36SCarlo Caione return ret; 194*6058bb36SCarlo Caione } 195*6058bb36SCarlo Caione 196*6058bb36SCarlo Caione static int __init sun6i_sc_nmi_irq_init(struct device_node *node, 197*6058bb36SCarlo Caione struct device_node *parent) 198*6058bb36SCarlo Caione { 199*6058bb36SCarlo Caione return sunxi_sc_nmi_irq_init(node, &sun6i_reg_offs); 200*6058bb36SCarlo Caione } 201*6058bb36SCarlo Caione IRQCHIP_DECLARE(sun6i_sc_nmi, "allwinner,sun6i-a31-sc-nmi", sun6i_sc_nmi_irq_init); 202*6058bb36SCarlo Caione 203*6058bb36SCarlo Caione static int __init sun7i_sc_nmi_irq_init(struct device_node *node, 204*6058bb36SCarlo Caione struct device_node *parent) 205*6058bb36SCarlo Caione { 206*6058bb36SCarlo Caione return sunxi_sc_nmi_irq_init(node, &sun7i_reg_offs); 207*6058bb36SCarlo Caione } 208*6058bb36SCarlo Caione IRQCHIP_DECLARE(sun7i_sc_nmi, "allwinner,sun7i-a20-sc-nmi", sun7i_sc_nmi_irq_init); 209