13fed0955SLad Prabhakar // SPDX-License-Identifier: GPL-2.0 23fed0955SLad Prabhakar /* 33fed0955SLad Prabhakar * Renesas RZ/G2L IRQC Driver 43fed0955SLad Prabhakar * 53fed0955SLad Prabhakar * Copyright (C) 2022 Renesas Electronics Corporation. 63fed0955SLad Prabhakar * 73fed0955SLad Prabhakar * Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> 83fed0955SLad Prabhakar */ 93fed0955SLad Prabhakar 103fed0955SLad Prabhakar #include <linux/bitfield.h> 113fed0955SLad Prabhakar #include <linux/clk.h> 123fed0955SLad Prabhakar #include <linux/err.h> 133fed0955SLad Prabhakar #include <linux/io.h> 143fed0955SLad Prabhakar #include <linux/irqchip.h> 153fed0955SLad Prabhakar #include <linux/irqdomain.h> 163fed0955SLad Prabhakar #include <linux/of_address.h> 173fed0955SLad Prabhakar #include <linux/of_platform.h> 183fed0955SLad Prabhakar #include <linux/pm_runtime.h> 193fed0955SLad Prabhakar #include <linux/reset.h> 203fed0955SLad Prabhakar #include <linux/spinlock.h> 2174d2ef5fSClaudiu Beznea #include <linux/syscore_ops.h> 223fed0955SLad Prabhakar 233fed0955SLad Prabhakar #define IRQC_IRQ_START 1 243fed0955SLad Prabhakar #define IRQC_IRQ_COUNT 8 253fed0955SLad Prabhakar #define IRQC_TINT_START (IRQC_IRQ_START + IRQC_IRQ_COUNT) 263fed0955SLad Prabhakar #define IRQC_TINT_COUNT 32 273fed0955SLad Prabhakar #define IRQC_NUM_IRQ (IRQC_TINT_START + IRQC_TINT_COUNT) 283fed0955SLad Prabhakar 293fed0955SLad Prabhakar #define ISCR 0x10 303fed0955SLad Prabhakar #define IITSR 0x14 313fed0955SLad Prabhakar #define TSCR 0x20 322eca4731SClaudiu Beznea #define TITSR(n) (0x24 + (n) * 4) 333fed0955SLad Prabhakar #define TITSR0_MAX_INT 16 343fed0955SLad Prabhakar #define TITSEL_WIDTH 0x2 353fed0955SLad Prabhakar #define TSSR(n) (0x30 + ((n) * 4)) 363fed0955SLad Prabhakar #define TIEN BIT(7) 373fed0955SLad Prabhakar #define TSSEL_SHIFT(n) (8 * (n)) 383fed0955SLad Prabhakar #define TSSEL_MASK GENMASK(7, 0) 393fed0955SLad Prabhakar #define IRQ_MASK 0x3 403fed0955SLad Prabhakar 413fed0955SLad Prabhakar #define TSSR_OFFSET(n) ((n) % 4) 423fed0955SLad Prabhakar #define TSSR_INDEX(n) ((n) / 4) 433fed0955SLad Prabhakar 443fed0955SLad Prabhakar #define TITSR_TITSEL_EDGE_RISING 0 453fed0955SLad Prabhakar #define TITSR_TITSEL_EDGE_FALLING 1 463fed0955SLad Prabhakar #define TITSR_TITSEL_LEVEL_HIGH 2 473fed0955SLad Prabhakar #define TITSR_TITSEL_LEVEL_LOW 3 483fed0955SLad Prabhakar 493fed0955SLad Prabhakar #define IITSR_IITSEL(n, sense) ((sense) << ((n) * 2)) 503fed0955SLad Prabhakar #define IITSR_IITSEL_LEVEL_LOW 0 513fed0955SLad Prabhakar #define IITSR_IITSEL_EDGE_FALLING 1 523fed0955SLad Prabhakar #define IITSR_IITSEL_EDGE_RISING 2 533fed0955SLad Prabhakar #define IITSR_IITSEL_EDGE_BOTH 3 543fed0955SLad Prabhakar #define IITSR_IITSEL_MASK(n) IITSR_IITSEL((n), 3) 553fed0955SLad Prabhakar 563fed0955SLad Prabhakar #define TINT_EXTRACT_HWIRQ(x) FIELD_GET(GENMASK(15, 0), (x)) 573fed0955SLad Prabhakar #define TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x)) 583fed0955SLad Prabhakar 59b94f4553SClaudiu Beznea /** 6074d2ef5fSClaudiu Beznea * struct rzg2l_irqc_reg_cache - registers cache (necessary for suspend/resume) 6174d2ef5fSClaudiu Beznea * @iitsr: IITSR register 6274d2ef5fSClaudiu Beznea * @titsr: TITSR registers 6374d2ef5fSClaudiu Beznea */ 6474d2ef5fSClaudiu Beznea struct rzg2l_irqc_reg_cache { 6574d2ef5fSClaudiu Beznea u32 iitsr; 6674d2ef5fSClaudiu Beznea u32 titsr[2]; 6774d2ef5fSClaudiu Beznea }; 6874d2ef5fSClaudiu Beznea 6974d2ef5fSClaudiu Beznea /** 70b94f4553SClaudiu Beznea * struct rzg2l_irqc_priv - IRQ controller private data structure 71b94f4553SClaudiu Beznea * @base: Controller's base address 72b94f4553SClaudiu Beznea * @fwspec: IRQ firmware specific data 73b94f4553SClaudiu Beznea * @lock: Lock to serialize access to hardware registers 7474d2ef5fSClaudiu Beznea * @cache: Registers cache for suspend/resume 75b94f4553SClaudiu Beznea */ 7674d2ef5fSClaudiu Beznea static struct rzg2l_irqc_priv { 773fed0955SLad Prabhakar void __iomem *base; 783fed0955SLad Prabhakar struct irq_fwspec fwspec[IRQC_NUM_IRQ]; 793fed0955SLad Prabhakar raw_spinlock_t lock; 8074d2ef5fSClaudiu Beznea struct rzg2l_irqc_reg_cache cache; 8174d2ef5fSClaudiu Beznea } *rzg2l_irqc_data; 823fed0955SLad Prabhakar 833fed0955SLad Prabhakar static struct rzg2l_irqc_priv *irq_data_to_priv(struct irq_data *data) 843fed0955SLad Prabhakar { 853fed0955SLad Prabhakar return data->domain->host_data; 863fed0955SLad Prabhakar } 873fed0955SLad Prabhakar 883fed0955SLad Prabhakar static void rzg2l_irq_eoi(struct irq_data *d) 893fed0955SLad Prabhakar { 903fed0955SLad Prabhakar unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_IRQ_START; 913fed0955SLad Prabhakar struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); 923fed0955SLad Prabhakar u32 bit = BIT(hw_irq); 93ef88eefbSClaudiu Beznea u32 iitsr, iscr; 943fed0955SLad Prabhakar 95ef88eefbSClaudiu Beznea iscr = readl_relaxed(priv->base + ISCR); 96ef88eefbSClaudiu Beznea iitsr = readl_relaxed(priv->base + IITSR); 97ef88eefbSClaudiu Beznea 98ef88eefbSClaudiu Beznea /* 99ef88eefbSClaudiu Beznea * ISCR can only be cleared if the type is falling-edge, rising-edge or 100ef88eefbSClaudiu Beznea * falling/rising-edge. 101ef88eefbSClaudiu Beznea */ 102*9eec61dfSBiju Das if ((iscr & bit) && (iitsr & IITSR_IITSEL_MASK(hw_irq))) { 103ef88eefbSClaudiu Beznea writel_relaxed(iscr & ~bit, priv->base + ISCR); 104*9eec61dfSBiju Das /* 105*9eec61dfSBiju Das * Enforce that the posted write is flushed to prevent that the 106*9eec61dfSBiju Das * just handled interrupt is raised again. 107*9eec61dfSBiju Das */ 108*9eec61dfSBiju Das readl_relaxed(priv->base + ISCR); 109*9eec61dfSBiju Das } 1103fed0955SLad Prabhakar } 1113fed0955SLad Prabhakar 1123fed0955SLad Prabhakar static void rzg2l_tint_eoi(struct irq_data *d) 1133fed0955SLad Prabhakar { 1143fed0955SLad Prabhakar unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_TINT_START; 1153fed0955SLad Prabhakar struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); 1163fed0955SLad Prabhakar u32 bit = BIT(hw_irq); 1173fed0955SLad Prabhakar u32 reg; 1183fed0955SLad Prabhakar 1193fed0955SLad Prabhakar reg = readl_relaxed(priv->base + TSCR); 120*9eec61dfSBiju Das if (reg & bit) { 1213fed0955SLad Prabhakar writel_relaxed(reg & ~bit, priv->base + TSCR); 122*9eec61dfSBiju Das /* 123*9eec61dfSBiju Das * Enforce that the posted write is flushed to prevent that the 124*9eec61dfSBiju Das * just handled interrupt is raised again. 125*9eec61dfSBiju Das */ 126*9eec61dfSBiju Das readl_relaxed(priv->base + TSCR); 127*9eec61dfSBiju Das } 1283fed0955SLad Prabhakar } 1293fed0955SLad Prabhakar 1303fed0955SLad Prabhakar static void rzg2l_irqc_eoi(struct irq_data *d) 1313fed0955SLad Prabhakar { 1323fed0955SLad Prabhakar struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); 1333fed0955SLad Prabhakar unsigned int hw_irq = irqd_to_hwirq(d); 1343fed0955SLad Prabhakar 1353fed0955SLad Prabhakar raw_spin_lock(&priv->lock); 1363fed0955SLad Prabhakar if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT) 1373fed0955SLad Prabhakar rzg2l_irq_eoi(d); 1383fed0955SLad Prabhakar else if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) 1393fed0955SLad Prabhakar rzg2l_tint_eoi(d); 1403fed0955SLad Prabhakar raw_spin_unlock(&priv->lock); 1413fed0955SLad Prabhakar irq_chip_eoi_parent(d); 1423fed0955SLad Prabhakar } 1433fed0955SLad Prabhakar 1443fed0955SLad Prabhakar static void rzg2l_irqc_irq_disable(struct irq_data *d) 1453fed0955SLad Prabhakar { 1463fed0955SLad Prabhakar unsigned int hw_irq = irqd_to_hwirq(d); 1473fed0955SLad Prabhakar 1483fed0955SLad Prabhakar if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) { 1493fed0955SLad Prabhakar struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); 1503fed0955SLad Prabhakar u32 offset = hw_irq - IRQC_TINT_START; 1513fed0955SLad Prabhakar u32 tssr_offset = TSSR_OFFSET(offset); 1523fed0955SLad Prabhakar u8 tssr_index = TSSR_INDEX(offset); 1533fed0955SLad Prabhakar u32 reg; 1543fed0955SLad Prabhakar 1553fed0955SLad Prabhakar raw_spin_lock(&priv->lock); 1563fed0955SLad Prabhakar reg = readl_relaxed(priv->base + TSSR(tssr_index)); 1579b8df572SBiju Das reg &= ~(TSSEL_MASK << TSSEL_SHIFT(tssr_offset)); 1583fed0955SLad Prabhakar writel_relaxed(reg, priv->base + TSSR(tssr_index)); 1593fed0955SLad Prabhakar raw_spin_unlock(&priv->lock); 1603fed0955SLad Prabhakar } 1613fed0955SLad Prabhakar irq_chip_disable_parent(d); 1623fed0955SLad Prabhakar } 1633fed0955SLad Prabhakar 1643fed0955SLad Prabhakar static void rzg2l_irqc_irq_enable(struct irq_data *d) 1653fed0955SLad Prabhakar { 1663fed0955SLad Prabhakar unsigned int hw_irq = irqd_to_hwirq(d); 1673fed0955SLad Prabhakar 1683fed0955SLad Prabhakar if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) { 1698a4f44f3SGeert Uytterhoeven unsigned long tint = (uintptr_t)irq_data_get_irq_chip_data(d); 1703fed0955SLad Prabhakar struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); 1713fed0955SLad Prabhakar u32 offset = hw_irq - IRQC_TINT_START; 1723fed0955SLad Prabhakar u32 tssr_offset = TSSR_OFFSET(offset); 1733fed0955SLad Prabhakar u8 tssr_index = TSSR_INDEX(offset); 1743fed0955SLad Prabhakar u32 reg; 1753fed0955SLad Prabhakar 1763fed0955SLad Prabhakar raw_spin_lock(&priv->lock); 1773fed0955SLad Prabhakar reg = readl_relaxed(priv->base + TSSR(tssr_index)); 1783fed0955SLad Prabhakar reg |= (TIEN | tint) << TSSEL_SHIFT(tssr_offset); 1793fed0955SLad Prabhakar writel_relaxed(reg, priv->base + TSSR(tssr_index)); 1803fed0955SLad Prabhakar raw_spin_unlock(&priv->lock); 1813fed0955SLad Prabhakar } 1823fed0955SLad Prabhakar irq_chip_enable_parent(d); 1833fed0955SLad Prabhakar } 1843fed0955SLad Prabhakar 1853fed0955SLad Prabhakar static int rzg2l_irq_set_type(struct irq_data *d, unsigned int type) 1863fed0955SLad Prabhakar { 1873fed0955SLad Prabhakar unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_IRQ_START; 1883fed0955SLad Prabhakar struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); 1893fed0955SLad Prabhakar u16 sense, tmp; 1903fed0955SLad Prabhakar 1913fed0955SLad Prabhakar switch (type & IRQ_TYPE_SENSE_MASK) { 1923fed0955SLad Prabhakar case IRQ_TYPE_LEVEL_LOW: 1933fed0955SLad Prabhakar sense = IITSR_IITSEL_LEVEL_LOW; 1943fed0955SLad Prabhakar break; 1953fed0955SLad Prabhakar 1963fed0955SLad Prabhakar case IRQ_TYPE_EDGE_FALLING: 1973fed0955SLad Prabhakar sense = IITSR_IITSEL_EDGE_FALLING; 1983fed0955SLad Prabhakar break; 1993fed0955SLad Prabhakar 2003fed0955SLad Prabhakar case IRQ_TYPE_EDGE_RISING: 2013fed0955SLad Prabhakar sense = IITSR_IITSEL_EDGE_RISING; 2023fed0955SLad Prabhakar break; 2033fed0955SLad Prabhakar 2043fed0955SLad Prabhakar case IRQ_TYPE_EDGE_BOTH: 2053fed0955SLad Prabhakar sense = IITSR_IITSEL_EDGE_BOTH; 2063fed0955SLad Prabhakar break; 2073fed0955SLad Prabhakar 2083fed0955SLad Prabhakar default: 2093fed0955SLad Prabhakar return -EINVAL; 2103fed0955SLad Prabhakar } 2113fed0955SLad Prabhakar 2123fed0955SLad Prabhakar raw_spin_lock(&priv->lock); 2133fed0955SLad Prabhakar tmp = readl_relaxed(priv->base + IITSR); 2143fed0955SLad Prabhakar tmp &= ~IITSR_IITSEL_MASK(hw_irq); 2153fed0955SLad Prabhakar tmp |= IITSR_IITSEL(hw_irq, sense); 2163fed0955SLad Prabhakar writel_relaxed(tmp, priv->base + IITSR); 2173fed0955SLad Prabhakar raw_spin_unlock(&priv->lock); 2183fed0955SLad Prabhakar 2193fed0955SLad Prabhakar return 0; 2203fed0955SLad Prabhakar } 2213fed0955SLad Prabhakar 2223fed0955SLad Prabhakar static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type) 2233fed0955SLad Prabhakar { 2243fed0955SLad Prabhakar struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); 2253fed0955SLad Prabhakar unsigned int hwirq = irqd_to_hwirq(d); 2263fed0955SLad Prabhakar u32 titseln = hwirq - IRQC_TINT_START; 2272eca4731SClaudiu Beznea u8 index, sense; 2283fed0955SLad Prabhakar u32 reg; 2293fed0955SLad Prabhakar 2303fed0955SLad Prabhakar switch (type & IRQ_TYPE_SENSE_MASK) { 2313fed0955SLad Prabhakar case IRQ_TYPE_EDGE_RISING: 2323fed0955SLad Prabhakar sense = TITSR_TITSEL_EDGE_RISING; 2333fed0955SLad Prabhakar break; 2343fed0955SLad Prabhakar 2353fed0955SLad Prabhakar case IRQ_TYPE_EDGE_FALLING: 2363fed0955SLad Prabhakar sense = TITSR_TITSEL_EDGE_FALLING; 2373fed0955SLad Prabhakar break; 2383fed0955SLad Prabhakar 2393fed0955SLad Prabhakar default: 2403fed0955SLad Prabhakar return -EINVAL; 2413fed0955SLad Prabhakar } 2423fed0955SLad Prabhakar 2432eca4731SClaudiu Beznea index = 0; 2443fed0955SLad Prabhakar if (titseln >= TITSR0_MAX_INT) { 2453fed0955SLad Prabhakar titseln -= TITSR0_MAX_INT; 2462eca4731SClaudiu Beznea index = 1; 2473fed0955SLad Prabhakar } 2483fed0955SLad Prabhakar 2493fed0955SLad Prabhakar raw_spin_lock(&priv->lock); 2502eca4731SClaudiu Beznea reg = readl_relaxed(priv->base + TITSR(index)); 2513fed0955SLad Prabhakar reg &= ~(IRQ_MASK << (titseln * TITSEL_WIDTH)); 2523fed0955SLad Prabhakar reg |= sense << (titseln * TITSEL_WIDTH); 2532eca4731SClaudiu Beznea writel_relaxed(reg, priv->base + TITSR(index)); 2543fed0955SLad Prabhakar raw_spin_unlock(&priv->lock); 2553fed0955SLad Prabhakar 2563fed0955SLad Prabhakar return 0; 2573fed0955SLad Prabhakar } 2583fed0955SLad Prabhakar 2593fed0955SLad Prabhakar static int rzg2l_irqc_set_type(struct irq_data *d, unsigned int type) 2603fed0955SLad Prabhakar { 2613fed0955SLad Prabhakar unsigned int hw_irq = irqd_to_hwirq(d); 2623fed0955SLad Prabhakar int ret = -EINVAL; 2633fed0955SLad Prabhakar 2643fed0955SLad Prabhakar if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT) 2653fed0955SLad Prabhakar ret = rzg2l_irq_set_type(d, type); 2663fed0955SLad Prabhakar else if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) 2673fed0955SLad Prabhakar ret = rzg2l_tint_set_edge(d, type); 2683fed0955SLad Prabhakar if (ret) 2693fed0955SLad Prabhakar return ret; 2703fed0955SLad Prabhakar 2713fed0955SLad Prabhakar return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH); 2723fed0955SLad Prabhakar } 2733fed0955SLad Prabhakar 27474d2ef5fSClaudiu Beznea static int rzg2l_irqc_irq_suspend(void) 27574d2ef5fSClaudiu Beznea { 27674d2ef5fSClaudiu Beznea struct rzg2l_irqc_reg_cache *cache = &rzg2l_irqc_data->cache; 27774d2ef5fSClaudiu Beznea void __iomem *base = rzg2l_irqc_data->base; 27874d2ef5fSClaudiu Beznea 27974d2ef5fSClaudiu Beznea cache->iitsr = readl_relaxed(base + IITSR); 28074d2ef5fSClaudiu Beznea for (u8 i = 0; i < 2; i++) 28174d2ef5fSClaudiu Beznea cache->titsr[i] = readl_relaxed(base + TITSR(i)); 28274d2ef5fSClaudiu Beznea 28374d2ef5fSClaudiu Beznea return 0; 28474d2ef5fSClaudiu Beznea } 28574d2ef5fSClaudiu Beznea 28674d2ef5fSClaudiu Beznea static void rzg2l_irqc_irq_resume(void) 28774d2ef5fSClaudiu Beznea { 28874d2ef5fSClaudiu Beznea struct rzg2l_irqc_reg_cache *cache = &rzg2l_irqc_data->cache; 28974d2ef5fSClaudiu Beznea void __iomem *base = rzg2l_irqc_data->base; 29074d2ef5fSClaudiu Beznea 29174d2ef5fSClaudiu Beznea /* 29274d2ef5fSClaudiu Beznea * Restore only interrupt type. TSSRx will be restored at the 29374d2ef5fSClaudiu Beznea * request of pin controller to avoid spurious interrupts due 29474d2ef5fSClaudiu Beznea * to invalid PIN states. 29574d2ef5fSClaudiu Beznea */ 29674d2ef5fSClaudiu Beznea for (u8 i = 0; i < 2; i++) 29774d2ef5fSClaudiu Beznea writel_relaxed(cache->titsr[i], base + TITSR(i)); 29874d2ef5fSClaudiu Beznea writel_relaxed(cache->iitsr, base + IITSR); 29974d2ef5fSClaudiu Beznea } 30074d2ef5fSClaudiu Beznea 30174d2ef5fSClaudiu Beznea static struct syscore_ops rzg2l_irqc_syscore_ops = { 30274d2ef5fSClaudiu Beznea .suspend = rzg2l_irqc_irq_suspend, 30374d2ef5fSClaudiu Beznea .resume = rzg2l_irqc_irq_resume, 30474d2ef5fSClaudiu Beznea }; 30574d2ef5fSClaudiu Beznea 3063fed0955SLad Prabhakar static const struct irq_chip irqc_chip = { 3073fed0955SLad Prabhakar .name = "rzg2l-irqc", 3083fed0955SLad Prabhakar .irq_eoi = rzg2l_irqc_eoi, 3093fed0955SLad Prabhakar .irq_mask = irq_chip_mask_parent, 3103fed0955SLad Prabhakar .irq_unmask = irq_chip_unmask_parent, 3113fed0955SLad Prabhakar .irq_disable = rzg2l_irqc_irq_disable, 3123fed0955SLad Prabhakar .irq_enable = rzg2l_irqc_irq_enable, 3133fed0955SLad Prabhakar .irq_get_irqchip_state = irq_chip_get_parent_state, 3143fed0955SLad Prabhakar .irq_set_irqchip_state = irq_chip_set_parent_state, 3153fed0955SLad Prabhakar .irq_retrigger = irq_chip_retrigger_hierarchy, 3163fed0955SLad Prabhakar .irq_set_type = rzg2l_irqc_set_type, 317f881feb1SLad Prabhakar .irq_set_affinity = irq_chip_set_affinity_parent, 3183fed0955SLad Prabhakar .flags = IRQCHIP_MASK_ON_SUSPEND | 3193fed0955SLad Prabhakar IRQCHIP_SET_TYPE_MASKED | 3203fed0955SLad Prabhakar IRQCHIP_SKIP_SET_WAKE, 3213fed0955SLad Prabhakar }; 3223fed0955SLad Prabhakar 3233fed0955SLad Prabhakar static int rzg2l_irqc_alloc(struct irq_domain *domain, unsigned int virq, 3243fed0955SLad Prabhakar unsigned int nr_irqs, void *arg) 3253fed0955SLad Prabhakar { 3263fed0955SLad Prabhakar struct rzg2l_irqc_priv *priv = domain->host_data; 3273fed0955SLad Prabhakar unsigned long tint = 0; 3283fed0955SLad Prabhakar irq_hw_number_t hwirq; 3293fed0955SLad Prabhakar unsigned int type; 3303fed0955SLad Prabhakar int ret; 3313fed0955SLad Prabhakar 3323fed0955SLad Prabhakar ret = irq_domain_translate_twocell(domain, arg, &hwirq, &type); 3333fed0955SLad Prabhakar if (ret) 3343fed0955SLad Prabhakar return ret; 3353fed0955SLad Prabhakar 3363fed0955SLad Prabhakar /* 3373fed0955SLad Prabhakar * For TINT interrupts ie where pinctrl driver is child of irqc domain 3383fed0955SLad Prabhakar * the hwirq and TINT are encoded in fwspec->param[0]. 3393fed0955SLad Prabhakar * hwirq for TINT range from 9-40, hwirq is embedded 0-15 bits and TINT 3403fed0955SLad Prabhakar * from 16-31 bits. TINT from the pinctrl driver needs to be programmed 3413fed0955SLad Prabhakar * in IRQC registers to enable a given gpio pin as interrupt. 3423fed0955SLad Prabhakar */ 3433fed0955SLad Prabhakar if (hwirq > IRQC_IRQ_COUNT) { 3443fed0955SLad Prabhakar tint = TINT_EXTRACT_GPIOINT(hwirq); 3453fed0955SLad Prabhakar hwirq = TINT_EXTRACT_HWIRQ(hwirq); 3463fed0955SLad Prabhakar 3473fed0955SLad Prabhakar if (hwirq < IRQC_TINT_START) 3483fed0955SLad Prabhakar return -EINVAL; 3493fed0955SLad Prabhakar } 3503fed0955SLad Prabhakar 3513fed0955SLad Prabhakar if (hwirq > (IRQC_NUM_IRQ - 1)) 3523fed0955SLad Prabhakar return -EINVAL; 3533fed0955SLad Prabhakar 3543fed0955SLad Prabhakar ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &irqc_chip, 3553fed0955SLad Prabhakar (void *)(uintptr_t)tint); 3563fed0955SLad Prabhakar if (ret) 3573fed0955SLad Prabhakar return ret; 3583fed0955SLad Prabhakar 3593fed0955SLad Prabhakar return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &priv->fwspec[hwirq]); 3603fed0955SLad Prabhakar } 3613fed0955SLad Prabhakar 3623fed0955SLad Prabhakar static const struct irq_domain_ops rzg2l_irqc_domain_ops = { 3633fed0955SLad Prabhakar .alloc = rzg2l_irqc_alloc, 3643fed0955SLad Prabhakar .free = irq_domain_free_irqs_common, 3653fed0955SLad Prabhakar .translate = irq_domain_translate_twocell, 3663fed0955SLad Prabhakar }; 3673fed0955SLad Prabhakar 3683fed0955SLad Prabhakar static int rzg2l_irqc_parse_interrupts(struct rzg2l_irqc_priv *priv, 3693fed0955SLad Prabhakar struct device_node *np) 3703fed0955SLad Prabhakar { 3713fed0955SLad Prabhakar struct of_phandle_args map; 3723fed0955SLad Prabhakar unsigned int i; 3733fed0955SLad Prabhakar int ret; 3743fed0955SLad Prabhakar 3753fed0955SLad Prabhakar for (i = 0; i < IRQC_NUM_IRQ; i++) { 3763fed0955SLad Prabhakar ret = of_irq_parse_one(np, i, &map); 3773fed0955SLad Prabhakar if (ret) 3783fed0955SLad Prabhakar return ret; 3793fed0955SLad Prabhakar of_phandle_args_to_fwspec(np, map.args, map.args_count, 3803fed0955SLad Prabhakar &priv->fwspec[i]); 3813fed0955SLad Prabhakar } 3823fed0955SLad Prabhakar 3833fed0955SLad Prabhakar return 0; 3843fed0955SLad Prabhakar } 3853fed0955SLad Prabhakar 3863fed0955SLad Prabhakar static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent) 3873fed0955SLad Prabhakar { 3883fed0955SLad Prabhakar struct irq_domain *irq_domain, *parent_domain; 3893fed0955SLad Prabhakar struct platform_device *pdev; 3903fed0955SLad Prabhakar struct reset_control *resetn; 3913fed0955SLad Prabhakar int ret; 3923fed0955SLad Prabhakar 3933fed0955SLad Prabhakar pdev = of_find_device_by_node(node); 3943fed0955SLad Prabhakar if (!pdev) 3953fed0955SLad Prabhakar return -ENODEV; 3963fed0955SLad Prabhakar 3973fed0955SLad Prabhakar parent_domain = irq_find_host(parent); 3983fed0955SLad Prabhakar if (!parent_domain) { 3993fed0955SLad Prabhakar dev_err(&pdev->dev, "cannot find parent domain\n"); 4003fed0955SLad Prabhakar return -ENODEV; 4013fed0955SLad Prabhakar } 4023fed0955SLad Prabhakar 40374d2ef5fSClaudiu Beznea rzg2l_irqc_data = devm_kzalloc(&pdev->dev, sizeof(*rzg2l_irqc_data), GFP_KERNEL); 40474d2ef5fSClaudiu Beznea if (!rzg2l_irqc_data) 4053fed0955SLad Prabhakar return -ENOMEM; 4063fed0955SLad Prabhakar 40774d2ef5fSClaudiu Beznea rzg2l_irqc_data->base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL); 40874d2ef5fSClaudiu Beznea if (IS_ERR(rzg2l_irqc_data->base)) 40974d2ef5fSClaudiu Beznea return PTR_ERR(rzg2l_irqc_data->base); 4103fed0955SLad Prabhakar 41174d2ef5fSClaudiu Beznea ret = rzg2l_irqc_parse_interrupts(rzg2l_irqc_data, node); 4123fed0955SLad Prabhakar if (ret) { 4133fed0955SLad Prabhakar dev_err(&pdev->dev, "cannot parse interrupts: %d\n", ret); 4143fed0955SLad Prabhakar return ret; 4153fed0955SLad Prabhakar } 4163fed0955SLad Prabhakar 4173fed0955SLad Prabhakar resetn = devm_reset_control_get_exclusive(&pdev->dev, NULL); 4183fed0955SLad Prabhakar if (IS_ERR(resetn)) 4193fed0955SLad Prabhakar return PTR_ERR(resetn); 4203fed0955SLad Prabhakar 4213fed0955SLad Prabhakar ret = reset_control_deassert(resetn); 4223fed0955SLad Prabhakar if (ret) { 4233fed0955SLad Prabhakar dev_err(&pdev->dev, "failed to deassert resetn pin, %d\n", ret); 4243fed0955SLad Prabhakar return ret; 4253fed0955SLad Prabhakar } 4263fed0955SLad Prabhakar 4273fed0955SLad Prabhakar pm_runtime_enable(&pdev->dev); 4283fed0955SLad Prabhakar ret = pm_runtime_resume_and_get(&pdev->dev); 4293fed0955SLad Prabhakar if (ret < 0) { 4303fed0955SLad Prabhakar dev_err(&pdev->dev, "pm_runtime_resume_and_get failed: %d\n", ret); 4313fed0955SLad Prabhakar goto pm_disable; 4323fed0955SLad Prabhakar } 4333fed0955SLad Prabhakar 43474d2ef5fSClaudiu Beznea raw_spin_lock_init(&rzg2l_irqc_data->lock); 4353fed0955SLad Prabhakar 4363fed0955SLad Prabhakar irq_domain = irq_domain_add_hierarchy(parent_domain, 0, IRQC_NUM_IRQ, 4373fed0955SLad Prabhakar node, &rzg2l_irqc_domain_ops, 43874d2ef5fSClaudiu Beznea rzg2l_irqc_data); 4393fed0955SLad Prabhakar if (!irq_domain) { 4403fed0955SLad Prabhakar dev_err(&pdev->dev, "failed to add irq domain\n"); 4413fed0955SLad Prabhakar ret = -ENOMEM; 4423fed0955SLad Prabhakar goto pm_put; 4433fed0955SLad Prabhakar } 4443fed0955SLad Prabhakar 44574d2ef5fSClaudiu Beznea register_syscore_ops(&rzg2l_irqc_syscore_ops); 44674d2ef5fSClaudiu Beznea 4473fed0955SLad Prabhakar return 0; 4483fed0955SLad Prabhakar 4493fed0955SLad Prabhakar pm_put: 4503fed0955SLad Prabhakar pm_runtime_put(&pdev->dev); 4513fed0955SLad Prabhakar pm_disable: 4523fed0955SLad Prabhakar pm_runtime_disable(&pdev->dev); 4533fed0955SLad Prabhakar reset_control_assert(resetn); 4543fed0955SLad Prabhakar return ret; 4553fed0955SLad Prabhakar } 4563fed0955SLad Prabhakar 4573fed0955SLad Prabhakar IRQCHIP_PLATFORM_DRIVER_BEGIN(rzg2l_irqc) 4583fed0955SLad Prabhakar IRQCHIP_MATCH("renesas,rzg2l-irqc", rzg2l_irqc_init) 4593fed0955SLad Prabhakar IRQCHIP_PLATFORM_DRIVER_END(rzg2l_irqc) 4603fed0955SLad Prabhakar MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>"); 4613fed0955SLad Prabhakar MODULE_DESCRIPTION("Renesas RZ/G2L IRQC Driver"); 462