1 /* 2 * Marvell Armada 370 and Armada XP SoC IRQ handling 3 * 4 * Copyright (C) 2012 Marvell 5 * 6 * Lior Amsalem <alior@marvell.com> 7 * Gregory CLEMENT <gregory.clement@free-electrons.com> 8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 9 * Ben Dooks <ben.dooks@codethink.co.uk> 10 * 11 * This file is licensed under the terms of the GNU General Public 12 * License version 2. This program is licensed "as is" without any 13 * warranty of any kind, whether express or implied. 14 */ 15 16 #include <linux/kernel.h> 17 #include <linux/module.h> 18 #include <linux/init.h> 19 #include <linux/irq.h> 20 #include <linux/interrupt.h> 21 #include <linux/irqchip.h> 22 #include <linux/irqchip/chained_irq.h> 23 #include <linux/cpu.h> 24 #include <linux/io.h> 25 #include <linux/of_address.h> 26 #include <linux/of_irq.h> 27 #include <linux/of_pci.h> 28 #include <linux/irqdomain.h> 29 #include <linux/slab.h> 30 #include <linux/syscore_ops.h> 31 #include <linux/msi.h> 32 #include <asm/mach/arch.h> 33 #include <asm/exception.h> 34 #include <asm/smp_plat.h> 35 #include <asm/mach/irq.h> 36 37 /* Interrupt Controller Registers Map */ 38 #define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48) 39 #define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C) 40 #define ARMADA_370_XP_INT_FABRIC_MASK_OFFS (0x54) 41 #define ARMADA_370_XP_INT_CAUSE_PERF(cpu) (1 << cpu) 42 43 #define ARMADA_370_XP_INT_CONTROL (0x00) 44 #define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30) 45 #define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS (0x34) 46 #define ARMADA_370_XP_INT_SOURCE_CTL(irq) (0x100 + irq*4) 47 #define ARMADA_370_XP_INT_SOURCE_CPU_MASK 0xF 48 #define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid) ((BIT(0) | BIT(8)) << cpuid) 49 50 #define ARMADA_370_XP_CPU_INTACK_OFFS (0x44) 51 #define ARMADA_375_PPI_CAUSE (0x10) 52 53 #define ARMADA_370_XP_SW_TRIG_INT_OFFS (0x4) 54 #define ARMADA_370_XP_IN_DRBEL_MSK_OFFS (0xc) 55 #define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS (0x8) 56 57 #define ARMADA_370_XP_MAX_PER_CPU_IRQS (28) 58 59 #define ARMADA_370_XP_TIMER0_PER_CPU_IRQ (5) 60 #define ARMADA_370_XP_FABRIC_IRQ (3) 61 62 #define IPI_DOORBELL_START (0) 63 #define IPI_DOORBELL_END (8) 64 #define IPI_DOORBELL_MASK 0xFF 65 #define PCI_MSI_DOORBELL_START (16) 66 #define PCI_MSI_DOORBELL_NR (16) 67 #define PCI_MSI_DOORBELL_END (32) 68 #define PCI_MSI_DOORBELL_MASK 0xFFFF0000 69 70 static void __iomem *per_cpu_int_base; 71 static void __iomem *main_int_base; 72 static struct irq_domain *armada_370_xp_mpic_domain; 73 static u32 doorbell_mask_reg; 74 static int parent_irq; 75 #ifdef CONFIG_PCI_MSI 76 static struct irq_domain *armada_370_xp_msi_domain; 77 static DECLARE_BITMAP(msi_used, PCI_MSI_DOORBELL_NR); 78 static DEFINE_MUTEX(msi_used_lock); 79 static phys_addr_t msi_doorbell_addr; 80 #endif 81 82 static inline bool is_percpu_irq(irq_hw_number_t irq) 83 { 84 switch (irq) { 85 case ARMADA_370_XP_TIMER0_PER_CPU_IRQ: 86 case ARMADA_370_XP_FABRIC_IRQ: 87 return true; 88 default: 89 return false; 90 } 91 } 92 93 /* 94 * In SMP mode: 95 * For shared global interrupts, mask/unmask global enable bit 96 * For CPU interrupts, mask/unmask the calling CPU's bit 97 */ 98 static void armada_370_xp_irq_mask(struct irq_data *d) 99 { 100 irq_hw_number_t hwirq = irqd_to_hwirq(d); 101 102 if (!is_percpu_irq(hwirq)) 103 writel(hwirq, main_int_base + 104 ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS); 105 else 106 writel(hwirq, per_cpu_int_base + 107 ARMADA_370_XP_INT_SET_MASK_OFFS); 108 } 109 110 static void armada_370_xp_irq_unmask(struct irq_data *d) 111 { 112 irq_hw_number_t hwirq = irqd_to_hwirq(d); 113 114 if (!is_percpu_irq(hwirq)) 115 writel(hwirq, main_int_base + 116 ARMADA_370_XP_INT_SET_ENABLE_OFFS); 117 else 118 writel(hwirq, per_cpu_int_base + 119 ARMADA_370_XP_INT_CLEAR_MASK_OFFS); 120 } 121 122 #ifdef CONFIG_PCI_MSI 123 124 static int armada_370_xp_alloc_msi(void) 125 { 126 int hwirq; 127 128 mutex_lock(&msi_used_lock); 129 hwirq = find_first_zero_bit(&msi_used, PCI_MSI_DOORBELL_NR); 130 if (hwirq >= PCI_MSI_DOORBELL_NR) 131 hwirq = -ENOSPC; 132 else 133 set_bit(hwirq, msi_used); 134 mutex_unlock(&msi_used_lock); 135 136 return hwirq; 137 } 138 139 static void armada_370_xp_free_msi(int hwirq) 140 { 141 mutex_lock(&msi_used_lock); 142 if (!test_bit(hwirq, msi_used)) 143 pr_err("trying to free unused MSI#%d\n", hwirq); 144 else 145 clear_bit(hwirq, msi_used); 146 mutex_unlock(&msi_used_lock); 147 } 148 149 static int armada_370_xp_setup_msi_irq(struct msi_controller *chip, 150 struct pci_dev *pdev, 151 struct msi_desc *desc) 152 { 153 struct msi_msg msg; 154 int virq, hwirq; 155 156 /* We support MSI, but not MSI-X */ 157 if (desc->msi_attrib.is_msix) 158 return -EINVAL; 159 160 hwirq = armada_370_xp_alloc_msi(); 161 if (hwirq < 0) 162 return hwirq; 163 164 virq = irq_create_mapping(armada_370_xp_msi_domain, hwirq); 165 if (!virq) { 166 armada_370_xp_free_msi(hwirq); 167 return -EINVAL; 168 } 169 170 irq_set_msi_desc(virq, desc); 171 172 msg.address_lo = msi_doorbell_addr; 173 msg.address_hi = 0; 174 msg.data = 0xf00 | (hwirq + 16); 175 176 pci_write_msi_msg(virq, &msg); 177 return 0; 178 } 179 180 static void armada_370_xp_teardown_msi_irq(struct msi_controller *chip, 181 unsigned int irq) 182 { 183 struct irq_data *d = irq_get_irq_data(irq); 184 unsigned long hwirq = d->hwirq; 185 186 irq_dispose_mapping(irq); 187 armada_370_xp_free_msi(hwirq); 188 } 189 190 static struct irq_chip armada_370_xp_msi_irq_chip = { 191 .name = "armada_370_xp_msi_irq", 192 .irq_enable = pci_msi_unmask_irq, 193 .irq_disable = pci_msi_mask_irq, 194 .irq_mask = pci_msi_mask_irq, 195 .irq_unmask = pci_msi_unmask_irq, 196 }; 197 198 static int armada_370_xp_msi_map(struct irq_domain *domain, unsigned int virq, 199 irq_hw_number_t hw) 200 { 201 irq_set_chip_and_handler(virq, &armada_370_xp_msi_irq_chip, 202 handle_simple_irq); 203 set_irq_flags(virq, IRQF_VALID); 204 205 return 0; 206 } 207 208 static const struct irq_domain_ops armada_370_xp_msi_irq_ops = { 209 .map = armada_370_xp_msi_map, 210 }; 211 212 static int armada_370_xp_msi_init(struct device_node *node, 213 phys_addr_t main_int_phys_base) 214 { 215 struct msi_controller *msi_chip; 216 u32 reg; 217 int ret; 218 219 msi_doorbell_addr = main_int_phys_base + 220 ARMADA_370_XP_SW_TRIG_INT_OFFS; 221 222 msi_chip = kzalloc(sizeof(*msi_chip), GFP_KERNEL); 223 if (!msi_chip) 224 return -ENOMEM; 225 226 msi_chip->setup_irq = armada_370_xp_setup_msi_irq; 227 msi_chip->teardown_irq = armada_370_xp_teardown_msi_irq; 228 msi_chip->of_node = node; 229 230 armada_370_xp_msi_domain = 231 irq_domain_add_linear(NULL, PCI_MSI_DOORBELL_NR, 232 &armada_370_xp_msi_irq_ops, 233 NULL); 234 if (!armada_370_xp_msi_domain) { 235 kfree(msi_chip); 236 return -ENOMEM; 237 } 238 239 ret = of_pci_msi_chip_add(msi_chip); 240 if (ret < 0) { 241 irq_domain_remove(armada_370_xp_msi_domain); 242 kfree(msi_chip); 243 return ret; 244 } 245 246 reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS) 247 | PCI_MSI_DOORBELL_MASK; 248 249 writel(reg, per_cpu_int_base + 250 ARMADA_370_XP_IN_DRBEL_MSK_OFFS); 251 252 /* Unmask IPI interrupt */ 253 writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); 254 255 return 0; 256 } 257 #else 258 static inline int armada_370_xp_msi_init(struct device_node *node, 259 phys_addr_t main_int_phys_base) 260 { 261 return 0; 262 } 263 #endif 264 265 #ifdef CONFIG_SMP 266 static DEFINE_RAW_SPINLOCK(irq_controller_lock); 267 268 static int armada_xp_set_affinity(struct irq_data *d, 269 const struct cpumask *mask_val, bool force) 270 { 271 irq_hw_number_t hwirq = irqd_to_hwirq(d); 272 unsigned long reg, mask; 273 int cpu; 274 275 /* Select a single core from the affinity mask which is online */ 276 cpu = cpumask_any_and(mask_val, cpu_online_mask); 277 mask = 1UL << cpu_logical_map(cpu); 278 279 raw_spin_lock(&irq_controller_lock); 280 reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq)); 281 reg = (reg & (~ARMADA_370_XP_INT_SOURCE_CPU_MASK)) | mask; 282 writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq)); 283 raw_spin_unlock(&irq_controller_lock); 284 285 return IRQ_SET_MASK_OK; 286 } 287 #endif 288 289 static struct irq_chip armada_370_xp_irq_chip = { 290 .name = "armada_370_xp_irq", 291 .irq_mask = armada_370_xp_irq_mask, 292 .irq_mask_ack = armada_370_xp_irq_mask, 293 .irq_unmask = armada_370_xp_irq_unmask, 294 #ifdef CONFIG_SMP 295 .irq_set_affinity = armada_xp_set_affinity, 296 #endif 297 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND, 298 }; 299 300 static int armada_370_xp_mpic_irq_map(struct irq_domain *h, 301 unsigned int virq, irq_hw_number_t hw) 302 { 303 armada_370_xp_irq_mask(irq_get_irq_data(virq)); 304 if (!is_percpu_irq(hw)) 305 writel(hw, per_cpu_int_base + 306 ARMADA_370_XP_INT_CLEAR_MASK_OFFS); 307 else 308 writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS); 309 irq_set_status_flags(virq, IRQ_LEVEL); 310 311 if (is_percpu_irq(hw)) { 312 irq_set_percpu_devid(virq); 313 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip, 314 handle_percpu_devid_irq); 315 316 } else { 317 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip, 318 handle_level_irq); 319 } 320 set_irq_flags(virq, IRQF_VALID | IRQF_PROBE); 321 322 return 0; 323 } 324 325 static void armada_xp_mpic_smp_cpu_init(void) 326 { 327 u32 control; 328 int nr_irqs, i; 329 330 control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL); 331 nr_irqs = (control >> 2) & 0x3ff; 332 333 for (i = 0; i < nr_irqs; i++) 334 writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS); 335 336 /* Clear pending IPIs */ 337 writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS); 338 339 /* Enable first 8 IPIs */ 340 writel(IPI_DOORBELL_MASK, per_cpu_int_base + 341 ARMADA_370_XP_IN_DRBEL_MSK_OFFS); 342 343 /* Unmask IPI interrupt */ 344 writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); 345 } 346 347 static void armada_xp_mpic_perf_init(void) 348 { 349 unsigned long cpuid = cpu_logical_map(smp_processor_id()); 350 351 /* Enable Performance Counter Overflow interrupts */ 352 writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid), 353 per_cpu_int_base + ARMADA_370_XP_INT_FABRIC_MASK_OFFS); 354 } 355 356 #ifdef CONFIG_SMP 357 static void armada_mpic_send_doorbell(const struct cpumask *mask, 358 unsigned int irq) 359 { 360 int cpu; 361 unsigned long map = 0; 362 363 /* Convert our logical CPU mask into a physical one. */ 364 for_each_cpu(cpu, mask) 365 map |= 1 << cpu_logical_map(cpu); 366 367 /* 368 * Ensure that stores to Normal memory are visible to the 369 * other CPUs before issuing the IPI. 370 */ 371 dsb(); 372 373 /* submit softirq */ 374 writel((map << 8) | irq, main_int_base + 375 ARMADA_370_XP_SW_TRIG_INT_OFFS); 376 } 377 378 static int armada_xp_mpic_secondary_init(struct notifier_block *nfb, 379 unsigned long action, void *hcpu) 380 { 381 if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) { 382 armada_xp_mpic_perf_init(); 383 armada_xp_mpic_smp_cpu_init(); 384 } 385 386 return NOTIFY_OK; 387 } 388 389 static struct notifier_block armada_370_xp_mpic_cpu_notifier = { 390 .notifier_call = armada_xp_mpic_secondary_init, 391 .priority = 100, 392 }; 393 394 static int mpic_cascaded_secondary_init(struct notifier_block *nfb, 395 unsigned long action, void *hcpu) 396 { 397 if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) { 398 armada_xp_mpic_perf_init(); 399 enable_percpu_irq(parent_irq, IRQ_TYPE_NONE); 400 } 401 402 return NOTIFY_OK; 403 } 404 405 static struct notifier_block mpic_cascaded_cpu_notifier = { 406 .notifier_call = mpic_cascaded_secondary_init, 407 .priority = 100, 408 }; 409 #endif /* CONFIG_SMP */ 410 411 static const struct irq_domain_ops armada_370_xp_mpic_irq_ops = { 412 .map = armada_370_xp_mpic_irq_map, 413 .xlate = irq_domain_xlate_onecell, 414 }; 415 416 #ifdef CONFIG_PCI_MSI 417 static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained) 418 { 419 u32 msimask, msinr; 420 421 msimask = readl_relaxed(per_cpu_int_base + 422 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS) 423 & PCI_MSI_DOORBELL_MASK; 424 425 writel(~msimask, per_cpu_int_base + 426 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS); 427 428 for (msinr = PCI_MSI_DOORBELL_START; 429 msinr < PCI_MSI_DOORBELL_END; msinr++) { 430 int irq; 431 432 if (!(msimask & BIT(msinr))) 433 continue; 434 435 if (is_chained) { 436 irq = irq_find_mapping(armada_370_xp_msi_domain, 437 msinr - 16); 438 generic_handle_irq(irq); 439 } else { 440 irq = msinr - 16; 441 handle_domain_irq(armada_370_xp_msi_domain, 442 irq, regs); 443 } 444 } 445 } 446 #else 447 static void armada_370_xp_handle_msi_irq(struct pt_regs *r, bool b) {} 448 #endif 449 450 static void armada_370_xp_mpic_handle_cascade_irq(unsigned int irq, 451 struct irq_desc *desc) 452 { 453 struct irq_chip *chip = irq_desc_get_chip(desc); 454 unsigned long irqmap, irqn, irqsrc, cpuid; 455 unsigned int cascade_irq; 456 457 chained_irq_enter(chip, desc); 458 459 irqmap = readl_relaxed(per_cpu_int_base + ARMADA_375_PPI_CAUSE); 460 cpuid = cpu_logical_map(smp_processor_id()); 461 462 for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) { 463 irqsrc = readl_relaxed(main_int_base + 464 ARMADA_370_XP_INT_SOURCE_CTL(irqn)); 465 466 /* Check if the interrupt is not masked on current CPU. 467 * Test IRQ (0-1) and FIQ (8-9) mask bits. 468 */ 469 if (!(irqsrc & ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid))) 470 continue; 471 472 if (irqn == 1) { 473 armada_370_xp_handle_msi_irq(NULL, true); 474 continue; 475 } 476 477 cascade_irq = irq_find_mapping(armada_370_xp_mpic_domain, irqn); 478 generic_handle_irq(cascade_irq); 479 } 480 481 chained_irq_exit(chip, desc); 482 } 483 484 static void __exception_irq_entry 485 armada_370_xp_handle_irq(struct pt_regs *regs) 486 { 487 u32 irqstat, irqnr; 488 489 do { 490 irqstat = readl_relaxed(per_cpu_int_base + 491 ARMADA_370_XP_CPU_INTACK_OFFS); 492 irqnr = irqstat & 0x3FF; 493 494 if (irqnr > 1022) 495 break; 496 497 if (irqnr > 1) { 498 handle_domain_irq(armada_370_xp_mpic_domain, 499 irqnr, regs); 500 continue; 501 } 502 503 /* MSI handling */ 504 if (irqnr == 1) 505 armada_370_xp_handle_msi_irq(regs, false); 506 507 #ifdef CONFIG_SMP 508 /* IPI Handling */ 509 if (irqnr == 0) { 510 u32 ipimask, ipinr; 511 512 ipimask = readl_relaxed(per_cpu_int_base + 513 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS) 514 & IPI_DOORBELL_MASK; 515 516 writel(~ipimask, per_cpu_int_base + 517 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS); 518 519 /* Handle all pending doorbells */ 520 for (ipinr = IPI_DOORBELL_START; 521 ipinr < IPI_DOORBELL_END; ipinr++) { 522 if (ipimask & (0x1 << ipinr)) 523 handle_IPI(ipinr, regs); 524 } 525 continue; 526 } 527 #endif 528 529 } while (1); 530 } 531 532 static int armada_370_xp_mpic_suspend(void) 533 { 534 doorbell_mask_reg = readl(per_cpu_int_base + 535 ARMADA_370_XP_IN_DRBEL_MSK_OFFS); 536 return 0; 537 } 538 539 static void armada_370_xp_mpic_resume(void) 540 { 541 int nirqs; 542 irq_hw_number_t irq; 543 544 /* Re-enable interrupts */ 545 nirqs = (readl(main_int_base + ARMADA_370_XP_INT_CONTROL) >> 2) & 0x3ff; 546 for (irq = 0; irq < nirqs; irq++) { 547 struct irq_data *data; 548 int virq; 549 550 virq = irq_linear_revmap(armada_370_xp_mpic_domain, irq); 551 if (virq == 0) 552 continue; 553 554 if (irq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ) 555 writel(irq, per_cpu_int_base + 556 ARMADA_370_XP_INT_CLEAR_MASK_OFFS); 557 else 558 writel(irq, main_int_base + 559 ARMADA_370_XP_INT_SET_ENABLE_OFFS); 560 561 data = irq_get_irq_data(virq); 562 if (!irqd_irq_disabled(data)) 563 armada_370_xp_irq_unmask(data); 564 } 565 566 /* Reconfigure doorbells for IPIs and MSIs */ 567 writel(doorbell_mask_reg, 568 per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS); 569 if (doorbell_mask_reg & IPI_DOORBELL_MASK) 570 writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); 571 if (doorbell_mask_reg & PCI_MSI_DOORBELL_MASK) 572 writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); 573 } 574 575 struct syscore_ops armada_370_xp_mpic_syscore_ops = { 576 .suspend = armada_370_xp_mpic_suspend, 577 .resume = armada_370_xp_mpic_resume, 578 }; 579 580 static int __init armada_370_xp_mpic_of_init(struct device_node *node, 581 struct device_node *parent) 582 { 583 struct resource main_int_res, per_cpu_int_res; 584 int nr_irqs, i; 585 u32 control; 586 587 BUG_ON(of_address_to_resource(node, 0, &main_int_res)); 588 BUG_ON(of_address_to_resource(node, 1, &per_cpu_int_res)); 589 590 BUG_ON(!request_mem_region(main_int_res.start, 591 resource_size(&main_int_res), 592 node->full_name)); 593 BUG_ON(!request_mem_region(per_cpu_int_res.start, 594 resource_size(&per_cpu_int_res), 595 node->full_name)); 596 597 main_int_base = ioremap(main_int_res.start, 598 resource_size(&main_int_res)); 599 BUG_ON(!main_int_base); 600 601 per_cpu_int_base = ioremap(per_cpu_int_res.start, 602 resource_size(&per_cpu_int_res)); 603 BUG_ON(!per_cpu_int_base); 604 605 control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL); 606 nr_irqs = (control >> 2) & 0x3ff; 607 608 for (i = 0; i < nr_irqs; i++) 609 writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS); 610 611 armada_370_xp_mpic_domain = 612 irq_domain_add_linear(node, nr_irqs, 613 &armada_370_xp_mpic_irq_ops, NULL); 614 615 BUG_ON(!armada_370_xp_mpic_domain); 616 617 /* Setup for the boot CPU */ 618 armada_xp_mpic_perf_init(); 619 armada_xp_mpic_smp_cpu_init(); 620 621 armada_370_xp_msi_init(node, main_int_res.start); 622 623 parent_irq = irq_of_parse_and_map(node, 0); 624 if (parent_irq <= 0) { 625 irq_set_default_host(armada_370_xp_mpic_domain); 626 set_handle_irq(armada_370_xp_handle_irq); 627 #ifdef CONFIG_SMP 628 set_smp_cross_call(armada_mpic_send_doorbell); 629 register_cpu_notifier(&armada_370_xp_mpic_cpu_notifier); 630 #endif 631 } else { 632 #ifdef CONFIG_SMP 633 register_cpu_notifier(&mpic_cascaded_cpu_notifier); 634 #endif 635 irq_set_chained_handler(parent_irq, 636 armada_370_xp_mpic_handle_cascade_irq); 637 } 638 639 register_syscore_ops(&armada_370_xp_mpic_syscore_ops); 640 641 return 0; 642 } 643 644 IRQCHIP_DECLARE(armada_370_xp_mpic, "marvell,mpic", armada_370_xp_mpic_of_init); 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