1config IRQCHIP 2 def_bool y 3 depends on OF_IRQ 4 5config ARM_GIC 6 bool 7 select IRQ_DOMAIN 8 select MULTI_IRQ_HANDLER 9 10config GIC_NON_BANKED 11 bool 12 13config ARM_GIC_V3 14 bool 15 select IRQ_DOMAIN 16 select MULTI_IRQ_HANDLER 17 18config ARM_NVIC 19 bool 20 select IRQ_DOMAIN 21 select GENERIC_IRQ_CHIP 22 23config ARM_VIC 24 bool 25 select IRQ_DOMAIN 26 select MULTI_IRQ_HANDLER 27 28config ARM_VIC_NR 29 int 30 default 4 if ARCH_S5PV210 31 default 2 32 depends on ARM_VIC 33 help 34 The maximum number of VICs available in the system, for 35 power management. 36 37config ATMEL_AIC_IRQ 38 bool 39 select GENERIC_IRQ_CHIP 40 select IRQ_DOMAIN 41 select MULTI_IRQ_HANDLER 42 select SPARSE_IRQ 43 44config ATMEL_AIC5_IRQ 45 bool 46 select GENERIC_IRQ_CHIP 47 select IRQ_DOMAIN 48 select MULTI_IRQ_HANDLER 49 select SPARSE_IRQ 50 51config BCM7120_L2_IRQ 52 bool 53 select GENERIC_IRQ_CHIP 54 select IRQ_DOMAIN 55 56config BRCMSTB_L2_IRQ 57 bool 58 select GENERIC_IRQ_CHIP 59 select IRQ_DOMAIN 60 61config DW_APB_ICTL 62 bool 63 select GENERIC_IRQ_CHIP 64 select IRQ_DOMAIN 65 66config IMGPDC_IRQ 67 bool 68 select GENERIC_IRQ_CHIP 69 select IRQ_DOMAIN 70 71config CLPS711X_IRQCHIP 72 bool 73 depends on ARCH_CLPS711X 74 select IRQ_DOMAIN 75 select MULTI_IRQ_HANDLER 76 select SPARSE_IRQ 77 default y 78 79config OR1K_PIC 80 bool 81 select IRQ_DOMAIN 82 83config OMAP_IRQCHIP 84 bool 85 select GENERIC_IRQ_CHIP 86 select IRQ_DOMAIN 87 88config ORION_IRQCHIP 89 bool 90 select IRQ_DOMAIN 91 select MULTI_IRQ_HANDLER 92 93config RENESAS_INTC_IRQPIN 94 bool 95 select IRQ_DOMAIN 96 97config RENESAS_IRQC 98 bool 99 select IRQ_DOMAIN 100 101config TB10X_IRQC 102 bool 103 select IRQ_DOMAIN 104 select GENERIC_IRQ_CHIP 105 106config VERSATILE_FPGA_IRQ 107 bool 108 select IRQ_DOMAIN 109 110config VERSATILE_FPGA_IRQ_NR 111 int 112 default 4 113 depends on VERSATILE_FPGA_IRQ 114 115config XTENSA_MX 116 bool 117 select IRQ_DOMAIN 118 119config IRQ_CROSSBAR 120 bool 121 help 122 Support for a CROSSBAR ip that precedes the main interrupt controller. 123 The primary irqchip invokes the crossbar's callback which inturn allocates 124 a free irq and configures the IP. Thus the peripheral interrupts are 125 routed to one of the free irqchip interrupt lines. 126 127config KEYSTONE_IRQ 128 tristate "Keystone 2 IRQ controller IP" 129 depends on ARCH_KEYSTONE 130 help 131 Support for Texas Instruments Keystone 2 IRQ controller IP which 132 is part of the Keystone 2 IPC mechanism 133 134config MIPS_GIC 135 bool 136 select MIPS_CM 137