11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 20df4fabeSYong Wu /* 30df4fabeSYong Wu * Copyright (c) 2015-2016 MediaTek Inc. 40df4fabeSYong Wu * Author: Yong Wu <yong.wu@mediatek.com> 50df4fabeSYong Wu */ 6946e719cSChengci.Xu #include <linux/arm-smccc.h> 7ef0f0986SYong Wu #include <linux/bitfield.h> 80df4fabeSYong Wu #include <linux/bug.h> 90df4fabeSYong Wu #include <linux/clk.h> 100df4fabeSYong Wu #include <linux/component.h> 110df4fabeSYong Wu #include <linux/device.h> 120df4fabeSYong Wu #include <linux/err.h> 130df4fabeSYong Wu #include <linux/interrupt.h> 140df4fabeSYong Wu #include <linux/io.h> 150df4fabeSYong Wu #include <linux/iommu.h> 160df4fabeSYong Wu #include <linux/iopoll.h> 176a513de3SYong Wu #include <linux/io-pgtable.h> 180df4fabeSYong Wu #include <linux/list.h> 19c2c59456SMiles Chen #include <linux/mfd/syscon.h> 2018d8c74eSYong Wu #include <linux/module.h> 210df4fabeSYong Wu #include <linux/of_address.h> 220df4fabeSYong Wu #include <linux/of_irq.h> 230df4fabeSYong Wu #include <linux/of_platform.h> 24e7629070SYong Wu #include <linux/pci.h> 250df4fabeSYong Wu #include <linux/platform_device.h> 26baf94e6eSYong Wu #include <linux/pm_runtime.h> 27c2c59456SMiles Chen #include <linux/regmap.h> 280df4fabeSYong Wu #include <linux/slab.h> 290df4fabeSYong Wu #include <linux/spinlock.h> 30c2c59456SMiles Chen #include <linux/soc/mediatek/infracfg.h> 31946e719cSChengci.Xu #include <linux/soc/mediatek/mtk_sip_svc.h> 320df4fabeSYong Wu #include <asm/barrier.h> 330df4fabeSYong Wu #include <soc/mediatek/smi.h> 340df4fabeSYong Wu 356a513de3SYong Wu #include <dt-bindings/memory/mtk-memory-port.h> 360df4fabeSYong Wu 370df4fabeSYong Wu #define REG_MMU_PT_BASE_ADDR 0x000 380df4fabeSYong Wu 390df4fabeSYong Wu #define REG_MMU_INVALIDATE 0x020 400df4fabeSYong Wu #define F_ALL_INVLD 0x2 410df4fabeSYong Wu #define F_MMU_INV_RANGE 0x1 420df4fabeSYong Wu 430df4fabeSYong Wu #define REG_MMU_INVLD_START_A 0x024 440df4fabeSYong Wu #define REG_MMU_INVLD_END_A 0x028 450df4fabeSYong Wu 46068c86e9SChao Hao #define REG_MMU_INV_SEL_GEN2 0x02c 47b053bc71SChao Hao #define REG_MMU_INV_SEL_GEN1 0x038 480df4fabeSYong Wu #define F_INVLD_EN0 BIT(0) 490df4fabeSYong Wu #define F_INVLD_EN1 BIT(1) 500df4fabeSYong Wu 5175eed350SChao Hao #define REG_MMU_MISC_CTRL 0x048 524bb2bf4cSChao Hao #define F_MMU_IN_ORDER_WR_EN_MASK (BIT(1) | BIT(17)) 534bb2bf4cSChao Hao #define F_MMU_STANDARD_AXI_MODE_MASK (BIT(3) | BIT(19)) 544bb2bf4cSChao Hao 550df4fabeSYong Wu #define REG_MMU_DCM_DIS 0x050 569a87005eSYong Wu #define F_MMU_DCM BIT(8) 579a87005eSYong Wu 5835c1b48dSChao Hao #define REG_MMU_WR_LEN_CTRL 0x054 5935c1b48dSChao Hao #define F_MMU_WR_THROT_DIS_MASK (BIT(5) | BIT(21)) 600df4fabeSYong Wu 610df4fabeSYong Wu #define REG_MMU_CTRL_REG 0x110 62acb3c92aSYong Wu #define F_MMU_TF_PROT_TO_PROGRAM_ADDR (2 << 4) 630df4fabeSYong Wu #define F_MMU_PREFETCH_RT_REPLACE_MOD BIT(4) 64acb3c92aSYong Wu #define F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173 (2 << 5) 650df4fabeSYong Wu 660df4fabeSYong Wu #define REG_MMU_IVRP_PADDR 0x114 6770ca608bSYong Wu 6830e2fccfSYong Wu #define REG_MMU_VLD_PA_RNG 0x118 6930e2fccfSYong Wu #define F_MMU_VLD_PA_RNG(EA, SA) (((EA) << 8) | (SA)) 700df4fabeSYong Wu 710df4fabeSYong Wu #define REG_MMU_INT_CONTROL0 0x120 720df4fabeSYong Wu #define F_L2_MULIT_HIT_EN BIT(0) 730df4fabeSYong Wu #define F_TABLE_WALK_FAULT_INT_EN BIT(1) 740df4fabeSYong Wu #define F_PREETCH_FIFO_OVERFLOW_INT_EN BIT(2) 750df4fabeSYong Wu #define F_MISS_FIFO_OVERFLOW_INT_EN BIT(3) 760df4fabeSYong Wu #define F_PREFETCH_FIFO_ERR_INT_EN BIT(5) 770df4fabeSYong Wu #define F_MISS_FIFO_ERR_INT_EN BIT(6) 780df4fabeSYong Wu #define F_INT_CLR_BIT BIT(12) 790df4fabeSYong Wu 800df4fabeSYong Wu #define REG_MMU_INT_MAIN_CONTROL 0x124 8115a01f4cSYong Wu /* mmu0 | mmu1 */ 8215a01f4cSYong Wu #define F_INT_TRANSLATION_FAULT (BIT(0) | BIT(7)) 8315a01f4cSYong Wu #define F_INT_MAIN_MULTI_HIT_FAULT (BIT(1) | BIT(8)) 8415a01f4cSYong Wu #define F_INT_INVALID_PA_FAULT (BIT(2) | BIT(9)) 8515a01f4cSYong Wu #define F_INT_ENTRY_REPLACEMENT_FAULT (BIT(3) | BIT(10)) 8615a01f4cSYong Wu #define F_INT_TLB_MISS_FAULT (BIT(4) | BIT(11)) 8715a01f4cSYong Wu #define F_INT_MISS_TRANSACTION_FIFO_FAULT (BIT(5) | BIT(12)) 8815a01f4cSYong Wu #define F_INT_PRETETCH_TRANSATION_FIFO_FAULT (BIT(6) | BIT(13)) 890df4fabeSYong Wu 900df4fabeSYong Wu #define REG_MMU_CPE_DONE 0x12C 910df4fabeSYong Wu 920df4fabeSYong Wu #define REG_MMU_FAULT_ST1 0x134 9315a01f4cSYong Wu #define F_REG_MMU0_FAULT_MASK GENMASK(6, 0) 9415a01f4cSYong Wu #define F_REG_MMU1_FAULT_MASK GENMASK(13, 7) 950df4fabeSYong Wu 9615a01f4cSYong Wu #define REG_MMU0_FAULT_VA 0x13c 97ef0f0986SYong Wu #define F_MMU_INVAL_VA_31_12_MASK GENMASK(31, 12) 98ef0f0986SYong Wu #define F_MMU_INVAL_VA_34_32_MASK GENMASK(11, 9) 99ef0f0986SYong Wu #define F_MMU_INVAL_PA_34_32_MASK GENMASK(8, 6) 1000df4fabeSYong Wu #define F_MMU_FAULT_VA_WRITE_BIT BIT(1) 1010df4fabeSYong Wu #define F_MMU_FAULT_VA_LAYER_BIT BIT(0) 1020df4fabeSYong Wu 10315a01f4cSYong Wu #define REG_MMU0_INVLD_PA 0x140 10415a01f4cSYong Wu #define REG_MMU1_FAULT_VA 0x144 10515a01f4cSYong Wu #define REG_MMU1_INVLD_PA 0x148 10615a01f4cSYong Wu #define REG_MMU0_INT_ID 0x150 10715a01f4cSYong Wu #define REG_MMU1_INT_ID 0x154 10837276e00SChao Hao #define F_MMU_INT_ID_COMM_ID(a) (((a) >> 9) & 0x7) 10937276e00SChao Hao #define F_MMU_INT_ID_SUB_COMM_ID(a) (((a) >> 7) & 0x3) 1109ec30c09SYong Wu #define F_MMU_INT_ID_COMM_ID_EXT(a) (((a) >> 10) & 0x7) 1119ec30c09SYong Wu #define F_MMU_INT_ID_SUB_COMM_ID_EXT(a) (((a) >> 7) & 0x7) 11265df7d82SFabien Parent /* Macro for 5 bits length port ID field (default) */ 11315a01f4cSYong Wu #define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7) 11415a01f4cSYong Wu #define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f) 11565df7d82SFabien Parent /* Macro for 6 bits length port ID field */ 11665df7d82SFabien Parent #define F_MMU_INT_ID_LARB_ID_WID_6(a) (((a) >> 8) & 0x7) 11765df7d82SFabien Parent #define F_MMU_INT_ID_PORT_ID_WID_6(a) (((a) >> 2) & 0x3f) 1180df4fabeSYong Wu 119829316b3SChao Hao #define MTK_PROTECT_PA_ALIGN 256 12042d57fc5SYong Wu #define MTK_IOMMU_BANK_SZ 0x1000 1210df4fabeSYong Wu 122f9b8c9b2SYong Wu #define PERICFG_IOMMU_1 0x714 123f9b8c9b2SYong Wu 1246b717796SChao Hao #define HAS_4GB_MODE BIT(0) 1256b717796SChao Hao /* HW will use the EMI clock if there isn't the "bclk". */ 1266b717796SChao Hao #define HAS_BCLK BIT(1) 1276b717796SChao Hao #define HAS_VLD_PA_RNG BIT(2) 1286b717796SChao Hao #define RESET_AXI BIT(3) 1294bb2bf4cSChao Hao #define OUT_ORDER_WR_EN BIT(4) 1309ec30c09SYong Wu #define HAS_SUB_COMM_2BITS BIT(5) 1319ec30c09SYong Wu #define HAS_SUB_COMM_3BITS BIT(6) 1329ec30c09SYong Wu #define WR_THROT_EN BIT(7) 1339ec30c09SYong Wu #define HAS_LEGACY_IVRP_PADDR BIT(8) 1349ec30c09SYong Wu #define IOVA_34_EN BIT(9) 1359ec30c09SYong Wu #define SHARE_PGTABLE BIT(10) /* 2 HW share pgtable */ 1369ec30c09SYong Wu #define DCM_DISABLE BIT(11) 1379ec30c09SYong Wu #define STD_AXI_MODE BIT(12) /* For non MM iommu */ 1388cd1e619SYong Wu /* 2 bits: iommu type */ 1398cd1e619SYong Wu #define MTK_IOMMU_TYPE_MM (0x0 << 13) 1408cd1e619SYong Wu #define MTK_IOMMU_TYPE_INFRA (0x1 << 13) 1418cd1e619SYong Wu #define MTK_IOMMU_TYPE_MASK (0x3 << 13) 1426077c7e5SYong Wu /* PM and clock always on. e.g. infra iommu */ 1436077c7e5SYong Wu #define PM_CLK_AO BIT(15) 144e7629070SYong Wu #define IFA_IOMMU_PCIE_SUPPORT BIT(16) 145301c3ca1SYunfei Wang #define PGTABLE_PA_35_EN BIT(17) 14686580ec9SAngeloGioacchino Del Regno #define TF_PORT_TO_ADDR_MT8173 BIT(18) 14765df7d82SFabien Parent #define INT_ID_PORT_WIDTH_6 BIT(19) 148946e719cSChengci.Xu #define CFG_IFA_MASTER_IN_ATF BIT(20) 1496b717796SChao Hao 1508cd1e619SYong Wu #define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \ 1518cd1e619SYong Wu ((((pdata)->flags) & (mask)) == (_x)) 1528cd1e619SYong Wu 1538cd1e619SYong Wu #define MTK_IOMMU_HAS_FLAG(pdata, _x) MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, _x) 1548cd1e619SYong Wu #define MTK_IOMMU_IS_TYPE(pdata, _x) MTK_IOMMU_HAS_FLAG_MASK(pdata, _x,\ 1558cd1e619SYong Wu MTK_IOMMU_TYPE_MASK) 1566b717796SChao Hao 157d2e9a110SYong Wu #define MTK_INVALID_LARBID MTK_LARB_NR_MAX 158d2e9a110SYong Wu 1599485a04aSYong Wu #define MTK_LARB_COM_MAX 8 1609485a04aSYong Wu #define MTK_LARB_SUBCOM_MAX 8 1619485a04aSYong Wu 1629485a04aSYong Wu #define MTK_IOMMU_GROUP_MAX 8 16399ca0228SYong Wu #define MTK_IOMMU_BANK_MAX 5 1649485a04aSYong Wu 1659485a04aSYong Wu enum mtk_iommu_plat { 1669485a04aSYong Wu M4U_MT2712, 1679485a04aSYong Wu M4U_MT6779, 168717ec15eSAngeloGioacchino Del Regno M4U_MT6795, 1699485a04aSYong Wu M4U_MT8167, 1709485a04aSYong Wu M4U_MT8173, 1719485a04aSYong Wu M4U_MT8183, 172e8d7ccaaSYong Wu M4U_MT8186, 173a09e8403SChengci.Xu M4U_MT8188, 1749485a04aSYong Wu M4U_MT8192, 1759485a04aSYong Wu M4U_MT8195, 1763cd0e4a3SFabien Parent M4U_MT8365, 1779485a04aSYong Wu }; 1789485a04aSYong Wu 1799485a04aSYong Wu struct mtk_iommu_iova_region { 1809485a04aSYong Wu dma_addr_t iova_base; 1819485a04aSYong Wu unsigned long long size; 1829485a04aSYong Wu }; 1839485a04aSYong Wu 1846a513de3SYong Wu struct mtk_iommu_suspend_reg { 1856a513de3SYong Wu u32 misc_ctrl; 1866a513de3SYong Wu u32 dcm_dis; 1876a513de3SYong Wu u32 ctrl_reg; 1886a513de3SYong Wu u32 vld_pa_rng; 1896a513de3SYong Wu u32 wr_len_ctrl; 190d7127de1SYong Wu 191d7127de1SYong Wu u32 int_control[MTK_IOMMU_BANK_MAX]; 192d7127de1SYong Wu u32 int_main_control[MTK_IOMMU_BANK_MAX]; 193d7127de1SYong Wu u32 ivrp_paddr[MTK_IOMMU_BANK_MAX]; 1946a513de3SYong Wu }; 1956a513de3SYong Wu 1969485a04aSYong Wu struct mtk_iommu_plat_data { 1979485a04aSYong Wu enum mtk_iommu_plat m4u_plat; 1989485a04aSYong Wu u32 flags; 1999485a04aSYong Wu u32 inv_sel_reg; 2009485a04aSYong Wu 2019485a04aSYong Wu char *pericfg_comp_str; 2029485a04aSYong Wu struct list_head *hw_list; 203ae669345SYong Wu 204ae669345SYong Wu /* 205ae669345SYong Wu * The IOMMU HW may support 16GB iova. In order to balance the IOVA ranges, 206ae669345SYong Wu * different masters will be put in different iova ranges, for example vcodec 207ae669345SYong Wu * is in 4G-8G and cam is in 8G-12G. Meanwhile, some masters may have the 208ae669345SYong Wu * special IOVA range requirement, like CCU can only support the address 209ae669345SYong Wu * 0x40000000-0x44000000. 210ae669345SYong Wu * Here list the iova ranges this SoC supports and which larbs/ports are in 211ae669345SYong Wu * which region. 212ae669345SYong Wu * 213ae669345SYong Wu * 16GB iova all use one pgtable, but each a region is a iommu group. 214ae669345SYong Wu */ 215ae669345SYong Wu struct { 2169485a04aSYong Wu unsigned int iova_region_nr; 2179485a04aSYong Wu const struct mtk_iommu_iova_region *iova_region; 218b2a6876dSYong Wu /* 219b2a6876dSYong Wu * Indicate the correspondance between larbs, ports and regions. 220b2a6876dSYong Wu * 221b2a6876dSYong Wu * The index is the same as iova_region and larb port numbers are 222b2a6876dSYong Wu * described as bit positions. 223b2a6876dSYong Wu * For example, storing BIT(0) at index 2,1 means "larb 1, port0 is in region 2". 224b2a6876dSYong Wu * [2] = { [1] = BIT(0) } 225b2a6876dSYong Wu */ 226b2a6876dSYong Wu const u32 (*iova_region_larb_msk)[MTK_LARB_NR_MAX]; 227ae669345SYong Wu }; 22899ca0228SYong Wu 229ae669345SYong Wu /* 230ae669345SYong Wu * The IOMMU HW may have 5 banks. Each bank has a independent pgtable. 231ae669345SYong Wu * Here list how many banks this SoC supports/enables and which ports are in which bank. 232ae669345SYong Wu */ 233ae669345SYong Wu struct { 23499ca0228SYong Wu u8 banks_num; 23599ca0228SYong Wu bool banks_enable[MTK_IOMMU_BANK_MAX]; 23657fb481fSYong Wu unsigned int banks_portmsk[MTK_IOMMU_BANK_MAX]; 237ae669345SYong Wu }; 238ae669345SYong Wu 2399485a04aSYong Wu unsigned char larbid_remap[MTK_LARB_COM_MAX][MTK_LARB_SUBCOM_MAX]; 2409485a04aSYong Wu }; 2419485a04aSYong Wu 24299ca0228SYong Wu struct mtk_iommu_bank_data { 2439485a04aSYong Wu void __iomem *base; 2449485a04aSYong Wu int irq; 24599ca0228SYong Wu u8 id; 24699ca0228SYong Wu struct device *parent_dev; 24799ca0228SYong Wu struct mtk_iommu_data *parent_data; 24899ca0228SYong Wu spinlock_t tlb_lock; /* lock for tlb range flush */ 24999ca0228SYong Wu struct mtk_iommu_domain *m4u_dom; /* Each bank has a domain */ 25099ca0228SYong Wu }; 25199ca0228SYong Wu 25299ca0228SYong Wu struct mtk_iommu_data { 2539485a04aSYong Wu struct device *dev; 2549485a04aSYong Wu struct clk *bclk; 2559485a04aSYong Wu phys_addr_t protect_base; /* protect memory base */ 2569485a04aSYong Wu struct mtk_iommu_suspend_reg reg; 2579485a04aSYong Wu struct iommu_group *m4u_group[MTK_IOMMU_GROUP_MAX]; 2589485a04aSYong Wu bool enable_4GB; 2599485a04aSYong Wu 2609485a04aSYong Wu struct iommu_device iommu; 2619485a04aSYong Wu const struct mtk_iommu_plat_data *plat_data; 2629485a04aSYong Wu struct device *smicomm_dev; 2639485a04aSYong Wu 26499ca0228SYong Wu struct mtk_iommu_bank_data *bank; 265*b07eba71SYong Wu struct mtk_iommu_domain *share_dom; 266cf69ef46SChengci.Xu 2679485a04aSYong Wu struct regmap *pericfg; 2689485a04aSYong Wu struct mutex mutex; /* Protect m4u_group/m4u_dom above */ 2699485a04aSYong Wu 2709485a04aSYong Wu /* 2719485a04aSYong Wu * In the sharing pgtable case, list data->list to the global list like m4ulist. 2729485a04aSYong Wu * In the non-sharing pgtable case, list data->list to the itself hw_list_head. 2739485a04aSYong Wu */ 2749485a04aSYong Wu struct list_head *hw_list; 2759485a04aSYong Wu struct list_head hw_list_head; 2769485a04aSYong Wu struct list_head list; 2779485a04aSYong Wu struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX]; 2789485a04aSYong Wu }; 2799485a04aSYong Wu 2800df4fabeSYong Wu struct mtk_iommu_domain { 2810df4fabeSYong Wu struct io_pgtable_cfg cfg; 2820df4fabeSYong Wu struct io_pgtable_ops *iop; 2830df4fabeSYong Wu 28499ca0228SYong Wu struct mtk_iommu_bank_data *bank; 2850df4fabeSYong Wu struct iommu_domain domain; 286ddf67a87SYong Wu 287ddf67a87SYong Wu struct mutex mutex; /* Protect "data" in this structure */ 2880df4fabeSYong Wu }; 2890df4fabeSYong Wu 2909485a04aSYong Wu static int mtk_iommu_bind(struct device *dev) 2919485a04aSYong Wu { 2929485a04aSYong Wu struct mtk_iommu_data *data = dev_get_drvdata(dev); 2939485a04aSYong Wu 2949485a04aSYong Wu return component_bind_all(dev, &data->larb_imu); 2959485a04aSYong Wu } 2969485a04aSYong Wu 2979485a04aSYong Wu static void mtk_iommu_unbind(struct device *dev) 2989485a04aSYong Wu { 2999485a04aSYong Wu struct mtk_iommu_data *data = dev_get_drvdata(dev); 3009485a04aSYong Wu 3019485a04aSYong Wu component_unbind_all(dev, &data->larb_imu); 3029485a04aSYong Wu } 3039485a04aSYong Wu 304b65f5016SArvind Yadav static const struct iommu_ops mtk_iommu_ops; 3050df4fabeSYong Wu 306e24453e1SYong Wu static int mtk_iommu_hw_init(const struct mtk_iommu_data *data, unsigned int bankid); 3077f37a91dSYong Wu 308bfed8731SYong Wu #define MTK_IOMMU_TLB_ADDR(iova) ({ \ 309bfed8731SYong Wu dma_addr_t _addr = iova; \ 310bfed8731SYong Wu ((lower_32_bits(_addr) & GENMASK(31, 12)) | upper_32_bits(_addr));\ 311bfed8731SYong Wu }) 312bfed8731SYong Wu 31376ce6546SYong Wu /* 31476ce6546SYong Wu * In M4U 4GB mode, the physical address is remapped as below: 31576ce6546SYong Wu * 31676ce6546SYong Wu * CPU Physical address: 31776ce6546SYong Wu * ==================== 31876ce6546SYong Wu * 31976ce6546SYong Wu * 0 1G 2G 3G 4G 5G 32076ce6546SYong Wu * |---A---|---B---|---C---|---D---|---E---| 32176ce6546SYong Wu * +--I/O--+------------Memory-------------+ 32276ce6546SYong Wu * 32376ce6546SYong Wu * IOMMU output physical address: 32476ce6546SYong Wu * ============================= 32576ce6546SYong Wu * 32676ce6546SYong Wu * 4G 5G 6G 7G 8G 32776ce6546SYong Wu * |---E---|---B---|---C---|---D---| 32876ce6546SYong Wu * +------------Memory-------------+ 32976ce6546SYong Wu * 33076ce6546SYong Wu * The Region 'A'(I/O) can NOT be mapped by M4U; For Region 'B'/'C'/'D', the 33176ce6546SYong Wu * bit32 of the CPU physical address always is needed to set, and for Region 33276ce6546SYong Wu * 'E', the CPU physical address keep as is. 33376ce6546SYong Wu * Additionally, The iommu consumers always use the CPU phyiscal address. 33476ce6546SYong Wu */ 335b4dad40eSYong Wu #define MTK_IOMMU_4GB_MODE_REMAP_BASE 0x140000000UL 33676ce6546SYong Wu 3377c3a2ec0SYong Wu static LIST_HEAD(m4ulist); /* List all the M4U HWs */ 3387c3a2ec0SYong Wu 3399e3a2a64SYong Wu #define for_each_m4u(data, head) list_for_each_entry(data, head, list) 3407c3a2ec0SYong Wu 3413df9bdd4SYong Wu #define MTK_IOMMU_IOVA_SZ_4G (SZ_4G - SZ_8M) /* 8M as gap */ 3423df9bdd4SYong Wu 343585e58f4SYong Wu static const struct mtk_iommu_iova_region single_domain[] = { 3443df9bdd4SYong Wu {.iova_base = 0, .size = MTK_IOMMU_IOVA_SZ_4G}, 345585e58f4SYong Wu }; 346585e58f4SYong Wu 3476b1317f9SYong Wu #define MT8192_MULTI_REGION_NR_MAX 6 3486b1317f9SYong Wu 3496b1317f9SYong Wu #define MT8192_MULTI_REGION_NR (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) ? \ 3506b1317f9SYong Wu MT8192_MULTI_REGION_NR_MAX : 1) 3516b1317f9SYong Wu 3526b1317f9SYong Wu static const struct mtk_iommu_iova_region mt8192_multi_dom[MT8192_MULTI_REGION_NR] = { 3533df9bdd4SYong Wu { .iova_base = 0x0, .size = MTK_IOMMU_IOVA_SZ_4G}, /* 0 ~ 4G, */ 3549e3489e0SYong Wu #if IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) 3553df9bdd4SYong Wu { .iova_base = SZ_4G, .size = MTK_IOMMU_IOVA_SZ_4G}, /* 4G ~ 8G */ 3563df9bdd4SYong Wu { .iova_base = SZ_4G * 2, .size = MTK_IOMMU_IOVA_SZ_4G}, /* 8G ~ 12G */ 3573df9bdd4SYong Wu { .iova_base = SZ_4G * 3, .size = MTK_IOMMU_IOVA_SZ_4G}, /* 12G ~ 16G */ 358129a3b88SYong Wu 3599e3489e0SYong Wu { .iova_base = 0x240000000ULL, .size = 0x4000000}, /* CCU0 */ 3609e3489e0SYong Wu { .iova_base = 0x244000000ULL, .size = 0x4000000}, /* CCU1 */ 3619e3489e0SYong Wu #endif 3629e3489e0SYong Wu }; 3639e3489e0SYong Wu 3649e3a2a64SYong Wu /* If 2 M4U share a domain(use the same hwlist), Put the corresponding info in first data.*/ 3659e3a2a64SYong Wu static struct mtk_iommu_data *mtk_iommu_get_frst_data(struct list_head *hwlist) 3667c3a2ec0SYong Wu { 3679e3a2a64SYong Wu return list_first_entry(hwlist, struct mtk_iommu_data, list); 3687c3a2ec0SYong Wu } 3697c3a2ec0SYong Wu 3700df4fabeSYong Wu static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom) 3710df4fabeSYong Wu { 3720df4fabeSYong Wu return container_of(dom, struct mtk_iommu_domain, domain); 3730df4fabeSYong Wu } 3740df4fabeSYong Wu 3750954d61aSYong Wu static void mtk_iommu_tlb_flush_all(struct mtk_iommu_data *data) 3760df4fabeSYong Wu { 37799ca0228SYong Wu /* Tlb flush all always is in bank0. */ 37899ca0228SYong Wu struct mtk_iommu_bank_data *bank = &data->bank[0]; 37999ca0228SYong Wu void __iomem *base = bank->base; 38015672b6dSYong Wu unsigned long flags; 381c0b57581SYong Wu 38299ca0228SYong Wu spin_lock_irqsave(&bank->tlb_lock, flags); 383887cf6a7SYong Wu writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, base + data->plat_data->inv_sel_reg); 384887cf6a7SYong Wu writel_relaxed(F_ALL_INVLD, base + REG_MMU_INVALIDATE); 3850df4fabeSYong Wu wmb(); /* Make sure the tlb flush all done */ 38699ca0228SYong Wu spin_unlock_irqrestore(&bank->tlb_lock, flags); 3877c3a2ec0SYong Wu } 3880df4fabeSYong Wu 3891f4fd624SYong Wu static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size, 39099ca0228SYong Wu struct mtk_iommu_bank_data *bank) 3910df4fabeSYong Wu { 39299ca0228SYong Wu struct list_head *head = bank->parent_data->hw_list; 39399ca0228SYong Wu struct mtk_iommu_bank_data *curbank; 39499ca0228SYong Wu struct mtk_iommu_data *data; 3956077c7e5SYong Wu bool check_pm_status; 3961f4fd624SYong Wu unsigned long flags; 397887cf6a7SYong Wu void __iomem *base; 3981f4fd624SYong Wu int ret; 3991f4fd624SYong Wu u32 tmp; 4000df4fabeSYong Wu 4019e3a2a64SYong Wu for_each_m4u(data, head) { 4026077c7e5SYong Wu /* 4036077c7e5SYong Wu * To avoid resume the iommu device frequently when the iommu device 4046077c7e5SYong Wu * is not active, it doesn't always call pm_runtime_get here, then tlb 4056077c7e5SYong Wu * flush depends on the tlb flush all in the runtime resume. 4066077c7e5SYong Wu * 4076077c7e5SYong Wu * There are 2 special cases: 4086077c7e5SYong Wu * 4096077c7e5SYong Wu * Case1: The iommu dev doesn't have power domain but has bclk. This case 4106077c7e5SYong Wu * should also avoid the tlb flush while the dev is not active to mute 4116077c7e5SYong Wu * the tlb timeout log. like mt8173. 4126077c7e5SYong Wu * 4136077c7e5SYong Wu * Case2: The power/clock of infra iommu is always on, and it doesn't 4146077c7e5SYong Wu * have the device link with the master devices. This case should avoid 4156077c7e5SYong Wu * the PM status check. 4166077c7e5SYong Wu */ 4176077c7e5SYong Wu check_pm_status = !MTK_IOMMU_HAS_FLAG(data->plat_data, PM_CLK_AO); 4186077c7e5SYong Wu 4196077c7e5SYong Wu if (check_pm_status) { 420c0b57581SYong Wu if (pm_runtime_get_if_in_use(data->dev) <= 0) 421c0b57581SYong Wu continue; 4226077c7e5SYong Wu } 423c0b57581SYong Wu 42499ca0228SYong Wu curbank = &data->bank[bank->id]; 42599ca0228SYong Wu base = curbank->base; 426887cf6a7SYong Wu 42799ca0228SYong Wu spin_lock_irqsave(&curbank->tlb_lock, flags); 4287c3a2ec0SYong Wu writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, 429887cf6a7SYong Wu base + data->plat_data->inv_sel_reg); 4300df4fabeSYong Wu 431887cf6a7SYong Wu writel_relaxed(MTK_IOMMU_TLB_ADDR(iova), base + REG_MMU_INVLD_START_A); 432bfed8731SYong Wu writel_relaxed(MTK_IOMMU_TLB_ADDR(iova + size - 1), 433887cf6a7SYong Wu base + REG_MMU_INVLD_END_A); 434887cf6a7SYong Wu writel_relaxed(F_MMU_INV_RANGE, base + REG_MMU_INVALIDATE); 4350df4fabeSYong Wu 4361f4fd624SYong Wu /* tlb sync */ 437887cf6a7SYong Wu ret = readl_poll_timeout_atomic(base + REG_MMU_CPE_DONE, 438c90ae4a6SYong Wu tmp, tmp != 0, 10, 1000); 43915672b6dSYong Wu 44015672b6dSYong Wu /* Clear the CPE status */ 441887cf6a7SYong Wu writel_relaxed(0, base + REG_MMU_CPE_DONE); 44299ca0228SYong Wu spin_unlock_irqrestore(&curbank->tlb_lock, flags); 44315672b6dSYong Wu 4440df4fabeSYong Wu if (ret) { 4450df4fabeSYong Wu dev_warn(data->dev, 4460df4fabeSYong Wu "Partial TLB flush timed out, falling back to full flush\n"); 4470954d61aSYong Wu mtk_iommu_tlb_flush_all(data); 4480df4fabeSYong Wu } 449c0b57581SYong Wu 4506077c7e5SYong Wu if (check_pm_status) 451c0b57581SYong Wu pm_runtime_put(data->dev); 4520df4fabeSYong Wu } 4537c3a2ec0SYong Wu } 4540df4fabeSYong Wu 4550df4fabeSYong Wu static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) 4560df4fabeSYong Wu { 45799ca0228SYong Wu struct mtk_iommu_bank_data *bank = dev_id; 45899ca0228SYong Wu struct mtk_iommu_data *data = bank->parent_data; 45999ca0228SYong Wu struct mtk_iommu_domain *dom = bank->m4u_dom; 460d2e9a110SYong Wu unsigned int fault_larb = MTK_INVALID_LARBID, fault_port = 0, sub_comm = 0; 461ef0f0986SYong Wu u32 int_state, regval, va34_32, pa34_32; 462887cf6a7SYong Wu const struct mtk_iommu_plat_data *plat_data = data->plat_data; 46399ca0228SYong Wu void __iomem *base = bank->base; 464ef0f0986SYong Wu u64 fault_iova, fault_pa; 4650df4fabeSYong Wu bool layer, write; 4660df4fabeSYong Wu 4670df4fabeSYong Wu /* Read error info from registers */ 468887cf6a7SYong Wu int_state = readl_relaxed(base + REG_MMU_FAULT_ST1); 46915a01f4cSYong Wu if (int_state & F_REG_MMU0_FAULT_MASK) { 470887cf6a7SYong Wu regval = readl_relaxed(base + REG_MMU0_INT_ID); 471887cf6a7SYong Wu fault_iova = readl_relaxed(base + REG_MMU0_FAULT_VA); 472887cf6a7SYong Wu fault_pa = readl_relaxed(base + REG_MMU0_INVLD_PA); 47315a01f4cSYong Wu } else { 474887cf6a7SYong Wu regval = readl_relaxed(base + REG_MMU1_INT_ID); 475887cf6a7SYong Wu fault_iova = readl_relaxed(base + REG_MMU1_FAULT_VA); 476887cf6a7SYong Wu fault_pa = readl_relaxed(base + REG_MMU1_INVLD_PA); 47715a01f4cSYong Wu } 4780df4fabeSYong Wu layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT; 4790df4fabeSYong Wu write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT; 480887cf6a7SYong Wu if (MTK_IOMMU_HAS_FLAG(plat_data, IOVA_34_EN)) { 481ef0f0986SYong Wu va34_32 = FIELD_GET(F_MMU_INVAL_VA_34_32_MASK, fault_iova); 482ef0f0986SYong Wu fault_iova = fault_iova & F_MMU_INVAL_VA_31_12_MASK; 483ef0f0986SYong Wu fault_iova |= (u64)va34_32 << 32; 484ef0f0986SYong Wu } 48582e51771SYong Wu pa34_32 = FIELD_GET(F_MMU_INVAL_PA_34_32_MASK, fault_iova); 48682e51771SYong Wu fault_pa |= (u64)pa34_32 << 32; 487ef0f0986SYong Wu 488887cf6a7SYong Wu if (MTK_IOMMU_IS_TYPE(plat_data, MTK_IOMMU_TYPE_MM)) { 489887cf6a7SYong Wu if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_2BITS)) { 49037276e00SChao Hao fault_larb = F_MMU_INT_ID_COMM_ID(regval); 49137276e00SChao Hao sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval); 49265df7d82SFabien Parent fault_port = F_MMU_INT_ID_PORT_ID(regval); 493887cf6a7SYong Wu } else if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_3BITS)) { 4949ec30c09SYong Wu fault_larb = F_MMU_INT_ID_COMM_ID_EXT(regval); 4959ec30c09SYong Wu sub_comm = F_MMU_INT_ID_SUB_COMM_ID_EXT(regval); 49665df7d82SFabien Parent fault_port = F_MMU_INT_ID_PORT_ID(regval); 49765df7d82SFabien Parent } else if (MTK_IOMMU_HAS_FLAG(plat_data, INT_ID_PORT_WIDTH_6)) { 49865df7d82SFabien Parent fault_port = F_MMU_INT_ID_PORT_ID_WID_6(regval); 49965df7d82SFabien Parent fault_larb = F_MMU_INT_ID_LARB_ID_WID_6(regval); 50037276e00SChao Hao } else { 50165df7d82SFabien Parent fault_port = F_MMU_INT_ID_PORT_ID(regval); 50237276e00SChao Hao fault_larb = F_MMU_INT_ID_LARB_ID(regval); 50337276e00SChao Hao } 50437276e00SChao Hao fault_larb = data->plat_data->larbid_remap[fault_larb][sub_comm]; 505d2e9a110SYong Wu } 506b3e5eee7SYong Wu 50700ef8885SRicardo Ribalda if (!dom || report_iommu_fault(&dom->domain, bank->parent_dev, fault_iova, 5080df4fabeSYong Wu write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) { 5090df4fabeSYong Wu dev_err_ratelimited( 51099ca0228SYong Wu bank->parent_dev, 511f9b8c9b2SYong Wu "fault type=0x%x iova=0x%llx pa=0x%llx master=0x%x(larb=%d port=%d) layer=%d %s\n", 512f9b8c9b2SYong Wu int_state, fault_iova, fault_pa, regval, fault_larb, fault_port, 5130df4fabeSYong Wu layer, write ? "write" : "read"); 5140df4fabeSYong Wu } 5150df4fabeSYong Wu 5160df4fabeSYong Wu /* Interrupt clear */ 517887cf6a7SYong Wu regval = readl_relaxed(base + REG_MMU_INT_CONTROL0); 5180df4fabeSYong Wu regval |= F_INT_CLR_BIT; 519887cf6a7SYong Wu writel_relaxed(regval, base + REG_MMU_INT_CONTROL0); 5200df4fabeSYong Wu 5210df4fabeSYong Wu mtk_iommu_tlb_flush_all(data); 5220df4fabeSYong Wu 5230df4fabeSYong Wu return IRQ_HANDLED; 5240df4fabeSYong Wu } 5250df4fabeSYong Wu 52657fb481fSYong Wu static unsigned int mtk_iommu_get_bank_id(struct device *dev, 52757fb481fSYong Wu const struct mtk_iommu_plat_data *plat_data) 52857fb481fSYong Wu { 52957fb481fSYong Wu struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 53057fb481fSYong Wu unsigned int i, portmsk = 0, bankid = 0; 53157fb481fSYong Wu 53257fb481fSYong Wu if (plat_data->banks_num == 1) 53357fb481fSYong Wu return bankid; 53457fb481fSYong Wu 53557fb481fSYong Wu for (i = 0; i < fwspec->num_ids; i++) 53657fb481fSYong Wu portmsk |= BIT(MTK_M4U_TO_PORT(fwspec->ids[i])); 53757fb481fSYong Wu 53857fb481fSYong Wu for (i = 0; i < plat_data->banks_num && i < MTK_IOMMU_BANK_MAX; i++) { 53957fb481fSYong Wu if (!plat_data->banks_enable[i]) 54057fb481fSYong Wu continue; 54157fb481fSYong Wu 54257fb481fSYong Wu if (portmsk & plat_data->banks_portmsk[i]) { 54357fb481fSYong Wu bankid = i; 54457fb481fSYong Wu break; 54557fb481fSYong Wu } 54657fb481fSYong Wu } 54757fb481fSYong Wu return bankid; /* default is 0 */ 54857fb481fSYong Wu } 54957fb481fSYong Wu 550d72e0ff5SYong Wu static int mtk_iommu_get_iova_region_id(struct device *dev, 551803cf9e5SYong Wu const struct mtk_iommu_plat_data *plat_data) 552803cf9e5SYong Wu { 553b2a6876dSYong Wu struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 554b2a6876dSYong Wu unsigned int portidmsk = 0, larbid; 555b2a6876dSYong Wu const u32 *rgn_larb_msk; 556b2a6876dSYong Wu int i; 557803cf9e5SYong Wu 558b2a6876dSYong Wu if (plat_data->iova_region_nr == 1) 559803cf9e5SYong Wu return 0; 560803cf9e5SYong Wu 561b2a6876dSYong Wu larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); 562b2a6876dSYong Wu for (i = 0; i < fwspec->num_ids; i++) 563b2a6876dSYong Wu portidmsk |= BIT(MTK_M4U_TO_PORT(fwspec->ids[i])); 564b2a6876dSYong Wu 565b2a6876dSYong Wu for (i = 0; i < plat_data->iova_region_nr; i++) { 566b2a6876dSYong Wu rgn_larb_msk = plat_data->iova_region_larb_msk[i]; 567b2a6876dSYong Wu if (!rgn_larb_msk) 568b2a6876dSYong Wu continue; 569b2a6876dSYong Wu 570b2a6876dSYong Wu if ((rgn_larb_msk[larbid] & portidmsk) == portidmsk) 571803cf9e5SYong Wu return i; 572803cf9e5SYong Wu } 573803cf9e5SYong Wu 574b2a6876dSYong Wu dev_err(dev, "Can NOT find the region for larb(%d-%x).\n", 575b2a6876dSYong Wu larbid, portidmsk); 576803cf9e5SYong Wu return -EINVAL; 577803cf9e5SYong Wu } 578803cf9e5SYong Wu 579f9b8c9b2SYong Wu static int mtk_iommu_config(struct mtk_iommu_data *data, struct device *dev, 580d72e0ff5SYong Wu bool enable, unsigned int regionid) 5810df4fabeSYong Wu { 5820df4fabeSYong Wu struct mtk_smi_larb_iommu *larb_mmu; 5830df4fabeSYong Wu unsigned int larbid, portid; 584a9bf2eecSJoerg Roedel struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 5858d2c749eSYong Wu const struct mtk_iommu_iova_region *region; 5869a890510SChengci.Xu unsigned long portid_msk = 0; 587946e719cSChengci.Xu struct arm_smccc_res res; 588f9b8c9b2SYong Wu int i, ret = 0; 5890df4fabeSYong Wu 59058f0d1d5SRobin Murphy for (i = 0; i < fwspec->num_ids; ++i) { 59158f0d1d5SRobin Murphy portid = MTK_M4U_TO_PORT(fwspec->ids[i]); 5929a890510SChengci.Xu portid_msk |= BIT(portid); 5939a890510SChengci.Xu } 5948d2c749eSYong Wu 595d2e9a110SYong Wu if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { 5969a890510SChengci.Xu /* All ports should be in the same larb. just use 0 here */ 5979a890510SChengci.Xu larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); 5981ee9feb2SYong Wu larb_mmu = &data->larb_imu[larbid]; 599d72e0ff5SYong Wu region = data->plat_data->iova_region + regionid; 6009a890510SChengci.Xu 6019a890510SChengci.Xu for_each_set_bit(portid, &portid_msk, 32) 6028d2c749eSYong Wu larb_mmu->bank[portid] = upper_32_bits(region->iova_base); 6038d2c749eSYong Wu 6049a890510SChengci.Xu dev_dbg(dev, "%s iommu for larb(%s) port 0x%lx region %d rgn-bank %d.\n", 6058d2c749eSYong Wu enable ? "enable" : "disable", dev_name(larb_mmu->dev), 6069a890510SChengci.Xu portid_msk, regionid, upper_32_bits(region->iova_base)); 6070df4fabeSYong Wu 6080df4fabeSYong Wu if (enable) 6099a890510SChengci.Xu larb_mmu->mmu |= portid_msk; 6100df4fabeSYong Wu else 6119a890510SChengci.Xu larb_mmu->mmu &= ~portid_msk; 612f9b8c9b2SYong Wu } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA)) { 613946e719cSChengci.Xu if (MTK_IOMMU_HAS_FLAG(data->plat_data, CFG_IFA_MASTER_IN_ATF)) { 614946e719cSChengci.Xu arm_smccc_smc(MTK_SIP_KERNEL_IOMMU_CONTROL, 615946e719cSChengci.Xu IOMMU_ATF_CMD_CONFIG_INFRA_IOMMU, 616946e719cSChengci.Xu portid_msk, enable, 0, 0, 0, 0, &res); 617946e719cSChengci.Xu ret = res.a0; 618946e719cSChengci.Xu } else { 619e7629070SYong Wu /* PCI dev has only one output id, enable the next writing bit for PCIe */ 6209a890510SChengci.Xu if (dev_is_pci(dev)) { 6219a890510SChengci.Xu if (fwspec->num_ids != 1) { 6229a890510SChengci.Xu dev_err(dev, "PCI dev can only have one port.\n"); 6239a890510SChengci.Xu return -ENODEV; 6240df4fabeSYong Wu } 6259a890510SChengci.Xu portid_msk |= BIT(portid + 1); 6269a890510SChengci.Xu } 6279a890510SChengci.Xu 6289a890510SChengci.Xu ret = regmap_update_bits(data->pericfg, PERICFG_IOMMU_1, 6299a890510SChengci.Xu (u32)portid_msk, enable ? (u32)portid_msk : 0); 630946e719cSChengci.Xu } 6319a890510SChengci.Xu if (ret) 6329a890510SChengci.Xu dev_err(dev, "%s iommu(%s) inframaster 0x%lx fail(%d).\n", 6339a890510SChengci.Xu enable ? "enable" : "disable", 6349a890510SChengci.Xu dev_name(data->dev), portid_msk, ret); 6350df4fabeSYong Wu } 636f9b8c9b2SYong Wu return ret; 637d2e9a110SYong Wu } 6380df4fabeSYong Wu 6394f956c97SYong Wu static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom, 640c3045f39SYong Wu struct mtk_iommu_data *data, 641d72e0ff5SYong Wu unsigned int region_id) 6420df4fabeSYong Wu { 643cf69ef46SChengci.Xu struct mtk_iommu_domain *share_dom = data->share_dom; 644c3045f39SYong Wu const struct mtk_iommu_iova_region *region; 645c3045f39SYong Wu 646*b07eba71SYong Wu /* Share pgtable when 2 MM IOMMU share the pgtable or one IOMMU use multiple iova ranges */ 647*b07eba71SYong Wu if (share_dom) { 648cf69ef46SChengci.Xu dom->iop = share_dom->iop; 649cf69ef46SChengci.Xu dom->cfg = share_dom->cfg; 650cf69ef46SChengci.Xu dom->domain.pgsize_bitmap = share_dom->cfg.pgsize_bitmap; 651c3045f39SYong Wu goto update_iova_region; 652c3045f39SYong Wu } 653c3045f39SYong Wu 6540df4fabeSYong Wu dom->cfg = (struct io_pgtable_cfg) { 6550df4fabeSYong Wu .quirks = IO_PGTABLE_QUIRK_ARM_NS | 6560df4fabeSYong Wu IO_PGTABLE_QUIRK_NO_PERMS | 657b4dad40eSYong Wu IO_PGTABLE_QUIRK_ARM_MTK_EXT, 6580df4fabeSYong Wu .pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap, 6592f317da4SYong Wu .ias = MTK_IOMMU_HAS_FLAG(data->plat_data, IOVA_34_EN) ? 34 : 32, 6600df4fabeSYong Wu .iommu_dev = data->dev, 6610df4fabeSYong Wu }; 6620df4fabeSYong Wu 663301c3ca1SYunfei Wang if (MTK_IOMMU_HAS_FLAG(data->plat_data, PGTABLE_PA_35_EN)) 664301c3ca1SYunfei Wang dom->cfg.quirks |= IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT; 665301c3ca1SYunfei Wang 6669bdfe4c1SYong Wu if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) 6679bdfe4c1SYong Wu dom->cfg.oas = data->enable_4GB ? 33 : 32; 6689bdfe4c1SYong Wu else 6699bdfe4c1SYong Wu dom->cfg.oas = 35; 6709bdfe4c1SYong Wu 6710df4fabeSYong Wu dom->iop = alloc_io_pgtable_ops(ARM_V7S, &dom->cfg, data); 6720df4fabeSYong Wu if (!dom->iop) { 6730df4fabeSYong Wu dev_err(data->dev, "Failed to alloc io pgtable\n"); 674bd7ebb77SNicolin Chen return -ENOMEM; 6750df4fabeSYong Wu } 6760df4fabeSYong Wu 6770df4fabeSYong Wu /* Update our support page sizes bitmap */ 678d16e0faaSRobin Murphy dom->domain.pgsize_bitmap = dom->cfg.pgsize_bitmap; 679b7875eb9SYong Wu 680cf69ef46SChengci.Xu data->share_dom = dom; 681cf69ef46SChengci.Xu 682c3045f39SYong Wu update_iova_region: 683c3045f39SYong Wu /* Update the iova region for this domain */ 684d72e0ff5SYong Wu region = data->plat_data->iova_region + region_id; 685c3045f39SYong Wu dom->domain.geometry.aperture_start = region->iova_base; 686c3045f39SYong Wu dom->domain.geometry.aperture_end = region->iova_base + region->size - 1; 687b7875eb9SYong Wu dom->domain.geometry.force_aperture = true; 6880df4fabeSYong Wu return 0; 6890df4fabeSYong Wu } 6900df4fabeSYong Wu 6910df4fabeSYong Wu static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type) 6920df4fabeSYong Wu { 6930df4fabeSYong Wu struct mtk_iommu_domain *dom; 6940df4fabeSYong Wu 69532e1cccfSYong Wu if (type != IOMMU_DOMAIN_DMA && type != IOMMU_DOMAIN_UNMANAGED) 6960df4fabeSYong Wu return NULL; 6970df4fabeSYong Wu 6980df4fabeSYong Wu dom = kzalloc(sizeof(*dom), GFP_KERNEL); 6990df4fabeSYong Wu if (!dom) 7000df4fabeSYong Wu return NULL; 701ddf67a87SYong Wu mutex_init(&dom->mutex); 7020df4fabeSYong Wu 7034f956c97SYong Wu return &dom->domain; 7044f956c97SYong Wu } 7054f956c97SYong Wu 7060df4fabeSYong Wu static void mtk_iommu_domain_free(struct iommu_domain *domain) 7070df4fabeSYong Wu { 7080df4fabeSYong Wu kfree(to_mtk_domain(domain)); 7090df4fabeSYong Wu } 7100df4fabeSYong Wu 7110df4fabeSYong Wu static int mtk_iommu_attach_device(struct iommu_domain *domain, 7120df4fabeSYong Wu struct device *dev) 7130df4fabeSYong Wu { 714645b87c1SYong Wu struct mtk_iommu_data *data = dev_iommu_priv_get(dev), *frstdata; 7150df4fabeSYong Wu struct mtk_iommu_domain *dom = to_mtk_domain(domain); 7169e3a2a64SYong Wu struct list_head *hw_list = data->hw_list; 717c0b57581SYong Wu struct device *m4udev = data->dev; 71899ca0228SYong Wu struct mtk_iommu_bank_data *bank; 71957fb481fSYong Wu unsigned int bankid; 720d72e0ff5SYong Wu int ret, region_id; 7210df4fabeSYong Wu 722d72e0ff5SYong Wu region_id = mtk_iommu_get_iova_region_id(dev, data->plat_data); 723d72e0ff5SYong Wu if (region_id < 0) 724d72e0ff5SYong Wu return region_id; 725803cf9e5SYong Wu 72657fb481fSYong Wu bankid = mtk_iommu_get_bank_id(dev, data->plat_data); 727ddf67a87SYong Wu mutex_lock(&dom->mutex); 72899ca0228SYong Wu if (!dom->bank) { 729645b87c1SYong Wu /* Data is in the frstdata in sharing pgtable case. */ 7309e3a2a64SYong Wu frstdata = mtk_iommu_get_frst_data(hw_list); 731645b87c1SYong Wu 732cf69ef46SChengci.Xu mutex_lock(&frstdata->mutex); 733d72e0ff5SYong Wu ret = mtk_iommu_domain_finalise(dom, frstdata, region_id); 734cf69ef46SChengci.Xu mutex_unlock(&frstdata->mutex); 735ddf67a87SYong Wu if (ret) { 736ddf67a87SYong Wu mutex_unlock(&dom->mutex); 73704cee82eSNicolin Chen return ret; 738ddf67a87SYong Wu } 73999ca0228SYong Wu dom->bank = &data->bank[bankid]; 7404f956c97SYong Wu } 741ddf67a87SYong Wu mutex_unlock(&dom->mutex); 7424f956c97SYong Wu 7430e5a3f2eSYong Wu mutex_lock(&data->mutex); 74499ca0228SYong Wu bank = &data->bank[bankid]; 745e24453e1SYong Wu if (!bank->m4u_dom) { /* Initialize the M4U HW for each a BANK */ 746c0b57581SYong Wu ret = pm_runtime_resume_and_get(m4udev); 747e24453e1SYong Wu if (ret < 0) { 748e24453e1SYong Wu dev_err(m4udev, "pm get fail(%d) in attach.\n", ret); 7490e5a3f2eSYong Wu goto err_unlock; 750e24453e1SYong Wu } 751c0b57581SYong Wu 752e24453e1SYong Wu ret = mtk_iommu_hw_init(data, bankid); 753c0b57581SYong Wu if (ret) { 754c0b57581SYong Wu pm_runtime_put(m4udev); 7550e5a3f2eSYong Wu goto err_unlock; 756c0b57581SYong Wu } 75799ca0228SYong Wu bank->m4u_dom = dom; 758301c3ca1SYunfei Wang writel(dom->cfg.arm_v7s_cfg.ttbr, bank->base + REG_MMU_PT_BASE_ADDR); 759c0b57581SYong Wu 760c0b57581SYong Wu pm_runtime_put(m4udev); 7610df4fabeSYong Wu } 7620e5a3f2eSYong Wu mutex_unlock(&data->mutex); 7630df4fabeSYong Wu 764f7da2da8SYong Wu if (region_id > 0) { 765f7da2da8SYong Wu ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(34)); 766f7da2da8SYong Wu if (ret) { 767f7da2da8SYong Wu dev_err(m4udev, "Failed to set dma_mask for %s(%d).\n", dev_name(dev), ret); 768f7da2da8SYong Wu return ret; 769f7da2da8SYong Wu } 770f7da2da8SYong Wu } 771f7da2da8SYong Wu 772d72e0ff5SYong Wu return mtk_iommu_config(data, dev, true, region_id); 7730e5a3f2eSYong Wu 7740e5a3f2eSYong Wu err_unlock: 7750e5a3f2eSYong Wu mutex_unlock(&data->mutex); 7760e5a3f2eSYong Wu return ret; 7770df4fabeSYong Wu } 7780df4fabeSYong Wu 7790df4fabeSYong Wu static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova, 78085637380SRobin Murphy phys_addr_t paddr, size_t pgsize, size_t pgcount, 78185637380SRobin Murphy int prot, gfp_t gfp, size_t *mapped) 7820df4fabeSYong Wu { 7830df4fabeSYong Wu struct mtk_iommu_domain *dom = to_mtk_domain(domain); 7840df4fabeSYong Wu 785b4dad40eSYong Wu /* The "4GB mode" M4U physically can not use the lower remap of Dram. */ 78699ca0228SYong Wu if (dom->bank->parent_data->enable_4GB) 787b4dad40eSYong Wu paddr |= BIT_ULL(32); 788b4dad40eSYong Wu 78960829b4dSYong Wu /* Synchronize with the tlb_lock */ 79085637380SRobin Murphy return dom->iop->map_pages(dom->iop, iova, paddr, pgsize, pgcount, prot, gfp, mapped); 7910df4fabeSYong Wu } 7920df4fabeSYong Wu 7930df4fabeSYong Wu static size_t mtk_iommu_unmap(struct iommu_domain *domain, 79485637380SRobin Murphy unsigned long iova, size_t pgsize, size_t pgcount, 79556f8af5eSWill Deacon struct iommu_iotlb_gather *gather) 7960df4fabeSYong Wu { 7970df4fabeSYong Wu struct mtk_iommu_domain *dom = to_mtk_domain(domain); 7980df4fabeSYong Wu 79985637380SRobin Murphy iommu_iotlb_gather_add_range(gather, iova, pgsize * pgcount); 80085637380SRobin Murphy return dom->iop->unmap_pages(dom->iop, iova, pgsize, pgcount, gather); 8010df4fabeSYong Wu } 8020df4fabeSYong Wu 80356f8af5eSWill Deacon static void mtk_iommu_flush_iotlb_all(struct iommu_domain *domain) 80456f8af5eSWill Deacon { 80508500c43SYong Wu struct mtk_iommu_domain *dom = to_mtk_domain(domain); 80608500c43SYong Wu 807b3fc9570SChen-Yu Tsai if (dom->bank) 80899ca0228SYong Wu mtk_iommu_tlb_flush_all(dom->bank->parent_data); 80956f8af5eSWill Deacon } 81056f8af5eSWill Deacon 81156f8af5eSWill Deacon static void mtk_iommu_iotlb_sync(struct iommu_domain *domain, 81256f8af5eSWill Deacon struct iommu_iotlb_gather *gather) 8134d689b61SRobin Murphy { 81408500c43SYong Wu struct mtk_iommu_domain *dom = to_mtk_domain(domain); 815862c3715SYong Wu size_t length = gather->end - gather->start + 1; 816da3cc91bSYong Wu 81799ca0228SYong Wu mtk_iommu_tlb_flush_range_sync(gather->start, length, dom->bank); 8184d689b61SRobin Murphy } 8194d689b61SRobin Murphy 82020143451SYong Wu static void mtk_iommu_sync_map(struct iommu_domain *domain, unsigned long iova, 82120143451SYong Wu size_t size) 82220143451SYong Wu { 82308500c43SYong Wu struct mtk_iommu_domain *dom = to_mtk_domain(domain); 82420143451SYong Wu 82599ca0228SYong Wu mtk_iommu_tlb_flush_range_sync(iova, size, dom->bank); 82620143451SYong Wu } 82720143451SYong Wu 8280df4fabeSYong Wu static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain, 8290df4fabeSYong Wu dma_addr_t iova) 8300df4fabeSYong Wu { 8310df4fabeSYong Wu struct mtk_iommu_domain *dom = to_mtk_domain(domain); 8320df4fabeSYong Wu phys_addr_t pa; 8330df4fabeSYong Wu 8340df4fabeSYong Wu pa = dom->iop->iova_to_phys(dom->iop, iova); 835f13efafcSArnd Bergmann if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) && 83699ca0228SYong Wu dom->bank->parent_data->enable_4GB && 837f13efafcSArnd Bergmann pa >= MTK_IOMMU_4GB_MODE_REMAP_BASE) 838b4dad40eSYong Wu pa &= ~BIT_ULL(32); 83930e2fccfSYong Wu 8400df4fabeSYong Wu return pa; 8410df4fabeSYong Wu } 8420df4fabeSYong Wu 84380e4592aSJoerg Roedel static struct iommu_device *mtk_iommu_probe_device(struct device *dev) 8440df4fabeSYong Wu { 845a9bf2eecSJoerg Roedel struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 846b16c0170SJoerg Roedel struct mtk_iommu_data *data; 847635319a4SYong Wu struct device_link *link; 848635319a4SYong Wu struct device *larbdev; 849635319a4SYong Wu unsigned int larbid, larbidx, i; 8500df4fabeSYong Wu 851a9bf2eecSJoerg Roedel if (!fwspec || fwspec->ops != &mtk_iommu_ops) 85280e4592aSJoerg Roedel return ERR_PTR(-ENODEV); /* Not a iommu client device */ 8530df4fabeSYong Wu 8543524b559SJoerg Roedel data = dev_iommu_priv_get(dev); 855b16c0170SJoerg Roedel 856d2e9a110SYong Wu if (!MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) 857d2e9a110SYong Wu return &data->iommu; 858d2e9a110SYong Wu 859635319a4SYong Wu /* 860635319a4SYong Wu * Link the consumer device with the smi-larb device(supplier). 861635319a4SYong Wu * The device that connects with each a larb is a independent HW. 862635319a4SYong Wu * All the ports in each a device should be in the same larbs. 863635319a4SYong Wu */ 864635319a4SYong Wu larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); 865de78657eSMiles Chen if (larbid >= MTK_LARB_NR_MAX) 866de78657eSMiles Chen return ERR_PTR(-EINVAL); 867de78657eSMiles Chen 868635319a4SYong Wu for (i = 1; i < fwspec->num_ids; i++) { 869635319a4SYong Wu larbidx = MTK_M4U_TO_LARB(fwspec->ids[i]); 870635319a4SYong Wu if (larbid != larbidx) { 871635319a4SYong Wu dev_err(dev, "Can only use one larb. Fail@larb%d-%d.\n", 872635319a4SYong Wu larbid, larbidx); 873635319a4SYong Wu return ERR_PTR(-EINVAL); 874635319a4SYong Wu } 875635319a4SYong Wu } 876635319a4SYong Wu larbdev = data->larb_imu[larbid].dev; 877de78657eSMiles Chen if (!larbdev) 878de78657eSMiles Chen return ERR_PTR(-EINVAL); 879de78657eSMiles Chen 880635319a4SYong Wu link = device_link_add(dev, larbdev, 881635319a4SYong Wu DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS); 882635319a4SYong Wu if (!link) 883635319a4SYong Wu dev_err(dev, "Unable to link %s\n", dev_name(larbdev)); 88480e4592aSJoerg Roedel return &data->iommu; 8850df4fabeSYong Wu } 8860df4fabeSYong Wu 88780e4592aSJoerg Roedel static void mtk_iommu_release_device(struct device *dev) 8880df4fabeSYong Wu { 889a9bf2eecSJoerg Roedel struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 890635319a4SYong Wu struct mtk_iommu_data *data; 891635319a4SYong Wu struct device *larbdev; 892635319a4SYong Wu unsigned int larbid; 893b16c0170SJoerg Roedel 894635319a4SYong Wu data = dev_iommu_priv_get(dev); 895d2e9a110SYong Wu if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { 896635319a4SYong Wu larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); 897635319a4SYong Wu larbdev = data->larb_imu[larbid].dev; 898635319a4SYong Wu device_link_remove(dev, larbdev); 899d2e9a110SYong Wu } 9000df4fabeSYong Wu } 9010df4fabeSYong Wu 90257fb481fSYong Wu static int mtk_iommu_get_group_id(struct device *dev, const struct mtk_iommu_plat_data *plat_data) 90357fb481fSYong Wu { 90457fb481fSYong Wu unsigned int bankid; 90557fb481fSYong Wu 90657fb481fSYong Wu /* 90757fb481fSYong Wu * If the bank function is enabled, each bank is a iommu group/domain. 90857fb481fSYong Wu * Otherwise, each iova region is a iommu group/domain. 90957fb481fSYong Wu */ 91057fb481fSYong Wu bankid = mtk_iommu_get_bank_id(dev, plat_data); 91157fb481fSYong Wu if (bankid) 91257fb481fSYong Wu return bankid; 91357fb481fSYong Wu 91457fb481fSYong Wu return mtk_iommu_get_iova_region_id(dev, plat_data); 91557fb481fSYong Wu } 91657fb481fSYong Wu 9170df4fabeSYong Wu static struct iommu_group *mtk_iommu_device_group(struct device *dev) 9180df4fabeSYong Wu { 9199e3a2a64SYong Wu struct mtk_iommu_data *c_data = dev_iommu_priv_get(dev), *data; 9209e3a2a64SYong Wu struct list_head *hw_list = c_data->hw_list; 921c3045f39SYong Wu struct iommu_group *group; 92257fb481fSYong Wu int groupid; 9230df4fabeSYong Wu 9249e3a2a64SYong Wu data = mtk_iommu_get_frst_data(hw_list); 92558f0d1d5SRobin Murphy if (!data) 9260df4fabeSYong Wu return ERR_PTR(-ENODEV); 9270df4fabeSYong Wu 92857fb481fSYong Wu groupid = mtk_iommu_get_group_id(dev, data->plat_data); 92957fb481fSYong Wu if (groupid < 0) 93057fb481fSYong Wu return ERR_PTR(groupid); 931803cf9e5SYong Wu 9320e5a3f2eSYong Wu mutex_lock(&data->mutex); 93357fb481fSYong Wu group = data->m4u_group[groupid]; 934c3045f39SYong Wu if (!group) { 935c3045f39SYong Wu group = iommu_group_alloc(); 936c3045f39SYong Wu if (!IS_ERR(group)) 93757fb481fSYong Wu data->m4u_group[groupid] = group; 9383a8d40b6SRobin Murphy } else { 939c3045f39SYong Wu iommu_group_ref_get(group); 9400df4fabeSYong Wu } 9410e5a3f2eSYong Wu mutex_unlock(&data->mutex); 942c3045f39SYong Wu return group; 9430df4fabeSYong Wu } 9440df4fabeSYong Wu 9450df4fabeSYong Wu static int mtk_iommu_of_xlate(struct device *dev, struct of_phandle_args *args) 9460df4fabeSYong Wu { 9470df4fabeSYong Wu struct platform_device *m4updev; 9480df4fabeSYong Wu 9490df4fabeSYong Wu if (args->args_count != 1) { 9500df4fabeSYong Wu dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n", 9510df4fabeSYong Wu args->args_count); 9520df4fabeSYong Wu return -EINVAL; 9530df4fabeSYong Wu } 9540df4fabeSYong Wu 9553524b559SJoerg Roedel if (!dev_iommu_priv_get(dev)) { 9560df4fabeSYong Wu /* Get the m4u device */ 9570df4fabeSYong Wu m4updev = of_find_device_by_node(args->np); 9580df4fabeSYong Wu if (WARN_ON(!m4updev)) 9590df4fabeSYong Wu return -EINVAL; 9600df4fabeSYong Wu 9613524b559SJoerg Roedel dev_iommu_priv_set(dev, platform_get_drvdata(m4updev)); 9620df4fabeSYong Wu } 9630df4fabeSYong Wu 96458f0d1d5SRobin Murphy return iommu_fwspec_add_ids(dev, args->args, 1); 9650df4fabeSYong Wu } 9660df4fabeSYong Wu 967ab1d5281SYong Wu static void mtk_iommu_get_resv_regions(struct device *dev, 968ab1d5281SYong Wu struct list_head *head) 969ab1d5281SYong Wu { 970ab1d5281SYong Wu struct mtk_iommu_data *data = dev_iommu_priv_get(dev); 971d72e0ff5SYong Wu unsigned int regionid = mtk_iommu_get_iova_region_id(dev, data->plat_data), i; 972ab1d5281SYong Wu const struct mtk_iommu_iova_region *resv, *curdom; 973ab1d5281SYong Wu struct iommu_resv_region *region; 974ab1d5281SYong Wu int prot = IOMMU_WRITE | IOMMU_READ; 975ab1d5281SYong Wu 976d72e0ff5SYong Wu if ((int)regionid < 0) 977ab1d5281SYong Wu return; 978d72e0ff5SYong Wu curdom = data->plat_data->iova_region + regionid; 979ab1d5281SYong Wu for (i = 0; i < data->plat_data->iova_region_nr; i++) { 980ab1d5281SYong Wu resv = data->plat_data->iova_region + i; 981ab1d5281SYong Wu 982ab1d5281SYong Wu /* Only reserve when the region is inside the current domain */ 983ab1d5281SYong Wu if (resv->iova_base <= curdom->iova_base || 984ab1d5281SYong Wu resv->iova_base + resv->size >= curdom->iova_base + curdom->size) 985ab1d5281SYong Wu continue; 986ab1d5281SYong Wu 987ab1d5281SYong Wu region = iommu_alloc_resv_region(resv->iova_base, resv->size, 9880251d010SLu Baolu prot, IOMMU_RESV_RESERVED, 9890251d010SLu Baolu GFP_KERNEL); 990ab1d5281SYong Wu if (!region) 991ab1d5281SYong Wu return; 992ab1d5281SYong Wu 993ab1d5281SYong Wu list_add_tail(®ion->list, head); 994ab1d5281SYong Wu } 995ab1d5281SYong Wu } 996ab1d5281SYong Wu 997b65f5016SArvind Yadav static const struct iommu_ops mtk_iommu_ops = { 9980df4fabeSYong Wu .domain_alloc = mtk_iommu_domain_alloc, 99980e4592aSJoerg Roedel .probe_device = mtk_iommu_probe_device, 100080e4592aSJoerg Roedel .release_device = mtk_iommu_release_device, 10010df4fabeSYong Wu .device_group = mtk_iommu_device_group, 10020df4fabeSYong Wu .of_xlate = mtk_iommu_of_xlate, 1003ab1d5281SYong Wu .get_resv_regions = mtk_iommu_get_resv_regions, 10040df4fabeSYong Wu .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M, 100518d8c74eSYong Wu .owner = THIS_MODULE, 10069a630a4bSLu Baolu .default_domain_ops = &(const struct iommu_domain_ops) { 10079a630a4bSLu Baolu .attach_dev = mtk_iommu_attach_device, 100885637380SRobin Murphy .map_pages = mtk_iommu_map, 100985637380SRobin Murphy .unmap_pages = mtk_iommu_unmap, 10109a630a4bSLu Baolu .flush_iotlb_all = mtk_iommu_flush_iotlb_all, 10119a630a4bSLu Baolu .iotlb_sync = mtk_iommu_iotlb_sync, 10129a630a4bSLu Baolu .iotlb_sync_map = mtk_iommu_sync_map, 10139a630a4bSLu Baolu .iova_to_phys = mtk_iommu_iova_to_phys, 10149a630a4bSLu Baolu .free = mtk_iommu_domain_free, 10159a630a4bSLu Baolu } 10160df4fabeSYong Wu }; 10170df4fabeSYong Wu 1018e24453e1SYong Wu static int mtk_iommu_hw_init(const struct mtk_iommu_data *data, unsigned int bankid) 10190df4fabeSYong Wu { 1020e24453e1SYong Wu const struct mtk_iommu_bank_data *bankx = &data->bank[bankid]; 102199ca0228SYong Wu const struct mtk_iommu_bank_data *bank0 = &data->bank[0]; 10220df4fabeSYong Wu u32 regval; 10230df4fabeSYong Wu 1024e24453e1SYong Wu /* 1025e24453e1SYong Wu * Global control settings are in bank0. May re-init these global registers 1026e24453e1SYong Wu * since no sure if there is bank0 consumers. 1027e24453e1SYong Wu */ 102886580ec9SAngeloGioacchino Del Regno if (MTK_IOMMU_HAS_FLAG(data->plat_data, TF_PORT_TO_ADDR_MT8173)) { 1029acb3c92aSYong Wu regval = F_MMU_PREFETCH_RT_REPLACE_MOD | 1030acb3c92aSYong Wu F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173; 103186444413SChao Hao } else { 103299ca0228SYong Wu regval = readl_relaxed(bank0->base + REG_MMU_CTRL_REG); 103386444413SChao Hao regval |= F_MMU_TF_PROT_TO_PROGRAM_ADDR; 103486444413SChao Hao } 103599ca0228SYong Wu writel_relaxed(regval, bank0->base + REG_MMU_CTRL_REG); 10360df4fabeSYong Wu 10376b717796SChao Hao if (data->enable_4GB && 10386b717796SChao Hao MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_VLD_PA_RNG)) { 103930e2fccfSYong Wu /* 104030e2fccfSYong Wu * If 4GB mode is enabled, the validate PA range is from 104130e2fccfSYong Wu * 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30]. 104230e2fccfSYong Wu */ 104330e2fccfSYong Wu regval = F_MMU_VLD_PA_RNG(7, 4); 104499ca0228SYong Wu writel_relaxed(regval, bank0->base + REG_MMU_VLD_PA_RNG); 104530e2fccfSYong Wu } 10469a87005eSYong Wu if (MTK_IOMMU_HAS_FLAG(data->plat_data, DCM_DISABLE)) 104799ca0228SYong Wu writel_relaxed(F_MMU_DCM, bank0->base + REG_MMU_DCM_DIS); 10489a87005eSYong Wu else 104999ca0228SYong Wu writel_relaxed(0, bank0->base + REG_MMU_DCM_DIS); 10509a87005eSYong Wu 105135c1b48dSChao Hao if (MTK_IOMMU_HAS_FLAG(data->plat_data, WR_THROT_EN)) { 105235c1b48dSChao Hao /* write command throttling mode */ 105399ca0228SYong Wu regval = readl_relaxed(bank0->base + REG_MMU_WR_LEN_CTRL); 105435c1b48dSChao Hao regval &= ~F_MMU_WR_THROT_DIS_MASK; 105599ca0228SYong Wu writel_relaxed(regval, bank0->base + REG_MMU_WR_LEN_CTRL); 105635c1b48dSChao Hao } 1057e6dec923SYong Wu 10586b717796SChao Hao if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) { 105975eed350SChao Hao /* The register is called STANDARD_AXI_MODE in this case */ 10604bb2bf4cSChao Hao regval = 0; 10614bb2bf4cSChao Hao } else { 106299ca0228SYong Wu regval = readl_relaxed(bank0->base + REG_MMU_MISC_CTRL); 1063d265a4adSYong Wu if (!MTK_IOMMU_HAS_FLAG(data->plat_data, STD_AXI_MODE)) 10644bb2bf4cSChao Hao regval &= ~F_MMU_STANDARD_AXI_MODE_MASK; 10654bb2bf4cSChao Hao if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_WR_EN)) 10664bb2bf4cSChao Hao regval &= ~F_MMU_IN_ORDER_WR_EN_MASK; 106775eed350SChao Hao } 106899ca0228SYong Wu writel_relaxed(regval, bank0->base + REG_MMU_MISC_CTRL); 10690df4fabeSYong Wu 1070e24453e1SYong Wu /* Independent settings for each bank */ 1071634f57dfSYong Wu regval = F_L2_MULIT_HIT_EN | 1072634f57dfSYong Wu F_TABLE_WALK_FAULT_INT_EN | 1073634f57dfSYong Wu F_PREETCH_FIFO_OVERFLOW_INT_EN | 1074634f57dfSYong Wu F_MISS_FIFO_OVERFLOW_INT_EN | 1075634f57dfSYong Wu F_PREFETCH_FIFO_ERR_INT_EN | 1076634f57dfSYong Wu F_MISS_FIFO_ERR_INT_EN; 1077e24453e1SYong Wu writel_relaxed(regval, bankx->base + REG_MMU_INT_CONTROL0); 1078634f57dfSYong Wu 1079634f57dfSYong Wu regval = F_INT_TRANSLATION_FAULT | 1080634f57dfSYong Wu F_INT_MAIN_MULTI_HIT_FAULT | 1081634f57dfSYong Wu F_INT_INVALID_PA_FAULT | 1082634f57dfSYong Wu F_INT_ENTRY_REPLACEMENT_FAULT | 1083634f57dfSYong Wu F_INT_TLB_MISS_FAULT | 1084634f57dfSYong Wu F_INT_MISS_TRANSACTION_FIFO_FAULT | 1085634f57dfSYong Wu F_INT_PRETETCH_TRANSATION_FIFO_FAULT; 1086e24453e1SYong Wu writel_relaxed(regval, bankx->base + REG_MMU_INT_MAIN_CONTROL); 1087634f57dfSYong Wu 1088634f57dfSYong Wu if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_LEGACY_IVRP_PADDR)) 1089634f57dfSYong Wu regval = (data->protect_base >> 1) | (data->enable_4GB << 31); 1090634f57dfSYong Wu else 1091634f57dfSYong Wu regval = lower_32_bits(data->protect_base) | 1092634f57dfSYong Wu upper_32_bits(data->protect_base); 1093e24453e1SYong Wu writel_relaxed(regval, bankx->base + REG_MMU_IVRP_PADDR); 1094634f57dfSYong Wu 1095e24453e1SYong Wu if (devm_request_irq(bankx->parent_dev, bankx->irq, mtk_iommu_isr, 0, 1096e24453e1SYong Wu dev_name(bankx->parent_dev), (void *)bankx)) { 1097e24453e1SYong Wu writel_relaxed(0, bankx->base + REG_MMU_PT_BASE_ADDR); 1098e24453e1SYong Wu dev_err(bankx->parent_dev, "Failed @ IRQ-%d Request\n", bankx->irq); 10990df4fabeSYong Wu return -ENODEV; 11000df4fabeSYong Wu } 11010df4fabeSYong Wu 11020df4fabeSYong Wu return 0; 11030df4fabeSYong Wu } 11040df4fabeSYong Wu 11050df4fabeSYong Wu static const struct component_master_ops mtk_iommu_com_ops = { 11060df4fabeSYong Wu .bind = mtk_iommu_bind, 11070df4fabeSYong Wu .unbind = mtk_iommu_unbind, 11080df4fabeSYong Wu }; 11090df4fabeSYong Wu 1110d2e9a110SYong Wu static int mtk_iommu_mm_dts_parse(struct device *dev, struct component_match **match, 1111d2e9a110SYong Wu struct mtk_iommu_data *data) 1112d2e9a110SYong Wu { 11136cde583dSYong Wu struct device_node *larbnode, *frst_avail_smicomm_node = NULL; 1114dcb40e9fSYong Wu struct platform_device *plarbdev, *pcommdev; 1115d2e9a110SYong Wu struct device_link *link; 1116d2e9a110SYong Wu int i, larb_nr, ret; 1117d2e9a110SYong Wu 1118d2e9a110SYong Wu larb_nr = of_count_phandle_with_args(dev->of_node, "mediatek,larbs", NULL); 1119d2e9a110SYong Wu if (larb_nr < 0) 1120d2e9a110SYong Wu return larb_nr; 1121ef693a84SGuenter Roeck if (larb_nr == 0 || larb_nr > MTK_LARB_NR_MAX) 1122ef693a84SGuenter Roeck return -EINVAL; 1123d2e9a110SYong Wu 1124d2e9a110SYong Wu for (i = 0; i < larb_nr; i++) { 11256cde583dSYong Wu struct device_node *smicomm_node, *smi_subcomm_node; 1126d2e9a110SYong Wu u32 id; 1127d2e9a110SYong Wu 1128d2e9a110SYong Wu larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i); 112926593928SYong Wu if (!larbnode) { 113026593928SYong Wu ret = -EINVAL; 113126593928SYong Wu goto err_larbdev_put; 113226593928SYong Wu } 1133d2e9a110SYong Wu 1134d2e9a110SYong Wu if (!of_device_is_available(larbnode)) { 1135d2e9a110SYong Wu of_node_put(larbnode); 1136d2e9a110SYong Wu continue; 1137d2e9a110SYong Wu } 1138d2e9a110SYong Wu 1139d2e9a110SYong Wu ret = of_property_read_u32(larbnode, "mediatek,larb-id", &id); 1140d2e9a110SYong Wu if (ret)/* The id is consecutive if there is no this property */ 1141d2e9a110SYong Wu id = i; 1142ef693a84SGuenter Roeck if (id >= MTK_LARB_NR_MAX) { 1143ef693a84SGuenter Roeck of_node_put(larbnode); 1144ef693a84SGuenter Roeck ret = -EINVAL; 1145ef693a84SGuenter Roeck goto err_larbdev_put; 1146ef693a84SGuenter Roeck } 1147d2e9a110SYong Wu 1148d2e9a110SYong Wu plarbdev = of_find_device_by_node(larbnode); 1149d2e9a110SYong Wu of_node_put(larbnode); 1150d2e9a110SYong Wu if (!plarbdev) { 115126593928SYong Wu ret = -ENODEV; 115226593928SYong Wu goto err_larbdev_put; 1153d2e9a110SYong Wu } 1154ef693a84SGuenter Roeck if (data->larb_imu[id].dev) { 1155ef693a84SGuenter Roeck platform_device_put(plarbdev); 1156ef693a84SGuenter Roeck ret = -EEXIST; 1157ef693a84SGuenter Roeck goto err_larbdev_put; 1158d2e9a110SYong Wu } 1159d2e9a110SYong Wu data->larb_imu[id].dev = &plarbdev->dev; 1160d2e9a110SYong Wu 116126593928SYong Wu if (!plarbdev->dev.driver) { 116226593928SYong Wu ret = -EPROBE_DEFER; 116326593928SYong Wu goto err_larbdev_put; 1164d2e9a110SYong Wu } 1165d2e9a110SYong Wu 1166f7b71d0dSYong Wu /* Get smi-(sub)-common dev from the last larb. */ 1167f7b71d0dSYong Wu smi_subcomm_node = of_parse_phandle(larbnode, "mediatek,smi", 0); 11686cde583dSYong Wu if (!smi_subcomm_node) { 11696cde583dSYong Wu ret = -EINVAL; 11706cde583dSYong Wu goto err_larbdev_put; 11716cde583dSYong Wu } 1172d2e9a110SYong Wu 1173f7b71d0dSYong Wu /* 1174f7b71d0dSYong Wu * It may have two level smi-common. the node is smi-sub-common if it 1175f7b71d0dSYong Wu * has a new mediatek,smi property. otherwise it is smi-commmon. 1176f7b71d0dSYong Wu */ 1177f7b71d0dSYong Wu smicomm_node = of_parse_phandle(smi_subcomm_node, "mediatek,smi", 0); 1178f7b71d0dSYong Wu if (smicomm_node) 1179f7b71d0dSYong Wu of_node_put(smi_subcomm_node); 1180f7b71d0dSYong Wu else 1181f7b71d0dSYong Wu smicomm_node = smi_subcomm_node; 1182f7b71d0dSYong Wu 11836cde583dSYong Wu /* 11846cde583dSYong Wu * All the larbs that connect to one IOMMU must connect with the same 11856cde583dSYong Wu * smi-common. 11866cde583dSYong Wu */ 11876cde583dSYong Wu if (!frst_avail_smicomm_node) { 11886cde583dSYong Wu frst_avail_smicomm_node = smicomm_node; 11896cde583dSYong Wu } else if (frst_avail_smicomm_node != smicomm_node) { 11906cde583dSYong Wu dev_err(dev, "mediatek,smi property is not right @larb%d.", id); 1191d2e9a110SYong Wu of_node_put(smicomm_node); 11926cde583dSYong Wu ret = -EINVAL; 11936cde583dSYong Wu goto err_larbdev_put; 11946cde583dSYong Wu } else { 11956cde583dSYong Wu of_node_put(smicomm_node); 11966cde583dSYong Wu } 11976cde583dSYong Wu 11986cde583dSYong Wu component_match_add(dev, match, component_compare_dev, &plarbdev->dev); 11996cde583dSYong Wu platform_device_put(plarbdev); 12006cde583dSYong Wu } 12016cde583dSYong Wu 12026cde583dSYong Wu if (!frst_avail_smicomm_node) 12036cde583dSYong Wu return -EINVAL; 12046cde583dSYong Wu 12056cde583dSYong Wu pcommdev = of_find_device_by_node(frst_avail_smicomm_node); 12066cde583dSYong Wu of_node_put(frst_avail_smicomm_node); 1207dcb40e9fSYong Wu if (!pcommdev) 1208dcb40e9fSYong Wu return -ENODEV; 1209dcb40e9fSYong Wu data->smicomm_dev = &pcommdev->dev; 1210d2e9a110SYong Wu 1211d2e9a110SYong Wu link = device_link_add(data->smicomm_dev, dev, 1212d2e9a110SYong Wu DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME); 1213dcb40e9fSYong Wu platform_device_put(pcommdev); 1214d2e9a110SYong Wu if (!link) { 1215d2e9a110SYong Wu dev_err(dev, "Unable to link %s.\n", dev_name(data->smicomm_dev)); 1216d2e9a110SYong Wu return -EINVAL; 1217d2e9a110SYong Wu } 1218d2e9a110SYong Wu return 0; 121926593928SYong Wu 122026593928SYong Wu err_larbdev_put: 1221462e768bSDan Carpenter for (i = MTK_LARB_NR_MAX - 1; i >= 0; i--) { 122226593928SYong Wu if (!data->larb_imu[i].dev) 122326593928SYong Wu continue; 122426593928SYong Wu put_device(data->larb_imu[i].dev); 122526593928SYong Wu } 122626593928SYong Wu return ret; 1227d2e9a110SYong Wu } 1228d2e9a110SYong Wu 12290df4fabeSYong Wu static int mtk_iommu_probe(struct platform_device *pdev) 12300df4fabeSYong Wu { 12310df4fabeSYong Wu struct mtk_iommu_data *data; 12320df4fabeSYong Wu struct device *dev = &pdev->dev; 12330df4fabeSYong Wu struct resource *res; 1234b16c0170SJoerg Roedel resource_size_t ioaddr; 12350df4fabeSYong Wu struct component_match *match = NULL; 1236c2c59456SMiles Chen struct regmap *infracfg; 12370df4fabeSYong Wu void *protect; 123842d57fc5SYong Wu int ret, banks_num, i = 0; 1239c2c59456SMiles Chen u32 val; 1240c2c59456SMiles Chen char *p; 124199ca0228SYong Wu struct mtk_iommu_bank_data *bank; 124299ca0228SYong Wu void __iomem *base; 12430df4fabeSYong Wu 12440df4fabeSYong Wu data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 12450df4fabeSYong Wu if (!data) 12460df4fabeSYong Wu return -ENOMEM; 12470df4fabeSYong Wu data->dev = dev; 1248cecdce9dSYong Wu data->plat_data = of_device_get_match_data(dev); 12490df4fabeSYong Wu 12500df4fabeSYong Wu /* Protect memory. HW will access here while translation fault.*/ 12510df4fabeSYong Wu protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2, GFP_KERNEL); 12520df4fabeSYong Wu if (!protect) 12530df4fabeSYong Wu return -ENOMEM; 12540df4fabeSYong Wu data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN); 12550df4fabeSYong Wu 1256c2c59456SMiles Chen if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) { 12577d748ffdSAngeloGioacchino Del Regno infracfg = syscon_regmap_lookup_by_phandle(dev->of_node, "mediatek,infracfg"); 12587d748ffdSAngeloGioacchino Del Regno if (IS_ERR(infracfg)) { 12597d748ffdSAngeloGioacchino Del Regno /* 12607d748ffdSAngeloGioacchino Del Regno * Legacy devicetrees will not specify a phandle to 12617d748ffdSAngeloGioacchino Del Regno * mediatek,infracfg: in that case, we use the older 12627d748ffdSAngeloGioacchino Del Regno * way to retrieve a syscon to infra. 12637d748ffdSAngeloGioacchino Del Regno * 12647d748ffdSAngeloGioacchino Del Regno * This is for retrocompatibility purposes only, hence 12657d748ffdSAngeloGioacchino Del Regno * no more compatibles shall be added to this. 12667d748ffdSAngeloGioacchino Del Regno */ 1267c2c59456SMiles Chen switch (data->plat_data->m4u_plat) { 1268c2c59456SMiles Chen case M4U_MT2712: 1269c2c59456SMiles Chen p = "mediatek,mt2712-infracfg"; 1270c2c59456SMiles Chen break; 1271c2c59456SMiles Chen case M4U_MT8173: 1272c2c59456SMiles Chen p = "mediatek,mt8173-infracfg"; 1273c2c59456SMiles Chen break; 1274c2c59456SMiles Chen default: 1275c2c59456SMiles Chen p = NULL; 1276c2c59456SMiles Chen } 1277c2c59456SMiles Chen 1278c2c59456SMiles Chen infracfg = syscon_regmap_lookup_by_compatible(p); 1279c2c59456SMiles Chen if (IS_ERR(infracfg)) 1280c2c59456SMiles Chen return PTR_ERR(infracfg); 12817d748ffdSAngeloGioacchino Del Regno } 1282c2c59456SMiles Chen 1283c2c59456SMiles Chen ret = regmap_read(infracfg, REG_INFRA_MISC, &val); 1284c2c59456SMiles Chen if (ret) 1285c2c59456SMiles Chen return ret; 1286c2c59456SMiles Chen data->enable_4GB = !!(val & F_DDR_4GB_SUPPORT_EN); 1287c2c59456SMiles Chen } 128801e23c93SYong Wu 128942d57fc5SYong Wu banks_num = data->plat_data->banks_num; 12900df4fabeSYong Wu res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 129173b6924cSYang Yingliang if (!res) 129273b6924cSYang Yingliang return -EINVAL; 129342d57fc5SYong Wu if (resource_size(res) < banks_num * MTK_IOMMU_BANK_SZ) { 129442d57fc5SYong Wu dev_err(dev, "banknr %d. res %pR is not enough.\n", banks_num, res); 129542d57fc5SYong Wu return -EINVAL; 129642d57fc5SYong Wu } 129799ca0228SYong Wu base = devm_ioremap_resource(dev, res); 129899ca0228SYong Wu if (IS_ERR(base)) 129999ca0228SYong Wu return PTR_ERR(base); 1300b16c0170SJoerg Roedel ioaddr = res->start; 13010df4fabeSYong Wu 130299ca0228SYong Wu data->bank = devm_kmalloc(dev, banks_num * sizeof(*data->bank), GFP_KERNEL); 130399ca0228SYong Wu if (!data->bank) 130499ca0228SYong Wu return -ENOMEM; 130599ca0228SYong Wu 130642d57fc5SYong Wu do { 130742d57fc5SYong Wu if (!data->plat_data->banks_enable[i]) 130842d57fc5SYong Wu continue; 130942d57fc5SYong Wu bank = &data->bank[i]; 131042d57fc5SYong Wu bank->id = i; 131142d57fc5SYong Wu bank->base = base + i * MTK_IOMMU_BANK_SZ; 131299ca0228SYong Wu bank->m4u_dom = NULL; 131342d57fc5SYong Wu 131442d57fc5SYong Wu bank->irq = platform_get_irq(pdev, i); 131599ca0228SYong Wu if (bank->irq < 0) 131699ca0228SYong Wu return bank->irq; 131799ca0228SYong Wu bank->parent_dev = dev; 131899ca0228SYong Wu bank->parent_data = data; 131999ca0228SYong Wu spin_lock_init(&bank->tlb_lock); 132042d57fc5SYong Wu } while (++i < banks_num); 13210df4fabeSYong Wu 13226b717796SChao Hao if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_BCLK)) { 13230df4fabeSYong Wu data->bclk = devm_clk_get(dev, "bclk"); 13240df4fabeSYong Wu if (IS_ERR(data->bclk)) 13250df4fabeSYong Wu return PTR_ERR(data->bclk); 13262aa4c259SYong Wu } 13270df4fabeSYong Wu 1328f045e9dfSYong Wu if (MTK_IOMMU_HAS_FLAG(data->plat_data, PGTABLE_PA_35_EN)) { 1329f045e9dfSYong Wu ret = dma_set_mask(dev, DMA_BIT_MASK(35)); 1330f045e9dfSYong Wu if (ret) { 1331f045e9dfSYong Wu dev_err(dev, "Failed to set dma_mask 35.\n"); 1332f045e9dfSYong Wu return ret; 1333f045e9dfSYong Wu } 1334f045e9dfSYong Wu } 1335f045e9dfSYong Wu 1336c0b57581SYong Wu pm_runtime_enable(dev); 1337c0b57581SYong Wu 1338d2e9a110SYong Wu if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { 1339d2e9a110SYong Wu ret = mtk_iommu_mm_dts_parse(dev, &match, data); 1340d2e9a110SYong Wu if (ret) { 13413168010dSNícolas F. R. A. Prado dev_err_probe(dev, ret, "mm dts parse fail\n"); 1342c0b57581SYong Wu goto out_runtime_disable; 1343baf94e6eSYong Wu } 1344946e719cSChengci.Xu } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA) && 1345946e719cSChengci.Xu !MTK_IOMMU_HAS_FLAG(data->plat_data, CFG_IFA_MASTER_IN_ATF)) { 134621fd9be4SAngeloGioacchino Del Regno p = data->plat_data->pericfg_comp_str; 134721fd9be4SAngeloGioacchino Del Regno data->pericfg = syscon_regmap_lookup_by_compatible(p); 134821fd9be4SAngeloGioacchino Del Regno if (IS_ERR(data->pericfg)) { 134921fd9be4SAngeloGioacchino Del Regno ret = PTR_ERR(data->pericfg); 1350f9b8c9b2SYong Wu goto out_runtime_disable; 1351f9b8c9b2SYong Wu } 1352d2e9a110SYong Wu } 1353baf94e6eSYong Wu 13540df4fabeSYong Wu platform_set_drvdata(pdev, data); 13550e5a3f2eSYong Wu mutex_init(&data->mutex); 13560df4fabeSYong Wu 1357b16c0170SJoerg Roedel ret = iommu_device_sysfs_add(&data->iommu, dev, NULL, 1358b16c0170SJoerg Roedel "mtk-iommu.%pa", &ioaddr); 1359b16c0170SJoerg Roedel if (ret) 1360baf94e6eSYong Wu goto out_link_remove; 1361b16c0170SJoerg Roedel 13622d471b20SRobin Murphy ret = iommu_device_register(&data->iommu, &mtk_iommu_ops, dev); 1363b16c0170SJoerg Roedel if (ret) 1364986d9ec5SYong Wu goto out_sysfs_remove; 1365b16c0170SJoerg Roedel 13669e3a2a64SYong Wu if (MTK_IOMMU_HAS_FLAG(data->plat_data, SHARE_PGTABLE)) { 13679e3a2a64SYong Wu list_add_tail(&data->list, data->plat_data->hw_list); 13689e3a2a64SYong Wu data->hw_list = data->plat_data->hw_list; 13699e3a2a64SYong Wu } else { 13709e3a2a64SYong Wu INIT_LIST_HEAD(&data->hw_list_head); 13719e3a2a64SYong Wu list_add_tail(&data->list, &data->hw_list_head); 13729e3a2a64SYong Wu data->hw_list = &data->hw_list_head; 13739e3a2a64SYong Wu } 13747c3a2ec0SYong Wu 1375d2e9a110SYong Wu if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { 1376986d9ec5SYong Wu ret = component_master_add_with_match(dev, &mtk_iommu_com_ops, match); 1377986d9ec5SYong Wu if (ret) 1378e7629070SYong Wu goto out_list_del; 1379e7629070SYong Wu } 1380986d9ec5SYong Wu return ret; 1381986d9ec5SYong Wu 1382986d9ec5SYong Wu out_list_del: 1383986d9ec5SYong Wu list_del(&data->list); 1384986d9ec5SYong Wu iommu_device_unregister(&data->iommu); 1385986d9ec5SYong Wu out_sysfs_remove: 1386986d9ec5SYong Wu iommu_device_sysfs_remove(&data->iommu); 1387baf94e6eSYong Wu out_link_remove: 1388d2e9a110SYong Wu if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) 1389baf94e6eSYong Wu device_link_remove(data->smicomm_dev, dev); 1390c0b57581SYong Wu out_runtime_disable: 1391c0b57581SYong Wu pm_runtime_disable(dev); 1392986d9ec5SYong Wu return ret; 13930df4fabeSYong Wu } 13940df4fabeSYong Wu 1395d8149d39SUwe Kleine-König static void mtk_iommu_remove(struct platform_device *pdev) 13960df4fabeSYong Wu { 13970df4fabeSYong Wu struct mtk_iommu_data *data = platform_get_drvdata(pdev); 139842d57fc5SYong Wu struct mtk_iommu_bank_data *bank; 139942d57fc5SYong Wu int i; 14000df4fabeSYong Wu 1401b16c0170SJoerg Roedel iommu_device_sysfs_remove(&data->iommu); 1402b16c0170SJoerg Roedel iommu_device_unregister(&data->iommu); 1403b16c0170SJoerg Roedel 1404ee55f75eSYong Wu list_del(&data->list); 14050df4fabeSYong Wu 1406d2e9a110SYong Wu if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { 1407baf94e6eSYong Wu device_link_remove(data->smicomm_dev, &pdev->dev); 1408d2e9a110SYong Wu component_master_del(&pdev->dev, &mtk_iommu_com_ops); 1409d2e9a110SYong Wu } 1410c0b57581SYong Wu pm_runtime_disable(&pdev->dev); 141142d57fc5SYong Wu for (i = 0; i < data->plat_data->banks_num; i++) { 141242d57fc5SYong Wu bank = &data->bank[i]; 141342d57fc5SYong Wu if (!bank->m4u_dom) 141442d57fc5SYong Wu continue; 141599ca0228SYong Wu devm_free_irq(&pdev->dev, bank->irq, bank); 141642d57fc5SYong Wu } 14170df4fabeSYong Wu } 14180df4fabeSYong Wu 141934665c79SYong Wu static int __maybe_unused mtk_iommu_runtime_suspend(struct device *dev) 14200df4fabeSYong Wu { 14210df4fabeSYong Wu struct mtk_iommu_data *data = dev_get_drvdata(dev); 14220df4fabeSYong Wu struct mtk_iommu_suspend_reg *reg = &data->reg; 1423d7127de1SYong Wu void __iomem *base; 1424d7127de1SYong Wu int i = 0; 14250df4fabeSYong Wu 1426d7127de1SYong Wu base = data->bank[i].base; 142735c1b48dSChao Hao reg->wr_len_ctrl = readl_relaxed(base + REG_MMU_WR_LEN_CTRL); 142875eed350SChao Hao reg->misc_ctrl = readl_relaxed(base + REG_MMU_MISC_CTRL); 14290df4fabeSYong Wu reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS); 14300df4fabeSYong Wu reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG); 1431b9475b34SYong Wu reg->vld_pa_rng = readl_relaxed(base + REG_MMU_VLD_PA_RNG); 1432d7127de1SYong Wu do { 1433d7127de1SYong Wu if (!data->plat_data->banks_enable[i]) 1434d7127de1SYong Wu continue; 1435d7127de1SYong Wu base = data->bank[i].base; 1436d7127de1SYong Wu reg->int_control[i] = readl_relaxed(base + REG_MMU_INT_CONTROL0); 1437d7127de1SYong Wu reg->int_main_control[i] = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL); 1438d7127de1SYong Wu reg->ivrp_paddr[i] = readl_relaxed(base + REG_MMU_IVRP_PADDR); 1439d7127de1SYong Wu } while (++i < data->plat_data->banks_num); 14406254b64fSYong Wu clk_disable_unprepare(data->bclk); 14410df4fabeSYong Wu return 0; 14420df4fabeSYong Wu } 14430df4fabeSYong Wu 144434665c79SYong Wu static int __maybe_unused mtk_iommu_runtime_resume(struct device *dev) 14450df4fabeSYong Wu { 14460df4fabeSYong Wu struct mtk_iommu_data *data = dev_get_drvdata(dev); 14470df4fabeSYong Wu struct mtk_iommu_suspend_reg *reg = &data->reg; 1448d7127de1SYong Wu struct mtk_iommu_domain *m4u_dom; 1449d7127de1SYong Wu void __iomem *base; 1450d7127de1SYong Wu int ret, i = 0; 14510df4fabeSYong Wu 14526254b64fSYong Wu ret = clk_prepare_enable(data->bclk); 14536254b64fSYong Wu if (ret) { 14546254b64fSYong Wu dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret); 14556254b64fSYong Wu return ret; 14566254b64fSYong Wu } 1457b34ea31fSDafna Hirschfeld 1458b34ea31fSDafna Hirschfeld /* 1459b34ea31fSDafna Hirschfeld * Uppon first resume, only enable the clk and return, since the values of the 1460b34ea31fSDafna Hirschfeld * registers are not yet set. 1461b34ea31fSDafna Hirschfeld */ 1462d7127de1SYong Wu if (!reg->wr_len_ctrl) 1463b34ea31fSDafna Hirschfeld return 0; 1464b34ea31fSDafna Hirschfeld 1465d7127de1SYong Wu base = data->bank[i].base; 146635c1b48dSChao Hao writel_relaxed(reg->wr_len_ctrl, base + REG_MMU_WR_LEN_CTRL); 146775eed350SChao Hao writel_relaxed(reg->misc_ctrl, base + REG_MMU_MISC_CTRL); 14680df4fabeSYong Wu writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS); 14690df4fabeSYong Wu writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG); 1470b9475b34SYong Wu writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG); 1471d7127de1SYong Wu do { 1472d7127de1SYong Wu m4u_dom = data->bank[i].m4u_dom; 1473d7127de1SYong Wu if (!data->plat_data->banks_enable[i] || !m4u_dom) 1474d7127de1SYong Wu continue; 1475d7127de1SYong Wu base = data->bank[i].base; 1476d7127de1SYong Wu writel_relaxed(reg->int_control[i], base + REG_MMU_INT_CONTROL0); 1477d7127de1SYong Wu writel_relaxed(reg->int_main_control[i], base + REG_MMU_INT_MAIN_CONTROL); 1478d7127de1SYong Wu writel_relaxed(reg->ivrp_paddr[i], base + REG_MMU_IVRP_PADDR); 1479301c3ca1SYunfei Wang writel(m4u_dom->cfg.arm_v7s_cfg.ttbr, base + REG_MMU_PT_BASE_ADDR); 1480d7127de1SYong Wu } while (++i < data->plat_data->banks_num); 14814f23f6d4SYong Wu 14824f23f6d4SYong Wu /* 14834f23f6d4SYong Wu * Users may allocate dma buffer before they call pm_runtime_get, 14844f23f6d4SYong Wu * in which case it will lack the necessary tlb flush. 14854f23f6d4SYong Wu * Thus, make sure to update the tlb after each PM resume. 14864f23f6d4SYong Wu */ 14874f23f6d4SYong Wu mtk_iommu_tlb_flush_all(data); 14880df4fabeSYong Wu return 0; 14890df4fabeSYong Wu } 14900df4fabeSYong Wu 1491e6dec923SYong Wu static const struct dev_pm_ops mtk_iommu_pm_ops = { 149234665c79SYong Wu SET_RUNTIME_PM_OPS(mtk_iommu_runtime_suspend, mtk_iommu_runtime_resume, NULL) 149334665c79SYong Wu SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 149434665c79SYong Wu pm_runtime_force_resume) 14950df4fabeSYong Wu }; 14960df4fabeSYong Wu 1497cecdce9dSYong Wu static const struct mtk_iommu_plat_data mt2712_data = { 1498cecdce9dSYong Wu .m4u_plat = M4U_MT2712, 1499d2e9a110SYong Wu .flags = HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG | SHARE_PGTABLE | 1500d2e9a110SYong Wu MTK_IOMMU_TYPE_MM, 15019e3a2a64SYong Wu .hw_list = &m4ulist, 1502b053bc71SChao Hao .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 1503585e58f4SYong Wu .iova_region = single_domain, 150499ca0228SYong Wu .banks_num = 1, 150599ca0228SYong Wu .banks_enable = {true}, 1506585e58f4SYong Wu .iova_region_nr = ARRAY_SIZE(single_domain), 150737276e00SChao Hao .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}}, 1508cecdce9dSYong Wu }; 1509cecdce9dSYong Wu 1510068c86e9SChao Hao static const struct mtk_iommu_plat_data mt6779_data = { 1511068c86e9SChao Hao .m4u_plat = M4U_MT6779, 1512d2e9a110SYong Wu .flags = HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | WR_THROT_EN | 1513301c3ca1SYunfei Wang MTK_IOMMU_TYPE_MM | PGTABLE_PA_35_EN, 1514068c86e9SChao Hao .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 151599ca0228SYong Wu .banks_num = 1, 151699ca0228SYong Wu .banks_enable = {true}, 1517585e58f4SYong Wu .iova_region = single_domain, 1518585e58f4SYong Wu .iova_region_nr = ARRAY_SIZE(single_domain), 1519068c86e9SChao Hao .larbid_remap = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}}, 1520cecdce9dSYong Wu }; 1521cecdce9dSYong Wu 1522717ec15eSAngeloGioacchino Del Regno static const struct mtk_iommu_plat_data mt6795_data = { 1523717ec15eSAngeloGioacchino Del Regno .m4u_plat = M4U_MT6795, 1524717ec15eSAngeloGioacchino Del Regno .flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI | 1525717ec15eSAngeloGioacchino Del Regno HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM | 1526717ec15eSAngeloGioacchino Del Regno TF_PORT_TO_ADDR_MT8173, 1527717ec15eSAngeloGioacchino Del Regno .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 1528717ec15eSAngeloGioacchino Del Regno .banks_num = 1, 1529717ec15eSAngeloGioacchino Del Regno .banks_enable = {true}, 1530717ec15eSAngeloGioacchino Del Regno .iova_region = single_domain, 1531717ec15eSAngeloGioacchino Del Regno .iova_region_nr = ARRAY_SIZE(single_domain), 1532717ec15eSAngeloGioacchino Del Regno .larbid_remap = {{0}, {1}, {2}, {3}, {4}}, /* Linear mapping. */ 1533717ec15eSAngeloGioacchino Del Regno }; 1534717ec15eSAngeloGioacchino Del Regno 15353c213562SFabien Parent static const struct mtk_iommu_plat_data mt8167_data = { 15363c213562SFabien Parent .m4u_plat = M4U_MT8167, 1537d2e9a110SYong Wu .flags = RESET_AXI | HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM, 15383c213562SFabien Parent .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 153999ca0228SYong Wu .banks_num = 1, 154099ca0228SYong Wu .banks_enable = {true}, 1541585e58f4SYong Wu .iova_region = single_domain, 1542585e58f4SYong Wu .iova_region_nr = ARRAY_SIZE(single_domain), 15433c213562SFabien Parent .larbid_remap = {{0}, {1}, {2}}, /* Linear mapping. */ 15443c213562SFabien Parent }; 15453c213562SFabien Parent 1546cecdce9dSYong Wu static const struct mtk_iommu_plat_data mt8173_data = { 1547cecdce9dSYong Wu .m4u_plat = M4U_MT8173, 1548d1b5ef00SFabien Parent .flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI | 154986580ec9SAngeloGioacchino Del Regno HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM | 155086580ec9SAngeloGioacchino Del Regno TF_PORT_TO_ADDR_MT8173, 1551b053bc71SChao Hao .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 155299ca0228SYong Wu .banks_num = 1, 155399ca0228SYong Wu .banks_enable = {true}, 1554585e58f4SYong Wu .iova_region = single_domain, 1555585e58f4SYong Wu .iova_region_nr = ARRAY_SIZE(single_domain), 155637276e00SChao Hao .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */ 1557cecdce9dSYong Wu }; 1558cecdce9dSYong Wu 1559907ba6a1SYong Wu static const struct mtk_iommu_plat_data mt8183_data = { 1560907ba6a1SYong Wu .m4u_plat = M4U_MT8183, 1561d2e9a110SYong Wu .flags = RESET_AXI | MTK_IOMMU_TYPE_MM, 1562b053bc71SChao Hao .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 156399ca0228SYong Wu .banks_num = 1, 156499ca0228SYong Wu .banks_enable = {true}, 1565585e58f4SYong Wu .iova_region = single_domain, 1566585e58f4SYong Wu .iova_region_nr = ARRAY_SIZE(single_domain), 156737276e00SChao Hao .larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}}, 1568907ba6a1SYong Wu }; 1569907ba6a1SYong Wu 1570f5d4233aSYong Wu static const unsigned int mt8186_larb_region_msk[MT8192_MULTI_REGION_NR_MAX][MTK_LARB_NR_MAX] = { 1571f5d4233aSYong Wu [0] = {~0, ~0, ~0}, /* Region0: all ports for larb0/1/2 */ 1572f5d4233aSYong Wu [1] = {0, 0, 0, 0, ~0, 0, 0, ~0}, /* Region1: larb4/7 */ 1573f5d4233aSYong Wu [2] = {0, 0, 0, 0, 0, 0, 0, 0, /* Region2: larb8/9/11/13/16/17/19/20 */ 1574f5d4233aSYong Wu ~0, ~0, 0, ~0, 0, ~(u32)(BIT(9) | BIT(10)), 0, 0, 1575f5d4233aSYong Wu /* larb13: the other ports except port9/10 */ 1576f5d4233aSYong Wu ~0, ~0, 0, ~0, ~0}, 1577f5d4233aSYong Wu [3] = {0}, 1578f5d4233aSYong Wu [4] = {[13] = BIT(9) | BIT(10)}, /* larb13 port9/10 */ 1579f5d4233aSYong Wu [5] = {[14] = ~0}, /* larb14 */ 1580f5d4233aSYong Wu }; 1581f5d4233aSYong Wu 1582e8d7ccaaSYong Wu static const struct mtk_iommu_plat_data mt8186_data_mm = { 1583e8d7ccaaSYong Wu .m4u_plat = M4U_MT8186, 1584e8d7ccaaSYong Wu .flags = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | 1585e8d7ccaaSYong Wu WR_THROT_EN | IOVA_34_EN | MTK_IOMMU_TYPE_MM, 1586e8d7ccaaSYong Wu .larbid_remap = {{0}, {1, MTK_INVALID_LARBID, 8}, {4}, {7}, {2}, {9, 11, 19, 20}, 1587e8d7ccaaSYong Wu {MTK_INVALID_LARBID, 14, 16}, 1588e8d7ccaaSYong Wu {MTK_INVALID_LARBID, 13, MTK_INVALID_LARBID, 17}}, 1589e8d7ccaaSYong Wu .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 1590e8d7ccaaSYong Wu .banks_num = 1, 1591e8d7ccaaSYong Wu .banks_enable = {true}, 1592e8d7ccaaSYong Wu .iova_region = mt8192_multi_dom, 1593e8d7ccaaSYong Wu .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), 1594f5d4233aSYong Wu .iova_region_larb_msk = mt8186_larb_region_msk, 1595e8d7ccaaSYong Wu }; 1596e8d7ccaaSYong Wu 1597a09e8403SChengci.Xu static const struct mtk_iommu_plat_data mt8188_data_infra = { 1598a09e8403SChengci.Xu .m4u_plat = M4U_MT8188, 1599a09e8403SChengci.Xu .flags = WR_THROT_EN | DCM_DISABLE | STD_AXI_MODE | PM_CLK_AO | 1600a09e8403SChengci.Xu MTK_IOMMU_TYPE_INFRA | IFA_IOMMU_PCIE_SUPPORT | 1601a09e8403SChengci.Xu PGTABLE_PA_35_EN | CFG_IFA_MASTER_IN_ATF, 1602a09e8403SChengci.Xu .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 1603a09e8403SChengci.Xu .banks_num = 1, 1604a09e8403SChengci.Xu .banks_enable = {true}, 1605a09e8403SChengci.Xu .iova_region = single_domain, 1606a09e8403SChengci.Xu .iova_region_nr = ARRAY_SIZE(single_domain), 1607a09e8403SChengci.Xu }; 1608a09e8403SChengci.Xu 16091e8a4639SYong Wu static const u32 mt8188_larb_region_msk[MT8192_MULTI_REGION_NR_MAX][MTK_LARB_NR_MAX] = { 16101e8a4639SYong Wu [0] = {~0, ~0, ~0, ~0}, /* Region0: all ports for larb0/1/2/3 */ 16111e8a4639SYong Wu [1] = {0, 0, 0, 0, 0, 0, 0, 0, 16121e8a4639SYong Wu 0, 0, 0, 0, 0, 0, 0, 0, 16131e8a4639SYong Wu 0, 0, 0, 0, 0, ~0, ~0, ~0}, /* Region1: larb19(21)/21(22)/23 */ 16141e8a4639SYong Wu [2] = {0, 0, 0, 0, ~0, ~0, ~0, ~0, /* Region2: the other larbs. */ 16151e8a4639SYong Wu ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, 16161e8a4639SYong Wu ~0, ~0, ~0, ~0, ~0, 0, 0, 0, 16171e8a4639SYong Wu 0, ~0}, 16181e8a4639SYong Wu [3] = {0}, 16191e8a4639SYong Wu [4] = {[24] = BIT(0) | BIT(1)}, /* Only larb27(24) port0/1 */ 16201e8a4639SYong Wu [5] = {[24] = BIT(2) | BIT(3)}, /* Only larb27(24) port2/3 */ 16211e8a4639SYong Wu }; 16221e8a4639SYong Wu 1623a09e8403SChengci.Xu static const struct mtk_iommu_plat_data mt8188_data_vdo = { 1624a09e8403SChengci.Xu .m4u_plat = M4U_MT8188, 1625a09e8403SChengci.Xu .flags = HAS_BCLK | HAS_SUB_COMM_3BITS | OUT_ORDER_WR_EN | 1626a09e8403SChengci.Xu WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE | 1627a09e8403SChengci.Xu PGTABLE_PA_35_EN | MTK_IOMMU_TYPE_MM, 1628a09e8403SChengci.Xu .hw_list = &m4ulist, 1629a09e8403SChengci.Xu .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 1630a09e8403SChengci.Xu .banks_num = 1, 1631a09e8403SChengci.Xu .banks_enable = {true}, 1632a09e8403SChengci.Xu .iova_region = mt8192_multi_dom, 1633a09e8403SChengci.Xu .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), 16341e8a4639SYong Wu .iova_region_larb_msk = mt8188_larb_region_msk, 1635a09e8403SChengci.Xu .larbid_remap = {{2}, {0}, {21}, {0}, {19}, {9, 10, 1636a09e8403SChengci.Xu 11 /* 11a */, 25 /* 11c */}, 1637a09e8403SChengci.Xu {13, 0, 29 /* 16b */, 30 /* 17b */, 0}, {5}}, 1638a09e8403SChengci.Xu }; 1639a09e8403SChengci.Xu 1640a09e8403SChengci.Xu static const struct mtk_iommu_plat_data mt8188_data_vpp = { 1641a09e8403SChengci.Xu .m4u_plat = M4U_MT8188, 1642a09e8403SChengci.Xu .flags = HAS_BCLK | HAS_SUB_COMM_3BITS | OUT_ORDER_WR_EN | 1643a09e8403SChengci.Xu WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE | 1644a09e8403SChengci.Xu PGTABLE_PA_35_EN | MTK_IOMMU_TYPE_MM, 1645a09e8403SChengci.Xu .hw_list = &m4ulist, 1646a09e8403SChengci.Xu .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 1647a09e8403SChengci.Xu .banks_num = 1, 1648a09e8403SChengci.Xu .banks_enable = {true}, 1649a09e8403SChengci.Xu .iova_region = mt8192_multi_dom, 1650a09e8403SChengci.Xu .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), 16511e8a4639SYong Wu .iova_region_larb_msk = mt8188_larb_region_msk, 1652a09e8403SChengci.Xu .larbid_remap = {{1}, {3}, {23}, {7}, {MTK_INVALID_LARBID}, 1653a09e8403SChengci.Xu {12, 15, 24 /* 11b */}, {14, MTK_INVALID_LARBID, 1654a09e8403SChengci.Xu 16 /* 16a */, 17 /* 17a */, MTK_INVALID_LARBID, 1655a09e8403SChengci.Xu 27, 28 /* ccu0 */, MTK_INVALID_LARBID}, {4, 6}}, 1656a09e8403SChengci.Xu }; 1657a09e8403SChengci.Xu 16586b1317f9SYong Wu static const unsigned int mt8192_larb_region_msk[MT8192_MULTI_REGION_NR_MAX][MTK_LARB_NR_MAX] = { 16596b1317f9SYong Wu [0] = {~0, ~0}, /* Region0: larb0/1 */ 16606b1317f9SYong Wu [1] = {0, 0, 0, 0, ~0, ~0, 0, ~0}, /* Region1: larb4/5/7 */ 16616b1317f9SYong Wu [2] = {0, 0, ~0, 0, 0, 0, 0, 0, /* Region2: larb2/9/11/13/14/16/17/18/19/20 */ 16626b1317f9SYong Wu 0, ~0, 0, ~0, 0, ~(u32)(BIT(9) | BIT(10)), ~(u32)(BIT(4) | BIT(5)), 0, 16636b1317f9SYong Wu ~0, ~0, ~0, ~0, ~0}, 16646b1317f9SYong Wu [3] = {0}, 16656b1317f9SYong Wu [4] = {[13] = BIT(9) | BIT(10)}, /* larb13 port9/10 */ 16666b1317f9SYong Wu [5] = {[14] = BIT(4) | BIT(5)}, /* larb14 port4/5 */ 16670df4fabeSYong Wu }; 16680df4fabeSYong Wu 16699e3489e0SYong Wu static const struct mtk_iommu_plat_data mt8192_data = { 16709e3489e0SYong Wu .m4u_plat = M4U_MT8192, 16719ec30c09SYong Wu .flags = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | 1672d2e9a110SYong Wu WR_THROT_EN | IOVA_34_EN | MTK_IOMMU_TYPE_MM, 16739e3489e0SYong Wu .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 167499ca0228SYong Wu .banks_num = 1, 167599ca0228SYong Wu .banks_enable = {true}, 16769e3489e0SYong Wu .iova_region = mt8192_multi_dom, 16779e3489e0SYong Wu .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), 16786b1317f9SYong Wu .iova_region_larb_msk = mt8192_larb_region_msk, 16799e3489e0SYong Wu .larbid_remap = {{0}, {1}, {4, 5}, {7}, {2}, {9, 11, 19, 20}, 16809e3489e0SYong Wu {0, 14, 16}, {0, 13, 18, 17}}, 16819e3489e0SYong Wu }; 16829e3489e0SYong Wu 1683ef68a193SYong Wu static const struct mtk_iommu_plat_data mt8195_data_infra = { 1684ef68a193SYong Wu .m4u_plat = M4U_MT8195, 1685ef68a193SYong Wu .flags = WR_THROT_EN | DCM_DISABLE | STD_AXI_MODE | PM_CLK_AO | 1686ef68a193SYong Wu MTK_IOMMU_TYPE_INFRA | IFA_IOMMU_PCIE_SUPPORT, 1687ef68a193SYong Wu .pericfg_comp_str = "mediatek,mt8195-pericfg_ao", 1688ef68a193SYong Wu .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 16897597e3c5SYong Wu .banks_num = 5, 16907597e3c5SYong Wu .banks_enable = {true, false, false, false, true}, 16917597e3c5SYong Wu .banks_portmsk = {[0] = GENMASK(19, 16), /* PCIe */ 16927597e3c5SYong Wu [4] = GENMASK(31, 20), /* USB */ 16937597e3c5SYong Wu }, 1694ef68a193SYong Wu .iova_region = single_domain, 1695ef68a193SYong Wu .iova_region_nr = ARRAY_SIZE(single_domain), 1696ef68a193SYong Wu }; 1697ef68a193SYong Wu 1698a43e767dSYong Wu static const unsigned int mt8195_larb_region_msk[MT8192_MULTI_REGION_NR_MAX][MTK_LARB_NR_MAX] = { 1699a43e767dSYong Wu [0] = {~0, ~0, ~0, ~0}, /* Region0: all ports for larb0/1/2/3 */ 1700a43e767dSYong Wu [1] = {0, 0, 0, 0, 0, 0, 0, 0, 1701a43e767dSYong Wu 0, 0, 0, 0, 0, 0, 0, 0, 1702a43e767dSYong Wu 0, 0, 0, ~0, ~0, ~0, ~0, ~0, /* Region1: larb19/20/21/22/23/24 */ 1703a43e767dSYong Wu ~0}, 1704a43e767dSYong Wu [2] = {0, 0, 0, 0, ~0, ~0, ~0, ~0, /* Region2: the other larbs. */ 1705a43e767dSYong Wu ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, 1706a43e767dSYong Wu ~0, ~0, 0, 0, 0, 0, 0, 0, 1707a43e767dSYong Wu 0, ~0, ~0, ~0, ~0}, 1708a43e767dSYong Wu [3] = {0}, 1709a43e767dSYong Wu [4] = {[18] = BIT(0) | BIT(1)}, /* Only larb18 port0/1 */ 1710a43e767dSYong Wu [5] = {[18] = BIT(2) | BIT(3)}, /* Only larb18 port2/3 */ 1711a43e767dSYong Wu }; 1712a43e767dSYong Wu 1713ef68a193SYong Wu static const struct mtk_iommu_plat_data mt8195_data_vdo = { 1714ef68a193SYong Wu .m4u_plat = M4U_MT8195, 1715ef68a193SYong Wu .flags = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | 1716ef68a193SYong Wu WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE | MTK_IOMMU_TYPE_MM, 1717ef68a193SYong Wu .hw_list = &m4ulist, 1718ef68a193SYong Wu .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 171999ca0228SYong Wu .banks_num = 1, 172099ca0228SYong Wu .banks_enable = {true}, 1721ef68a193SYong Wu .iova_region = mt8192_multi_dom, 1722ef68a193SYong Wu .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), 1723a43e767dSYong Wu .iova_region_larb_msk = mt8195_larb_region_msk, 1724ef68a193SYong Wu .larbid_remap = {{2, 0}, {21}, {24}, {7}, {19}, {9, 10, 11}, 1725ef68a193SYong Wu {13, 17, 15/* 17b */, 25}, {5}}, 1726ef68a193SYong Wu }; 1727ef68a193SYong Wu 1728ef68a193SYong Wu static const struct mtk_iommu_plat_data mt8195_data_vpp = { 1729ef68a193SYong Wu .m4u_plat = M4U_MT8195, 1730ef68a193SYong Wu .flags = HAS_BCLK | HAS_SUB_COMM_3BITS | OUT_ORDER_WR_EN | 1731ef68a193SYong Wu WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE | MTK_IOMMU_TYPE_MM, 1732ef68a193SYong Wu .hw_list = &m4ulist, 1733ef68a193SYong Wu .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 173499ca0228SYong Wu .banks_num = 1, 173599ca0228SYong Wu .banks_enable = {true}, 1736ef68a193SYong Wu .iova_region = mt8192_multi_dom, 1737ef68a193SYong Wu .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), 1738a43e767dSYong Wu .iova_region_larb_msk = mt8195_larb_region_msk, 1739ef68a193SYong Wu .larbid_remap = {{1}, {3}, 1740ef68a193SYong Wu {22, MTK_INVALID_LARBID, MTK_INVALID_LARBID, MTK_INVALID_LARBID, 23}, 1741ef68a193SYong Wu {8}, {20}, {12}, 1742ef68a193SYong Wu /* 16: 16a; 29: 16b; 30: CCUtop0; 31: CCUtop1 */ 1743ef68a193SYong Wu {14, 16, 29, 26, 30, 31, 18}, 1744ef68a193SYong Wu {4, MTK_INVALID_LARBID, MTK_INVALID_LARBID, MTK_INVALID_LARBID, 6}}, 1745ef68a193SYong Wu }; 1746ef68a193SYong Wu 17473cd0e4a3SFabien Parent static const struct mtk_iommu_plat_data mt8365_data = { 17483cd0e4a3SFabien Parent .m4u_plat = M4U_MT8365, 17493cd0e4a3SFabien Parent .flags = RESET_AXI | INT_ID_PORT_WIDTH_6, 17503cd0e4a3SFabien Parent .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 17513cd0e4a3SFabien Parent .banks_num = 1, 17523cd0e4a3SFabien Parent .banks_enable = {true}, 17533cd0e4a3SFabien Parent .iova_region = single_domain, 17543cd0e4a3SFabien Parent .iova_region_nr = ARRAY_SIZE(single_domain), 17553cd0e4a3SFabien Parent .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */ 17563cd0e4a3SFabien Parent }; 17573cd0e4a3SFabien Parent 17580df4fabeSYong Wu static const struct of_device_id mtk_iommu_of_ids[] = { 1759cecdce9dSYong Wu { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data}, 1760068c86e9SChao Hao { .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data}, 1761717ec15eSAngeloGioacchino Del Regno { .compatible = "mediatek,mt6795-m4u", .data = &mt6795_data}, 17623c213562SFabien Parent { .compatible = "mediatek,mt8167-m4u", .data = &mt8167_data}, 1763cecdce9dSYong Wu { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data}, 1764907ba6a1SYong Wu { .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data}, 1765e8d7ccaaSYong Wu { .compatible = "mediatek,mt8186-iommu-mm", .data = &mt8186_data_mm}, /* mm: m4u */ 1766a09e8403SChengci.Xu { .compatible = "mediatek,mt8188-iommu-infra", .data = &mt8188_data_infra}, 1767a09e8403SChengci.Xu { .compatible = "mediatek,mt8188-iommu-vdo", .data = &mt8188_data_vdo}, 1768a09e8403SChengci.Xu { .compatible = "mediatek,mt8188-iommu-vpp", .data = &mt8188_data_vpp}, 17699e3489e0SYong Wu { .compatible = "mediatek,mt8192-m4u", .data = &mt8192_data}, 1770ef68a193SYong Wu { .compatible = "mediatek,mt8195-iommu-infra", .data = &mt8195_data_infra}, 1771ef68a193SYong Wu { .compatible = "mediatek,mt8195-iommu-vdo", .data = &mt8195_data_vdo}, 1772ef68a193SYong Wu { .compatible = "mediatek,mt8195-iommu-vpp", .data = &mt8195_data_vpp}, 17733cd0e4a3SFabien Parent { .compatible = "mediatek,mt8365-m4u", .data = &mt8365_data}, 17740df4fabeSYong Wu {} 17750df4fabeSYong Wu }; 17760df4fabeSYong Wu 17770df4fabeSYong Wu static struct platform_driver mtk_iommu_driver = { 17780df4fabeSYong Wu .probe = mtk_iommu_probe, 1779d8149d39SUwe Kleine-König .remove_new = mtk_iommu_remove, 17800df4fabeSYong Wu .driver = { 17810df4fabeSYong Wu .name = "mtk-iommu", 1782f53dd978SKrzysztof Kozlowski .of_match_table = mtk_iommu_of_ids, 17830df4fabeSYong Wu .pm = &mtk_iommu_pm_ops, 17840df4fabeSYong Wu } 17850df4fabeSYong Wu }; 178618d8c74eSYong Wu module_platform_driver(mtk_iommu_driver); 17870df4fabeSYong Wu 178818d8c74eSYong Wu MODULE_DESCRIPTION("IOMMU API for MediaTek M4U implementations"); 178918d8c74eSYong Wu MODULE_LICENSE("GPL v2"); 1790