11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 20df4fabeSYong Wu /* 30df4fabeSYong Wu * Copyright (c) 2015-2016 MediaTek Inc. 40df4fabeSYong Wu * Author: Yong Wu <yong.wu@mediatek.com> 50df4fabeSYong Wu */ 6ef0f0986SYong Wu #include <linux/bitfield.h> 70df4fabeSYong Wu #include <linux/bug.h> 80df4fabeSYong Wu #include <linux/clk.h> 90df4fabeSYong Wu #include <linux/component.h> 100df4fabeSYong Wu #include <linux/device.h> 110df4fabeSYong Wu #include <linux/err.h> 120df4fabeSYong Wu #include <linux/interrupt.h> 130df4fabeSYong Wu #include <linux/io.h> 140df4fabeSYong Wu #include <linux/iommu.h> 150df4fabeSYong Wu #include <linux/iopoll.h> 166a513de3SYong Wu #include <linux/io-pgtable.h> 170df4fabeSYong Wu #include <linux/list.h> 18c2c59456SMiles Chen #include <linux/mfd/syscon.h> 1918d8c74eSYong Wu #include <linux/module.h> 200df4fabeSYong Wu #include <linux/of_address.h> 210df4fabeSYong Wu #include <linux/of_irq.h> 220df4fabeSYong Wu #include <linux/of_platform.h> 23e7629070SYong Wu #include <linux/pci.h> 240df4fabeSYong Wu #include <linux/platform_device.h> 25baf94e6eSYong Wu #include <linux/pm_runtime.h> 26c2c59456SMiles Chen #include <linux/regmap.h> 270df4fabeSYong Wu #include <linux/slab.h> 280df4fabeSYong Wu #include <linux/spinlock.h> 29c2c59456SMiles Chen #include <linux/soc/mediatek/infracfg.h> 300df4fabeSYong Wu #include <asm/barrier.h> 310df4fabeSYong Wu #include <soc/mediatek/smi.h> 320df4fabeSYong Wu 336a513de3SYong Wu #include <dt-bindings/memory/mtk-memory-port.h> 340df4fabeSYong Wu 350df4fabeSYong Wu #define REG_MMU_PT_BASE_ADDR 0x000 360df4fabeSYong Wu 370df4fabeSYong Wu #define REG_MMU_INVALIDATE 0x020 380df4fabeSYong Wu #define F_ALL_INVLD 0x2 390df4fabeSYong Wu #define F_MMU_INV_RANGE 0x1 400df4fabeSYong Wu 410df4fabeSYong Wu #define REG_MMU_INVLD_START_A 0x024 420df4fabeSYong Wu #define REG_MMU_INVLD_END_A 0x028 430df4fabeSYong Wu 44068c86e9SChao Hao #define REG_MMU_INV_SEL_GEN2 0x02c 45b053bc71SChao Hao #define REG_MMU_INV_SEL_GEN1 0x038 460df4fabeSYong Wu #define F_INVLD_EN0 BIT(0) 470df4fabeSYong Wu #define F_INVLD_EN1 BIT(1) 480df4fabeSYong Wu 4975eed350SChao Hao #define REG_MMU_MISC_CTRL 0x048 504bb2bf4cSChao Hao #define F_MMU_IN_ORDER_WR_EN_MASK (BIT(1) | BIT(17)) 514bb2bf4cSChao Hao #define F_MMU_STANDARD_AXI_MODE_MASK (BIT(3) | BIT(19)) 524bb2bf4cSChao Hao 530df4fabeSYong Wu #define REG_MMU_DCM_DIS 0x050 549a87005eSYong Wu #define F_MMU_DCM BIT(8) 559a87005eSYong Wu 5635c1b48dSChao Hao #define REG_MMU_WR_LEN_CTRL 0x054 5735c1b48dSChao Hao #define F_MMU_WR_THROT_DIS_MASK (BIT(5) | BIT(21)) 580df4fabeSYong Wu 590df4fabeSYong Wu #define REG_MMU_CTRL_REG 0x110 60acb3c92aSYong Wu #define F_MMU_TF_PROT_TO_PROGRAM_ADDR (2 << 4) 610df4fabeSYong Wu #define F_MMU_PREFETCH_RT_REPLACE_MOD BIT(4) 62acb3c92aSYong Wu #define F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173 (2 << 5) 630df4fabeSYong Wu 640df4fabeSYong Wu #define REG_MMU_IVRP_PADDR 0x114 6570ca608bSYong Wu 6630e2fccfSYong Wu #define REG_MMU_VLD_PA_RNG 0x118 6730e2fccfSYong Wu #define F_MMU_VLD_PA_RNG(EA, SA) (((EA) << 8) | (SA)) 680df4fabeSYong Wu 690df4fabeSYong Wu #define REG_MMU_INT_CONTROL0 0x120 700df4fabeSYong Wu #define F_L2_MULIT_HIT_EN BIT(0) 710df4fabeSYong Wu #define F_TABLE_WALK_FAULT_INT_EN BIT(1) 720df4fabeSYong Wu #define F_PREETCH_FIFO_OVERFLOW_INT_EN BIT(2) 730df4fabeSYong Wu #define F_MISS_FIFO_OVERFLOW_INT_EN BIT(3) 740df4fabeSYong Wu #define F_PREFETCH_FIFO_ERR_INT_EN BIT(5) 750df4fabeSYong Wu #define F_MISS_FIFO_ERR_INT_EN BIT(6) 760df4fabeSYong Wu #define F_INT_CLR_BIT BIT(12) 770df4fabeSYong Wu 780df4fabeSYong Wu #define REG_MMU_INT_MAIN_CONTROL 0x124 7915a01f4cSYong Wu /* mmu0 | mmu1 */ 8015a01f4cSYong Wu #define F_INT_TRANSLATION_FAULT (BIT(0) | BIT(7)) 8115a01f4cSYong Wu #define F_INT_MAIN_MULTI_HIT_FAULT (BIT(1) | BIT(8)) 8215a01f4cSYong Wu #define F_INT_INVALID_PA_FAULT (BIT(2) | BIT(9)) 8315a01f4cSYong Wu #define F_INT_ENTRY_REPLACEMENT_FAULT (BIT(3) | BIT(10)) 8415a01f4cSYong Wu #define F_INT_TLB_MISS_FAULT (BIT(4) | BIT(11)) 8515a01f4cSYong Wu #define F_INT_MISS_TRANSACTION_FIFO_FAULT (BIT(5) | BIT(12)) 8615a01f4cSYong Wu #define F_INT_PRETETCH_TRANSATION_FIFO_FAULT (BIT(6) | BIT(13)) 870df4fabeSYong Wu 880df4fabeSYong Wu #define REG_MMU_CPE_DONE 0x12C 890df4fabeSYong Wu 900df4fabeSYong Wu #define REG_MMU_FAULT_ST1 0x134 9115a01f4cSYong Wu #define F_REG_MMU0_FAULT_MASK GENMASK(6, 0) 9215a01f4cSYong Wu #define F_REG_MMU1_FAULT_MASK GENMASK(13, 7) 930df4fabeSYong Wu 9415a01f4cSYong Wu #define REG_MMU0_FAULT_VA 0x13c 95ef0f0986SYong Wu #define F_MMU_INVAL_VA_31_12_MASK GENMASK(31, 12) 96ef0f0986SYong Wu #define F_MMU_INVAL_VA_34_32_MASK GENMASK(11, 9) 97ef0f0986SYong Wu #define F_MMU_INVAL_PA_34_32_MASK GENMASK(8, 6) 980df4fabeSYong Wu #define F_MMU_FAULT_VA_WRITE_BIT BIT(1) 990df4fabeSYong Wu #define F_MMU_FAULT_VA_LAYER_BIT BIT(0) 1000df4fabeSYong Wu 10115a01f4cSYong Wu #define REG_MMU0_INVLD_PA 0x140 10215a01f4cSYong Wu #define REG_MMU1_FAULT_VA 0x144 10315a01f4cSYong Wu #define REG_MMU1_INVLD_PA 0x148 10415a01f4cSYong Wu #define REG_MMU0_INT_ID 0x150 10515a01f4cSYong Wu #define REG_MMU1_INT_ID 0x154 10637276e00SChao Hao #define F_MMU_INT_ID_COMM_ID(a) (((a) >> 9) & 0x7) 10737276e00SChao Hao #define F_MMU_INT_ID_SUB_COMM_ID(a) (((a) >> 7) & 0x3) 1089ec30c09SYong Wu #define F_MMU_INT_ID_COMM_ID_EXT(a) (((a) >> 10) & 0x7) 1099ec30c09SYong Wu #define F_MMU_INT_ID_SUB_COMM_ID_EXT(a) (((a) >> 7) & 0x7) 11065df7d82SFabien Parent /* Macro for 5 bits length port ID field (default) */ 11115a01f4cSYong Wu #define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7) 11215a01f4cSYong Wu #define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f) 11365df7d82SFabien Parent /* Macro for 6 bits length port ID field */ 11465df7d82SFabien Parent #define F_MMU_INT_ID_LARB_ID_WID_6(a) (((a) >> 8) & 0x7) 11565df7d82SFabien Parent #define F_MMU_INT_ID_PORT_ID_WID_6(a) (((a) >> 2) & 0x3f) 1160df4fabeSYong Wu 117829316b3SChao Hao #define MTK_PROTECT_PA_ALIGN 256 11842d57fc5SYong Wu #define MTK_IOMMU_BANK_SZ 0x1000 1190df4fabeSYong Wu 120f9b8c9b2SYong Wu #define PERICFG_IOMMU_1 0x714 121f9b8c9b2SYong Wu 1226b717796SChao Hao #define HAS_4GB_MODE BIT(0) 1236b717796SChao Hao /* HW will use the EMI clock if there isn't the "bclk". */ 1246b717796SChao Hao #define HAS_BCLK BIT(1) 1256b717796SChao Hao #define HAS_VLD_PA_RNG BIT(2) 1266b717796SChao Hao #define RESET_AXI BIT(3) 1274bb2bf4cSChao Hao #define OUT_ORDER_WR_EN BIT(4) 1289ec30c09SYong Wu #define HAS_SUB_COMM_2BITS BIT(5) 1299ec30c09SYong Wu #define HAS_SUB_COMM_3BITS BIT(6) 1309ec30c09SYong Wu #define WR_THROT_EN BIT(7) 1319ec30c09SYong Wu #define HAS_LEGACY_IVRP_PADDR BIT(8) 1329ec30c09SYong Wu #define IOVA_34_EN BIT(9) 1339ec30c09SYong Wu #define SHARE_PGTABLE BIT(10) /* 2 HW share pgtable */ 1349ec30c09SYong Wu #define DCM_DISABLE BIT(11) 1359ec30c09SYong Wu #define STD_AXI_MODE BIT(12) /* For non MM iommu */ 1368cd1e619SYong Wu /* 2 bits: iommu type */ 1378cd1e619SYong Wu #define MTK_IOMMU_TYPE_MM (0x0 << 13) 1388cd1e619SYong Wu #define MTK_IOMMU_TYPE_INFRA (0x1 << 13) 1398cd1e619SYong Wu #define MTK_IOMMU_TYPE_MASK (0x3 << 13) 1406077c7e5SYong Wu /* PM and clock always on. e.g. infra iommu */ 1416077c7e5SYong Wu #define PM_CLK_AO BIT(15) 142e7629070SYong Wu #define IFA_IOMMU_PCIE_SUPPORT BIT(16) 143301c3ca1SYunfei Wang #define PGTABLE_PA_35_EN BIT(17) 14486580ec9SAngeloGioacchino Del Regno #define TF_PORT_TO_ADDR_MT8173 BIT(18) 14565df7d82SFabien Parent #define INT_ID_PORT_WIDTH_6 BIT(19) 1466b717796SChao Hao 1478cd1e619SYong Wu #define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \ 1488cd1e619SYong Wu ((((pdata)->flags) & (mask)) == (_x)) 1498cd1e619SYong Wu 1508cd1e619SYong Wu #define MTK_IOMMU_HAS_FLAG(pdata, _x) MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, _x) 1518cd1e619SYong Wu #define MTK_IOMMU_IS_TYPE(pdata, _x) MTK_IOMMU_HAS_FLAG_MASK(pdata, _x,\ 1528cd1e619SYong Wu MTK_IOMMU_TYPE_MASK) 1536b717796SChao Hao 154d2e9a110SYong Wu #define MTK_INVALID_LARBID MTK_LARB_NR_MAX 155d2e9a110SYong Wu 1569485a04aSYong Wu #define MTK_LARB_COM_MAX 8 1579485a04aSYong Wu #define MTK_LARB_SUBCOM_MAX 8 1589485a04aSYong Wu 1599485a04aSYong Wu #define MTK_IOMMU_GROUP_MAX 8 16099ca0228SYong Wu #define MTK_IOMMU_BANK_MAX 5 1619485a04aSYong Wu 1629485a04aSYong Wu enum mtk_iommu_plat { 1639485a04aSYong Wu M4U_MT2712, 1649485a04aSYong Wu M4U_MT6779, 165717ec15eSAngeloGioacchino Del Regno M4U_MT6795, 1669485a04aSYong Wu M4U_MT8167, 1679485a04aSYong Wu M4U_MT8173, 1689485a04aSYong Wu M4U_MT8183, 169e8d7ccaaSYong Wu M4U_MT8186, 1709485a04aSYong Wu M4U_MT8192, 1719485a04aSYong Wu M4U_MT8195, 1723cd0e4a3SFabien Parent M4U_MT8365, 1739485a04aSYong Wu }; 1749485a04aSYong Wu 1759485a04aSYong Wu struct mtk_iommu_iova_region { 1769485a04aSYong Wu dma_addr_t iova_base; 1779485a04aSYong Wu unsigned long long size; 1789485a04aSYong Wu }; 1799485a04aSYong Wu 1806a513de3SYong Wu struct mtk_iommu_suspend_reg { 1816a513de3SYong Wu u32 misc_ctrl; 1826a513de3SYong Wu u32 dcm_dis; 1836a513de3SYong Wu u32 ctrl_reg; 1846a513de3SYong Wu u32 vld_pa_rng; 1856a513de3SYong Wu u32 wr_len_ctrl; 186d7127de1SYong Wu 187d7127de1SYong Wu u32 int_control[MTK_IOMMU_BANK_MAX]; 188d7127de1SYong Wu u32 int_main_control[MTK_IOMMU_BANK_MAX]; 189d7127de1SYong Wu u32 ivrp_paddr[MTK_IOMMU_BANK_MAX]; 1906a513de3SYong Wu }; 1916a513de3SYong Wu 1929485a04aSYong Wu struct mtk_iommu_plat_data { 1939485a04aSYong Wu enum mtk_iommu_plat m4u_plat; 1949485a04aSYong Wu u32 flags; 1959485a04aSYong Wu u32 inv_sel_reg; 1969485a04aSYong Wu 1979485a04aSYong Wu char *pericfg_comp_str; 1989485a04aSYong Wu struct list_head *hw_list; 199ae669345SYong Wu 200ae669345SYong Wu /* 201ae669345SYong Wu * The IOMMU HW may support 16GB iova. In order to balance the IOVA ranges, 202ae669345SYong Wu * different masters will be put in different iova ranges, for example vcodec 203ae669345SYong Wu * is in 4G-8G and cam is in 8G-12G. Meanwhile, some masters may have the 204ae669345SYong Wu * special IOVA range requirement, like CCU can only support the address 205ae669345SYong Wu * 0x40000000-0x44000000. 206ae669345SYong Wu * Here list the iova ranges this SoC supports and which larbs/ports are in 207ae669345SYong Wu * which region. 208ae669345SYong Wu * 209ae669345SYong Wu * 16GB iova all use one pgtable, but each a region is a iommu group. 210ae669345SYong Wu */ 211ae669345SYong Wu struct { 2129485a04aSYong Wu unsigned int iova_region_nr; 2139485a04aSYong Wu const struct mtk_iommu_iova_region *iova_region; 214b2a6876dSYong Wu /* 215b2a6876dSYong Wu * Indicate the correspondance between larbs, ports and regions. 216b2a6876dSYong Wu * 217b2a6876dSYong Wu * The index is the same as iova_region and larb port numbers are 218b2a6876dSYong Wu * described as bit positions. 219b2a6876dSYong Wu * For example, storing BIT(0) at index 2,1 means "larb 1, port0 is in region 2". 220b2a6876dSYong Wu * [2] = { [1] = BIT(0) } 221b2a6876dSYong Wu */ 222b2a6876dSYong Wu const u32 (*iova_region_larb_msk)[MTK_LARB_NR_MAX]; 223ae669345SYong Wu }; 22499ca0228SYong Wu 225ae669345SYong Wu /* 226ae669345SYong Wu * The IOMMU HW may have 5 banks. Each bank has a independent pgtable. 227ae669345SYong Wu * Here list how many banks this SoC supports/enables and which ports are in which bank. 228ae669345SYong Wu */ 229ae669345SYong Wu struct { 23099ca0228SYong Wu u8 banks_num; 23199ca0228SYong Wu bool banks_enable[MTK_IOMMU_BANK_MAX]; 23257fb481fSYong Wu unsigned int banks_portmsk[MTK_IOMMU_BANK_MAX]; 233ae669345SYong Wu }; 234ae669345SYong Wu 2359485a04aSYong Wu unsigned char larbid_remap[MTK_LARB_COM_MAX][MTK_LARB_SUBCOM_MAX]; 2369485a04aSYong Wu }; 2379485a04aSYong Wu 23899ca0228SYong Wu struct mtk_iommu_bank_data { 2399485a04aSYong Wu void __iomem *base; 2409485a04aSYong Wu int irq; 24199ca0228SYong Wu u8 id; 24299ca0228SYong Wu struct device *parent_dev; 24399ca0228SYong Wu struct mtk_iommu_data *parent_data; 24499ca0228SYong Wu spinlock_t tlb_lock; /* lock for tlb range flush */ 24599ca0228SYong Wu struct mtk_iommu_domain *m4u_dom; /* Each bank has a domain */ 24699ca0228SYong Wu }; 24799ca0228SYong Wu 24899ca0228SYong Wu struct mtk_iommu_data { 2499485a04aSYong Wu struct device *dev; 2509485a04aSYong Wu struct clk *bclk; 2519485a04aSYong Wu phys_addr_t protect_base; /* protect memory base */ 2529485a04aSYong Wu struct mtk_iommu_suspend_reg reg; 2539485a04aSYong Wu struct iommu_group *m4u_group[MTK_IOMMU_GROUP_MAX]; 2549485a04aSYong Wu bool enable_4GB; 2559485a04aSYong Wu 2569485a04aSYong Wu struct iommu_device iommu; 2579485a04aSYong Wu const struct mtk_iommu_plat_data *plat_data; 2589485a04aSYong Wu struct device *smicomm_dev; 2599485a04aSYong Wu 26099ca0228SYong Wu struct mtk_iommu_bank_data *bank; 2619485a04aSYong Wu struct regmap *pericfg; 2629485a04aSYong Wu struct mutex mutex; /* Protect m4u_group/m4u_dom above */ 2639485a04aSYong Wu 2649485a04aSYong Wu /* 2659485a04aSYong Wu * In the sharing pgtable case, list data->list to the global list like m4ulist. 2669485a04aSYong Wu * In the non-sharing pgtable case, list data->list to the itself hw_list_head. 2679485a04aSYong Wu */ 2689485a04aSYong Wu struct list_head *hw_list; 2699485a04aSYong Wu struct list_head hw_list_head; 2709485a04aSYong Wu struct list_head list; 2719485a04aSYong Wu struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX]; 2729485a04aSYong Wu }; 2739485a04aSYong Wu 2740df4fabeSYong Wu struct mtk_iommu_domain { 2750df4fabeSYong Wu struct io_pgtable_cfg cfg; 2760df4fabeSYong Wu struct io_pgtable_ops *iop; 2770df4fabeSYong Wu 27899ca0228SYong Wu struct mtk_iommu_bank_data *bank; 2790df4fabeSYong Wu struct iommu_domain domain; 280ddf67a87SYong Wu 281ddf67a87SYong Wu struct mutex mutex; /* Protect "data" in this structure */ 2820df4fabeSYong Wu }; 2830df4fabeSYong Wu 2849485a04aSYong Wu static int mtk_iommu_bind(struct device *dev) 2859485a04aSYong Wu { 2869485a04aSYong Wu struct mtk_iommu_data *data = dev_get_drvdata(dev); 2879485a04aSYong Wu 2889485a04aSYong Wu return component_bind_all(dev, &data->larb_imu); 2899485a04aSYong Wu } 2909485a04aSYong Wu 2919485a04aSYong Wu static void mtk_iommu_unbind(struct device *dev) 2929485a04aSYong Wu { 2939485a04aSYong Wu struct mtk_iommu_data *data = dev_get_drvdata(dev); 2949485a04aSYong Wu 2959485a04aSYong Wu component_unbind_all(dev, &data->larb_imu); 2969485a04aSYong Wu } 2979485a04aSYong Wu 298b65f5016SArvind Yadav static const struct iommu_ops mtk_iommu_ops; 2990df4fabeSYong Wu 300e24453e1SYong Wu static int mtk_iommu_hw_init(const struct mtk_iommu_data *data, unsigned int bankid); 3017f37a91dSYong Wu 302bfed8731SYong Wu #define MTK_IOMMU_TLB_ADDR(iova) ({ \ 303bfed8731SYong Wu dma_addr_t _addr = iova; \ 304bfed8731SYong Wu ((lower_32_bits(_addr) & GENMASK(31, 12)) | upper_32_bits(_addr));\ 305bfed8731SYong Wu }) 306bfed8731SYong Wu 30776ce6546SYong Wu /* 30876ce6546SYong Wu * In M4U 4GB mode, the physical address is remapped as below: 30976ce6546SYong Wu * 31076ce6546SYong Wu * CPU Physical address: 31176ce6546SYong Wu * ==================== 31276ce6546SYong Wu * 31376ce6546SYong Wu * 0 1G 2G 3G 4G 5G 31476ce6546SYong Wu * |---A---|---B---|---C---|---D---|---E---| 31576ce6546SYong Wu * +--I/O--+------------Memory-------------+ 31676ce6546SYong Wu * 31776ce6546SYong Wu * IOMMU output physical address: 31876ce6546SYong Wu * ============================= 31976ce6546SYong Wu * 32076ce6546SYong Wu * 4G 5G 6G 7G 8G 32176ce6546SYong Wu * |---E---|---B---|---C---|---D---| 32276ce6546SYong Wu * +------------Memory-------------+ 32376ce6546SYong Wu * 32476ce6546SYong Wu * The Region 'A'(I/O) can NOT be mapped by M4U; For Region 'B'/'C'/'D', the 32576ce6546SYong Wu * bit32 of the CPU physical address always is needed to set, and for Region 32676ce6546SYong Wu * 'E', the CPU physical address keep as is. 32776ce6546SYong Wu * Additionally, The iommu consumers always use the CPU phyiscal address. 32876ce6546SYong Wu */ 329b4dad40eSYong Wu #define MTK_IOMMU_4GB_MODE_REMAP_BASE 0x140000000UL 33076ce6546SYong Wu 3317c3a2ec0SYong Wu static LIST_HEAD(m4ulist); /* List all the M4U HWs */ 3327c3a2ec0SYong Wu 3339e3a2a64SYong Wu #define for_each_m4u(data, head) list_for_each_entry(data, head, list) 3347c3a2ec0SYong Wu 335585e58f4SYong Wu static const struct mtk_iommu_iova_region single_domain[] = { 336585e58f4SYong Wu {.iova_base = 0, .size = SZ_4G}, 337585e58f4SYong Wu }; 338585e58f4SYong Wu 3396b1317f9SYong Wu #define MT8192_MULTI_REGION_NR_MAX 6 3406b1317f9SYong Wu 3416b1317f9SYong Wu #define MT8192_MULTI_REGION_NR (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) ? \ 3426b1317f9SYong Wu MT8192_MULTI_REGION_NR_MAX : 1) 3436b1317f9SYong Wu 3446b1317f9SYong Wu static const struct mtk_iommu_iova_region mt8192_multi_dom[MT8192_MULTI_REGION_NR] = { 345129a3b88SYong Wu { .iova_base = 0x0, .size = SZ_4G}, /* 0 ~ 4G */ 3469e3489e0SYong Wu #if IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) 347129a3b88SYong Wu { .iova_base = SZ_4G, .size = SZ_4G}, /* 4G ~ 8G */ 348129a3b88SYong Wu { .iova_base = SZ_4G * 2, .size = SZ_4G}, /* 8G ~ 12G */ 349129a3b88SYong Wu { .iova_base = SZ_4G * 3, .size = SZ_4G}, /* 12G ~ 16G */ 350129a3b88SYong Wu 3519e3489e0SYong Wu { .iova_base = 0x240000000ULL, .size = 0x4000000}, /* CCU0 */ 3529e3489e0SYong Wu { .iova_base = 0x244000000ULL, .size = 0x4000000}, /* CCU1 */ 3539e3489e0SYong Wu #endif 3549e3489e0SYong Wu }; 3559e3489e0SYong Wu 3569e3a2a64SYong Wu /* If 2 M4U share a domain(use the same hwlist), Put the corresponding info in first data.*/ 3579e3a2a64SYong Wu static struct mtk_iommu_data *mtk_iommu_get_frst_data(struct list_head *hwlist) 3587c3a2ec0SYong Wu { 3599e3a2a64SYong Wu return list_first_entry(hwlist, struct mtk_iommu_data, list); 3607c3a2ec0SYong Wu } 3617c3a2ec0SYong Wu 3620df4fabeSYong Wu static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom) 3630df4fabeSYong Wu { 3640df4fabeSYong Wu return container_of(dom, struct mtk_iommu_domain, domain); 3650df4fabeSYong Wu } 3660df4fabeSYong Wu 3670954d61aSYong Wu static void mtk_iommu_tlb_flush_all(struct mtk_iommu_data *data) 3680df4fabeSYong Wu { 36999ca0228SYong Wu /* Tlb flush all always is in bank0. */ 37099ca0228SYong Wu struct mtk_iommu_bank_data *bank = &data->bank[0]; 37199ca0228SYong Wu void __iomem *base = bank->base; 37215672b6dSYong Wu unsigned long flags; 373c0b57581SYong Wu 37499ca0228SYong Wu spin_lock_irqsave(&bank->tlb_lock, flags); 375887cf6a7SYong Wu writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, base + data->plat_data->inv_sel_reg); 376887cf6a7SYong Wu writel_relaxed(F_ALL_INVLD, base + REG_MMU_INVALIDATE); 3770df4fabeSYong Wu wmb(); /* Make sure the tlb flush all done */ 37899ca0228SYong Wu spin_unlock_irqrestore(&bank->tlb_lock, flags); 3797c3a2ec0SYong Wu } 3800df4fabeSYong Wu 3811f4fd624SYong Wu static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size, 38299ca0228SYong Wu struct mtk_iommu_bank_data *bank) 3830df4fabeSYong Wu { 38499ca0228SYong Wu struct list_head *head = bank->parent_data->hw_list; 38599ca0228SYong Wu struct mtk_iommu_bank_data *curbank; 38699ca0228SYong Wu struct mtk_iommu_data *data; 3876077c7e5SYong Wu bool check_pm_status; 3881f4fd624SYong Wu unsigned long flags; 389887cf6a7SYong Wu void __iomem *base; 3901f4fd624SYong Wu int ret; 3911f4fd624SYong Wu u32 tmp; 3920df4fabeSYong Wu 3939e3a2a64SYong Wu for_each_m4u(data, head) { 3946077c7e5SYong Wu /* 3956077c7e5SYong Wu * To avoid resume the iommu device frequently when the iommu device 3966077c7e5SYong Wu * is not active, it doesn't always call pm_runtime_get here, then tlb 3976077c7e5SYong Wu * flush depends on the tlb flush all in the runtime resume. 3986077c7e5SYong Wu * 3996077c7e5SYong Wu * There are 2 special cases: 4006077c7e5SYong Wu * 4016077c7e5SYong Wu * Case1: The iommu dev doesn't have power domain but has bclk. This case 4026077c7e5SYong Wu * should also avoid the tlb flush while the dev is not active to mute 4036077c7e5SYong Wu * the tlb timeout log. like mt8173. 4046077c7e5SYong Wu * 4056077c7e5SYong Wu * Case2: The power/clock of infra iommu is always on, and it doesn't 4066077c7e5SYong Wu * have the device link with the master devices. This case should avoid 4076077c7e5SYong Wu * the PM status check. 4086077c7e5SYong Wu */ 4096077c7e5SYong Wu check_pm_status = !MTK_IOMMU_HAS_FLAG(data->plat_data, PM_CLK_AO); 4106077c7e5SYong Wu 4116077c7e5SYong Wu if (check_pm_status) { 412c0b57581SYong Wu if (pm_runtime_get_if_in_use(data->dev) <= 0) 413c0b57581SYong Wu continue; 4146077c7e5SYong Wu } 415c0b57581SYong Wu 41699ca0228SYong Wu curbank = &data->bank[bank->id]; 41799ca0228SYong Wu base = curbank->base; 418887cf6a7SYong Wu 41999ca0228SYong Wu spin_lock_irqsave(&curbank->tlb_lock, flags); 4207c3a2ec0SYong Wu writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, 421887cf6a7SYong Wu base + data->plat_data->inv_sel_reg); 4220df4fabeSYong Wu 423887cf6a7SYong Wu writel_relaxed(MTK_IOMMU_TLB_ADDR(iova), base + REG_MMU_INVLD_START_A); 424bfed8731SYong Wu writel_relaxed(MTK_IOMMU_TLB_ADDR(iova + size - 1), 425887cf6a7SYong Wu base + REG_MMU_INVLD_END_A); 426887cf6a7SYong Wu writel_relaxed(F_MMU_INV_RANGE, base + REG_MMU_INVALIDATE); 4270df4fabeSYong Wu 4281f4fd624SYong Wu /* tlb sync */ 429887cf6a7SYong Wu ret = readl_poll_timeout_atomic(base + REG_MMU_CPE_DONE, 430c90ae4a6SYong Wu tmp, tmp != 0, 10, 1000); 43115672b6dSYong Wu 43215672b6dSYong Wu /* Clear the CPE status */ 433887cf6a7SYong Wu writel_relaxed(0, base + REG_MMU_CPE_DONE); 43499ca0228SYong Wu spin_unlock_irqrestore(&curbank->tlb_lock, flags); 43515672b6dSYong Wu 4360df4fabeSYong Wu if (ret) { 4370df4fabeSYong Wu dev_warn(data->dev, 4380df4fabeSYong Wu "Partial TLB flush timed out, falling back to full flush\n"); 4390954d61aSYong Wu mtk_iommu_tlb_flush_all(data); 4400df4fabeSYong Wu } 441c0b57581SYong Wu 4426077c7e5SYong Wu if (check_pm_status) 443c0b57581SYong Wu pm_runtime_put(data->dev); 4440df4fabeSYong Wu } 4457c3a2ec0SYong Wu } 4460df4fabeSYong Wu 4470df4fabeSYong Wu static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) 4480df4fabeSYong Wu { 44999ca0228SYong Wu struct mtk_iommu_bank_data *bank = dev_id; 45099ca0228SYong Wu struct mtk_iommu_data *data = bank->parent_data; 45199ca0228SYong Wu struct mtk_iommu_domain *dom = bank->m4u_dom; 452d2e9a110SYong Wu unsigned int fault_larb = MTK_INVALID_LARBID, fault_port = 0, sub_comm = 0; 453ef0f0986SYong Wu u32 int_state, regval, va34_32, pa34_32; 454887cf6a7SYong Wu const struct mtk_iommu_plat_data *plat_data = data->plat_data; 45599ca0228SYong Wu void __iomem *base = bank->base; 456ef0f0986SYong Wu u64 fault_iova, fault_pa; 4570df4fabeSYong Wu bool layer, write; 4580df4fabeSYong Wu 4590df4fabeSYong Wu /* Read error info from registers */ 460887cf6a7SYong Wu int_state = readl_relaxed(base + REG_MMU_FAULT_ST1); 46115a01f4cSYong Wu if (int_state & F_REG_MMU0_FAULT_MASK) { 462887cf6a7SYong Wu regval = readl_relaxed(base + REG_MMU0_INT_ID); 463887cf6a7SYong Wu fault_iova = readl_relaxed(base + REG_MMU0_FAULT_VA); 464887cf6a7SYong Wu fault_pa = readl_relaxed(base + REG_MMU0_INVLD_PA); 46515a01f4cSYong Wu } else { 466887cf6a7SYong Wu regval = readl_relaxed(base + REG_MMU1_INT_ID); 467887cf6a7SYong Wu fault_iova = readl_relaxed(base + REG_MMU1_FAULT_VA); 468887cf6a7SYong Wu fault_pa = readl_relaxed(base + REG_MMU1_INVLD_PA); 46915a01f4cSYong Wu } 4700df4fabeSYong Wu layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT; 4710df4fabeSYong Wu write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT; 472887cf6a7SYong Wu if (MTK_IOMMU_HAS_FLAG(plat_data, IOVA_34_EN)) { 473ef0f0986SYong Wu va34_32 = FIELD_GET(F_MMU_INVAL_VA_34_32_MASK, fault_iova); 474ef0f0986SYong Wu fault_iova = fault_iova & F_MMU_INVAL_VA_31_12_MASK; 475ef0f0986SYong Wu fault_iova |= (u64)va34_32 << 32; 476ef0f0986SYong Wu } 47782e51771SYong Wu pa34_32 = FIELD_GET(F_MMU_INVAL_PA_34_32_MASK, fault_iova); 47882e51771SYong Wu fault_pa |= (u64)pa34_32 << 32; 479ef0f0986SYong Wu 480887cf6a7SYong Wu if (MTK_IOMMU_IS_TYPE(plat_data, MTK_IOMMU_TYPE_MM)) { 481887cf6a7SYong Wu if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_2BITS)) { 48237276e00SChao Hao fault_larb = F_MMU_INT_ID_COMM_ID(regval); 48337276e00SChao Hao sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval); 48465df7d82SFabien Parent fault_port = F_MMU_INT_ID_PORT_ID(regval); 485887cf6a7SYong Wu } else if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_3BITS)) { 4869ec30c09SYong Wu fault_larb = F_MMU_INT_ID_COMM_ID_EXT(regval); 4879ec30c09SYong Wu sub_comm = F_MMU_INT_ID_SUB_COMM_ID_EXT(regval); 48865df7d82SFabien Parent fault_port = F_MMU_INT_ID_PORT_ID(regval); 48965df7d82SFabien Parent } else if (MTK_IOMMU_HAS_FLAG(plat_data, INT_ID_PORT_WIDTH_6)) { 49065df7d82SFabien Parent fault_port = F_MMU_INT_ID_PORT_ID_WID_6(regval); 49165df7d82SFabien Parent fault_larb = F_MMU_INT_ID_LARB_ID_WID_6(regval); 49237276e00SChao Hao } else { 49365df7d82SFabien Parent fault_port = F_MMU_INT_ID_PORT_ID(regval); 49437276e00SChao Hao fault_larb = F_MMU_INT_ID_LARB_ID(regval); 49537276e00SChao Hao } 49637276e00SChao Hao fault_larb = data->plat_data->larbid_remap[fault_larb][sub_comm]; 497d2e9a110SYong Wu } 498b3e5eee7SYong Wu 49900ef8885SRicardo Ribalda if (!dom || report_iommu_fault(&dom->domain, bank->parent_dev, fault_iova, 5000df4fabeSYong Wu write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) { 5010df4fabeSYong Wu dev_err_ratelimited( 50299ca0228SYong Wu bank->parent_dev, 503f9b8c9b2SYong Wu "fault type=0x%x iova=0x%llx pa=0x%llx master=0x%x(larb=%d port=%d) layer=%d %s\n", 504f9b8c9b2SYong Wu int_state, fault_iova, fault_pa, regval, fault_larb, fault_port, 5050df4fabeSYong Wu layer, write ? "write" : "read"); 5060df4fabeSYong Wu } 5070df4fabeSYong Wu 5080df4fabeSYong Wu /* Interrupt clear */ 509887cf6a7SYong Wu regval = readl_relaxed(base + REG_MMU_INT_CONTROL0); 5100df4fabeSYong Wu regval |= F_INT_CLR_BIT; 511887cf6a7SYong Wu writel_relaxed(regval, base + REG_MMU_INT_CONTROL0); 5120df4fabeSYong Wu 5130df4fabeSYong Wu mtk_iommu_tlb_flush_all(data); 5140df4fabeSYong Wu 5150df4fabeSYong Wu return IRQ_HANDLED; 5160df4fabeSYong Wu } 5170df4fabeSYong Wu 51857fb481fSYong Wu static unsigned int mtk_iommu_get_bank_id(struct device *dev, 51957fb481fSYong Wu const struct mtk_iommu_plat_data *plat_data) 52057fb481fSYong Wu { 52157fb481fSYong Wu struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 52257fb481fSYong Wu unsigned int i, portmsk = 0, bankid = 0; 52357fb481fSYong Wu 52457fb481fSYong Wu if (plat_data->banks_num == 1) 52557fb481fSYong Wu return bankid; 52657fb481fSYong Wu 52757fb481fSYong Wu for (i = 0; i < fwspec->num_ids; i++) 52857fb481fSYong Wu portmsk |= BIT(MTK_M4U_TO_PORT(fwspec->ids[i])); 52957fb481fSYong Wu 53057fb481fSYong Wu for (i = 0; i < plat_data->banks_num && i < MTK_IOMMU_BANK_MAX; i++) { 53157fb481fSYong Wu if (!plat_data->banks_enable[i]) 53257fb481fSYong Wu continue; 53357fb481fSYong Wu 53457fb481fSYong Wu if (portmsk & plat_data->banks_portmsk[i]) { 53557fb481fSYong Wu bankid = i; 53657fb481fSYong Wu break; 53757fb481fSYong Wu } 53857fb481fSYong Wu } 53957fb481fSYong Wu return bankid; /* default is 0 */ 54057fb481fSYong Wu } 54157fb481fSYong Wu 542d72e0ff5SYong Wu static int mtk_iommu_get_iova_region_id(struct device *dev, 543803cf9e5SYong Wu const struct mtk_iommu_plat_data *plat_data) 544803cf9e5SYong Wu { 545b2a6876dSYong Wu struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 546b2a6876dSYong Wu unsigned int portidmsk = 0, larbid; 547b2a6876dSYong Wu const u32 *rgn_larb_msk; 548b2a6876dSYong Wu int i; 549803cf9e5SYong Wu 550b2a6876dSYong Wu if (plat_data->iova_region_nr == 1) 551803cf9e5SYong Wu return 0; 552803cf9e5SYong Wu 553b2a6876dSYong Wu larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); 554b2a6876dSYong Wu for (i = 0; i < fwspec->num_ids; i++) 555b2a6876dSYong Wu portidmsk |= BIT(MTK_M4U_TO_PORT(fwspec->ids[i])); 556b2a6876dSYong Wu 557b2a6876dSYong Wu for (i = 0; i < plat_data->iova_region_nr; i++) { 558b2a6876dSYong Wu rgn_larb_msk = plat_data->iova_region_larb_msk[i]; 559b2a6876dSYong Wu if (!rgn_larb_msk) 560b2a6876dSYong Wu continue; 561b2a6876dSYong Wu 562b2a6876dSYong Wu if ((rgn_larb_msk[larbid] & portidmsk) == portidmsk) 563803cf9e5SYong Wu return i; 564803cf9e5SYong Wu } 565803cf9e5SYong Wu 566b2a6876dSYong Wu dev_err(dev, "Can NOT find the region for larb(%d-%x).\n", 567b2a6876dSYong Wu larbid, portidmsk); 568803cf9e5SYong Wu return -EINVAL; 569803cf9e5SYong Wu } 570803cf9e5SYong Wu 571f9b8c9b2SYong Wu static int mtk_iommu_config(struct mtk_iommu_data *data, struct device *dev, 572d72e0ff5SYong Wu bool enable, unsigned int regionid) 5730df4fabeSYong Wu { 5740df4fabeSYong Wu struct mtk_smi_larb_iommu *larb_mmu; 5750df4fabeSYong Wu unsigned int larbid, portid; 576a9bf2eecSJoerg Roedel struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 5778d2c749eSYong Wu const struct mtk_iommu_iova_region *region; 578f9b8c9b2SYong Wu u32 peri_mmuen, peri_mmuen_msk; 579f9b8c9b2SYong Wu int i, ret = 0; 5800df4fabeSYong Wu 58158f0d1d5SRobin Murphy for (i = 0; i < fwspec->num_ids; ++i) { 58258f0d1d5SRobin Murphy larbid = MTK_M4U_TO_LARB(fwspec->ids[i]); 58358f0d1d5SRobin Murphy portid = MTK_M4U_TO_PORT(fwspec->ids[i]); 5848d2c749eSYong Wu 585d2e9a110SYong Wu if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { 5861ee9feb2SYong Wu larb_mmu = &data->larb_imu[larbid]; 5870df4fabeSYong Wu 588d72e0ff5SYong Wu region = data->plat_data->iova_region + regionid; 5898d2c749eSYong Wu larb_mmu->bank[portid] = upper_32_bits(region->iova_base); 5908d2c749eSYong Wu 591d72e0ff5SYong Wu dev_dbg(dev, "%s iommu for larb(%s) port %d region %d rgn-bank %d.\n", 5928d2c749eSYong Wu enable ? "enable" : "disable", dev_name(larb_mmu->dev), 593d72e0ff5SYong Wu portid, regionid, larb_mmu->bank[portid]); 5940df4fabeSYong Wu 5950df4fabeSYong Wu if (enable) 5960df4fabeSYong Wu larb_mmu->mmu |= MTK_SMI_MMU_EN(portid); 5970df4fabeSYong Wu else 5980df4fabeSYong Wu larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid); 599f9b8c9b2SYong Wu } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA)) { 600f9b8c9b2SYong Wu peri_mmuen_msk = BIT(portid); 601e7629070SYong Wu /* PCI dev has only one output id, enable the next writing bit for PCIe */ 602e7629070SYong Wu if (dev_is_pci(dev)) 603e7629070SYong Wu peri_mmuen_msk |= BIT(portid + 1); 604f9b8c9b2SYong Wu 605e7629070SYong Wu peri_mmuen = enable ? peri_mmuen_msk : 0; 606f9b8c9b2SYong Wu ret = regmap_update_bits(data->pericfg, PERICFG_IOMMU_1, 607f9b8c9b2SYong Wu peri_mmuen_msk, peri_mmuen); 608f9b8c9b2SYong Wu if (ret) 609f9b8c9b2SYong Wu dev_err(dev, "%s iommu(%s) inframaster 0x%x fail(%d).\n", 610f9b8c9b2SYong Wu enable ? "enable" : "disable", 611f9b8c9b2SYong Wu dev_name(data->dev), peri_mmuen_msk, ret); 6120df4fabeSYong Wu } 6130df4fabeSYong Wu } 614f9b8c9b2SYong Wu return ret; 615d2e9a110SYong Wu } 6160df4fabeSYong Wu 6174f956c97SYong Wu static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom, 618c3045f39SYong Wu struct mtk_iommu_data *data, 619d72e0ff5SYong Wu unsigned int region_id) 6200df4fabeSYong Wu { 621c3045f39SYong Wu const struct mtk_iommu_iova_region *region; 62299ca0228SYong Wu struct mtk_iommu_domain *m4u_dom; 623c3045f39SYong Wu 62499ca0228SYong Wu /* Always use bank0 in sharing pgtable case */ 62599ca0228SYong Wu m4u_dom = data->bank[0].m4u_dom; 62699ca0228SYong Wu if (m4u_dom) { 62799ca0228SYong Wu dom->iop = m4u_dom->iop; 62899ca0228SYong Wu dom->cfg = m4u_dom->cfg; 62999ca0228SYong Wu dom->domain.pgsize_bitmap = m4u_dom->cfg.pgsize_bitmap; 630c3045f39SYong Wu goto update_iova_region; 631c3045f39SYong Wu } 632c3045f39SYong Wu 6330df4fabeSYong Wu dom->cfg = (struct io_pgtable_cfg) { 6340df4fabeSYong Wu .quirks = IO_PGTABLE_QUIRK_ARM_NS | 6350df4fabeSYong Wu IO_PGTABLE_QUIRK_NO_PERMS | 636b4dad40eSYong Wu IO_PGTABLE_QUIRK_ARM_MTK_EXT, 6370df4fabeSYong Wu .pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap, 6382f317da4SYong Wu .ias = MTK_IOMMU_HAS_FLAG(data->plat_data, IOVA_34_EN) ? 34 : 32, 6390df4fabeSYong Wu .iommu_dev = data->dev, 6400df4fabeSYong Wu }; 6410df4fabeSYong Wu 642301c3ca1SYunfei Wang if (MTK_IOMMU_HAS_FLAG(data->plat_data, PGTABLE_PA_35_EN)) 643301c3ca1SYunfei Wang dom->cfg.quirks |= IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT; 644301c3ca1SYunfei Wang 6459bdfe4c1SYong Wu if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) 6469bdfe4c1SYong Wu dom->cfg.oas = data->enable_4GB ? 33 : 32; 6479bdfe4c1SYong Wu else 6489bdfe4c1SYong Wu dom->cfg.oas = 35; 6499bdfe4c1SYong Wu 6500df4fabeSYong Wu dom->iop = alloc_io_pgtable_ops(ARM_V7S, &dom->cfg, data); 6510df4fabeSYong Wu if (!dom->iop) { 6520df4fabeSYong Wu dev_err(data->dev, "Failed to alloc io pgtable\n"); 653bd7ebb77SNicolin Chen return -ENOMEM; 6540df4fabeSYong Wu } 6550df4fabeSYong Wu 6560df4fabeSYong Wu /* Update our support page sizes bitmap */ 657d16e0faaSRobin Murphy dom->domain.pgsize_bitmap = dom->cfg.pgsize_bitmap; 658b7875eb9SYong Wu 659c3045f39SYong Wu update_iova_region: 660c3045f39SYong Wu /* Update the iova region for this domain */ 661d72e0ff5SYong Wu region = data->plat_data->iova_region + region_id; 662c3045f39SYong Wu dom->domain.geometry.aperture_start = region->iova_base; 663c3045f39SYong Wu dom->domain.geometry.aperture_end = region->iova_base + region->size - 1; 664b7875eb9SYong Wu dom->domain.geometry.force_aperture = true; 6650df4fabeSYong Wu return 0; 6660df4fabeSYong Wu } 6670df4fabeSYong Wu 6680df4fabeSYong Wu static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type) 6690df4fabeSYong Wu { 6700df4fabeSYong Wu struct mtk_iommu_domain *dom; 6710df4fabeSYong Wu 67232e1cccfSYong Wu if (type != IOMMU_DOMAIN_DMA && type != IOMMU_DOMAIN_UNMANAGED) 6730df4fabeSYong Wu return NULL; 6740df4fabeSYong Wu 6750df4fabeSYong Wu dom = kzalloc(sizeof(*dom), GFP_KERNEL); 6760df4fabeSYong Wu if (!dom) 6770df4fabeSYong Wu return NULL; 678ddf67a87SYong Wu mutex_init(&dom->mutex); 6790df4fabeSYong Wu 6804f956c97SYong Wu return &dom->domain; 6814f956c97SYong Wu } 6824f956c97SYong Wu 6830df4fabeSYong Wu static void mtk_iommu_domain_free(struct iommu_domain *domain) 6840df4fabeSYong Wu { 6850df4fabeSYong Wu kfree(to_mtk_domain(domain)); 6860df4fabeSYong Wu } 6870df4fabeSYong Wu 6880df4fabeSYong Wu static int mtk_iommu_attach_device(struct iommu_domain *domain, 6890df4fabeSYong Wu struct device *dev) 6900df4fabeSYong Wu { 691645b87c1SYong Wu struct mtk_iommu_data *data = dev_iommu_priv_get(dev), *frstdata; 6920df4fabeSYong Wu struct mtk_iommu_domain *dom = to_mtk_domain(domain); 6939e3a2a64SYong Wu struct list_head *hw_list = data->hw_list; 694c0b57581SYong Wu struct device *m4udev = data->dev; 69599ca0228SYong Wu struct mtk_iommu_bank_data *bank; 69657fb481fSYong Wu unsigned int bankid; 697d72e0ff5SYong Wu int ret, region_id; 6980df4fabeSYong Wu 699d72e0ff5SYong Wu region_id = mtk_iommu_get_iova_region_id(dev, data->plat_data); 700d72e0ff5SYong Wu if (region_id < 0) 701d72e0ff5SYong Wu return region_id; 702803cf9e5SYong Wu 70357fb481fSYong Wu bankid = mtk_iommu_get_bank_id(dev, data->plat_data); 704ddf67a87SYong Wu mutex_lock(&dom->mutex); 70599ca0228SYong Wu if (!dom->bank) { 706645b87c1SYong Wu /* Data is in the frstdata in sharing pgtable case. */ 7079e3a2a64SYong Wu frstdata = mtk_iommu_get_frst_data(hw_list); 708645b87c1SYong Wu 709d72e0ff5SYong Wu ret = mtk_iommu_domain_finalise(dom, frstdata, region_id); 710ddf67a87SYong Wu if (ret) { 711ddf67a87SYong Wu mutex_unlock(&dom->mutex); 71204cee82eSNicolin Chen return ret; 713ddf67a87SYong Wu } 71499ca0228SYong Wu dom->bank = &data->bank[bankid]; 7154f956c97SYong Wu } 716ddf67a87SYong Wu mutex_unlock(&dom->mutex); 7174f956c97SYong Wu 7180e5a3f2eSYong Wu mutex_lock(&data->mutex); 71999ca0228SYong Wu bank = &data->bank[bankid]; 720e24453e1SYong Wu if (!bank->m4u_dom) { /* Initialize the M4U HW for each a BANK */ 721c0b57581SYong Wu ret = pm_runtime_resume_and_get(m4udev); 722e24453e1SYong Wu if (ret < 0) { 723e24453e1SYong Wu dev_err(m4udev, "pm get fail(%d) in attach.\n", ret); 7240e5a3f2eSYong Wu goto err_unlock; 725e24453e1SYong Wu } 726c0b57581SYong Wu 727e24453e1SYong Wu ret = mtk_iommu_hw_init(data, bankid); 728c0b57581SYong Wu if (ret) { 729c0b57581SYong Wu pm_runtime_put(m4udev); 7300e5a3f2eSYong Wu goto err_unlock; 731c0b57581SYong Wu } 73299ca0228SYong Wu bank->m4u_dom = dom; 733301c3ca1SYunfei Wang writel(dom->cfg.arm_v7s_cfg.ttbr, bank->base + REG_MMU_PT_BASE_ADDR); 734c0b57581SYong Wu 735c0b57581SYong Wu pm_runtime_put(m4udev); 7360df4fabeSYong Wu } 7370e5a3f2eSYong Wu mutex_unlock(&data->mutex); 7380df4fabeSYong Wu 739d72e0ff5SYong Wu return mtk_iommu_config(data, dev, true, region_id); 7400e5a3f2eSYong Wu 7410e5a3f2eSYong Wu err_unlock: 7420e5a3f2eSYong Wu mutex_unlock(&data->mutex); 7430e5a3f2eSYong Wu return ret; 7440df4fabeSYong Wu } 7450df4fabeSYong Wu 7460df4fabeSYong Wu static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova, 74785637380SRobin Murphy phys_addr_t paddr, size_t pgsize, size_t pgcount, 74885637380SRobin Murphy int prot, gfp_t gfp, size_t *mapped) 7490df4fabeSYong Wu { 7500df4fabeSYong Wu struct mtk_iommu_domain *dom = to_mtk_domain(domain); 7510df4fabeSYong Wu 752b4dad40eSYong Wu /* The "4GB mode" M4U physically can not use the lower remap of Dram. */ 75399ca0228SYong Wu if (dom->bank->parent_data->enable_4GB) 754b4dad40eSYong Wu paddr |= BIT_ULL(32); 755b4dad40eSYong Wu 75660829b4dSYong Wu /* Synchronize with the tlb_lock */ 75785637380SRobin Murphy return dom->iop->map_pages(dom->iop, iova, paddr, pgsize, pgcount, prot, gfp, mapped); 7580df4fabeSYong Wu } 7590df4fabeSYong Wu 7600df4fabeSYong Wu static size_t mtk_iommu_unmap(struct iommu_domain *domain, 76185637380SRobin Murphy unsigned long iova, size_t pgsize, size_t pgcount, 76256f8af5eSWill Deacon struct iommu_iotlb_gather *gather) 7630df4fabeSYong Wu { 7640df4fabeSYong Wu struct mtk_iommu_domain *dom = to_mtk_domain(domain); 7650df4fabeSYong Wu 76685637380SRobin Murphy iommu_iotlb_gather_add_range(gather, iova, pgsize * pgcount); 76785637380SRobin Murphy return dom->iop->unmap_pages(dom->iop, iova, pgsize, pgcount, gather); 7680df4fabeSYong Wu } 7690df4fabeSYong Wu 77056f8af5eSWill Deacon static void mtk_iommu_flush_iotlb_all(struct iommu_domain *domain) 77156f8af5eSWill Deacon { 77208500c43SYong Wu struct mtk_iommu_domain *dom = to_mtk_domain(domain); 77308500c43SYong Wu 77499ca0228SYong Wu mtk_iommu_tlb_flush_all(dom->bank->parent_data); 77556f8af5eSWill Deacon } 77656f8af5eSWill Deacon 77756f8af5eSWill Deacon static void mtk_iommu_iotlb_sync(struct iommu_domain *domain, 77856f8af5eSWill Deacon struct iommu_iotlb_gather *gather) 7794d689b61SRobin Murphy { 78008500c43SYong Wu struct mtk_iommu_domain *dom = to_mtk_domain(domain); 781862c3715SYong Wu size_t length = gather->end - gather->start + 1; 782da3cc91bSYong Wu 78399ca0228SYong Wu mtk_iommu_tlb_flush_range_sync(gather->start, length, dom->bank); 7844d689b61SRobin Murphy } 7854d689b61SRobin Murphy 78620143451SYong Wu static void mtk_iommu_sync_map(struct iommu_domain *domain, unsigned long iova, 78720143451SYong Wu size_t size) 78820143451SYong Wu { 78908500c43SYong Wu struct mtk_iommu_domain *dom = to_mtk_domain(domain); 79020143451SYong Wu 79199ca0228SYong Wu mtk_iommu_tlb_flush_range_sync(iova, size, dom->bank); 79220143451SYong Wu } 79320143451SYong Wu 7940df4fabeSYong Wu static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain, 7950df4fabeSYong Wu dma_addr_t iova) 7960df4fabeSYong Wu { 7970df4fabeSYong Wu struct mtk_iommu_domain *dom = to_mtk_domain(domain); 7980df4fabeSYong Wu phys_addr_t pa; 7990df4fabeSYong Wu 8000df4fabeSYong Wu pa = dom->iop->iova_to_phys(dom->iop, iova); 801f13efafcSArnd Bergmann if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) && 80299ca0228SYong Wu dom->bank->parent_data->enable_4GB && 803f13efafcSArnd Bergmann pa >= MTK_IOMMU_4GB_MODE_REMAP_BASE) 804b4dad40eSYong Wu pa &= ~BIT_ULL(32); 80530e2fccfSYong Wu 8060df4fabeSYong Wu return pa; 8070df4fabeSYong Wu } 8080df4fabeSYong Wu 80980e4592aSJoerg Roedel static struct iommu_device *mtk_iommu_probe_device(struct device *dev) 8100df4fabeSYong Wu { 811a9bf2eecSJoerg Roedel struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 812b16c0170SJoerg Roedel struct mtk_iommu_data *data; 813635319a4SYong Wu struct device_link *link; 814635319a4SYong Wu struct device *larbdev; 815635319a4SYong Wu unsigned int larbid, larbidx, i; 8160df4fabeSYong Wu 817a9bf2eecSJoerg Roedel if (!fwspec || fwspec->ops != &mtk_iommu_ops) 81880e4592aSJoerg Roedel return ERR_PTR(-ENODEV); /* Not a iommu client device */ 8190df4fabeSYong Wu 8203524b559SJoerg Roedel data = dev_iommu_priv_get(dev); 821b16c0170SJoerg Roedel 822d2e9a110SYong Wu if (!MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) 823d2e9a110SYong Wu return &data->iommu; 824d2e9a110SYong Wu 825635319a4SYong Wu /* 826635319a4SYong Wu * Link the consumer device with the smi-larb device(supplier). 827635319a4SYong Wu * The device that connects with each a larb is a independent HW. 828635319a4SYong Wu * All the ports in each a device should be in the same larbs. 829635319a4SYong Wu */ 830635319a4SYong Wu larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); 831de78657eSMiles Chen if (larbid >= MTK_LARB_NR_MAX) 832de78657eSMiles Chen return ERR_PTR(-EINVAL); 833de78657eSMiles Chen 834635319a4SYong Wu for (i = 1; i < fwspec->num_ids; i++) { 835635319a4SYong Wu larbidx = MTK_M4U_TO_LARB(fwspec->ids[i]); 836635319a4SYong Wu if (larbid != larbidx) { 837635319a4SYong Wu dev_err(dev, "Can only use one larb. Fail@larb%d-%d.\n", 838635319a4SYong Wu larbid, larbidx); 839635319a4SYong Wu return ERR_PTR(-EINVAL); 840635319a4SYong Wu } 841635319a4SYong Wu } 842635319a4SYong Wu larbdev = data->larb_imu[larbid].dev; 843de78657eSMiles Chen if (!larbdev) 844de78657eSMiles Chen return ERR_PTR(-EINVAL); 845de78657eSMiles Chen 846635319a4SYong Wu link = device_link_add(dev, larbdev, 847635319a4SYong Wu DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS); 848635319a4SYong Wu if (!link) 849635319a4SYong Wu dev_err(dev, "Unable to link %s\n", dev_name(larbdev)); 85080e4592aSJoerg Roedel return &data->iommu; 8510df4fabeSYong Wu } 8520df4fabeSYong Wu 85380e4592aSJoerg Roedel static void mtk_iommu_release_device(struct device *dev) 8540df4fabeSYong Wu { 855a9bf2eecSJoerg Roedel struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 856635319a4SYong Wu struct mtk_iommu_data *data; 857635319a4SYong Wu struct device *larbdev; 858635319a4SYong Wu unsigned int larbid; 859b16c0170SJoerg Roedel 860635319a4SYong Wu data = dev_iommu_priv_get(dev); 861d2e9a110SYong Wu if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { 862635319a4SYong Wu larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); 863635319a4SYong Wu larbdev = data->larb_imu[larbid].dev; 864635319a4SYong Wu device_link_remove(dev, larbdev); 865d2e9a110SYong Wu } 8660df4fabeSYong Wu } 8670df4fabeSYong Wu 86857fb481fSYong Wu static int mtk_iommu_get_group_id(struct device *dev, const struct mtk_iommu_plat_data *plat_data) 86957fb481fSYong Wu { 87057fb481fSYong Wu unsigned int bankid; 87157fb481fSYong Wu 87257fb481fSYong Wu /* 87357fb481fSYong Wu * If the bank function is enabled, each bank is a iommu group/domain. 87457fb481fSYong Wu * Otherwise, each iova region is a iommu group/domain. 87557fb481fSYong Wu */ 87657fb481fSYong Wu bankid = mtk_iommu_get_bank_id(dev, plat_data); 87757fb481fSYong Wu if (bankid) 87857fb481fSYong Wu return bankid; 87957fb481fSYong Wu 88057fb481fSYong Wu return mtk_iommu_get_iova_region_id(dev, plat_data); 88157fb481fSYong Wu } 88257fb481fSYong Wu 8830df4fabeSYong Wu static struct iommu_group *mtk_iommu_device_group(struct device *dev) 8840df4fabeSYong Wu { 8859e3a2a64SYong Wu struct mtk_iommu_data *c_data = dev_iommu_priv_get(dev), *data; 8869e3a2a64SYong Wu struct list_head *hw_list = c_data->hw_list; 887c3045f39SYong Wu struct iommu_group *group; 88857fb481fSYong Wu int groupid; 8890df4fabeSYong Wu 8909e3a2a64SYong Wu data = mtk_iommu_get_frst_data(hw_list); 89158f0d1d5SRobin Murphy if (!data) 8920df4fabeSYong Wu return ERR_PTR(-ENODEV); 8930df4fabeSYong Wu 89457fb481fSYong Wu groupid = mtk_iommu_get_group_id(dev, data->plat_data); 89557fb481fSYong Wu if (groupid < 0) 89657fb481fSYong Wu return ERR_PTR(groupid); 897803cf9e5SYong Wu 8980e5a3f2eSYong Wu mutex_lock(&data->mutex); 89957fb481fSYong Wu group = data->m4u_group[groupid]; 900c3045f39SYong Wu if (!group) { 901c3045f39SYong Wu group = iommu_group_alloc(); 902c3045f39SYong Wu if (!IS_ERR(group)) 90357fb481fSYong Wu data->m4u_group[groupid] = group; 9043a8d40b6SRobin Murphy } else { 905c3045f39SYong Wu iommu_group_ref_get(group); 9060df4fabeSYong Wu } 9070e5a3f2eSYong Wu mutex_unlock(&data->mutex); 908c3045f39SYong Wu return group; 9090df4fabeSYong Wu } 9100df4fabeSYong Wu 9110df4fabeSYong Wu static int mtk_iommu_of_xlate(struct device *dev, struct of_phandle_args *args) 9120df4fabeSYong Wu { 9130df4fabeSYong Wu struct platform_device *m4updev; 9140df4fabeSYong Wu 9150df4fabeSYong Wu if (args->args_count != 1) { 9160df4fabeSYong Wu dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n", 9170df4fabeSYong Wu args->args_count); 9180df4fabeSYong Wu return -EINVAL; 9190df4fabeSYong Wu } 9200df4fabeSYong Wu 9213524b559SJoerg Roedel if (!dev_iommu_priv_get(dev)) { 9220df4fabeSYong Wu /* Get the m4u device */ 9230df4fabeSYong Wu m4updev = of_find_device_by_node(args->np); 9240df4fabeSYong Wu if (WARN_ON(!m4updev)) 9250df4fabeSYong Wu return -EINVAL; 9260df4fabeSYong Wu 9273524b559SJoerg Roedel dev_iommu_priv_set(dev, platform_get_drvdata(m4updev)); 9280df4fabeSYong Wu } 9290df4fabeSYong Wu 93058f0d1d5SRobin Murphy return iommu_fwspec_add_ids(dev, args->args, 1); 9310df4fabeSYong Wu } 9320df4fabeSYong Wu 933ab1d5281SYong Wu static void mtk_iommu_get_resv_regions(struct device *dev, 934ab1d5281SYong Wu struct list_head *head) 935ab1d5281SYong Wu { 936ab1d5281SYong Wu struct mtk_iommu_data *data = dev_iommu_priv_get(dev); 937d72e0ff5SYong Wu unsigned int regionid = mtk_iommu_get_iova_region_id(dev, data->plat_data), i; 938ab1d5281SYong Wu const struct mtk_iommu_iova_region *resv, *curdom; 939ab1d5281SYong Wu struct iommu_resv_region *region; 940ab1d5281SYong Wu int prot = IOMMU_WRITE | IOMMU_READ; 941ab1d5281SYong Wu 942d72e0ff5SYong Wu if ((int)regionid < 0) 943ab1d5281SYong Wu return; 944d72e0ff5SYong Wu curdom = data->plat_data->iova_region + regionid; 945ab1d5281SYong Wu for (i = 0; i < data->plat_data->iova_region_nr; i++) { 946ab1d5281SYong Wu resv = data->plat_data->iova_region + i; 947ab1d5281SYong Wu 948ab1d5281SYong Wu /* Only reserve when the region is inside the current domain */ 949ab1d5281SYong Wu if (resv->iova_base <= curdom->iova_base || 950ab1d5281SYong Wu resv->iova_base + resv->size >= curdom->iova_base + curdom->size) 951ab1d5281SYong Wu continue; 952ab1d5281SYong Wu 953ab1d5281SYong Wu region = iommu_alloc_resv_region(resv->iova_base, resv->size, 9540251d010SLu Baolu prot, IOMMU_RESV_RESERVED, 9550251d010SLu Baolu GFP_KERNEL); 956ab1d5281SYong Wu if (!region) 957ab1d5281SYong Wu return; 958ab1d5281SYong Wu 959ab1d5281SYong Wu list_add_tail(®ion->list, head); 960ab1d5281SYong Wu } 961ab1d5281SYong Wu } 962ab1d5281SYong Wu 963b65f5016SArvind Yadav static const struct iommu_ops mtk_iommu_ops = { 9640df4fabeSYong Wu .domain_alloc = mtk_iommu_domain_alloc, 96580e4592aSJoerg Roedel .probe_device = mtk_iommu_probe_device, 96680e4592aSJoerg Roedel .release_device = mtk_iommu_release_device, 9670df4fabeSYong Wu .device_group = mtk_iommu_device_group, 9680df4fabeSYong Wu .of_xlate = mtk_iommu_of_xlate, 969ab1d5281SYong Wu .get_resv_regions = mtk_iommu_get_resv_regions, 9700df4fabeSYong Wu .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M, 97118d8c74eSYong Wu .owner = THIS_MODULE, 9729a630a4bSLu Baolu .default_domain_ops = &(const struct iommu_domain_ops) { 9739a630a4bSLu Baolu .attach_dev = mtk_iommu_attach_device, 97485637380SRobin Murphy .map_pages = mtk_iommu_map, 97585637380SRobin Murphy .unmap_pages = mtk_iommu_unmap, 9769a630a4bSLu Baolu .flush_iotlb_all = mtk_iommu_flush_iotlb_all, 9779a630a4bSLu Baolu .iotlb_sync = mtk_iommu_iotlb_sync, 9789a630a4bSLu Baolu .iotlb_sync_map = mtk_iommu_sync_map, 9799a630a4bSLu Baolu .iova_to_phys = mtk_iommu_iova_to_phys, 9809a630a4bSLu Baolu .free = mtk_iommu_domain_free, 9819a630a4bSLu Baolu } 9820df4fabeSYong Wu }; 9830df4fabeSYong Wu 984e24453e1SYong Wu static int mtk_iommu_hw_init(const struct mtk_iommu_data *data, unsigned int bankid) 9850df4fabeSYong Wu { 986e24453e1SYong Wu const struct mtk_iommu_bank_data *bankx = &data->bank[bankid]; 98799ca0228SYong Wu const struct mtk_iommu_bank_data *bank0 = &data->bank[0]; 9880df4fabeSYong Wu u32 regval; 9890df4fabeSYong Wu 990e24453e1SYong Wu /* 991e24453e1SYong Wu * Global control settings are in bank0. May re-init these global registers 992e24453e1SYong Wu * since no sure if there is bank0 consumers. 993e24453e1SYong Wu */ 99486580ec9SAngeloGioacchino Del Regno if (MTK_IOMMU_HAS_FLAG(data->plat_data, TF_PORT_TO_ADDR_MT8173)) { 995acb3c92aSYong Wu regval = F_MMU_PREFETCH_RT_REPLACE_MOD | 996acb3c92aSYong Wu F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173; 99786444413SChao Hao } else { 99899ca0228SYong Wu regval = readl_relaxed(bank0->base + REG_MMU_CTRL_REG); 99986444413SChao Hao regval |= F_MMU_TF_PROT_TO_PROGRAM_ADDR; 100086444413SChao Hao } 100199ca0228SYong Wu writel_relaxed(regval, bank0->base + REG_MMU_CTRL_REG); 10020df4fabeSYong Wu 10036b717796SChao Hao if (data->enable_4GB && 10046b717796SChao Hao MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_VLD_PA_RNG)) { 100530e2fccfSYong Wu /* 100630e2fccfSYong Wu * If 4GB mode is enabled, the validate PA range is from 100730e2fccfSYong Wu * 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30]. 100830e2fccfSYong Wu */ 100930e2fccfSYong Wu regval = F_MMU_VLD_PA_RNG(7, 4); 101099ca0228SYong Wu writel_relaxed(regval, bank0->base + REG_MMU_VLD_PA_RNG); 101130e2fccfSYong Wu } 10129a87005eSYong Wu if (MTK_IOMMU_HAS_FLAG(data->plat_data, DCM_DISABLE)) 101399ca0228SYong Wu writel_relaxed(F_MMU_DCM, bank0->base + REG_MMU_DCM_DIS); 10149a87005eSYong Wu else 101599ca0228SYong Wu writel_relaxed(0, bank0->base + REG_MMU_DCM_DIS); 10169a87005eSYong Wu 101735c1b48dSChao Hao if (MTK_IOMMU_HAS_FLAG(data->plat_data, WR_THROT_EN)) { 101835c1b48dSChao Hao /* write command throttling mode */ 101999ca0228SYong Wu regval = readl_relaxed(bank0->base + REG_MMU_WR_LEN_CTRL); 102035c1b48dSChao Hao regval &= ~F_MMU_WR_THROT_DIS_MASK; 102199ca0228SYong Wu writel_relaxed(regval, bank0->base + REG_MMU_WR_LEN_CTRL); 102235c1b48dSChao Hao } 1023e6dec923SYong Wu 10246b717796SChao Hao if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) { 102575eed350SChao Hao /* The register is called STANDARD_AXI_MODE in this case */ 10264bb2bf4cSChao Hao regval = 0; 10274bb2bf4cSChao Hao } else { 102899ca0228SYong Wu regval = readl_relaxed(bank0->base + REG_MMU_MISC_CTRL); 1029d265a4adSYong Wu if (!MTK_IOMMU_HAS_FLAG(data->plat_data, STD_AXI_MODE)) 10304bb2bf4cSChao Hao regval &= ~F_MMU_STANDARD_AXI_MODE_MASK; 10314bb2bf4cSChao Hao if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_WR_EN)) 10324bb2bf4cSChao Hao regval &= ~F_MMU_IN_ORDER_WR_EN_MASK; 103375eed350SChao Hao } 103499ca0228SYong Wu writel_relaxed(regval, bank0->base + REG_MMU_MISC_CTRL); 10350df4fabeSYong Wu 1036e24453e1SYong Wu /* Independent settings for each bank */ 1037634f57dfSYong Wu regval = F_L2_MULIT_HIT_EN | 1038634f57dfSYong Wu F_TABLE_WALK_FAULT_INT_EN | 1039634f57dfSYong Wu F_PREETCH_FIFO_OVERFLOW_INT_EN | 1040634f57dfSYong Wu F_MISS_FIFO_OVERFLOW_INT_EN | 1041634f57dfSYong Wu F_PREFETCH_FIFO_ERR_INT_EN | 1042634f57dfSYong Wu F_MISS_FIFO_ERR_INT_EN; 1043e24453e1SYong Wu writel_relaxed(regval, bankx->base + REG_MMU_INT_CONTROL0); 1044634f57dfSYong Wu 1045634f57dfSYong Wu regval = F_INT_TRANSLATION_FAULT | 1046634f57dfSYong Wu F_INT_MAIN_MULTI_HIT_FAULT | 1047634f57dfSYong Wu F_INT_INVALID_PA_FAULT | 1048634f57dfSYong Wu F_INT_ENTRY_REPLACEMENT_FAULT | 1049634f57dfSYong Wu F_INT_TLB_MISS_FAULT | 1050634f57dfSYong Wu F_INT_MISS_TRANSACTION_FIFO_FAULT | 1051634f57dfSYong Wu F_INT_PRETETCH_TRANSATION_FIFO_FAULT; 1052e24453e1SYong Wu writel_relaxed(regval, bankx->base + REG_MMU_INT_MAIN_CONTROL); 1053634f57dfSYong Wu 1054634f57dfSYong Wu if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_LEGACY_IVRP_PADDR)) 1055634f57dfSYong Wu regval = (data->protect_base >> 1) | (data->enable_4GB << 31); 1056634f57dfSYong Wu else 1057634f57dfSYong Wu regval = lower_32_bits(data->protect_base) | 1058634f57dfSYong Wu upper_32_bits(data->protect_base); 1059e24453e1SYong Wu writel_relaxed(regval, bankx->base + REG_MMU_IVRP_PADDR); 1060634f57dfSYong Wu 1061e24453e1SYong Wu if (devm_request_irq(bankx->parent_dev, bankx->irq, mtk_iommu_isr, 0, 1062e24453e1SYong Wu dev_name(bankx->parent_dev), (void *)bankx)) { 1063e24453e1SYong Wu writel_relaxed(0, bankx->base + REG_MMU_PT_BASE_ADDR); 1064e24453e1SYong Wu dev_err(bankx->parent_dev, "Failed @ IRQ-%d Request\n", bankx->irq); 10650df4fabeSYong Wu return -ENODEV; 10660df4fabeSYong Wu } 10670df4fabeSYong Wu 10680df4fabeSYong Wu return 0; 10690df4fabeSYong Wu } 10700df4fabeSYong Wu 10710df4fabeSYong Wu static const struct component_master_ops mtk_iommu_com_ops = { 10720df4fabeSYong Wu .bind = mtk_iommu_bind, 10730df4fabeSYong Wu .unbind = mtk_iommu_unbind, 10740df4fabeSYong Wu }; 10750df4fabeSYong Wu 1076d2e9a110SYong Wu static int mtk_iommu_mm_dts_parse(struct device *dev, struct component_match **match, 1077d2e9a110SYong Wu struct mtk_iommu_data *data) 1078d2e9a110SYong Wu { 10796cde583dSYong Wu struct device_node *larbnode, *frst_avail_smicomm_node = NULL; 1080dcb40e9fSYong Wu struct platform_device *plarbdev, *pcommdev; 1081d2e9a110SYong Wu struct device_link *link; 1082d2e9a110SYong Wu int i, larb_nr, ret; 1083d2e9a110SYong Wu 1084d2e9a110SYong Wu larb_nr = of_count_phandle_with_args(dev->of_node, "mediatek,larbs", NULL); 1085d2e9a110SYong Wu if (larb_nr < 0) 1086d2e9a110SYong Wu return larb_nr; 1087ef693a84SGuenter Roeck if (larb_nr == 0 || larb_nr > MTK_LARB_NR_MAX) 1088ef693a84SGuenter Roeck return -EINVAL; 1089d2e9a110SYong Wu 1090d2e9a110SYong Wu for (i = 0; i < larb_nr; i++) { 10916cde583dSYong Wu struct device_node *smicomm_node, *smi_subcomm_node; 1092d2e9a110SYong Wu u32 id; 1093d2e9a110SYong Wu 1094d2e9a110SYong Wu larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i); 109526593928SYong Wu if (!larbnode) { 109626593928SYong Wu ret = -EINVAL; 109726593928SYong Wu goto err_larbdev_put; 109826593928SYong Wu } 1099d2e9a110SYong Wu 1100d2e9a110SYong Wu if (!of_device_is_available(larbnode)) { 1101d2e9a110SYong Wu of_node_put(larbnode); 1102d2e9a110SYong Wu continue; 1103d2e9a110SYong Wu } 1104d2e9a110SYong Wu 1105d2e9a110SYong Wu ret = of_property_read_u32(larbnode, "mediatek,larb-id", &id); 1106d2e9a110SYong Wu if (ret)/* The id is consecutive if there is no this property */ 1107d2e9a110SYong Wu id = i; 1108ef693a84SGuenter Roeck if (id >= MTK_LARB_NR_MAX) { 1109ef693a84SGuenter Roeck of_node_put(larbnode); 1110ef693a84SGuenter Roeck ret = -EINVAL; 1111ef693a84SGuenter Roeck goto err_larbdev_put; 1112ef693a84SGuenter Roeck } 1113d2e9a110SYong Wu 1114d2e9a110SYong Wu plarbdev = of_find_device_by_node(larbnode); 1115d2e9a110SYong Wu of_node_put(larbnode); 1116d2e9a110SYong Wu if (!plarbdev) { 111726593928SYong Wu ret = -ENODEV; 111826593928SYong Wu goto err_larbdev_put; 1119d2e9a110SYong Wu } 1120ef693a84SGuenter Roeck if (data->larb_imu[id].dev) { 1121ef693a84SGuenter Roeck platform_device_put(plarbdev); 1122ef693a84SGuenter Roeck ret = -EEXIST; 1123ef693a84SGuenter Roeck goto err_larbdev_put; 1124d2e9a110SYong Wu } 1125d2e9a110SYong Wu data->larb_imu[id].dev = &plarbdev->dev; 1126d2e9a110SYong Wu 112726593928SYong Wu if (!plarbdev->dev.driver) { 112826593928SYong Wu ret = -EPROBE_DEFER; 112926593928SYong Wu goto err_larbdev_put; 1130d2e9a110SYong Wu } 1131d2e9a110SYong Wu 1132f7b71d0dSYong Wu /* Get smi-(sub)-common dev from the last larb. */ 1133f7b71d0dSYong Wu smi_subcomm_node = of_parse_phandle(larbnode, "mediatek,smi", 0); 11346cde583dSYong Wu if (!smi_subcomm_node) { 11356cde583dSYong Wu ret = -EINVAL; 11366cde583dSYong Wu goto err_larbdev_put; 11376cde583dSYong Wu } 1138d2e9a110SYong Wu 1139f7b71d0dSYong Wu /* 1140f7b71d0dSYong Wu * It may have two level smi-common. the node is smi-sub-common if it 1141f7b71d0dSYong Wu * has a new mediatek,smi property. otherwise it is smi-commmon. 1142f7b71d0dSYong Wu */ 1143f7b71d0dSYong Wu smicomm_node = of_parse_phandle(smi_subcomm_node, "mediatek,smi", 0); 1144f7b71d0dSYong Wu if (smicomm_node) 1145f7b71d0dSYong Wu of_node_put(smi_subcomm_node); 1146f7b71d0dSYong Wu else 1147f7b71d0dSYong Wu smicomm_node = smi_subcomm_node; 1148f7b71d0dSYong Wu 11496cde583dSYong Wu /* 11506cde583dSYong Wu * All the larbs that connect to one IOMMU must connect with the same 11516cde583dSYong Wu * smi-common. 11526cde583dSYong Wu */ 11536cde583dSYong Wu if (!frst_avail_smicomm_node) { 11546cde583dSYong Wu frst_avail_smicomm_node = smicomm_node; 11556cde583dSYong Wu } else if (frst_avail_smicomm_node != smicomm_node) { 11566cde583dSYong Wu dev_err(dev, "mediatek,smi property is not right @larb%d.", id); 1157d2e9a110SYong Wu of_node_put(smicomm_node); 11586cde583dSYong Wu ret = -EINVAL; 11596cde583dSYong Wu goto err_larbdev_put; 11606cde583dSYong Wu } else { 11616cde583dSYong Wu of_node_put(smicomm_node); 11626cde583dSYong Wu } 11636cde583dSYong Wu 11646cde583dSYong Wu component_match_add(dev, match, component_compare_dev, &plarbdev->dev); 11656cde583dSYong Wu platform_device_put(plarbdev); 11666cde583dSYong Wu } 11676cde583dSYong Wu 11686cde583dSYong Wu if (!frst_avail_smicomm_node) 11696cde583dSYong Wu return -EINVAL; 11706cde583dSYong Wu 11716cde583dSYong Wu pcommdev = of_find_device_by_node(frst_avail_smicomm_node); 11726cde583dSYong Wu of_node_put(frst_avail_smicomm_node); 1173dcb40e9fSYong Wu if (!pcommdev) 1174dcb40e9fSYong Wu return -ENODEV; 1175dcb40e9fSYong Wu data->smicomm_dev = &pcommdev->dev; 1176d2e9a110SYong Wu 1177d2e9a110SYong Wu link = device_link_add(data->smicomm_dev, dev, 1178d2e9a110SYong Wu DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME); 1179dcb40e9fSYong Wu platform_device_put(pcommdev); 1180d2e9a110SYong Wu if (!link) { 1181d2e9a110SYong Wu dev_err(dev, "Unable to link %s.\n", dev_name(data->smicomm_dev)); 1182d2e9a110SYong Wu return -EINVAL; 1183d2e9a110SYong Wu } 1184d2e9a110SYong Wu return 0; 118526593928SYong Wu 118626593928SYong Wu err_larbdev_put: 1187462e768bSDan Carpenter for (i = MTK_LARB_NR_MAX - 1; i >= 0; i--) { 118826593928SYong Wu if (!data->larb_imu[i].dev) 118926593928SYong Wu continue; 119026593928SYong Wu put_device(data->larb_imu[i].dev); 119126593928SYong Wu } 119226593928SYong Wu return ret; 1193d2e9a110SYong Wu } 1194d2e9a110SYong Wu 11950df4fabeSYong Wu static int mtk_iommu_probe(struct platform_device *pdev) 11960df4fabeSYong Wu { 11970df4fabeSYong Wu struct mtk_iommu_data *data; 11980df4fabeSYong Wu struct device *dev = &pdev->dev; 11990df4fabeSYong Wu struct resource *res; 1200b16c0170SJoerg Roedel resource_size_t ioaddr; 12010df4fabeSYong Wu struct component_match *match = NULL; 1202c2c59456SMiles Chen struct regmap *infracfg; 12030df4fabeSYong Wu void *protect; 120442d57fc5SYong Wu int ret, banks_num, i = 0; 1205c2c59456SMiles Chen u32 val; 1206c2c59456SMiles Chen char *p; 120799ca0228SYong Wu struct mtk_iommu_bank_data *bank; 120899ca0228SYong Wu void __iomem *base; 12090df4fabeSYong Wu 12100df4fabeSYong Wu data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 12110df4fabeSYong Wu if (!data) 12120df4fabeSYong Wu return -ENOMEM; 12130df4fabeSYong Wu data->dev = dev; 1214cecdce9dSYong Wu data->plat_data = of_device_get_match_data(dev); 12150df4fabeSYong Wu 12160df4fabeSYong Wu /* Protect memory. HW will access here while translation fault.*/ 12170df4fabeSYong Wu protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2, GFP_KERNEL); 12180df4fabeSYong Wu if (!protect) 12190df4fabeSYong Wu return -ENOMEM; 12200df4fabeSYong Wu data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN); 12210df4fabeSYong Wu 1222c2c59456SMiles Chen if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) { 12237d748ffdSAngeloGioacchino Del Regno infracfg = syscon_regmap_lookup_by_phandle(dev->of_node, "mediatek,infracfg"); 12247d748ffdSAngeloGioacchino Del Regno if (IS_ERR(infracfg)) { 12257d748ffdSAngeloGioacchino Del Regno /* 12267d748ffdSAngeloGioacchino Del Regno * Legacy devicetrees will not specify a phandle to 12277d748ffdSAngeloGioacchino Del Regno * mediatek,infracfg: in that case, we use the older 12287d748ffdSAngeloGioacchino Del Regno * way to retrieve a syscon to infra. 12297d748ffdSAngeloGioacchino Del Regno * 12307d748ffdSAngeloGioacchino Del Regno * This is for retrocompatibility purposes only, hence 12317d748ffdSAngeloGioacchino Del Regno * no more compatibles shall be added to this. 12327d748ffdSAngeloGioacchino Del Regno */ 1233c2c59456SMiles Chen switch (data->plat_data->m4u_plat) { 1234c2c59456SMiles Chen case M4U_MT2712: 1235c2c59456SMiles Chen p = "mediatek,mt2712-infracfg"; 1236c2c59456SMiles Chen break; 1237c2c59456SMiles Chen case M4U_MT8173: 1238c2c59456SMiles Chen p = "mediatek,mt8173-infracfg"; 1239c2c59456SMiles Chen break; 1240c2c59456SMiles Chen default: 1241c2c59456SMiles Chen p = NULL; 1242c2c59456SMiles Chen } 1243c2c59456SMiles Chen 1244c2c59456SMiles Chen infracfg = syscon_regmap_lookup_by_compatible(p); 1245c2c59456SMiles Chen if (IS_ERR(infracfg)) 1246c2c59456SMiles Chen return PTR_ERR(infracfg); 12477d748ffdSAngeloGioacchino Del Regno } 1248c2c59456SMiles Chen 1249c2c59456SMiles Chen ret = regmap_read(infracfg, REG_INFRA_MISC, &val); 1250c2c59456SMiles Chen if (ret) 1251c2c59456SMiles Chen return ret; 1252c2c59456SMiles Chen data->enable_4GB = !!(val & F_DDR_4GB_SUPPORT_EN); 1253c2c59456SMiles Chen } 125401e23c93SYong Wu 125542d57fc5SYong Wu banks_num = data->plat_data->banks_num; 12560df4fabeSYong Wu res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 125773b6924cSYang Yingliang if (!res) 125873b6924cSYang Yingliang return -EINVAL; 125942d57fc5SYong Wu if (resource_size(res) < banks_num * MTK_IOMMU_BANK_SZ) { 126042d57fc5SYong Wu dev_err(dev, "banknr %d. res %pR is not enough.\n", banks_num, res); 126142d57fc5SYong Wu return -EINVAL; 126242d57fc5SYong Wu } 126399ca0228SYong Wu base = devm_ioremap_resource(dev, res); 126499ca0228SYong Wu if (IS_ERR(base)) 126599ca0228SYong Wu return PTR_ERR(base); 1266b16c0170SJoerg Roedel ioaddr = res->start; 12670df4fabeSYong Wu 126899ca0228SYong Wu data->bank = devm_kmalloc(dev, banks_num * sizeof(*data->bank), GFP_KERNEL); 126999ca0228SYong Wu if (!data->bank) 127099ca0228SYong Wu return -ENOMEM; 127199ca0228SYong Wu 127242d57fc5SYong Wu do { 127342d57fc5SYong Wu if (!data->plat_data->banks_enable[i]) 127442d57fc5SYong Wu continue; 127542d57fc5SYong Wu bank = &data->bank[i]; 127642d57fc5SYong Wu bank->id = i; 127742d57fc5SYong Wu bank->base = base + i * MTK_IOMMU_BANK_SZ; 127899ca0228SYong Wu bank->m4u_dom = NULL; 127942d57fc5SYong Wu 128042d57fc5SYong Wu bank->irq = platform_get_irq(pdev, i); 128199ca0228SYong Wu if (bank->irq < 0) 128299ca0228SYong Wu return bank->irq; 128399ca0228SYong Wu bank->parent_dev = dev; 128499ca0228SYong Wu bank->parent_data = data; 128599ca0228SYong Wu spin_lock_init(&bank->tlb_lock); 128642d57fc5SYong Wu } while (++i < banks_num); 12870df4fabeSYong Wu 12886b717796SChao Hao if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_BCLK)) { 12890df4fabeSYong Wu data->bclk = devm_clk_get(dev, "bclk"); 12900df4fabeSYong Wu if (IS_ERR(data->bclk)) 12910df4fabeSYong Wu return PTR_ERR(data->bclk); 12922aa4c259SYong Wu } 12930df4fabeSYong Wu 1294f045e9dfSYong Wu if (MTK_IOMMU_HAS_FLAG(data->plat_data, PGTABLE_PA_35_EN)) { 1295f045e9dfSYong Wu ret = dma_set_mask(dev, DMA_BIT_MASK(35)); 1296f045e9dfSYong Wu if (ret) { 1297f045e9dfSYong Wu dev_err(dev, "Failed to set dma_mask 35.\n"); 1298f045e9dfSYong Wu return ret; 1299f045e9dfSYong Wu } 1300f045e9dfSYong Wu } 1301f045e9dfSYong Wu 1302c0b57581SYong Wu pm_runtime_enable(dev); 1303c0b57581SYong Wu 1304d2e9a110SYong Wu if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { 1305d2e9a110SYong Wu ret = mtk_iommu_mm_dts_parse(dev, &match, data); 1306d2e9a110SYong Wu if (ret) { 13073168010dSNícolas F. R. A. Prado dev_err_probe(dev, ret, "mm dts parse fail\n"); 1308c0b57581SYong Wu goto out_runtime_disable; 1309baf94e6eSYong Wu } 131021fd9be4SAngeloGioacchino Del Regno } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA)) { 131121fd9be4SAngeloGioacchino Del Regno p = data->plat_data->pericfg_comp_str; 131221fd9be4SAngeloGioacchino Del Regno data->pericfg = syscon_regmap_lookup_by_compatible(p); 131321fd9be4SAngeloGioacchino Del Regno if (IS_ERR(data->pericfg)) { 131421fd9be4SAngeloGioacchino Del Regno ret = PTR_ERR(data->pericfg); 1315f9b8c9b2SYong Wu goto out_runtime_disable; 1316f9b8c9b2SYong Wu } 1317d2e9a110SYong Wu } 1318baf94e6eSYong Wu 13190df4fabeSYong Wu platform_set_drvdata(pdev, data); 13200e5a3f2eSYong Wu mutex_init(&data->mutex); 13210df4fabeSYong Wu 1322b16c0170SJoerg Roedel ret = iommu_device_sysfs_add(&data->iommu, dev, NULL, 1323b16c0170SJoerg Roedel "mtk-iommu.%pa", &ioaddr); 1324b16c0170SJoerg Roedel if (ret) 1325baf94e6eSYong Wu goto out_link_remove; 1326b16c0170SJoerg Roedel 13272d471b20SRobin Murphy ret = iommu_device_register(&data->iommu, &mtk_iommu_ops, dev); 1328b16c0170SJoerg Roedel if (ret) 1329986d9ec5SYong Wu goto out_sysfs_remove; 1330b16c0170SJoerg Roedel 13319e3a2a64SYong Wu if (MTK_IOMMU_HAS_FLAG(data->plat_data, SHARE_PGTABLE)) { 13329e3a2a64SYong Wu list_add_tail(&data->list, data->plat_data->hw_list); 13339e3a2a64SYong Wu data->hw_list = data->plat_data->hw_list; 13349e3a2a64SYong Wu } else { 13359e3a2a64SYong Wu INIT_LIST_HEAD(&data->hw_list_head); 13369e3a2a64SYong Wu list_add_tail(&data->list, &data->hw_list_head); 13379e3a2a64SYong Wu data->hw_list = &data->hw_list_head; 13389e3a2a64SYong Wu } 13397c3a2ec0SYong Wu 1340d2e9a110SYong Wu if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { 1341986d9ec5SYong Wu ret = component_master_add_with_match(dev, &mtk_iommu_com_ops, match); 1342986d9ec5SYong Wu if (ret) 1343e7629070SYong Wu goto out_list_del; 1344e7629070SYong Wu } 1345986d9ec5SYong Wu return ret; 1346986d9ec5SYong Wu 1347986d9ec5SYong Wu out_list_del: 1348986d9ec5SYong Wu list_del(&data->list); 1349986d9ec5SYong Wu iommu_device_unregister(&data->iommu); 1350986d9ec5SYong Wu out_sysfs_remove: 1351986d9ec5SYong Wu iommu_device_sysfs_remove(&data->iommu); 1352baf94e6eSYong Wu out_link_remove: 1353d2e9a110SYong Wu if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) 1354baf94e6eSYong Wu device_link_remove(data->smicomm_dev, dev); 1355c0b57581SYong Wu out_runtime_disable: 1356c0b57581SYong Wu pm_runtime_disable(dev); 1357986d9ec5SYong Wu return ret; 13580df4fabeSYong Wu } 13590df4fabeSYong Wu 13600df4fabeSYong Wu static int mtk_iommu_remove(struct platform_device *pdev) 13610df4fabeSYong Wu { 13620df4fabeSYong Wu struct mtk_iommu_data *data = platform_get_drvdata(pdev); 136342d57fc5SYong Wu struct mtk_iommu_bank_data *bank; 136442d57fc5SYong Wu int i; 13650df4fabeSYong Wu 1366b16c0170SJoerg Roedel iommu_device_sysfs_remove(&data->iommu); 1367b16c0170SJoerg Roedel iommu_device_unregister(&data->iommu); 1368b16c0170SJoerg Roedel 1369ee55f75eSYong Wu list_del(&data->list); 13700df4fabeSYong Wu 1371d2e9a110SYong Wu if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { 1372baf94e6eSYong Wu device_link_remove(data->smicomm_dev, &pdev->dev); 1373d2e9a110SYong Wu component_master_del(&pdev->dev, &mtk_iommu_com_ops); 1374d2e9a110SYong Wu } 1375c0b57581SYong Wu pm_runtime_disable(&pdev->dev); 137642d57fc5SYong Wu for (i = 0; i < data->plat_data->banks_num; i++) { 137742d57fc5SYong Wu bank = &data->bank[i]; 137842d57fc5SYong Wu if (!bank->m4u_dom) 137942d57fc5SYong Wu continue; 138099ca0228SYong Wu devm_free_irq(&pdev->dev, bank->irq, bank); 138142d57fc5SYong Wu } 13820df4fabeSYong Wu return 0; 13830df4fabeSYong Wu } 13840df4fabeSYong Wu 138534665c79SYong Wu static int __maybe_unused mtk_iommu_runtime_suspend(struct device *dev) 13860df4fabeSYong Wu { 13870df4fabeSYong Wu struct mtk_iommu_data *data = dev_get_drvdata(dev); 13880df4fabeSYong Wu struct mtk_iommu_suspend_reg *reg = &data->reg; 1389d7127de1SYong Wu void __iomem *base; 1390d7127de1SYong Wu int i = 0; 13910df4fabeSYong Wu 1392d7127de1SYong Wu base = data->bank[i].base; 139335c1b48dSChao Hao reg->wr_len_ctrl = readl_relaxed(base + REG_MMU_WR_LEN_CTRL); 139475eed350SChao Hao reg->misc_ctrl = readl_relaxed(base + REG_MMU_MISC_CTRL); 13950df4fabeSYong Wu reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS); 13960df4fabeSYong Wu reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG); 1397b9475b34SYong Wu reg->vld_pa_rng = readl_relaxed(base + REG_MMU_VLD_PA_RNG); 1398d7127de1SYong Wu do { 1399d7127de1SYong Wu if (!data->plat_data->banks_enable[i]) 1400d7127de1SYong Wu continue; 1401d7127de1SYong Wu base = data->bank[i].base; 1402d7127de1SYong Wu reg->int_control[i] = readl_relaxed(base + REG_MMU_INT_CONTROL0); 1403d7127de1SYong Wu reg->int_main_control[i] = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL); 1404d7127de1SYong Wu reg->ivrp_paddr[i] = readl_relaxed(base + REG_MMU_IVRP_PADDR); 1405d7127de1SYong Wu } while (++i < data->plat_data->banks_num); 14066254b64fSYong Wu clk_disable_unprepare(data->bclk); 14070df4fabeSYong Wu return 0; 14080df4fabeSYong Wu } 14090df4fabeSYong Wu 141034665c79SYong Wu static int __maybe_unused mtk_iommu_runtime_resume(struct device *dev) 14110df4fabeSYong Wu { 14120df4fabeSYong Wu struct mtk_iommu_data *data = dev_get_drvdata(dev); 14130df4fabeSYong Wu struct mtk_iommu_suspend_reg *reg = &data->reg; 1414d7127de1SYong Wu struct mtk_iommu_domain *m4u_dom; 1415d7127de1SYong Wu void __iomem *base; 1416d7127de1SYong Wu int ret, i = 0; 14170df4fabeSYong Wu 14186254b64fSYong Wu ret = clk_prepare_enable(data->bclk); 14196254b64fSYong Wu if (ret) { 14206254b64fSYong Wu dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret); 14216254b64fSYong Wu return ret; 14226254b64fSYong Wu } 1423b34ea31fSDafna Hirschfeld 1424b34ea31fSDafna Hirschfeld /* 1425b34ea31fSDafna Hirschfeld * Uppon first resume, only enable the clk and return, since the values of the 1426b34ea31fSDafna Hirschfeld * registers are not yet set. 1427b34ea31fSDafna Hirschfeld */ 1428d7127de1SYong Wu if (!reg->wr_len_ctrl) 1429b34ea31fSDafna Hirschfeld return 0; 1430b34ea31fSDafna Hirschfeld 1431d7127de1SYong Wu base = data->bank[i].base; 143235c1b48dSChao Hao writel_relaxed(reg->wr_len_ctrl, base + REG_MMU_WR_LEN_CTRL); 143375eed350SChao Hao writel_relaxed(reg->misc_ctrl, base + REG_MMU_MISC_CTRL); 14340df4fabeSYong Wu writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS); 14350df4fabeSYong Wu writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG); 1436b9475b34SYong Wu writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG); 1437d7127de1SYong Wu do { 1438d7127de1SYong Wu m4u_dom = data->bank[i].m4u_dom; 1439d7127de1SYong Wu if (!data->plat_data->banks_enable[i] || !m4u_dom) 1440d7127de1SYong Wu continue; 1441d7127de1SYong Wu base = data->bank[i].base; 1442d7127de1SYong Wu writel_relaxed(reg->int_control[i], base + REG_MMU_INT_CONTROL0); 1443d7127de1SYong Wu writel_relaxed(reg->int_main_control[i], base + REG_MMU_INT_MAIN_CONTROL); 1444d7127de1SYong Wu writel_relaxed(reg->ivrp_paddr[i], base + REG_MMU_IVRP_PADDR); 1445301c3ca1SYunfei Wang writel(m4u_dom->cfg.arm_v7s_cfg.ttbr, base + REG_MMU_PT_BASE_ADDR); 1446d7127de1SYong Wu } while (++i < data->plat_data->banks_num); 14474f23f6d4SYong Wu 14484f23f6d4SYong Wu /* 14494f23f6d4SYong Wu * Users may allocate dma buffer before they call pm_runtime_get, 14504f23f6d4SYong Wu * in which case it will lack the necessary tlb flush. 14514f23f6d4SYong Wu * Thus, make sure to update the tlb after each PM resume. 14524f23f6d4SYong Wu */ 14534f23f6d4SYong Wu mtk_iommu_tlb_flush_all(data); 14540df4fabeSYong Wu return 0; 14550df4fabeSYong Wu } 14560df4fabeSYong Wu 1457e6dec923SYong Wu static const struct dev_pm_ops mtk_iommu_pm_ops = { 145834665c79SYong Wu SET_RUNTIME_PM_OPS(mtk_iommu_runtime_suspend, mtk_iommu_runtime_resume, NULL) 145934665c79SYong Wu SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 146034665c79SYong Wu pm_runtime_force_resume) 14610df4fabeSYong Wu }; 14620df4fabeSYong Wu 1463cecdce9dSYong Wu static const struct mtk_iommu_plat_data mt2712_data = { 1464cecdce9dSYong Wu .m4u_plat = M4U_MT2712, 1465d2e9a110SYong Wu .flags = HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG | SHARE_PGTABLE | 1466d2e9a110SYong Wu MTK_IOMMU_TYPE_MM, 14679e3a2a64SYong Wu .hw_list = &m4ulist, 1468b053bc71SChao Hao .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 1469585e58f4SYong Wu .iova_region = single_domain, 147099ca0228SYong Wu .banks_num = 1, 147199ca0228SYong Wu .banks_enable = {true}, 1472585e58f4SYong Wu .iova_region_nr = ARRAY_SIZE(single_domain), 147337276e00SChao Hao .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}}, 1474cecdce9dSYong Wu }; 1475cecdce9dSYong Wu 1476068c86e9SChao Hao static const struct mtk_iommu_plat_data mt6779_data = { 1477068c86e9SChao Hao .m4u_plat = M4U_MT6779, 1478d2e9a110SYong Wu .flags = HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | WR_THROT_EN | 1479301c3ca1SYunfei Wang MTK_IOMMU_TYPE_MM | PGTABLE_PA_35_EN, 1480068c86e9SChao Hao .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 148199ca0228SYong Wu .banks_num = 1, 148299ca0228SYong Wu .banks_enable = {true}, 1483585e58f4SYong Wu .iova_region = single_domain, 1484585e58f4SYong Wu .iova_region_nr = ARRAY_SIZE(single_domain), 1485068c86e9SChao Hao .larbid_remap = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}}, 1486cecdce9dSYong Wu }; 1487cecdce9dSYong Wu 1488717ec15eSAngeloGioacchino Del Regno static const struct mtk_iommu_plat_data mt6795_data = { 1489717ec15eSAngeloGioacchino Del Regno .m4u_plat = M4U_MT6795, 1490717ec15eSAngeloGioacchino Del Regno .flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI | 1491717ec15eSAngeloGioacchino Del Regno HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM | 1492717ec15eSAngeloGioacchino Del Regno TF_PORT_TO_ADDR_MT8173, 1493717ec15eSAngeloGioacchino Del Regno .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 1494717ec15eSAngeloGioacchino Del Regno .banks_num = 1, 1495717ec15eSAngeloGioacchino Del Regno .banks_enable = {true}, 1496717ec15eSAngeloGioacchino Del Regno .iova_region = single_domain, 1497717ec15eSAngeloGioacchino Del Regno .iova_region_nr = ARRAY_SIZE(single_domain), 1498717ec15eSAngeloGioacchino Del Regno .larbid_remap = {{0}, {1}, {2}, {3}, {4}}, /* Linear mapping. */ 1499717ec15eSAngeloGioacchino Del Regno }; 1500717ec15eSAngeloGioacchino Del Regno 15013c213562SFabien Parent static const struct mtk_iommu_plat_data mt8167_data = { 15023c213562SFabien Parent .m4u_plat = M4U_MT8167, 1503d2e9a110SYong Wu .flags = RESET_AXI | HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM, 15043c213562SFabien Parent .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 150599ca0228SYong Wu .banks_num = 1, 150699ca0228SYong Wu .banks_enable = {true}, 1507585e58f4SYong Wu .iova_region = single_domain, 1508585e58f4SYong Wu .iova_region_nr = ARRAY_SIZE(single_domain), 15093c213562SFabien Parent .larbid_remap = {{0}, {1}, {2}}, /* Linear mapping. */ 15103c213562SFabien Parent }; 15113c213562SFabien Parent 1512cecdce9dSYong Wu static const struct mtk_iommu_plat_data mt8173_data = { 1513cecdce9dSYong Wu .m4u_plat = M4U_MT8173, 1514d1b5ef00SFabien Parent .flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI | 151586580ec9SAngeloGioacchino Del Regno HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM | 151686580ec9SAngeloGioacchino Del Regno TF_PORT_TO_ADDR_MT8173, 1517b053bc71SChao Hao .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 151899ca0228SYong Wu .banks_num = 1, 151999ca0228SYong Wu .banks_enable = {true}, 1520585e58f4SYong Wu .iova_region = single_domain, 1521585e58f4SYong Wu .iova_region_nr = ARRAY_SIZE(single_domain), 152237276e00SChao Hao .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */ 1523cecdce9dSYong Wu }; 1524cecdce9dSYong Wu 1525907ba6a1SYong Wu static const struct mtk_iommu_plat_data mt8183_data = { 1526907ba6a1SYong Wu .m4u_plat = M4U_MT8183, 1527d2e9a110SYong Wu .flags = RESET_AXI | MTK_IOMMU_TYPE_MM, 1528b053bc71SChao Hao .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 152999ca0228SYong Wu .banks_num = 1, 153099ca0228SYong Wu .banks_enable = {true}, 1531585e58f4SYong Wu .iova_region = single_domain, 1532585e58f4SYong Wu .iova_region_nr = ARRAY_SIZE(single_domain), 153337276e00SChao Hao .larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}}, 1534907ba6a1SYong Wu }; 1535907ba6a1SYong Wu 1536e8d7ccaaSYong Wu static const struct mtk_iommu_plat_data mt8186_data_mm = { 1537e8d7ccaaSYong Wu .m4u_plat = M4U_MT8186, 1538e8d7ccaaSYong Wu .flags = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | 1539e8d7ccaaSYong Wu WR_THROT_EN | IOVA_34_EN | MTK_IOMMU_TYPE_MM, 1540e8d7ccaaSYong Wu .larbid_remap = {{0}, {1, MTK_INVALID_LARBID, 8}, {4}, {7}, {2}, {9, 11, 19, 20}, 1541e8d7ccaaSYong Wu {MTK_INVALID_LARBID, 14, 16}, 1542e8d7ccaaSYong Wu {MTK_INVALID_LARBID, 13, MTK_INVALID_LARBID, 17}}, 1543e8d7ccaaSYong Wu .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 1544e8d7ccaaSYong Wu .banks_num = 1, 1545e8d7ccaaSYong Wu .banks_enable = {true}, 1546e8d7ccaaSYong Wu .iova_region = mt8192_multi_dom, 1547e8d7ccaaSYong Wu .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), 1548e8d7ccaaSYong Wu }; 1549e8d7ccaaSYong Wu 15506b1317f9SYong Wu static const unsigned int mt8192_larb_region_msk[MT8192_MULTI_REGION_NR_MAX][MTK_LARB_NR_MAX] = { 15516b1317f9SYong Wu [0] = {~0, ~0}, /* Region0: larb0/1 */ 15526b1317f9SYong Wu [1] = {0, 0, 0, 0, ~0, ~0, 0, ~0}, /* Region1: larb4/5/7 */ 15536b1317f9SYong Wu [2] = {0, 0, ~0, 0, 0, 0, 0, 0, /* Region2: larb2/9/11/13/14/16/17/18/19/20 */ 15546b1317f9SYong Wu 0, ~0, 0, ~0, 0, ~(u32)(BIT(9) | BIT(10)), ~(u32)(BIT(4) | BIT(5)), 0, 15556b1317f9SYong Wu ~0, ~0, ~0, ~0, ~0}, 15566b1317f9SYong Wu [3] = {0}, 15576b1317f9SYong Wu [4] = {[13] = BIT(9) | BIT(10)}, /* larb13 port9/10 */ 15586b1317f9SYong Wu [5] = {[14] = BIT(4) | BIT(5)}, /* larb14 port4/5 */ 15596b1317f9SYong Wu }; 15606b1317f9SYong Wu 15619e3489e0SYong Wu static const struct mtk_iommu_plat_data mt8192_data = { 15629e3489e0SYong Wu .m4u_plat = M4U_MT8192, 15639ec30c09SYong Wu .flags = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | 1564d2e9a110SYong Wu WR_THROT_EN | IOVA_34_EN | MTK_IOMMU_TYPE_MM, 15659e3489e0SYong Wu .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 156699ca0228SYong Wu .banks_num = 1, 156799ca0228SYong Wu .banks_enable = {true}, 15689e3489e0SYong Wu .iova_region = mt8192_multi_dom, 15699e3489e0SYong Wu .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), 15706b1317f9SYong Wu .iova_region_larb_msk = mt8192_larb_region_msk, 15719e3489e0SYong Wu .larbid_remap = {{0}, {1}, {4, 5}, {7}, {2}, {9, 11, 19, 20}, 15729e3489e0SYong Wu {0, 14, 16}, {0, 13, 18, 17}}, 15739e3489e0SYong Wu }; 15749e3489e0SYong Wu 1575ef68a193SYong Wu static const struct mtk_iommu_plat_data mt8195_data_infra = { 1576ef68a193SYong Wu .m4u_plat = M4U_MT8195, 1577ef68a193SYong Wu .flags = WR_THROT_EN | DCM_DISABLE | STD_AXI_MODE | PM_CLK_AO | 1578ef68a193SYong Wu MTK_IOMMU_TYPE_INFRA | IFA_IOMMU_PCIE_SUPPORT, 1579ef68a193SYong Wu .pericfg_comp_str = "mediatek,mt8195-pericfg_ao", 1580ef68a193SYong Wu .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 15817597e3c5SYong Wu .banks_num = 5, 15827597e3c5SYong Wu .banks_enable = {true, false, false, false, true}, 15837597e3c5SYong Wu .banks_portmsk = {[0] = GENMASK(19, 16), /* PCIe */ 15847597e3c5SYong Wu [4] = GENMASK(31, 20), /* USB */ 15857597e3c5SYong Wu }, 1586ef68a193SYong Wu .iova_region = single_domain, 1587ef68a193SYong Wu .iova_region_nr = ARRAY_SIZE(single_domain), 1588ef68a193SYong Wu }; 1589ef68a193SYong Wu 1590*a43e767dSYong Wu static const unsigned int mt8195_larb_region_msk[MT8192_MULTI_REGION_NR_MAX][MTK_LARB_NR_MAX] = { 1591*a43e767dSYong Wu [0] = {~0, ~0, ~0, ~0}, /* Region0: all ports for larb0/1/2/3 */ 1592*a43e767dSYong Wu [1] = {0, 0, 0, 0, 0, 0, 0, 0, 1593*a43e767dSYong Wu 0, 0, 0, 0, 0, 0, 0, 0, 1594*a43e767dSYong Wu 0, 0, 0, ~0, ~0, ~0, ~0, ~0, /* Region1: larb19/20/21/22/23/24 */ 1595*a43e767dSYong Wu ~0}, 1596*a43e767dSYong Wu [2] = {0, 0, 0, 0, ~0, ~0, ~0, ~0, /* Region2: the other larbs. */ 1597*a43e767dSYong Wu ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, 1598*a43e767dSYong Wu ~0, ~0, 0, 0, 0, 0, 0, 0, 1599*a43e767dSYong Wu 0, ~0, ~0, ~0, ~0}, 1600*a43e767dSYong Wu [3] = {0}, 1601*a43e767dSYong Wu [4] = {[18] = BIT(0) | BIT(1)}, /* Only larb18 port0/1 */ 1602*a43e767dSYong Wu [5] = {[18] = BIT(2) | BIT(3)}, /* Only larb18 port2/3 */ 1603*a43e767dSYong Wu }; 1604*a43e767dSYong Wu 1605ef68a193SYong Wu static const struct mtk_iommu_plat_data mt8195_data_vdo = { 1606ef68a193SYong Wu .m4u_plat = M4U_MT8195, 1607ef68a193SYong Wu .flags = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | 1608ef68a193SYong Wu WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE | MTK_IOMMU_TYPE_MM, 1609ef68a193SYong Wu .hw_list = &m4ulist, 1610ef68a193SYong Wu .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 161199ca0228SYong Wu .banks_num = 1, 161299ca0228SYong Wu .banks_enable = {true}, 1613ef68a193SYong Wu .iova_region = mt8192_multi_dom, 1614ef68a193SYong Wu .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), 1615*a43e767dSYong Wu .iova_region_larb_msk = mt8195_larb_region_msk, 1616ef68a193SYong Wu .larbid_remap = {{2, 0}, {21}, {24}, {7}, {19}, {9, 10, 11}, 1617ef68a193SYong Wu {13, 17, 15/* 17b */, 25}, {5}}, 1618ef68a193SYong Wu }; 1619ef68a193SYong Wu 1620ef68a193SYong Wu static const struct mtk_iommu_plat_data mt8195_data_vpp = { 1621ef68a193SYong Wu .m4u_plat = M4U_MT8195, 1622ef68a193SYong Wu .flags = HAS_BCLK | HAS_SUB_COMM_3BITS | OUT_ORDER_WR_EN | 1623ef68a193SYong Wu WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE | MTK_IOMMU_TYPE_MM, 1624ef68a193SYong Wu .hw_list = &m4ulist, 1625ef68a193SYong Wu .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 162699ca0228SYong Wu .banks_num = 1, 162799ca0228SYong Wu .banks_enable = {true}, 1628ef68a193SYong Wu .iova_region = mt8192_multi_dom, 1629ef68a193SYong Wu .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), 1630*a43e767dSYong Wu .iova_region_larb_msk = mt8195_larb_region_msk, 1631ef68a193SYong Wu .larbid_remap = {{1}, {3}, 1632ef68a193SYong Wu {22, MTK_INVALID_LARBID, MTK_INVALID_LARBID, MTK_INVALID_LARBID, 23}, 1633ef68a193SYong Wu {8}, {20}, {12}, 1634ef68a193SYong Wu /* 16: 16a; 29: 16b; 30: CCUtop0; 31: CCUtop1 */ 1635ef68a193SYong Wu {14, 16, 29, 26, 30, 31, 18}, 1636ef68a193SYong Wu {4, MTK_INVALID_LARBID, MTK_INVALID_LARBID, MTK_INVALID_LARBID, 6}}, 1637ef68a193SYong Wu }; 1638ef68a193SYong Wu 16393cd0e4a3SFabien Parent static const struct mtk_iommu_plat_data mt8365_data = { 16403cd0e4a3SFabien Parent .m4u_plat = M4U_MT8365, 16413cd0e4a3SFabien Parent .flags = RESET_AXI | INT_ID_PORT_WIDTH_6, 16423cd0e4a3SFabien Parent .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 16433cd0e4a3SFabien Parent .banks_num = 1, 16443cd0e4a3SFabien Parent .banks_enable = {true}, 16453cd0e4a3SFabien Parent .iova_region = single_domain, 16463cd0e4a3SFabien Parent .iova_region_nr = ARRAY_SIZE(single_domain), 16473cd0e4a3SFabien Parent .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */ 16483cd0e4a3SFabien Parent }; 16493cd0e4a3SFabien Parent 16500df4fabeSYong Wu static const struct of_device_id mtk_iommu_of_ids[] = { 1651cecdce9dSYong Wu { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data}, 1652068c86e9SChao Hao { .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data}, 1653717ec15eSAngeloGioacchino Del Regno { .compatible = "mediatek,mt6795-m4u", .data = &mt6795_data}, 16543c213562SFabien Parent { .compatible = "mediatek,mt8167-m4u", .data = &mt8167_data}, 1655cecdce9dSYong Wu { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data}, 1656907ba6a1SYong Wu { .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data}, 1657e8d7ccaaSYong Wu { .compatible = "mediatek,mt8186-iommu-mm", .data = &mt8186_data_mm}, /* mm: m4u */ 16589e3489e0SYong Wu { .compatible = "mediatek,mt8192-m4u", .data = &mt8192_data}, 1659ef68a193SYong Wu { .compatible = "mediatek,mt8195-iommu-infra", .data = &mt8195_data_infra}, 1660ef68a193SYong Wu { .compatible = "mediatek,mt8195-iommu-vdo", .data = &mt8195_data_vdo}, 1661ef68a193SYong Wu { .compatible = "mediatek,mt8195-iommu-vpp", .data = &mt8195_data_vpp}, 16623cd0e4a3SFabien Parent { .compatible = "mediatek,mt8365-m4u", .data = &mt8365_data}, 16630df4fabeSYong Wu {} 16640df4fabeSYong Wu }; 16650df4fabeSYong Wu 16660df4fabeSYong Wu static struct platform_driver mtk_iommu_driver = { 16670df4fabeSYong Wu .probe = mtk_iommu_probe, 16680df4fabeSYong Wu .remove = mtk_iommu_remove, 16690df4fabeSYong Wu .driver = { 16700df4fabeSYong Wu .name = "mtk-iommu", 1671f53dd978SKrzysztof Kozlowski .of_match_table = mtk_iommu_of_ids, 16720df4fabeSYong Wu .pm = &mtk_iommu_pm_ops, 16730df4fabeSYong Wu } 16740df4fabeSYong Wu }; 167518d8c74eSYong Wu module_platform_driver(mtk_iommu_driver); 16760df4fabeSYong Wu 167718d8c74eSYong Wu MODULE_DESCRIPTION("IOMMU API for MediaTek M4U implementations"); 167818d8c74eSYong Wu MODULE_LICENSE("GPL v2"); 1679