11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 20df4fabeSYong Wu /* 30df4fabeSYong Wu * Copyright (c) 2015-2016 MediaTek Inc. 40df4fabeSYong Wu * Author: Yong Wu <yong.wu@mediatek.com> 50df4fabeSYong Wu */ 6ef0f0986SYong Wu #include <linux/bitfield.h> 70df4fabeSYong Wu #include <linux/bug.h> 80df4fabeSYong Wu #include <linux/clk.h> 90df4fabeSYong Wu #include <linux/component.h> 100df4fabeSYong Wu #include <linux/device.h> 11803cf9e5SYong Wu #include <linux/dma-direct.h> 120df4fabeSYong Wu #include <linux/err.h> 130df4fabeSYong Wu #include <linux/interrupt.h> 140df4fabeSYong Wu #include <linux/io.h> 150df4fabeSYong Wu #include <linux/iommu.h> 160df4fabeSYong Wu #include <linux/iopoll.h> 176a513de3SYong Wu #include <linux/io-pgtable.h> 180df4fabeSYong Wu #include <linux/list.h> 19c2c59456SMiles Chen #include <linux/mfd/syscon.h> 2018d8c74eSYong Wu #include <linux/module.h> 210df4fabeSYong Wu #include <linux/of_address.h> 220df4fabeSYong Wu #include <linux/of_irq.h> 230df4fabeSYong Wu #include <linux/of_platform.h> 24e7629070SYong Wu #include <linux/pci.h> 250df4fabeSYong Wu #include <linux/platform_device.h> 26baf94e6eSYong Wu #include <linux/pm_runtime.h> 27c2c59456SMiles Chen #include <linux/regmap.h> 280df4fabeSYong Wu #include <linux/slab.h> 290df4fabeSYong Wu #include <linux/spinlock.h> 30c2c59456SMiles Chen #include <linux/soc/mediatek/infracfg.h> 310df4fabeSYong Wu #include <asm/barrier.h> 320df4fabeSYong Wu #include <soc/mediatek/smi.h> 330df4fabeSYong Wu 346a513de3SYong Wu #include <dt-bindings/memory/mtk-memory-port.h> 350df4fabeSYong Wu 360df4fabeSYong Wu #define REG_MMU_PT_BASE_ADDR 0x000 37907ba6a1SYong Wu #define MMU_PT_ADDR_MASK GENMASK(31, 7) 380df4fabeSYong Wu 390df4fabeSYong Wu #define REG_MMU_INVALIDATE 0x020 400df4fabeSYong Wu #define F_ALL_INVLD 0x2 410df4fabeSYong Wu #define F_MMU_INV_RANGE 0x1 420df4fabeSYong Wu 430df4fabeSYong Wu #define REG_MMU_INVLD_START_A 0x024 440df4fabeSYong Wu #define REG_MMU_INVLD_END_A 0x028 450df4fabeSYong Wu 46068c86e9SChao Hao #define REG_MMU_INV_SEL_GEN2 0x02c 47b053bc71SChao Hao #define REG_MMU_INV_SEL_GEN1 0x038 480df4fabeSYong Wu #define F_INVLD_EN0 BIT(0) 490df4fabeSYong Wu #define F_INVLD_EN1 BIT(1) 500df4fabeSYong Wu 5175eed350SChao Hao #define REG_MMU_MISC_CTRL 0x048 524bb2bf4cSChao Hao #define F_MMU_IN_ORDER_WR_EN_MASK (BIT(1) | BIT(17)) 534bb2bf4cSChao Hao #define F_MMU_STANDARD_AXI_MODE_MASK (BIT(3) | BIT(19)) 544bb2bf4cSChao Hao 550df4fabeSYong Wu #define REG_MMU_DCM_DIS 0x050 569a87005eSYong Wu #define F_MMU_DCM BIT(8) 579a87005eSYong Wu 5835c1b48dSChao Hao #define REG_MMU_WR_LEN_CTRL 0x054 5935c1b48dSChao Hao #define F_MMU_WR_THROT_DIS_MASK (BIT(5) | BIT(21)) 600df4fabeSYong Wu 610df4fabeSYong Wu #define REG_MMU_CTRL_REG 0x110 62acb3c92aSYong Wu #define F_MMU_TF_PROT_TO_PROGRAM_ADDR (2 << 4) 630df4fabeSYong Wu #define F_MMU_PREFETCH_RT_REPLACE_MOD BIT(4) 64acb3c92aSYong Wu #define F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173 (2 << 5) 650df4fabeSYong Wu 660df4fabeSYong Wu #define REG_MMU_IVRP_PADDR 0x114 6770ca608bSYong Wu 6830e2fccfSYong Wu #define REG_MMU_VLD_PA_RNG 0x118 6930e2fccfSYong Wu #define F_MMU_VLD_PA_RNG(EA, SA) (((EA) << 8) | (SA)) 700df4fabeSYong Wu 710df4fabeSYong Wu #define REG_MMU_INT_CONTROL0 0x120 720df4fabeSYong Wu #define F_L2_MULIT_HIT_EN BIT(0) 730df4fabeSYong Wu #define F_TABLE_WALK_FAULT_INT_EN BIT(1) 740df4fabeSYong Wu #define F_PREETCH_FIFO_OVERFLOW_INT_EN BIT(2) 750df4fabeSYong Wu #define F_MISS_FIFO_OVERFLOW_INT_EN BIT(3) 760df4fabeSYong Wu #define F_PREFETCH_FIFO_ERR_INT_EN BIT(5) 770df4fabeSYong Wu #define F_MISS_FIFO_ERR_INT_EN BIT(6) 780df4fabeSYong Wu #define F_INT_CLR_BIT BIT(12) 790df4fabeSYong Wu 800df4fabeSYong Wu #define REG_MMU_INT_MAIN_CONTROL 0x124 8115a01f4cSYong Wu /* mmu0 | mmu1 */ 8215a01f4cSYong Wu #define F_INT_TRANSLATION_FAULT (BIT(0) | BIT(7)) 8315a01f4cSYong Wu #define F_INT_MAIN_MULTI_HIT_FAULT (BIT(1) | BIT(8)) 8415a01f4cSYong Wu #define F_INT_INVALID_PA_FAULT (BIT(2) | BIT(9)) 8515a01f4cSYong Wu #define F_INT_ENTRY_REPLACEMENT_FAULT (BIT(3) | BIT(10)) 8615a01f4cSYong Wu #define F_INT_TLB_MISS_FAULT (BIT(4) | BIT(11)) 8715a01f4cSYong Wu #define F_INT_MISS_TRANSACTION_FIFO_FAULT (BIT(5) | BIT(12)) 8815a01f4cSYong Wu #define F_INT_PRETETCH_TRANSATION_FIFO_FAULT (BIT(6) | BIT(13)) 890df4fabeSYong Wu 900df4fabeSYong Wu #define REG_MMU_CPE_DONE 0x12C 910df4fabeSYong Wu 920df4fabeSYong Wu #define REG_MMU_FAULT_ST1 0x134 9315a01f4cSYong Wu #define F_REG_MMU0_FAULT_MASK GENMASK(6, 0) 9415a01f4cSYong Wu #define F_REG_MMU1_FAULT_MASK GENMASK(13, 7) 950df4fabeSYong Wu 9615a01f4cSYong Wu #define REG_MMU0_FAULT_VA 0x13c 97ef0f0986SYong Wu #define F_MMU_INVAL_VA_31_12_MASK GENMASK(31, 12) 98ef0f0986SYong Wu #define F_MMU_INVAL_VA_34_32_MASK GENMASK(11, 9) 99ef0f0986SYong Wu #define F_MMU_INVAL_PA_34_32_MASK GENMASK(8, 6) 1000df4fabeSYong Wu #define F_MMU_FAULT_VA_WRITE_BIT BIT(1) 1010df4fabeSYong Wu #define F_MMU_FAULT_VA_LAYER_BIT BIT(0) 1020df4fabeSYong Wu 10315a01f4cSYong Wu #define REG_MMU0_INVLD_PA 0x140 10415a01f4cSYong Wu #define REG_MMU1_FAULT_VA 0x144 10515a01f4cSYong Wu #define REG_MMU1_INVLD_PA 0x148 10615a01f4cSYong Wu #define REG_MMU0_INT_ID 0x150 10715a01f4cSYong Wu #define REG_MMU1_INT_ID 0x154 10837276e00SChao Hao #define F_MMU_INT_ID_COMM_ID(a) (((a) >> 9) & 0x7) 10937276e00SChao Hao #define F_MMU_INT_ID_SUB_COMM_ID(a) (((a) >> 7) & 0x3) 1109ec30c09SYong Wu #define F_MMU_INT_ID_COMM_ID_EXT(a) (((a) >> 10) & 0x7) 1119ec30c09SYong Wu #define F_MMU_INT_ID_SUB_COMM_ID_EXT(a) (((a) >> 7) & 0x7) 11215a01f4cSYong Wu #define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7) 11315a01f4cSYong Wu #define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f) 1140df4fabeSYong Wu 115829316b3SChao Hao #define MTK_PROTECT_PA_ALIGN 256 116*42d57fc5SYong Wu #define MTK_IOMMU_BANK_SZ 0x1000 1170df4fabeSYong Wu 118f9b8c9b2SYong Wu #define PERICFG_IOMMU_1 0x714 119f9b8c9b2SYong Wu 1206b717796SChao Hao #define HAS_4GB_MODE BIT(0) 1216b717796SChao Hao /* HW will use the EMI clock if there isn't the "bclk". */ 1226b717796SChao Hao #define HAS_BCLK BIT(1) 1236b717796SChao Hao #define HAS_VLD_PA_RNG BIT(2) 1246b717796SChao Hao #define RESET_AXI BIT(3) 1254bb2bf4cSChao Hao #define OUT_ORDER_WR_EN BIT(4) 1269ec30c09SYong Wu #define HAS_SUB_COMM_2BITS BIT(5) 1279ec30c09SYong Wu #define HAS_SUB_COMM_3BITS BIT(6) 1289ec30c09SYong Wu #define WR_THROT_EN BIT(7) 1299ec30c09SYong Wu #define HAS_LEGACY_IVRP_PADDR BIT(8) 1309ec30c09SYong Wu #define IOVA_34_EN BIT(9) 1319ec30c09SYong Wu #define SHARE_PGTABLE BIT(10) /* 2 HW share pgtable */ 1329ec30c09SYong Wu #define DCM_DISABLE BIT(11) 1339ec30c09SYong Wu #define STD_AXI_MODE BIT(12) /* For non MM iommu */ 1348cd1e619SYong Wu /* 2 bits: iommu type */ 1358cd1e619SYong Wu #define MTK_IOMMU_TYPE_MM (0x0 << 13) 1368cd1e619SYong Wu #define MTK_IOMMU_TYPE_INFRA (0x1 << 13) 1378cd1e619SYong Wu #define MTK_IOMMU_TYPE_MASK (0x3 << 13) 1386077c7e5SYong Wu /* PM and clock always on. e.g. infra iommu */ 1396077c7e5SYong Wu #define PM_CLK_AO BIT(15) 140e7629070SYong Wu #define IFA_IOMMU_PCIE_SUPPORT BIT(16) 1416b717796SChao Hao 1428cd1e619SYong Wu #define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \ 1438cd1e619SYong Wu ((((pdata)->flags) & (mask)) == (_x)) 1448cd1e619SYong Wu 1458cd1e619SYong Wu #define MTK_IOMMU_HAS_FLAG(pdata, _x) MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, _x) 1468cd1e619SYong Wu #define MTK_IOMMU_IS_TYPE(pdata, _x) MTK_IOMMU_HAS_FLAG_MASK(pdata, _x,\ 1478cd1e619SYong Wu MTK_IOMMU_TYPE_MASK) 1486b717796SChao Hao 149d2e9a110SYong Wu #define MTK_INVALID_LARBID MTK_LARB_NR_MAX 150d2e9a110SYong Wu 1519485a04aSYong Wu #define MTK_LARB_COM_MAX 8 1529485a04aSYong Wu #define MTK_LARB_SUBCOM_MAX 8 1539485a04aSYong Wu 1549485a04aSYong Wu #define MTK_IOMMU_GROUP_MAX 8 15599ca0228SYong Wu #define MTK_IOMMU_BANK_MAX 5 1569485a04aSYong Wu 1579485a04aSYong Wu enum mtk_iommu_plat { 1589485a04aSYong Wu M4U_MT2712, 1599485a04aSYong Wu M4U_MT6779, 1609485a04aSYong Wu M4U_MT8167, 1619485a04aSYong Wu M4U_MT8173, 1629485a04aSYong Wu M4U_MT8183, 1639485a04aSYong Wu M4U_MT8192, 1649485a04aSYong Wu M4U_MT8195, 1659485a04aSYong Wu }; 1669485a04aSYong Wu 1679485a04aSYong Wu struct mtk_iommu_iova_region { 1689485a04aSYong Wu dma_addr_t iova_base; 1699485a04aSYong Wu unsigned long long size; 1709485a04aSYong Wu }; 1719485a04aSYong Wu 1726a513de3SYong Wu struct mtk_iommu_suspend_reg { 1736a513de3SYong Wu u32 misc_ctrl; 1746a513de3SYong Wu u32 dcm_dis; 1756a513de3SYong Wu u32 ctrl_reg; 1766a513de3SYong Wu u32 int_control0; 1776a513de3SYong Wu u32 int_main_control; 1786a513de3SYong Wu u32 ivrp_paddr; 1796a513de3SYong Wu u32 vld_pa_rng; 1806a513de3SYong Wu u32 wr_len_ctrl; 1816a513de3SYong Wu }; 1826a513de3SYong Wu 1839485a04aSYong Wu struct mtk_iommu_plat_data { 1849485a04aSYong Wu enum mtk_iommu_plat m4u_plat; 1859485a04aSYong Wu u32 flags; 1869485a04aSYong Wu u32 inv_sel_reg; 1879485a04aSYong Wu 1889485a04aSYong Wu char *pericfg_comp_str; 1899485a04aSYong Wu struct list_head *hw_list; 1909485a04aSYong Wu unsigned int iova_region_nr; 1919485a04aSYong Wu const struct mtk_iommu_iova_region *iova_region; 19299ca0228SYong Wu 19399ca0228SYong Wu u8 banks_num; 19499ca0228SYong Wu bool banks_enable[MTK_IOMMU_BANK_MAX]; 19557fb481fSYong Wu unsigned int banks_portmsk[MTK_IOMMU_BANK_MAX]; 1969485a04aSYong Wu unsigned char larbid_remap[MTK_LARB_COM_MAX][MTK_LARB_SUBCOM_MAX]; 1979485a04aSYong Wu }; 1989485a04aSYong Wu 19999ca0228SYong Wu struct mtk_iommu_bank_data { 2009485a04aSYong Wu void __iomem *base; 2019485a04aSYong Wu int irq; 20299ca0228SYong Wu u8 id; 20399ca0228SYong Wu struct device *parent_dev; 20499ca0228SYong Wu struct mtk_iommu_data *parent_data; 20599ca0228SYong Wu spinlock_t tlb_lock; /* lock for tlb range flush */ 20699ca0228SYong Wu struct mtk_iommu_domain *m4u_dom; /* Each bank has a domain */ 20799ca0228SYong Wu }; 20899ca0228SYong Wu 20999ca0228SYong Wu struct mtk_iommu_data { 2109485a04aSYong Wu struct device *dev; 2119485a04aSYong Wu struct clk *bclk; 2129485a04aSYong Wu phys_addr_t protect_base; /* protect memory base */ 2139485a04aSYong Wu struct mtk_iommu_suspend_reg reg; 2149485a04aSYong Wu struct iommu_group *m4u_group[MTK_IOMMU_GROUP_MAX]; 2159485a04aSYong Wu bool enable_4GB; 2169485a04aSYong Wu 2179485a04aSYong Wu struct iommu_device iommu; 2189485a04aSYong Wu const struct mtk_iommu_plat_data *plat_data; 2199485a04aSYong Wu struct device *smicomm_dev; 2209485a04aSYong Wu 22199ca0228SYong Wu struct mtk_iommu_bank_data *bank; 22299ca0228SYong Wu 2239485a04aSYong Wu struct dma_iommu_mapping *mapping; /* For mtk_iommu_v1.c */ 2249485a04aSYong Wu struct regmap *pericfg; 2259485a04aSYong Wu 2269485a04aSYong Wu struct mutex mutex; /* Protect m4u_group/m4u_dom above */ 2279485a04aSYong Wu 2289485a04aSYong Wu /* 2299485a04aSYong Wu * In the sharing pgtable case, list data->list to the global list like m4ulist. 2309485a04aSYong Wu * In the non-sharing pgtable case, list data->list to the itself hw_list_head. 2319485a04aSYong Wu */ 2329485a04aSYong Wu struct list_head *hw_list; 2339485a04aSYong Wu struct list_head hw_list_head; 2349485a04aSYong Wu struct list_head list; 2359485a04aSYong Wu struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX]; 2369485a04aSYong Wu }; 2379485a04aSYong Wu 2380df4fabeSYong Wu struct mtk_iommu_domain { 2390df4fabeSYong Wu struct io_pgtable_cfg cfg; 2400df4fabeSYong Wu struct io_pgtable_ops *iop; 2410df4fabeSYong Wu 24299ca0228SYong Wu struct mtk_iommu_bank_data *bank; 2430df4fabeSYong Wu struct iommu_domain domain; 244ddf67a87SYong Wu 245ddf67a87SYong Wu struct mutex mutex; /* Protect "data" in this structure */ 2460df4fabeSYong Wu }; 2470df4fabeSYong Wu 2489485a04aSYong Wu static int mtk_iommu_bind(struct device *dev) 2499485a04aSYong Wu { 2509485a04aSYong Wu struct mtk_iommu_data *data = dev_get_drvdata(dev); 2519485a04aSYong Wu 2529485a04aSYong Wu return component_bind_all(dev, &data->larb_imu); 2539485a04aSYong Wu } 2549485a04aSYong Wu 2559485a04aSYong Wu static void mtk_iommu_unbind(struct device *dev) 2569485a04aSYong Wu { 2579485a04aSYong Wu struct mtk_iommu_data *data = dev_get_drvdata(dev); 2589485a04aSYong Wu 2599485a04aSYong Wu component_unbind_all(dev, &data->larb_imu); 2609485a04aSYong Wu } 2619485a04aSYong Wu 262b65f5016SArvind Yadav static const struct iommu_ops mtk_iommu_ops; 2630df4fabeSYong Wu 264e24453e1SYong Wu static int mtk_iommu_hw_init(const struct mtk_iommu_data *data, unsigned int bankid); 2657f37a91dSYong Wu 266bfed8731SYong Wu #define MTK_IOMMU_TLB_ADDR(iova) ({ \ 267bfed8731SYong Wu dma_addr_t _addr = iova; \ 268bfed8731SYong Wu ((lower_32_bits(_addr) & GENMASK(31, 12)) | upper_32_bits(_addr));\ 269bfed8731SYong Wu }) 270bfed8731SYong Wu 27176ce6546SYong Wu /* 27276ce6546SYong Wu * In M4U 4GB mode, the physical address is remapped as below: 27376ce6546SYong Wu * 27476ce6546SYong Wu * CPU Physical address: 27576ce6546SYong Wu * ==================== 27676ce6546SYong Wu * 27776ce6546SYong Wu * 0 1G 2G 3G 4G 5G 27876ce6546SYong Wu * |---A---|---B---|---C---|---D---|---E---| 27976ce6546SYong Wu * +--I/O--+------------Memory-------------+ 28076ce6546SYong Wu * 28176ce6546SYong Wu * IOMMU output physical address: 28276ce6546SYong Wu * ============================= 28376ce6546SYong Wu * 28476ce6546SYong Wu * 4G 5G 6G 7G 8G 28576ce6546SYong Wu * |---E---|---B---|---C---|---D---| 28676ce6546SYong Wu * +------------Memory-------------+ 28776ce6546SYong Wu * 28876ce6546SYong Wu * The Region 'A'(I/O) can NOT be mapped by M4U; For Region 'B'/'C'/'D', the 28976ce6546SYong Wu * bit32 of the CPU physical address always is needed to set, and for Region 29076ce6546SYong Wu * 'E', the CPU physical address keep as is. 29176ce6546SYong Wu * Additionally, The iommu consumers always use the CPU phyiscal address. 29276ce6546SYong Wu */ 293b4dad40eSYong Wu #define MTK_IOMMU_4GB_MODE_REMAP_BASE 0x140000000UL 29476ce6546SYong Wu 2957c3a2ec0SYong Wu static LIST_HEAD(m4ulist); /* List all the M4U HWs */ 2967c3a2ec0SYong Wu 2979e3a2a64SYong Wu #define for_each_m4u(data, head) list_for_each_entry(data, head, list) 2987c3a2ec0SYong Wu 299585e58f4SYong Wu static const struct mtk_iommu_iova_region single_domain[] = { 300585e58f4SYong Wu {.iova_base = 0, .size = SZ_4G}, 301585e58f4SYong Wu }; 302585e58f4SYong Wu 3039e3489e0SYong Wu static const struct mtk_iommu_iova_region mt8192_multi_dom[] = { 304129a3b88SYong Wu { .iova_base = 0x0, .size = SZ_4G}, /* 0 ~ 4G */ 3059e3489e0SYong Wu #if IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) 306129a3b88SYong Wu { .iova_base = SZ_4G, .size = SZ_4G}, /* 4G ~ 8G */ 307129a3b88SYong Wu { .iova_base = SZ_4G * 2, .size = SZ_4G}, /* 8G ~ 12G */ 308129a3b88SYong Wu { .iova_base = SZ_4G * 3, .size = SZ_4G}, /* 12G ~ 16G */ 309129a3b88SYong Wu 3109e3489e0SYong Wu { .iova_base = 0x240000000ULL, .size = 0x4000000}, /* CCU0 */ 3119e3489e0SYong Wu { .iova_base = 0x244000000ULL, .size = 0x4000000}, /* CCU1 */ 3129e3489e0SYong Wu #endif 3139e3489e0SYong Wu }; 3149e3489e0SYong Wu 3159e3a2a64SYong Wu /* If 2 M4U share a domain(use the same hwlist), Put the corresponding info in first data.*/ 3169e3a2a64SYong Wu static struct mtk_iommu_data *mtk_iommu_get_frst_data(struct list_head *hwlist) 3177c3a2ec0SYong Wu { 3189e3a2a64SYong Wu return list_first_entry(hwlist, struct mtk_iommu_data, list); 3197c3a2ec0SYong Wu } 3207c3a2ec0SYong Wu 3210df4fabeSYong Wu static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom) 3220df4fabeSYong Wu { 3230df4fabeSYong Wu return container_of(dom, struct mtk_iommu_domain, domain); 3240df4fabeSYong Wu } 3250df4fabeSYong Wu 3260954d61aSYong Wu static void mtk_iommu_tlb_flush_all(struct mtk_iommu_data *data) 3270df4fabeSYong Wu { 32899ca0228SYong Wu /* Tlb flush all always is in bank0. */ 32999ca0228SYong Wu struct mtk_iommu_bank_data *bank = &data->bank[0]; 33099ca0228SYong Wu void __iomem *base = bank->base; 33115672b6dSYong Wu unsigned long flags; 332c0b57581SYong Wu 33399ca0228SYong Wu spin_lock_irqsave(&bank->tlb_lock, flags); 334887cf6a7SYong Wu writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, base + data->plat_data->inv_sel_reg); 335887cf6a7SYong Wu writel_relaxed(F_ALL_INVLD, base + REG_MMU_INVALIDATE); 3360df4fabeSYong Wu wmb(); /* Make sure the tlb flush all done */ 33799ca0228SYong Wu spin_unlock_irqrestore(&bank->tlb_lock, flags); 3387c3a2ec0SYong Wu } 3390df4fabeSYong Wu 3401f4fd624SYong Wu static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size, 34199ca0228SYong Wu struct mtk_iommu_bank_data *bank) 3420df4fabeSYong Wu { 34399ca0228SYong Wu struct list_head *head = bank->parent_data->hw_list; 34499ca0228SYong Wu struct mtk_iommu_bank_data *curbank; 34599ca0228SYong Wu struct mtk_iommu_data *data; 3466077c7e5SYong Wu bool check_pm_status; 3471f4fd624SYong Wu unsigned long flags; 348887cf6a7SYong Wu void __iomem *base; 3491f4fd624SYong Wu int ret; 3501f4fd624SYong Wu u32 tmp; 3510df4fabeSYong Wu 3529e3a2a64SYong Wu for_each_m4u(data, head) { 3536077c7e5SYong Wu /* 3546077c7e5SYong Wu * To avoid resume the iommu device frequently when the iommu device 3556077c7e5SYong Wu * is not active, it doesn't always call pm_runtime_get here, then tlb 3566077c7e5SYong Wu * flush depends on the tlb flush all in the runtime resume. 3576077c7e5SYong Wu * 3586077c7e5SYong Wu * There are 2 special cases: 3596077c7e5SYong Wu * 3606077c7e5SYong Wu * Case1: The iommu dev doesn't have power domain but has bclk. This case 3616077c7e5SYong Wu * should also avoid the tlb flush while the dev is not active to mute 3626077c7e5SYong Wu * the tlb timeout log. like mt8173. 3636077c7e5SYong Wu * 3646077c7e5SYong Wu * Case2: The power/clock of infra iommu is always on, and it doesn't 3656077c7e5SYong Wu * have the device link with the master devices. This case should avoid 3666077c7e5SYong Wu * the PM status check. 3676077c7e5SYong Wu */ 3686077c7e5SYong Wu check_pm_status = !MTK_IOMMU_HAS_FLAG(data->plat_data, PM_CLK_AO); 3696077c7e5SYong Wu 3706077c7e5SYong Wu if (check_pm_status) { 371c0b57581SYong Wu if (pm_runtime_get_if_in_use(data->dev) <= 0) 372c0b57581SYong Wu continue; 3736077c7e5SYong Wu } 374c0b57581SYong Wu 37599ca0228SYong Wu curbank = &data->bank[bank->id]; 37699ca0228SYong Wu base = curbank->base; 377887cf6a7SYong Wu 37899ca0228SYong Wu spin_lock_irqsave(&curbank->tlb_lock, flags); 3797c3a2ec0SYong Wu writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, 380887cf6a7SYong Wu base + data->plat_data->inv_sel_reg); 3810df4fabeSYong Wu 382887cf6a7SYong Wu writel_relaxed(MTK_IOMMU_TLB_ADDR(iova), base + REG_MMU_INVLD_START_A); 383bfed8731SYong Wu writel_relaxed(MTK_IOMMU_TLB_ADDR(iova + size - 1), 384887cf6a7SYong Wu base + REG_MMU_INVLD_END_A); 385887cf6a7SYong Wu writel_relaxed(F_MMU_INV_RANGE, base + REG_MMU_INVALIDATE); 3860df4fabeSYong Wu 3871f4fd624SYong Wu /* tlb sync */ 388887cf6a7SYong Wu ret = readl_poll_timeout_atomic(base + REG_MMU_CPE_DONE, 389c90ae4a6SYong Wu tmp, tmp != 0, 10, 1000); 39015672b6dSYong Wu 39115672b6dSYong Wu /* Clear the CPE status */ 392887cf6a7SYong Wu writel_relaxed(0, base + REG_MMU_CPE_DONE); 39399ca0228SYong Wu spin_unlock_irqrestore(&curbank->tlb_lock, flags); 39415672b6dSYong Wu 3950df4fabeSYong Wu if (ret) { 3960df4fabeSYong Wu dev_warn(data->dev, 3970df4fabeSYong Wu "Partial TLB flush timed out, falling back to full flush\n"); 3980954d61aSYong Wu mtk_iommu_tlb_flush_all(data); 3990df4fabeSYong Wu } 400c0b57581SYong Wu 4016077c7e5SYong Wu if (check_pm_status) 402c0b57581SYong Wu pm_runtime_put(data->dev); 4030df4fabeSYong Wu } 4047c3a2ec0SYong Wu } 4050df4fabeSYong Wu 4060df4fabeSYong Wu static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) 4070df4fabeSYong Wu { 40899ca0228SYong Wu struct mtk_iommu_bank_data *bank = dev_id; 40999ca0228SYong Wu struct mtk_iommu_data *data = bank->parent_data; 41099ca0228SYong Wu struct mtk_iommu_domain *dom = bank->m4u_dom; 411d2e9a110SYong Wu unsigned int fault_larb = MTK_INVALID_LARBID, fault_port = 0, sub_comm = 0; 412ef0f0986SYong Wu u32 int_state, regval, va34_32, pa34_32; 413887cf6a7SYong Wu const struct mtk_iommu_plat_data *plat_data = data->plat_data; 41499ca0228SYong Wu void __iomem *base = bank->base; 415ef0f0986SYong Wu u64 fault_iova, fault_pa; 4160df4fabeSYong Wu bool layer, write; 4170df4fabeSYong Wu 4180df4fabeSYong Wu /* Read error info from registers */ 419887cf6a7SYong Wu int_state = readl_relaxed(base + REG_MMU_FAULT_ST1); 42015a01f4cSYong Wu if (int_state & F_REG_MMU0_FAULT_MASK) { 421887cf6a7SYong Wu regval = readl_relaxed(base + REG_MMU0_INT_ID); 422887cf6a7SYong Wu fault_iova = readl_relaxed(base + REG_MMU0_FAULT_VA); 423887cf6a7SYong Wu fault_pa = readl_relaxed(base + REG_MMU0_INVLD_PA); 42415a01f4cSYong Wu } else { 425887cf6a7SYong Wu regval = readl_relaxed(base + REG_MMU1_INT_ID); 426887cf6a7SYong Wu fault_iova = readl_relaxed(base + REG_MMU1_FAULT_VA); 427887cf6a7SYong Wu fault_pa = readl_relaxed(base + REG_MMU1_INVLD_PA); 42815a01f4cSYong Wu } 4290df4fabeSYong Wu layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT; 4300df4fabeSYong Wu write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT; 431887cf6a7SYong Wu if (MTK_IOMMU_HAS_FLAG(plat_data, IOVA_34_EN)) { 432ef0f0986SYong Wu va34_32 = FIELD_GET(F_MMU_INVAL_VA_34_32_MASK, fault_iova); 433ef0f0986SYong Wu fault_iova = fault_iova & F_MMU_INVAL_VA_31_12_MASK; 434ef0f0986SYong Wu fault_iova |= (u64)va34_32 << 32; 435ef0f0986SYong Wu } 43682e51771SYong Wu pa34_32 = FIELD_GET(F_MMU_INVAL_PA_34_32_MASK, fault_iova); 43782e51771SYong Wu fault_pa |= (u64)pa34_32 << 32; 438ef0f0986SYong Wu 439887cf6a7SYong Wu if (MTK_IOMMU_IS_TYPE(plat_data, MTK_IOMMU_TYPE_MM)) { 44015a01f4cSYong Wu fault_port = F_MMU_INT_ID_PORT_ID(regval); 441887cf6a7SYong Wu if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_2BITS)) { 44237276e00SChao Hao fault_larb = F_MMU_INT_ID_COMM_ID(regval); 44337276e00SChao Hao sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval); 444887cf6a7SYong Wu } else if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_3BITS)) { 4459ec30c09SYong Wu fault_larb = F_MMU_INT_ID_COMM_ID_EXT(regval); 4469ec30c09SYong Wu sub_comm = F_MMU_INT_ID_SUB_COMM_ID_EXT(regval); 44737276e00SChao Hao } else { 44837276e00SChao Hao fault_larb = F_MMU_INT_ID_LARB_ID(regval); 44937276e00SChao Hao } 45037276e00SChao Hao fault_larb = data->plat_data->larbid_remap[fault_larb][sub_comm]; 451d2e9a110SYong Wu } 452b3e5eee7SYong Wu 45399ca0228SYong Wu if (report_iommu_fault(&dom->domain, bank->parent_dev, fault_iova, 4540df4fabeSYong Wu write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) { 4550df4fabeSYong Wu dev_err_ratelimited( 45699ca0228SYong Wu bank->parent_dev, 457f9b8c9b2SYong Wu "fault type=0x%x iova=0x%llx pa=0x%llx master=0x%x(larb=%d port=%d) layer=%d %s\n", 458f9b8c9b2SYong Wu int_state, fault_iova, fault_pa, regval, fault_larb, fault_port, 4590df4fabeSYong Wu layer, write ? "write" : "read"); 4600df4fabeSYong Wu } 4610df4fabeSYong Wu 4620df4fabeSYong Wu /* Interrupt clear */ 463887cf6a7SYong Wu regval = readl_relaxed(base + REG_MMU_INT_CONTROL0); 4640df4fabeSYong Wu regval |= F_INT_CLR_BIT; 465887cf6a7SYong Wu writel_relaxed(regval, base + REG_MMU_INT_CONTROL0); 4660df4fabeSYong Wu 4670df4fabeSYong Wu mtk_iommu_tlb_flush_all(data); 4680df4fabeSYong Wu 4690df4fabeSYong Wu return IRQ_HANDLED; 4700df4fabeSYong Wu } 4710df4fabeSYong Wu 47257fb481fSYong Wu static unsigned int mtk_iommu_get_bank_id(struct device *dev, 47357fb481fSYong Wu const struct mtk_iommu_plat_data *plat_data) 47457fb481fSYong Wu { 47557fb481fSYong Wu struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 47657fb481fSYong Wu unsigned int i, portmsk = 0, bankid = 0; 47757fb481fSYong Wu 47857fb481fSYong Wu if (plat_data->banks_num == 1) 47957fb481fSYong Wu return bankid; 48057fb481fSYong Wu 48157fb481fSYong Wu for (i = 0; i < fwspec->num_ids; i++) 48257fb481fSYong Wu portmsk |= BIT(MTK_M4U_TO_PORT(fwspec->ids[i])); 48357fb481fSYong Wu 48457fb481fSYong Wu for (i = 0; i < plat_data->banks_num && i < MTK_IOMMU_BANK_MAX; i++) { 48557fb481fSYong Wu if (!plat_data->banks_enable[i]) 48657fb481fSYong Wu continue; 48757fb481fSYong Wu 48857fb481fSYong Wu if (portmsk & plat_data->banks_portmsk[i]) { 48957fb481fSYong Wu bankid = i; 49057fb481fSYong Wu break; 49157fb481fSYong Wu } 49257fb481fSYong Wu } 49357fb481fSYong Wu return bankid; /* default is 0 */ 49457fb481fSYong Wu } 49557fb481fSYong Wu 496d72e0ff5SYong Wu static int mtk_iommu_get_iova_region_id(struct device *dev, 497803cf9e5SYong Wu const struct mtk_iommu_plat_data *plat_data) 498803cf9e5SYong Wu { 499803cf9e5SYong Wu const struct mtk_iommu_iova_region *rgn = plat_data->iova_region; 500803cf9e5SYong Wu const struct bus_dma_region *dma_rgn = dev->dma_range_map; 501803cf9e5SYong Wu int i, candidate = -1; 502803cf9e5SYong Wu dma_addr_t dma_end; 503803cf9e5SYong Wu 504803cf9e5SYong Wu if (!dma_rgn || plat_data->iova_region_nr == 1) 505803cf9e5SYong Wu return 0; 506803cf9e5SYong Wu 507803cf9e5SYong Wu dma_end = dma_rgn->dma_start + dma_rgn->size - 1; 508803cf9e5SYong Wu for (i = 0; i < plat_data->iova_region_nr; i++, rgn++) { 509803cf9e5SYong Wu /* Best fit. */ 510803cf9e5SYong Wu if (dma_rgn->dma_start == rgn->iova_base && 511803cf9e5SYong Wu dma_end == rgn->iova_base + rgn->size - 1) 512803cf9e5SYong Wu return i; 513803cf9e5SYong Wu /* ok if it is inside this region. */ 514803cf9e5SYong Wu if (dma_rgn->dma_start >= rgn->iova_base && 515803cf9e5SYong Wu dma_end < rgn->iova_base + rgn->size) 516803cf9e5SYong Wu candidate = i; 517803cf9e5SYong Wu } 518803cf9e5SYong Wu 519803cf9e5SYong Wu if (candidate >= 0) 520803cf9e5SYong Wu return candidate; 521803cf9e5SYong Wu dev_err(dev, "Can NOT find the iommu domain id(%pad 0x%llx).\n", 522803cf9e5SYong Wu &dma_rgn->dma_start, dma_rgn->size); 523803cf9e5SYong Wu return -EINVAL; 524803cf9e5SYong Wu } 525803cf9e5SYong Wu 526f9b8c9b2SYong Wu static int mtk_iommu_config(struct mtk_iommu_data *data, struct device *dev, 527d72e0ff5SYong Wu bool enable, unsigned int regionid) 5280df4fabeSYong Wu { 5290df4fabeSYong Wu struct mtk_smi_larb_iommu *larb_mmu; 5300df4fabeSYong Wu unsigned int larbid, portid; 531a9bf2eecSJoerg Roedel struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 5328d2c749eSYong Wu const struct mtk_iommu_iova_region *region; 533f9b8c9b2SYong Wu u32 peri_mmuen, peri_mmuen_msk; 534f9b8c9b2SYong Wu int i, ret = 0; 5350df4fabeSYong Wu 53658f0d1d5SRobin Murphy for (i = 0; i < fwspec->num_ids; ++i) { 53758f0d1d5SRobin Murphy larbid = MTK_M4U_TO_LARB(fwspec->ids[i]); 53858f0d1d5SRobin Murphy portid = MTK_M4U_TO_PORT(fwspec->ids[i]); 5398d2c749eSYong Wu 540d2e9a110SYong Wu if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { 5411ee9feb2SYong Wu larb_mmu = &data->larb_imu[larbid]; 5420df4fabeSYong Wu 543d72e0ff5SYong Wu region = data->plat_data->iova_region + regionid; 5448d2c749eSYong Wu larb_mmu->bank[portid] = upper_32_bits(region->iova_base); 5458d2c749eSYong Wu 546d72e0ff5SYong Wu dev_dbg(dev, "%s iommu for larb(%s) port %d region %d rgn-bank %d.\n", 5478d2c749eSYong Wu enable ? "enable" : "disable", dev_name(larb_mmu->dev), 548d72e0ff5SYong Wu portid, regionid, larb_mmu->bank[portid]); 5490df4fabeSYong Wu 5500df4fabeSYong Wu if (enable) 5510df4fabeSYong Wu larb_mmu->mmu |= MTK_SMI_MMU_EN(portid); 5520df4fabeSYong Wu else 5530df4fabeSYong Wu larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid); 554f9b8c9b2SYong Wu } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA)) { 555f9b8c9b2SYong Wu peri_mmuen_msk = BIT(portid); 556e7629070SYong Wu /* PCI dev has only one output id, enable the next writing bit for PCIe */ 557e7629070SYong Wu if (dev_is_pci(dev)) 558e7629070SYong Wu peri_mmuen_msk |= BIT(portid + 1); 559f9b8c9b2SYong Wu 560e7629070SYong Wu peri_mmuen = enable ? peri_mmuen_msk : 0; 561f9b8c9b2SYong Wu ret = regmap_update_bits(data->pericfg, PERICFG_IOMMU_1, 562f9b8c9b2SYong Wu peri_mmuen_msk, peri_mmuen); 563f9b8c9b2SYong Wu if (ret) 564f9b8c9b2SYong Wu dev_err(dev, "%s iommu(%s) inframaster 0x%x fail(%d).\n", 565f9b8c9b2SYong Wu enable ? "enable" : "disable", 566f9b8c9b2SYong Wu dev_name(data->dev), peri_mmuen_msk, ret); 5670df4fabeSYong Wu } 5680df4fabeSYong Wu } 569f9b8c9b2SYong Wu return ret; 570d2e9a110SYong Wu } 5710df4fabeSYong Wu 5724f956c97SYong Wu static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom, 573c3045f39SYong Wu struct mtk_iommu_data *data, 574d72e0ff5SYong Wu unsigned int region_id) 5750df4fabeSYong Wu { 576c3045f39SYong Wu const struct mtk_iommu_iova_region *region; 57799ca0228SYong Wu struct mtk_iommu_domain *m4u_dom; 578c3045f39SYong Wu 57999ca0228SYong Wu /* Always use bank0 in sharing pgtable case */ 58099ca0228SYong Wu m4u_dom = data->bank[0].m4u_dom; 58199ca0228SYong Wu if (m4u_dom) { 58299ca0228SYong Wu dom->iop = m4u_dom->iop; 58399ca0228SYong Wu dom->cfg = m4u_dom->cfg; 58499ca0228SYong Wu dom->domain.pgsize_bitmap = m4u_dom->cfg.pgsize_bitmap; 585c3045f39SYong Wu goto update_iova_region; 586c3045f39SYong Wu } 587c3045f39SYong Wu 5880df4fabeSYong Wu dom->cfg = (struct io_pgtable_cfg) { 5890df4fabeSYong Wu .quirks = IO_PGTABLE_QUIRK_ARM_NS | 5900df4fabeSYong Wu IO_PGTABLE_QUIRK_NO_PERMS | 591b4dad40eSYong Wu IO_PGTABLE_QUIRK_ARM_MTK_EXT, 5920df4fabeSYong Wu .pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap, 5932f317da4SYong Wu .ias = MTK_IOMMU_HAS_FLAG(data->plat_data, IOVA_34_EN) ? 34 : 32, 5940df4fabeSYong Wu .iommu_dev = data->dev, 5950df4fabeSYong Wu }; 5960df4fabeSYong Wu 5979bdfe4c1SYong Wu if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) 5989bdfe4c1SYong Wu dom->cfg.oas = data->enable_4GB ? 33 : 32; 5999bdfe4c1SYong Wu else 6009bdfe4c1SYong Wu dom->cfg.oas = 35; 6019bdfe4c1SYong Wu 6020df4fabeSYong Wu dom->iop = alloc_io_pgtable_ops(ARM_V7S, &dom->cfg, data); 6030df4fabeSYong Wu if (!dom->iop) { 6040df4fabeSYong Wu dev_err(data->dev, "Failed to alloc io pgtable\n"); 6050df4fabeSYong Wu return -EINVAL; 6060df4fabeSYong Wu } 6070df4fabeSYong Wu 6080df4fabeSYong Wu /* Update our support page sizes bitmap */ 609d16e0faaSRobin Murphy dom->domain.pgsize_bitmap = dom->cfg.pgsize_bitmap; 610b7875eb9SYong Wu 611c3045f39SYong Wu update_iova_region: 612c3045f39SYong Wu /* Update the iova region for this domain */ 613d72e0ff5SYong Wu region = data->plat_data->iova_region + region_id; 614c3045f39SYong Wu dom->domain.geometry.aperture_start = region->iova_base; 615c3045f39SYong Wu dom->domain.geometry.aperture_end = region->iova_base + region->size - 1; 616b7875eb9SYong Wu dom->domain.geometry.force_aperture = true; 6170df4fabeSYong Wu return 0; 6180df4fabeSYong Wu } 6190df4fabeSYong Wu 6200df4fabeSYong Wu static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type) 6210df4fabeSYong Wu { 6220df4fabeSYong Wu struct mtk_iommu_domain *dom; 6230df4fabeSYong Wu 62432e1cccfSYong Wu if (type != IOMMU_DOMAIN_DMA && type != IOMMU_DOMAIN_UNMANAGED) 6250df4fabeSYong Wu return NULL; 6260df4fabeSYong Wu 6270df4fabeSYong Wu dom = kzalloc(sizeof(*dom), GFP_KERNEL); 6280df4fabeSYong Wu if (!dom) 6290df4fabeSYong Wu return NULL; 630ddf67a87SYong Wu mutex_init(&dom->mutex); 6310df4fabeSYong Wu 6324f956c97SYong Wu return &dom->domain; 6334f956c97SYong Wu } 6344f956c97SYong Wu 6350df4fabeSYong Wu static void mtk_iommu_domain_free(struct iommu_domain *domain) 6360df4fabeSYong Wu { 6370df4fabeSYong Wu kfree(to_mtk_domain(domain)); 6380df4fabeSYong Wu } 6390df4fabeSYong Wu 6400df4fabeSYong Wu static int mtk_iommu_attach_device(struct iommu_domain *domain, 6410df4fabeSYong Wu struct device *dev) 6420df4fabeSYong Wu { 643645b87c1SYong Wu struct mtk_iommu_data *data = dev_iommu_priv_get(dev), *frstdata; 6440df4fabeSYong Wu struct mtk_iommu_domain *dom = to_mtk_domain(domain); 6459e3a2a64SYong Wu struct list_head *hw_list = data->hw_list; 646c0b57581SYong Wu struct device *m4udev = data->dev; 64799ca0228SYong Wu struct mtk_iommu_bank_data *bank; 64857fb481fSYong Wu unsigned int bankid; 649d72e0ff5SYong Wu int ret, region_id; 6500df4fabeSYong Wu 651d72e0ff5SYong Wu region_id = mtk_iommu_get_iova_region_id(dev, data->plat_data); 652d72e0ff5SYong Wu if (region_id < 0) 653d72e0ff5SYong Wu return region_id; 654803cf9e5SYong Wu 65557fb481fSYong Wu bankid = mtk_iommu_get_bank_id(dev, data->plat_data); 656ddf67a87SYong Wu mutex_lock(&dom->mutex); 65799ca0228SYong Wu if (!dom->bank) { 658645b87c1SYong Wu /* Data is in the frstdata in sharing pgtable case. */ 6599e3a2a64SYong Wu frstdata = mtk_iommu_get_frst_data(hw_list); 660645b87c1SYong Wu 661d72e0ff5SYong Wu ret = mtk_iommu_domain_finalise(dom, frstdata, region_id); 662ddf67a87SYong Wu if (ret) { 663ddf67a87SYong Wu mutex_unlock(&dom->mutex); 6644f956c97SYong Wu return -ENODEV; 665ddf67a87SYong Wu } 66699ca0228SYong Wu dom->bank = &data->bank[bankid]; 6674f956c97SYong Wu } 668ddf67a87SYong Wu mutex_unlock(&dom->mutex); 6694f956c97SYong Wu 6700e5a3f2eSYong Wu mutex_lock(&data->mutex); 67199ca0228SYong Wu bank = &data->bank[bankid]; 672e24453e1SYong Wu if (!bank->m4u_dom) { /* Initialize the M4U HW for each a BANK */ 673c0b57581SYong Wu ret = pm_runtime_resume_and_get(m4udev); 674e24453e1SYong Wu if (ret < 0) { 675e24453e1SYong Wu dev_err(m4udev, "pm get fail(%d) in attach.\n", ret); 6760e5a3f2eSYong Wu goto err_unlock; 677e24453e1SYong Wu } 678c0b57581SYong Wu 679e24453e1SYong Wu ret = mtk_iommu_hw_init(data, bankid); 680c0b57581SYong Wu if (ret) { 681c0b57581SYong Wu pm_runtime_put(m4udev); 6820e5a3f2eSYong Wu goto err_unlock; 683c0b57581SYong Wu } 68499ca0228SYong Wu bank->m4u_dom = dom; 685d1e5f26fSRobin Murphy writel(dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, 68699ca0228SYong Wu bank->base + REG_MMU_PT_BASE_ADDR); 687c0b57581SYong Wu 688c0b57581SYong Wu pm_runtime_put(m4udev); 6890df4fabeSYong Wu } 6900e5a3f2eSYong Wu mutex_unlock(&data->mutex); 6910df4fabeSYong Wu 692d72e0ff5SYong Wu return mtk_iommu_config(data, dev, true, region_id); 6930e5a3f2eSYong Wu 6940e5a3f2eSYong Wu err_unlock: 6950e5a3f2eSYong Wu mutex_unlock(&data->mutex); 6960e5a3f2eSYong Wu return ret; 6970df4fabeSYong Wu } 6980df4fabeSYong Wu 6990df4fabeSYong Wu static void mtk_iommu_detach_device(struct iommu_domain *domain, 7000df4fabeSYong Wu struct device *dev) 7010df4fabeSYong Wu { 7023524b559SJoerg Roedel struct mtk_iommu_data *data = dev_iommu_priv_get(dev); 7030df4fabeSYong Wu 7048d2c749eSYong Wu mtk_iommu_config(data, dev, false, 0); 7050df4fabeSYong Wu } 7060df4fabeSYong Wu 7070df4fabeSYong Wu static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova, 708781ca2deSTom Murphy phys_addr_t paddr, size_t size, int prot, gfp_t gfp) 7090df4fabeSYong Wu { 7100df4fabeSYong Wu struct mtk_iommu_domain *dom = to_mtk_domain(domain); 7110df4fabeSYong Wu 712b4dad40eSYong Wu /* The "4GB mode" M4U physically can not use the lower remap of Dram. */ 71399ca0228SYong Wu if (dom->bank->parent_data->enable_4GB) 714b4dad40eSYong Wu paddr |= BIT_ULL(32); 715b4dad40eSYong Wu 71660829b4dSYong Wu /* Synchronize with the tlb_lock */ 717f34ce7a7SBaolin Wang return dom->iop->map(dom->iop, iova, paddr, size, prot, gfp); 7180df4fabeSYong Wu } 7190df4fabeSYong Wu 7200df4fabeSYong Wu static size_t mtk_iommu_unmap(struct iommu_domain *domain, 72156f8af5eSWill Deacon unsigned long iova, size_t size, 72256f8af5eSWill Deacon struct iommu_iotlb_gather *gather) 7230df4fabeSYong Wu { 7240df4fabeSYong Wu struct mtk_iommu_domain *dom = to_mtk_domain(domain); 7250df4fabeSYong Wu 7263136895cSRobin Murphy iommu_iotlb_gather_add_range(gather, iova, size); 72760829b4dSYong Wu return dom->iop->unmap(dom->iop, iova, size, gather); 7280df4fabeSYong Wu } 7290df4fabeSYong Wu 73056f8af5eSWill Deacon static void mtk_iommu_flush_iotlb_all(struct iommu_domain *domain) 73156f8af5eSWill Deacon { 73208500c43SYong Wu struct mtk_iommu_domain *dom = to_mtk_domain(domain); 73308500c43SYong Wu 73499ca0228SYong Wu mtk_iommu_tlb_flush_all(dom->bank->parent_data); 73556f8af5eSWill Deacon } 73656f8af5eSWill Deacon 73756f8af5eSWill Deacon static void mtk_iommu_iotlb_sync(struct iommu_domain *domain, 73856f8af5eSWill Deacon struct iommu_iotlb_gather *gather) 7394d689b61SRobin Murphy { 74008500c43SYong Wu struct mtk_iommu_domain *dom = to_mtk_domain(domain); 741862c3715SYong Wu size_t length = gather->end - gather->start + 1; 742da3cc91bSYong Wu 74399ca0228SYong Wu mtk_iommu_tlb_flush_range_sync(gather->start, length, dom->bank); 7444d689b61SRobin Murphy } 7454d689b61SRobin Murphy 74620143451SYong Wu static void mtk_iommu_sync_map(struct iommu_domain *domain, unsigned long iova, 74720143451SYong Wu size_t size) 74820143451SYong Wu { 74908500c43SYong Wu struct mtk_iommu_domain *dom = to_mtk_domain(domain); 75020143451SYong Wu 75199ca0228SYong Wu mtk_iommu_tlb_flush_range_sync(iova, size, dom->bank); 75220143451SYong Wu } 75320143451SYong Wu 7540df4fabeSYong Wu static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain, 7550df4fabeSYong Wu dma_addr_t iova) 7560df4fabeSYong Wu { 7570df4fabeSYong Wu struct mtk_iommu_domain *dom = to_mtk_domain(domain); 7580df4fabeSYong Wu phys_addr_t pa; 7590df4fabeSYong Wu 7600df4fabeSYong Wu pa = dom->iop->iova_to_phys(dom->iop, iova); 761f13efafcSArnd Bergmann if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) && 76299ca0228SYong Wu dom->bank->parent_data->enable_4GB && 763f13efafcSArnd Bergmann pa >= MTK_IOMMU_4GB_MODE_REMAP_BASE) 764b4dad40eSYong Wu pa &= ~BIT_ULL(32); 76530e2fccfSYong Wu 7660df4fabeSYong Wu return pa; 7670df4fabeSYong Wu } 7680df4fabeSYong Wu 76980e4592aSJoerg Roedel static struct iommu_device *mtk_iommu_probe_device(struct device *dev) 7700df4fabeSYong Wu { 771a9bf2eecSJoerg Roedel struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 772b16c0170SJoerg Roedel struct mtk_iommu_data *data; 773635319a4SYong Wu struct device_link *link; 774635319a4SYong Wu struct device *larbdev; 775635319a4SYong Wu unsigned int larbid, larbidx, i; 7760df4fabeSYong Wu 777a9bf2eecSJoerg Roedel if (!fwspec || fwspec->ops != &mtk_iommu_ops) 77880e4592aSJoerg Roedel return ERR_PTR(-ENODEV); /* Not a iommu client device */ 7790df4fabeSYong Wu 7803524b559SJoerg Roedel data = dev_iommu_priv_get(dev); 781b16c0170SJoerg Roedel 782d2e9a110SYong Wu if (!MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) 783d2e9a110SYong Wu return &data->iommu; 784d2e9a110SYong Wu 785635319a4SYong Wu /* 786635319a4SYong Wu * Link the consumer device with the smi-larb device(supplier). 787635319a4SYong Wu * The device that connects with each a larb is a independent HW. 788635319a4SYong Wu * All the ports in each a device should be in the same larbs. 789635319a4SYong Wu */ 790635319a4SYong Wu larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); 791635319a4SYong Wu for (i = 1; i < fwspec->num_ids; i++) { 792635319a4SYong Wu larbidx = MTK_M4U_TO_LARB(fwspec->ids[i]); 793635319a4SYong Wu if (larbid != larbidx) { 794635319a4SYong Wu dev_err(dev, "Can only use one larb. Fail@larb%d-%d.\n", 795635319a4SYong Wu larbid, larbidx); 796635319a4SYong Wu return ERR_PTR(-EINVAL); 797635319a4SYong Wu } 798635319a4SYong Wu } 799635319a4SYong Wu larbdev = data->larb_imu[larbid].dev; 800635319a4SYong Wu link = device_link_add(dev, larbdev, 801635319a4SYong Wu DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS); 802635319a4SYong Wu if (!link) 803635319a4SYong Wu dev_err(dev, "Unable to link %s\n", dev_name(larbdev)); 80480e4592aSJoerg Roedel return &data->iommu; 8050df4fabeSYong Wu } 8060df4fabeSYong Wu 80780e4592aSJoerg Roedel static void mtk_iommu_release_device(struct device *dev) 8080df4fabeSYong Wu { 809a9bf2eecSJoerg Roedel struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 810635319a4SYong Wu struct mtk_iommu_data *data; 811635319a4SYong Wu struct device *larbdev; 812635319a4SYong Wu unsigned int larbid; 813b16c0170SJoerg Roedel 814a9bf2eecSJoerg Roedel if (!fwspec || fwspec->ops != &mtk_iommu_ops) 8150df4fabeSYong Wu return; 8160df4fabeSYong Wu 817635319a4SYong Wu data = dev_iommu_priv_get(dev); 818d2e9a110SYong Wu if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { 819635319a4SYong Wu larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); 820635319a4SYong Wu larbdev = data->larb_imu[larbid].dev; 821635319a4SYong Wu device_link_remove(dev, larbdev); 822d2e9a110SYong Wu } 823635319a4SYong Wu 82458f0d1d5SRobin Murphy iommu_fwspec_free(dev); 8250df4fabeSYong Wu } 8260df4fabeSYong Wu 82757fb481fSYong Wu static int mtk_iommu_get_group_id(struct device *dev, const struct mtk_iommu_plat_data *plat_data) 82857fb481fSYong Wu { 82957fb481fSYong Wu unsigned int bankid; 83057fb481fSYong Wu 83157fb481fSYong Wu /* 83257fb481fSYong Wu * If the bank function is enabled, each bank is a iommu group/domain. 83357fb481fSYong Wu * Otherwise, each iova region is a iommu group/domain. 83457fb481fSYong Wu */ 83557fb481fSYong Wu bankid = mtk_iommu_get_bank_id(dev, plat_data); 83657fb481fSYong Wu if (bankid) 83757fb481fSYong Wu return bankid; 83857fb481fSYong Wu 83957fb481fSYong Wu return mtk_iommu_get_iova_region_id(dev, plat_data); 84057fb481fSYong Wu } 84157fb481fSYong Wu 8420df4fabeSYong Wu static struct iommu_group *mtk_iommu_device_group(struct device *dev) 8430df4fabeSYong Wu { 8449e3a2a64SYong Wu struct mtk_iommu_data *c_data = dev_iommu_priv_get(dev), *data; 8459e3a2a64SYong Wu struct list_head *hw_list = c_data->hw_list; 846c3045f39SYong Wu struct iommu_group *group; 84757fb481fSYong Wu int groupid; 8480df4fabeSYong Wu 8499e3a2a64SYong Wu data = mtk_iommu_get_frst_data(hw_list); 85058f0d1d5SRobin Murphy if (!data) 8510df4fabeSYong Wu return ERR_PTR(-ENODEV); 8520df4fabeSYong Wu 85357fb481fSYong Wu groupid = mtk_iommu_get_group_id(dev, data->plat_data); 85457fb481fSYong Wu if (groupid < 0) 85557fb481fSYong Wu return ERR_PTR(groupid); 856803cf9e5SYong Wu 8570e5a3f2eSYong Wu mutex_lock(&data->mutex); 85857fb481fSYong Wu group = data->m4u_group[groupid]; 859c3045f39SYong Wu if (!group) { 860c3045f39SYong Wu group = iommu_group_alloc(); 861c3045f39SYong Wu if (!IS_ERR(group)) 86257fb481fSYong Wu data->m4u_group[groupid] = group; 8633a8d40b6SRobin Murphy } else { 864c3045f39SYong Wu iommu_group_ref_get(group); 8650df4fabeSYong Wu } 8660e5a3f2eSYong Wu mutex_unlock(&data->mutex); 867c3045f39SYong Wu return group; 8680df4fabeSYong Wu } 8690df4fabeSYong Wu 8700df4fabeSYong Wu static int mtk_iommu_of_xlate(struct device *dev, struct of_phandle_args *args) 8710df4fabeSYong Wu { 8720df4fabeSYong Wu struct platform_device *m4updev; 8730df4fabeSYong Wu 8740df4fabeSYong Wu if (args->args_count != 1) { 8750df4fabeSYong Wu dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n", 8760df4fabeSYong Wu args->args_count); 8770df4fabeSYong Wu return -EINVAL; 8780df4fabeSYong Wu } 8790df4fabeSYong Wu 8803524b559SJoerg Roedel if (!dev_iommu_priv_get(dev)) { 8810df4fabeSYong Wu /* Get the m4u device */ 8820df4fabeSYong Wu m4updev = of_find_device_by_node(args->np); 8830df4fabeSYong Wu if (WARN_ON(!m4updev)) 8840df4fabeSYong Wu return -EINVAL; 8850df4fabeSYong Wu 8863524b559SJoerg Roedel dev_iommu_priv_set(dev, platform_get_drvdata(m4updev)); 8870df4fabeSYong Wu } 8880df4fabeSYong Wu 88958f0d1d5SRobin Murphy return iommu_fwspec_add_ids(dev, args->args, 1); 8900df4fabeSYong Wu } 8910df4fabeSYong Wu 892ab1d5281SYong Wu static void mtk_iommu_get_resv_regions(struct device *dev, 893ab1d5281SYong Wu struct list_head *head) 894ab1d5281SYong Wu { 895ab1d5281SYong Wu struct mtk_iommu_data *data = dev_iommu_priv_get(dev); 896d72e0ff5SYong Wu unsigned int regionid = mtk_iommu_get_iova_region_id(dev, data->plat_data), i; 897ab1d5281SYong Wu const struct mtk_iommu_iova_region *resv, *curdom; 898ab1d5281SYong Wu struct iommu_resv_region *region; 899ab1d5281SYong Wu int prot = IOMMU_WRITE | IOMMU_READ; 900ab1d5281SYong Wu 901d72e0ff5SYong Wu if ((int)regionid < 0) 902ab1d5281SYong Wu return; 903d72e0ff5SYong Wu curdom = data->plat_data->iova_region + regionid; 904ab1d5281SYong Wu for (i = 0; i < data->plat_data->iova_region_nr; i++) { 905ab1d5281SYong Wu resv = data->plat_data->iova_region + i; 906ab1d5281SYong Wu 907ab1d5281SYong Wu /* Only reserve when the region is inside the current domain */ 908ab1d5281SYong Wu if (resv->iova_base <= curdom->iova_base || 909ab1d5281SYong Wu resv->iova_base + resv->size >= curdom->iova_base + curdom->size) 910ab1d5281SYong Wu continue; 911ab1d5281SYong Wu 912ab1d5281SYong Wu region = iommu_alloc_resv_region(resv->iova_base, resv->size, 913ab1d5281SYong Wu prot, IOMMU_RESV_RESERVED); 914ab1d5281SYong Wu if (!region) 915ab1d5281SYong Wu return; 916ab1d5281SYong Wu 917ab1d5281SYong Wu list_add_tail(®ion->list, head); 918ab1d5281SYong Wu } 919ab1d5281SYong Wu } 920ab1d5281SYong Wu 921b65f5016SArvind Yadav static const struct iommu_ops mtk_iommu_ops = { 9220df4fabeSYong Wu .domain_alloc = mtk_iommu_domain_alloc, 92380e4592aSJoerg Roedel .probe_device = mtk_iommu_probe_device, 92480e4592aSJoerg Roedel .release_device = mtk_iommu_release_device, 9250df4fabeSYong Wu .device_group = mtk_iommu_device_group, 9260df4fabeSYong Wu .of_xlate = mtk_iommu_of_xlate, 927ab1d5281SYong Wu .get_resv_regions = mtk_iommu_get_resv_regions, 928ab1d5281SYong Wu .put_resv_regions = generic_iommu_put_resv_regions, 9290df4fabeSYong Wu .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M, 93018d8c74eSYong Wu .owner = THIS_MODULE, 9319a630a4bSLu Baolu .default_domain_ops = &(const struct iommu_domain_ops) { 9329a630a4bSLu Baolu .attach_dev = mtk_iommu_attach_device, 9339a630a4bSLu Baolu .detach_dev = mtk_iommu_detach_device, 9349a630a4bSLu Baolu .map = mtk_iommu_map, 9359a630a4bSLu Baolu .unmap = mtk_iommu_unmap, 9369a630a4bSLu Baolu .flush_iotlb_all = mtk_iommu_flush_iotlb_all, 9379a630a4bSLu Baolu .iotlb_sync = mtk_iommu_iotlb_sync, 9389a630a4bSLu Baolu .iotlb_sync_map = mtk_iommu_sync_map, 9399a630a4bSLu Baolu .iova_to_phys = mtk_iommu_iova_to_phys, 9409a630a4bSLu Baolu .free = mtk_iommu_domain_free, 9419a630a4bSLu Baolu } 9420df4fabeSYong Wu }; 9430df4fabeSYong Wu 944e24453e1SYong Wu static int mtk_iommu_hw_init(const struct mtk_iommu_data *data, unsigned int bankid) 9450df4fabeSYong Wu { 946e24453e1SYong Wu const struct mtk_iommu_bank_data *bankx = &data->bank[bankid]; 94799ca0228SYong Wu const struct mtk_iommu_bank_data *bank0 = &data->bank[0]; 9480df4fabeSYong Wu u32 regval; 9490df4fabeSYong Wu 950e24453e1SYong Wu /* 951e24453e1SYong Wu * Global control settings are in bank0. May re-init these global registers 952e24453e1SYong Wu * since no sure if there is bank0 consumers. 953e24453e1SYong Wu */ 95486444413SChao Hao if (data->plat_data->m4u_plat == M4U_MT8173) { 955acb3c92aSYong Wu regval = F_MMU_PREFETCH_RT_REPLACE_MOD | 956acb3c92aSYong Wu F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173; 95786444413SChao Hao } else { 95899ca0228SYong Wu regval = readl_relaxed(bank0->base + REG_MMU_CTRL_REG); 95986444413SChao Hao regval |= F_MMU_TF_PROT_TO_PROGRAM_ADDR; 96086444413SChao Hao } 96199ca0228SYong Wu writel_relaxed(regval, bank0->base + REG_MMU_CTRL_REG); 9620df4fabeSYong Wu 9636b717796SChao Hao if (data->enable_4GB && 9646b717796SChao Hao MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_VLD_PA_RNG)) { 96530e2fccfSYong Wu /* 96630e2fccfSYong Wu * If 4GB mode is enabled, the validate PA range is from 96730e2fccfSYong Wu * 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30]. 96830e2fccfSYong Wu */ 96930e2fccfSYong Wu regval = F_MMU_VLD_PA_RNG(7, 4); 97099ca0228SYong Wu writel_relaxed(regval, bank0->base + REG_MMU_VLD_PA_RNG); 97130e2fccfSYong Wu } 9729a87005eSYong Wu if (MTK_IOMMU_HAS_FLAG(data->plat_data, DCM_DISABLE)) 97399ca0228SYong Wu writel_relaxed(F_MMU_DCM, bank0->base + REG_MMU_DCM_DIS); 9749a87005eSYong Wu else 97599ca0228SYong Wu writel_relaxed(0, bank0->base + REG_MMU_DCM_DIS); 9769a87005eSYong Wu 97735c1b48dSChao Hao if (MTK_IOMMU_HAS_FLAG(data->plat_data, WR_THROT_EN)) { 97835c1b48dSChao Hao /* write command throttling mode */ 97999ca0228SYong Wu regval = readl_relaxed(bank0->base + REG_MMU_WR_LEN_CTRL); 98035c1b48dSChao Hao regval &= ~F_MMU_WR_THROT_DIS_MASK; 98199ca0228SYong Wu writel_relaxed(regval, bank0->base + REG_MMU_WR_LEN_CTRL); 98235c1b48dSChao Hao } 983e6dec923SYong Wu 9846b717796SChao Hao if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) { 98575eed350SChao Hao /* The register is called STANDARD_AXI_MODE in this case */ 9864bb2bf4cSChao Hao regval = 0; 9874bb2bf4cSChao Hao } else { 98899ca0228SYong Wu regval = readl_relaxed(bank0->base + REG_MMU_MISC_CTRL); 989d265a4adSYong Wu if (!MTK_IOMMU_HAS_FLAG(data->plat_data, STD_AXI_MODE)) 9904bb2bf4cSChao Hao regval &= ~F_MMU_STANDARD_AXI_MODE_MASK; 9914bb2bf4cSChao Hao if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_WR_EN)) 9924bb2bf4cSChao Hao regval &= ~F_MMU_IN_ORDER_WR_EN_MASK; 99375eed350SChao Hao } 99499ca0228SYong Wu writel_relaxed(regval, bank0->base + REG_MMU_MISC_CTRL); 9950df4fabeSYong Wu 996e24453e1SYong Wu /* Independent settings for each bank */ 997634f57dfSYong Wu regval = F_L2_MULIT_HIT_EN | 998634f57dfSYong Wu F_TABLE_WALK_FAULT_INT_EN | 999634f57dfSYong Wu F_PREETCH_FIFO_OVERFLOW_INT_EN | 1000634f57dfSYong Wu F_MISS_FIFO_OVERFLOW_INT_EN | 1001634f57dfSYong Wu F_PREFETCH_FIFO_ERR_INT_EN | 1002634f57dfSYong Wu F_MISS_FIFO_ERR_INT_EN; 1003e24453e1SYong Wu writel_relaxed(regval, bankx->base + REG_MMU_INT_CONTROL0); 1004634f57dfSYong Wu 1005634f57dfSYong Wu regval = F_INT_TRANSLATION_FAULT | 1006634f57dfSYong Wu F_INT_MAIN_MULTI_HIT_FAULT | 1007634f57dfSYong Wu F_INT_INVALID_PA_FAULT | 1008634f57dfSYong Wu F_INT_ENTRY_REPLACEMENT_FAULT | 1009634f57dfSYong Wu F_INT_TLB_MISS_FAULT | 1010634f57dfSYong Wu F_INT_MISS_TRANSACTION_FIFO_FAULT | 1011634f57dfSYong Wu F_INT_PRETETCH_TRANSATION_FIFO_FAULT; 1012e24453e1SYong Wu writel_relaxed(regval, bankx->base + REG_MMU_INT_MAIN_CONTROL); 1013634f57dfSYong Wu 1014634f57dfSYong Wu if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_LEGACY_IVRP_PADDR)) 1015634f57dfSYong Wu regval = (data->protect_base >> 1) | (data->enable_4GB << 31); 1016634f57dfSYong Wu else 1017634f57dfSYong Wu regval = lower_32_bits(data->protect_base) | 1018634f57dfSYong Wu upper_32_bits(data->protect_base); 1019e24453e1SYong Wu writel_relaxed(regval, bankx->base + REG_MMU_IVRP_PADDR); 1020634f57dfSYong Wu 1021e24453e1SYong Wu if (devm_request_irq(bankx->parent_dev, bankx->irq, mtk_iommu_isr, 0, 1022e24453e1SYong Wu dev_name(bankx->parent_dev), (void *)bankx)) { 1023e24453e1SYong Wu writel_relaxed(0, bankx->base + REG_MMU_PT_BASE_ADDR); 1024e24453e1SYong Wu dev_err(bankx->parent_dev, "Failed @ IRQ-%d Request\n", bankx->irq); 10250df4fabeSYong Wu return -ENODEV; 10260df4fabeSYong Wu } 10270df4fabeSYong Wu 10280df4fabeSYong Wu return 0; 10290df4fabeSYong Wu } 10300df4fabeSYong Wu 10310df4fabeSYong Wu static const struct component_master_ops mtk_iommu_com_ops = { 10320df4fabeSYong Wu .bind = mtk_iommu_bind, 10330df4fabeSYong Wu .unbind = mtk_iommu_unbind, 10340df4fabeSYong Wu }; 10350df4fabeSYong Wu 1036d2e9a110SYong Wu static int mtk_iommu_mm_dts_parse(struct device *dev, struct component_match **match, 1037d2e9a110SYong Wu struct mtk_iommu_data *data) 1038d2e9a110SYong Wu { 1039f7b71d0dSYong Wu struct device_node *larbnode, *smicomm_node, *smi_subcomm_node; 1040d2e9a110SYong Wu struct platform_device *plarbdev; 1041d2e9a110SYong Wu struct device_link *link; 1042d2e9a110SYong Wu int i, larb_nr, ret; 1043d2e9a110SYong Wu 1044d2e9a110SYong Wu larb_nr = of_count_phandle_with_args(dev->of_node, "mediatek,larbs", NULL); 1045d2e9a110SYong Wu if (larb_nr < 0) 1046d2e9a110SYong Wu return larb_nr; 1047d2e9a110SYong Wu 1048d2e9a110SYong Wu for (i = 0; i < larb_nr; i++) { 1049d2e9a110SYong Wu u32 id; 1050d2e9a110SYong Wu 1051d2e9a110SYong Wu larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i); 1052d2e9a110SYong Wu if (!larbnode) 1053d2e9a110SYong Wu return -EINVAL; 1054d2e9a110SYong Wu 1055d2e9a110SYong Wu if (!of_device_is_available(larbnode)) { 1056d2e9a110SYong Wu of_node_put(larbnode); 1057d2e9a110SYong Wu continue; 1058d2e9a110SYong Wu } 1059d2e9a110SYong Wu 1060d2e9a110SYong Wu ret = of_property_read_u32(larbnode, "mediatek,larb-id", &id); 1061d2e9a110SYong Wu if (ret)/* The id is consecutive if there is no this property */ 1062d2e9a110SYong Wu id = i; 1063d2e9a110SYong Wu 1064d2e9a110SYong Wu plarbdev = of_find_device_by_node(larbnode); 1065d2e9a110SYong Wu if (!plarbdev) { 1066d2e9a110SYong Wu of_node_put(larbnode); 1067d2e9a110SYong Wu return -ENODEV; 1068d2e9a110SYong Wu } 1069d2e9a110SYong Wu if (!plarbdev->dev.driver) { 1070d2e9a110SYong Wu of_node_put(larbnode); 1071d2e9a110SYong Wu return -EPROBE_DEFER; 1072d2e9a110SYong Wu } 1073d2e9a110SYong Wu data->larb_imu[id].dev = &plarbdev->dev; 1074d2e9a110SYong Wu 1075d2e9a110SYong Wu component_match_add_release(dev, match, component_release_of, 1076d2e9a110SYong Wu component_compare_of, larbnode); 1077d2e9a110SYong Wu } 1078d2e9a110SYong Wu 1079f7b71d0dSYong Wu /* Get smi-(sub)-common dev from the last larb. */ 1080f7b71d0dSYong Wu smi_subcomm_node = of_parse_phandle(larbnode, "mediatek,smi", 0); 1081f7b71d0dSYong Wu if (!smi_subcomm_node) 1082d2e9a110SYong Wu return -EINVAL; 1083d2e9a110SYong Wu 1084f7b71d0dSYong Wu /* 1085f7b71d0dSYong Wu * It may have two level smi-common. the node is smi-sub-common if it 1086f7b71d0dSYong Wu * has a new mediatek,smi property. otherwise it is smi-commmon. 1087f7b71d0dSYong Wu */ 1088f7b71d0dSYong Wu smicomm_node = of_parse_phandle(smi_subcomm_node, "mediatek,smi", 0); 1089f7b71d0dSYong Wu if (smicomm_node) 1090f7b71d0dSYong Wu of_node_put(smi_subcomm_node); 1091f7b71d0dSYong Wu else 1092f7b71d0dSYong Wu smicomm_node = smi_subcomm_node; 1093f7b71d0dSYong Wu 1094d2e9a110SYong Wu plarbdev = of_find_device_by_node(smicomm_node); 1095d2e9a110SYong Wu of_node_put(smicomm_node); 1096d2e9a110SYong Wu data->smicomm_dev = &plarbdev->dev; 1097d2e9a110SYong Wu 1098d2e9a110SYong Wu link = device_link_add(data->smicomm_dev, dev, 1099d2e9a110SYong Wu DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME); 1100d2e9a110SYong Wu if (!link) { 1101d2e9a110SYong Wu dev_err(dev, "Unable to link %s.\n", dev_name(data->smicomm_dev)); 1102d2e9a110SYong Wu return -EINVAL; 1103d2e9a110SYong Wu } 1104d2e9a110SYong Wu return 0; 1105d2e9a110SYong Wu } 1106d2e9a110SYong Wu 11070df4fabeSYong Wu static int mtk_iommu_probe(struct platform_device *pdev) 11080df4fabeSYong Wu { 11090df4fabeSYong Wu struct mtk_iommu_data *data; 11100df4fabeSYong Wu struct device *dev = &pdev->dev; 11110df4fabeSYong Wu struct resource *res; 1112b16c0170SJoerg Roedel resource_size_t ioaddr; 11130df4fabeSYong Wu struct component_match *match = NULL; 1114c2c59456SMiles Chen struct regmap *infracfg; 11150df4fabeSYong Wu void *protect; 1116*42d57fc5SYong Wu int ret, banks_num, i = 0; 1117c2c59456SMiles Chen u32 val; 1118c2c59456SMiles Chen char *p; 111999ca0228SYong Wu struct mtk_iommu_bank_data *bank; 112099ca0228SYong Wu void __iomem *base; 11210df4fabeSYong Wu 11220df4fabeSYong Wu data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 11230df4fabeSYong Wu if (!data) 11240df4fabeSYong Wu return -ENOMEM; 11250df4fabeSYong Wu data->dev = dev; 1126cecdce9dSYong Wu data->plat_data = of_device_get_match_data(dev); 11270df4fabeSYong Wu 11280df4fabeSYong Wu /* Protect memory. HW will access here while translation fault.*/ 11290df4fabeSYong Wu protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2, GFP_KERNEL); 11300df4fabeSYong Wu if (!protect) 11310df4fabeSYong Wu return -ENOMEM; 11320df4fabeSYong Wu data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN); 11330df4fabeSYong Wu 1134c2c59456SMiles Chen if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) { 1135c2c59456SMiles Chen switch (data->plat_data->m4u_plat) { 1136c2c59456SMiles Chen case M4U_MT2712: 1137c2c59456SMiles Chen p = "mediatek,mt2712-infracfg"; 1138c2c59456SMiles Chen break; 1139c2c59456SMiles Chen case M4U_MT8173: 1140c2c59456SMiles Chen p = "mediatek,mt8173-infracfg"; 1141c2c59456SMiles Chen break; 1142c2c59456SMiles Chen default: 1143c2c59456SMiles Chen p = NULL; 1144c2c59456SMiles Chen } 1145c2c59456SMiles Chen 1146c2c59456SMiles Chen infracfg = syscon_regmap_lookup_by_compatible(p); 1147c2c59456SMiles Chen 1148c2c59456SMiles Chen if (IS_ERR(infracfg)) 1149c2c59456SMiles Chen return PTR_ERR(infracfg); 1150c2c59456SMiles Chen 1151c2c59456SMiles Chen ret = regmap_read(infracfg, REG_INFRA_MISC, &val); 1152c2c59456SMiles Chen if (ret) 1153c2c59456SMiles Chen return ret; 1154c2c59456SMiles Chen data->enable_4GB = !!(val & F_DDR_4GB_SUPPORT_EN); 1155c2c59456SMiles Chen } 115601e23c93SYong Wu 1157*42d57fc5SYong Wu banks_num = data->plat_data->banks_num; 11580df4fabeSYong Wu res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1159*42d57fc5SYong Wu if (resource_size(res) < banks_num * MTK_IOMMU_BANK_SZ) { 1160*42d57fc5SYong Wu dev_err(dev, "banknr %d. res %pR is not enough.\n", banks_num, res); 1161*42d57fc5SYong Wu return -EINVAL; 1162*42d57fc5SYong Wu } 116399ca0228SYong Wu base = devm_ioremap_resource(dev, res); 116499ca0228SYong Wu if (IS_ERR(base)) 116599ca0228SYong Wu return PTR_ERR(base); 1166b16c0170SJoerg Roedel ioaddr = res->start; 11670df4fabeSYong Wu 116899ca0228SYong Wu data->bank = devm_kmalloc(dev, banks_num * sizeof(*data->bank), GFP_KERNEL); 116999ca0228SYong Wu if (!data->bank) 117099ca0228SYong Wu return -ENOMEM; 117199ca0228SYong Wu 1172*42d57fc5SYong Wu do { 1173*42d57fc5SYong Wu if (!data->plat_data->banks_enable[i]) 1174*42d57fc5SYong Wu continue; 1175*42d57fc5SYong Wu bank = &data->bank[i]; 1176*42d57fc5SYong Wu bank->id = i; 1177*42d57fc5SYong Wu bank->base = base + i * MTK_IOMMU_BANK_SZ; 117899ca0228SYong Wu bank->m4u_dom = NULL; 1179*42d57fc5SYong Wu 1180*42d57fc5SYong Wu bank->irq = platform_get_irq(pdev, i); 118199ca0228SYong Wu if (bank->irq < 0) 118299ca0228SYong Wu return bank->irq; 118399ca0228SYong Wu bank->parent_dev = dev; 118499ca0228SYong Wu bank->parent_data = data; 118599ca0228SYong Wu spin_lock_init(&bank->tlb_lock); 1186*42d57fc5SYong Wu } while (++i < banks_num); 11870df4fabeSYong Wu 11886b717796SChao Hao if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_BCLK)) { 11890df4fabeSYong Wu data->bclk = devm_clk_get(dev, "bclk"); 11900df4fabeSYong Wu if (IS_ERR(data->bclk)) 11910df4fabeSYong Wu return PTR_ERR(data->bclk); 11922aa4c259SYong Wu } 11930df4fabeSYong Wu 1194c0b57581SYong Wu pm_runtime_enable(dev); 1195c0b57581SYong Wu 1196d2e9a110SYong Wu if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { 1197d2e9a110SYong Wu ret = mtk_iommu_mm_dts_parse(dev, &match, data); 1198d2e9a110SYong Wu if (ret) { 1199d2e9a110SYong Wu dev_err(dev, "mm dts parse fail(%d).", ret); 1200c0b57581SYong Wu goto out_runtime_disable; 1201baf94e6eSYong Wu } 1202f9b8c9b2SYong Wu } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA) && 1203f9b8c9b2SYong Wu data->plat_data->pericfg_comp_str) { 1204f9b8c9b2SYong Wu infracfg = syscon_regmap_lookup_by_compatible(data->plat_data->pericfg_comp_str); 1205f9b8c9b2SYong Wu if (IS_ERR(infracfg)) { 1206f9b8c9b2SYong Wu ret = PTR_ERR(infracfg); 1207f9b8c9b2SYong Wu goto out_runtime_disable; 1208f9b8c9b2SYong Wu } 1209f9b8c9b2SYong Wu 1210f9b8c9b2SYong Wu data->pericfg = infracfg; 1211d2e9a110SYong Wu } 1212baf94e6eSYong Wu 12130df4fabeSYong Wu platform_set_drvdata(pdev, data); 12140e5a3f2eSYong Wu mutex_init(&data->mutex); 12150df4fabeSYong Wu 1216b16c0170SJoerg Roedel ret = iommu_device_sysfs_add(&data->iommu, dev, NULL, 1217b16c0170SJoerg Roedel "mtk-iommu.%pa", &ioaddr); 1218b16c0170SJoerg Roedel if (ret) 1219baf94e6eSYong Wu goto out_link_remove; 1220b16c0170SJoerg Roedel 12212d471b20SRobin Murphy ret = iommu_device_register(&data->iommu, &mtk_iommu_ops, dev); 1222b16c0170SJoerg Roedel if (ret) 1223986d9ec5SYong Wu goto out_sysfs_remove; 1224b16c0170SJoerg Roedel 12259e3a2a64SYong Wu if (MTK_IOMMU_HAS_FLAG(data->plat_data, SHARE_PGTABLE)) { 12269e3a2a64SYong Wu list_add_tail(&data->list, data->plat_data->hw_list); 12279e3a2a64SYong Wu data->hw_list = data->plat_data->hw_list; 12289e3a2a64SYong Wu } else { 12299e3a2a64SYong Wu INIT_LIST_HEAD(&data->hw_list_head); 12309e3a2a64SYong Wu list_add_tail(&data->list, &data->hw_list_head); 12319e3a2a64SYong Wu data->hw_list = &data->hw_list_head; 12329e3a2a64SYong Wu } 12337c3a2ec0SYong Wu 1234986d9ec5SYong Wu if (!iommu_present(&platform_bus_type)) { 1235986d9ec5SYong Wu ret = bus_set_iommu(&platform_bus_type, &mtk_iommu_ops); 1236986d9ec5SYong Wu if (ret) 1237986d9ec5SYong Wu goto out_list_del; 1238986d9ec5SYong Wu } 12390df4fabeSYong Wu 1240d2e9a110SYong Wu if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { 1241986d9ec5SYong Wu ret = component_master_add_with_match(dev, &mtk_iommu_com_ops, match); 1242986d9ec5SYong Wu if (ret) 1243986d9ec5SYong Wu goto out_bus_set_null; 1244e7629070SYong Wu } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA) && 1245e7629070SYong Wu MTK_IOMMU_HAS_FLAG(data->plat_data, IFA_IOMMU_PCIE_SUPPORT)) { 1246e7629070SYong Wu #ifdef CONFIG_PCI 1247e7629070SYong Wu if (!iommu_present(&pci_bus_type)) { 1248e7629070SYong Wu ret = bus_set_iommu(&pci_bus_type, &mtk_iommu_ops); 1249e7629070SYong Wu if (ret) /* PCIe fail don't affect platform_bus. */ 1250e7629070SYong Wu goto out_list_del; 1251e7629070SYong Wu } 1252e7629070SYong Wu #endif 1253d2e9a110SYong Wu } 1254986d9ec5SYong Wu return ret; 1255986d9ec5SYong Wu 1256986d9ec5SYong Wu out_bus_set_null: 1257986d9ec5SYong Wu bus_set_iommu(&platform_bus_type, NULL); 1258986d9ec5SYong Wu out_list_del: 1259986d9ec5SYong Wu list_del(&data->list); 1260986d9ec5SYong Wu iommu_device_unregister(&data->iommu); 1261986d9ec5SYong Wu out_sysfs_remove: 1262986d9ec5SYong Wu iommu_device_sysfs_remove(&data->iommu); 1263baf94e6eSYong Wu out_link_remove: 1264d2e9a110SYong Wu if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) 1265baf94e6eSYong Wu device_link_remove(data->smicomm_dev, dev); 1266c0b57581SYong Wu out_runtime_disable: 1267c0b57581SYong Wu pm_runtime_disable(dev); 1268986d9ec5SYong Wu return ret; 12690df4fabeSYong Wu } 12700df4fabeSYong Wu 12710df4fabeSYong Wu static int mtk_iommu_remove(struct platform_device *pdev) 12720df4fabeSYong Wu { 12730df4fabeSYong Wu struct mtk_iommu_data *data = platform_get_drvdata(pdev); 1274*42d57fc5SYong Wu struct mtk_iommu_bank_data *bank; 1275*42d57fc5SYong Wu int i; 12760df4fabeSYong Wu 1277b16c0170SJoerg Roedel iommu_device_sysfs_remove(&data->iommu); 1278b16c0170SJoerg Roedel iommu_device_unregister(&data->iommu); 1279b16c0170SJoerg Roedel 1280ee55f75eSYong Wu list_del(&data->list); 12810df4fabeSYong Wu 1282d2e9a110SYong Wu if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { 1283baf94e6eSYong Wu device_link_remove(data->smicomm_dev, &pdev->dev); 1284d2e9a110SYong Wu component_master_del(&pdev->dev, &mtk_iommu_com_ops); 1285e7629070SYong Wu } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA) && 1286e7629070SYong Wu MTK_IOMMU_HAS_FLAG(data->plat_data, IFA_IOMMU_PCIE_SUPPORT)) { 1287e7629070SYong Wu #ifdef CONFIG_PCI 1288e7629070SYong Wu bus_set_iommu(&pci_bus_type, NULL); 1289e7629070SYong Wu #endif 1290d2e9a110SYong Wu } 1291c0b57581SYong Wu pm_runtime_disable(&pdev->dev); 1292*42d57fc5SYong Wu for (i = 0; i < data->plat_data->banks_num; i++) { 1293*42d57fc5SYong Wu bank = &data->bank[i]; 1294*42d57fc5SYong Wu if (!bank->m4u_dom) 1295*42d57fc5SYong Wu continue; 129699ca0228SYong Wu devm_free_irq(&pdev->dev, bank->irq, bank); 1297*42d57fc5SYong Wu } 12980df4fabeSYong Wu return 0; 12990df4fabeSYong Wu } 13000df4fabeSYong Wu 130134665c79SYong Wu static int __maybe_unused mtk_iommu_runtime_suspend(struct device *dev) 13020df4fabeSYong Wu { 13030df4fabeSYong Wu struct mtk_iommu_data *data = dev_get_drvdata(dev); 13040df4fabeSYong Wu struct mtk_iommu_suspend_reg *reg = &data->reg; 130599ca0228SYong Wu void __iomem *base = data->bank[0].base; 13060df4fabeSYong Wu 130735c1b48dSChao Hao reg->wr_len_ctrl = readl_relaxed(base + REG_MMU_WR_LEN_CTRL); 130875eed350SChao Hao reg->misc_ctrl = readl_relaxed(base + REG_MMU_MISC_CTRL); 13090df4fabeSYong Wu reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS); 13100df4fabeSYong Wu reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG); 13110df4fabeSYong Wu reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL0); 13120df4fabeSYong Wu reg->int_main_control = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL); 131370ca608bSYong Wu reg->ivrp_paddr = readl_relaxed(base + REG_MMU_IVRP_PADDR); 1314b9475b34SYong Wu reg->vld_pa_rng = readl_relaxed(base + REG_MMU_VLD_PA_RNG); 13156254b64fSYong Wu clk_disable_unprepare(data->bclk); 13160df4fabeSYong Wu return 0; 13170df4fabeSYong Wu } 13180df4fabeSYong Wu 131934665c79SYong Wu static int __maybe_unused mtk_iommu_runtime_resume(struct device *dev) 13200df4fabeSYong Wu { 13210df4fabeSYong Wu struct mtk_iommu_data *data = dev_get_drvdata(dev); 13220df4fabeSYong Wu struct mtk_iommu_suspend_reg *reg = &data->reg; 132399ca0228SYong Wu struct mtk_iommu_domain *m4u_dom = data->bank[0].m4u_dom; 132499ca0228SYong Wu void __iomem *base = data->bank[0].base; 13256254b64fSYong Wu int ret; 13260df4fabeSYong Wu 13276254b64fSYong Wu ret = clk_prepare_enable(data->bclk); 13286254b64fSYong Wu if (ret) { 13296254b64fSYong Wu dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret); 13306254b64fSYong Wu return ret; 13316254b64fSYong Wu } 1332b34ea31fSDafna Hirschfeld 1333b34ea31fSDafna Hirschfeld /* 1334b34ea31fSDafna Hirschfeld * Uppon first resume, only enable the clk and return, since the values of the 1335b34ea31fSDafna Hirschfeld * registers are not yet set. 1336b34ea31fSDafna Hirschfeld */ 1337b34ea31fSDafna Hirschfeld if (!m4u_dom) 1338b34ea31fSDafna Hirschfeld return 0; 1339b34ea31fSDafna Hirschfeld 134035c1b48dSChao Hao writel_relaxed(reg->wr_len_ctrl, base + REG_MMU_WR_LEN_CTRL); 134175eed350SChao Hao writel_relaxed(reg->misc_ctrl, base + REG_MMU_MISC_CTRL); 13420df4fabeSYong Wu writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS); 13430df4fabeSYong Wu writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG); 13440df4fabeSYong Wu writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0); 13450df4fabeSYong Wu writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL); 134670ca608bSYong Wu writel_relaxed(reg->ivrp_paddr, base + REG_MMU_IVRP_PADDR); 1347b9475b34SYong Wu writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG); 1348c0b57581SYong Wu writel(m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, base + REG_MMU_PT_BASE_ADDR); 13494f23f6d4SYong Wu 13504f23f6d4SYong Wu /* 13514f23f6d4SYong Wu * Users may allocate dma buffer before they call pm_runtime_get, 13524f23f6d4SYong Wu * in which case it will lack the necessary tlb flush. 13534f23f6d4SYong Wu * Thus, make sure to update the tlb after each PM resume. 13544f23f6d4SYong Wu */ 13554f23f6d4SYong Wu mtk_iommu_tlb_flush_all(data); 13560df4fabeSYong Wu return 0; 13570df4fabeSYong Wu } 13580df4fabeSYong Wu 1359e6dec923SYong Wu static const struct dev_pm_ops mtk_iommu_pm_ops = { 136034665c79SYong Wu SET_RUNTIME_PM_OPS(mtk_iommu_runtime_suspend, mtk_iommu_runtime_resume, NULL) 136134665c79SYong Wu SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 136234665c79SYong Wu pm_runtime_force_resume) 13630df4fabeSYong Wu }; 13640df4fabeSYong Wu 1365cecdce9dSYong Wu static const struct mtk_iommu_plat_data mt2712_data = { 1366cecdce9dSYong Wu .m4u_plat = M4U_MT2712, 1367d2e9a110SYong Wu .flags = HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG | SHARE_PGTABLE | 1368d2e9a110SYong Wu MTK_IOMMU_TYPE_MM, 13699e3a2a64SYong Wu .hw_list = &m4ulist, 1370b053bc71SChao Hao .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 1371585e58f4SYong Wu .iova_region = single_domain, 137299ca0228SYong Wu .banks_num = 1, 137399ca0228SYong Wu .banks_enable = {true}, 1374585e58f4SYong Wu .iova_region_nr = ARRAY_SIZE(single_domain), 137537276e00SChao Hao .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}}, 1376cecdce9dSYong Wu }; 1377cecdce9dSYong Wu 1378068c86e9SChao Hao static const struct mtk_iommu_plat_data mt6779_data = { 1379068c86e9SChao Hao .m4u_plat = M4U_MT6779, 1380d2e9a110SYong Wu .flags = HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | WR_THROT_EN | 1381d2e9a110SYong Wu MTK_IOMMU_TYPE_MM, 1382068c86e9SChao Hao .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 138399ca0228SYong Wu .banks_num = 1, 138499ca0228SYong Wu .banks_enable = {true}, 1385585e58f4SYong Wu .iova_region = single_domain, 1386585e58f4SYong Wu .iova_region_nr = ARRAY_SIZE(single_domain), 1387068c86e9SChao Hao .larbid_remap = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}}, 1388cecdce9dSYong Wu }; 1389cecdce9dSYong Wu 13903c213562SFabien Parent static const struct mtk_iommu_plat_data mt8167_data = { 13913c213562SFabien Parent .m4u_plat = M4U_MT8167, 1392d2e9a110SYong Wu .flags = RESET_AXI | HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM, 13933c213562SFabien Parent .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 139499ca0228SYong Wu .banks_num = 1, 139599ca0228SYong Wu .banks_enable = {true}, 1396585e58f4SYong Wu .iova_region = single_domain, 1397585e58f4SYong Wu .iova_region_nr = ARRAY_SIZE(single_domain), 13983c213562SFabien Parent .larbid_remap = {{0}, {1}, {2}}, /* Linear mapping. */ 13993c213562SFabien Parent }; 14003c213562SFabien Parent 1401cecdce9dSYong Wu static const struct mtk_iommu_plat_data mt8173_data = { 1402cecdce9dSYong Wu .m4u_plat = M4U_MT8173, 1403d1b5ef00SFabien Parent .flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI | 1404d2e9a110SYong Wu HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM, 1405b053bc71SChao Hao .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 140699ca0228SYong Wu .banks_num = 1, 140799ca0228SYong Wu .banks_enable = {true}, 1408585e58f4SYong Wu .iova_region = single_domain, 1409585e58f4SYong Wu .iova_region_nr = ARRAY_SIZE(single_domain), 141037276e00SChao Hao .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */ 1411cecdce9dSYong Wu }; 1412cecdce9dSYong Wu 1413907ba6a1SYong Wu static const struct mtk_iommu_plat_data mt8183_data = { 1414907ba6a1SYong Wu .m4u_plat = M4U_MT8183, 1415d2e9a110SYong Wu .flags = RESET_AXI | MTK_IOMMU_TYPE_MM, 1416b053bc71SChao Hao .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 141799ca0228SYong Wu .banks_num = 1, 141899ca0228SYong Wu .banks_enable = {true}, 1419585e58f4SYong Wu .iova_region = single_domain, 1420585e58f4SYong Wu .iova_region_nr = ARRAY_SIZE(single_domain), 142137276e00SChao Hao .larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}}, 1422907ba6a1SYong Wu }; 1423907ba6a1SYong Wu 14249e3489e0SYong Wu static const struct mtk_iommu_plat_data mt8192_data = { 14259e3489e0SYong Wu .m4u_plat = M4U_MT8192, 14269ec30c09SYong Wu .flags = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | 1427d2e9a110SYong Wu WR_THROT_EN | IOVA_34_EN | MTK_IOMMU_TYPE_MM, 14289e3489e0SYong Wu .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 142999ca0228SYong Wu .banks_num = 1, 143099ca0228SYong Wu .banks_enable = {true}, 14319e3489e0SYong Wu .iova_region = mt8192_multi_dom, 14329e3489e0SYong Wu .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), 14339e3489e0SYong Wu .larbid_remap = {{0}, {1}, {4, 5}, {7}, {2}, {9, 11, 19, 20}, 14349e3489e0SYong Wu {0, 14, 16}, {0, 13, 18, 17}}, 14359e3489e0SYong Wu }; 14369e3489e0SYong Wu 1437ef68a193SYong Wu static const struct mtk_iommu_plat_data mt8195_data_infra = { 1438ef68a193SYong Wu .m4u_plat = M4U_MT8195, 1439ef68a193SYong Wu .flags = WR_THROT_EN | DCM_DISABLE | STD_AXI_MODE | PM_CLK_AO | 1440ef68a193SYong Wu MTK_IOMMU_TYPE_INFRA | IFA_IOMMU_PCIE_SUPPORT, 1441ef68a193SYong Wu .pericfg_comp_str = "mediatek,mt8195-pericfg_ao", 1442ef68a193SYong Wu .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 144399ca0228SYong Wu .banks_num = 1, 144499ca0228SYong Wu .banks_enable = {true}, 1445ef68a193SYong Wu .iova_region = single_domain, 1446ef68a193SYong Wu .iova_region_nr = ARRAY_SIZE(single_domain), 1447ef68a193SYong Wu }; 1448ef68a193SYong Wu 1449ef68a193SYong Wu static const struct mtk_iommu_plat_data mt8195_data_vdo = { 1450ef68a193SYong Wu .m4u_plat = M4U_MT8195, 1451ef68a193SYong Wu .flags = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | 1452ef68a193SYong Wu WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE | MTK_IOMMU_TYPE_MM, 1453ef68a193SYong Wu .hw_list = &m4ulist, 1454ef68a193SYong Wu .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 145599ca0228SYong Wu .banks_num = 1, 145699ca0228SYong Wu .banks_enable = {true}, 1457ef68a193SYong Wu .iova_region = mt8192_multi_dom, 1458ef68a193SYong Wu .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), 1459ef68a193SYong Wu .larbid_remap = {{2, 0}, {21}, {24}, {7}, {19}, {9, 10, 11}, 1460ef68a193SYong Wu {13, 17, 15/* 17b */, 25}, {5}}, 1461ef68a193SYong Wu }; 1462ef68a193SYong Wu 1463ef68a193SYong Wu static const struct mtk_iommu_plat_data mt8195_data_vpp = { 1464ef68a193SYong Wu .m4u_plat = M4U_MT8195, 1465ef68a193SYong Wu .flags = HAS_BCLK | HAS_SUB_COMM_3BITS | OUT_ORDER_WR_EN | 1466ef68a193SYong Wu WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE | MTK_IOMMU_TYPE_MM, 1467ef68a193SYong Wu .hw_list = &m4ulist, 1468ef68a193SYong Wu .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 146999ca0228SYong Wu .banks_num = 1, 147099ca0228SYong Wu .banks_enable = {true}, 1471ef68a193SYong Wu .iova_region = mt8192_multi_dom, 1472ef68a193SYong Wu .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), 1473ef68a193SYong Wu .larbid_remap = {{1}, {3}, 1474ef68a193SYong Wu {22, MTK_INVALID_LARBID, MTK_INVALID_LARBID, MTK_INVALID_LARBID, 23}, 1475ef68a193SYong Wu {8}, {20}, {12}, 1476ef68a193SYong Wu /* 16: 16a; 29: 16b; 30: CCUtop0; 31: CCUtop1 */ 1477ef68a193SYong Wu {14, 16, 29, 26, 30, 31, 18}, 1478ef68a193SYong Wu {4, MTK_INVALID_LARBID, MTK_INVALID_LARBID, MTK_INVALID_LARBID, 6}}, 1479ef68a193SYong Wu }; 1480ef68a193SYong Wu 14810df4fabeSYong Wu static const struct of_device_id mtk_iommu_of_ids[] = { 1482cecdce9dSYong Wu { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data}, 1483068c86e9SChao Hao { .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data}, 14843c213562SFabien Parent { .compatible = "mediatek,mt8167-m4u", .data = &mt8167_data}, 1485cecdce9dSYong Wu { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data}, 1486907ba6a1SYong Wu { .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data}, 14879e3489e0SYong Wu { .compatible = "mediatek,mt8192-m4u", .data = &mt8192_data}, 1488ef68a193SYong Wu { .compatible = "mediatek,mt8195-iommu-infra", .data = &mt8195_data_infra}, 1489ef68a193SYong Wu { .compatible = "mediatek,mt8195-iommu-vdo", .data = &mt8195_data_vdo}, 1490ef68a193SYong Wu { .compatible = "mediatek,mt8195-iommu-vpp", .data = &mt8195_data_vpp}, 14910df4fabeSYong Wu {} 14920df4fabeSYong Wu }; 14930df4fabeSYong Wu 14940df4fabeSYong Wu static struct platform_driver mtk_iommu_driver = { 14950df4fabeSYong Wu .probe = mtk_iommu_probe, 14960df4fabeSYong Wu .remove = mtk_iommu_remove, 14970df4fabeSYong Wu .driver = { 14980df4fabeSYong Wu .name = "mtk-iommu", 1499f53dd978SKrzysztof Kozlowski .of_match_table = mtk_iommu_of_ids, 15000df4fabeSYong Wu .pm = &mtk_iommu_pm_ops, 15010df4fabeSYong Wu } 15020df4fabeSYong Wu }; 150318d8c74eSYong Wu module_platform_driver(mtk_iommu_driver); 15040df4fabeSYong Wu 150518d8c74eSYong Wu MODULE_DESCRIPTION("IOMMU API for MediaTek M4U implementations"); 150618d8c74eSYong Wu MODULE_LICENSE("GPL v2"); 1507