11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 20df4fabeSYong Wu /* 30df4fabeSYong Wu * Copyright (c) 2015-2016 MediaTek Inc. 40df4fabeSYong Wu * Author: Yong Wu <yong.wu@mediatek.com> 50df4fabeSYong Wu */ 6ef0f0986SYong Wu #include <linux/bitfield.h> 70df4fabeSYong Wu #include <linux/bug.h> 80df4fabeSYong Wu #include <linux/clk.h> 90df4fabeSYong Wu #include <linux/component.h> 100df4fabeSYong Wu #include <linux/device.h> 110df4fabeSYong Wu #include <linux/dma-iommu.h> 120df4fabeSYong Wu #include <linux/err.h> 130df4fabeSYong Wu #include <linux/interrupt.h> 140df4fabeSYong Wu #include <linux/io.h> 150df4fabeSYong Wu #include <linux/iommu.h> 160df4fabeSYong Wu #include <linux/iopoll.h> 170df4fabeSYong Wu #include <linux/list.h> 18c2c59456SMiles Chen #include <linux/mfd/syscon.h> 190df4fabeSYong Wu #include <linux/of_address.h> 200df4fabeSYong Wu #include <linux/of_iommu.h> 210df4fabeSYong Wu #include <linux/of_irq.h> 220df4fabeSYong Wu #include <linux/of_platform.h> 230df4fabeSYong Wu #include <linux/platform_device.h> 24baf94e6eSYong Wu #include <linux/pm_runtime.h> 25c2c59456SMiles Chen #include <linux/regmap.h> 260df4fabeSYong Wu #include <linux/slab.h> 270df4fabeSYong Wu #include <linux/spinlock.h> 28c2c59456SMiles Chen #include <linux/soc/mediatek/infracfg.h> 290df4fabeSYong Wu #include <asm/barrier.h> 300df4fabeSYong Wu #include <soc/mediatek/smi.h> 310df4fabeSYong Wu 329ca340c9SHonghui Zhang #include "mtk_iommu.h" 330df4fabeSYong Wu 340df4fabeSYong Wu #define REG_MMU_PT_BASE_ADDR 0x000 35907ba6a1SYong Wu #define MMU_PT_ADDR_MASK GENMASK(31, 7) 360df4fabeSYong Wu 370df4fabeSYong Wu #define REG_MMU_INVALIDATE 0x020 380df4fabeSYong Wu #define F_ALL_INVLD 0x2 390df4fabeSYong Wu #define F_MMU_INV_RANGE 0x1 400df4fabeSYong Wu 410df4fabeSYong Wu #define REG_MMU_INVLD_START_A 0x024 420df4fabeSYong Wu #define REG_MMU_INVLD_END_A 0x028 430df4fabeSYong Wu 44068c86e9SChao Hao #define REG_MMU_INV_SEL_GEN2 0x02c 45b053bc71SChao Hao #define REG_MMU_INV_SEL_GEN1 0x038 460df4fabeSYong Wu #define F_INVLD_EN0 BIT(0) 470df4fabeSYong Wu #define F_INVLD_EN1 BIT(1) 480df4fabeSYong Wu 4975eed350SChao Hao #define REG_MMU_MISC_CTRL 0x048 504bb2bf4cSChao Hao #define F_MMU_IN_ORDER_WR_EN_MASK (BIT(1) | BIT(17)) 514bb2bf4cSChao Hao #define F_MMU_STANDARD_AXI_MODE_MASK (BIT(3) | BIT(19)) 524bb2bf4cSChao Hao 530df4fabeSYong Wu #define REG_MMU_DCM_DIS 0x050 5435c1b48dSChao Hao #define REG_MMU_WR_LEN_CTRL 0x054 5535c1b48dSChao Hao #define F_MMU_WR_THROT_DIS_MASK (BIT(5) | BIT(21)) 560df4fabeSYong Wu 570df4fabeSYong Wu #define REG_MMU_CTRL_REG 0x110 58acb3c92aSYong Wu #define F_MMU_TF_PROT_TO_PROGRAM_ADDR (2 << 4) 590df4fabeSYong Wu #define F_MMU_PREFETCH_RT_REPLACE_MOD BIT(4) 60acb3c92aSYong Wu #define F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173 (2 << 5) 610df4fabeSYong Wu 620df4fabeSYong Wu #define REG_MMU_IVRP_PADDR 0x114 6370ca608bSYong Wu 6430e2fccfSYong Wu #define REG_MMU_VLD_PA_RNG 0x118 6530e2fccfSYong Wu #define F_MMU_VLD_PA_RNG(EA, SA) (((EA) << 8) | (SA)) 660df4fabeSYong Wu 670df4fabeSYong Wu #define REG_MMU_INT_CONTROL0 0x120 680df4fabeSYong Wu #define F_L2_MULIT_HIT_EN BIT(0) 690df4fabeSYong Wu #define F_TABLE_WALK_FAULT_INT_EN BIT(1) 700df4fabeSYong Wu #define F_PREETCH_FIFO_OVERFLOW_INT_EN BIT(2) 710df4fabeSYong Wu #define F_MISS_FIFO_OVERFLOW_INT_EN BIT(3) 720df4fabeSYong Wu #define F_PREFETCH_FIFO_ERR_INT_EN BIT(5) 730df4fabeSYong Wu #define F_MISS_FIFO_ERR_INT_EN BIT(6) 740df4fabeSYong Wu #define F_INT_CLR_BIT BIT(12) 750df4fabeSYong Wu 760df4fabeSYong Wu #define REG_MMU_INT_MAIN_CONTROL 0x124 7715a01f4cSYong Wu /* mmu0 | mmu1 */ 7815a01f4cSYong Wu #define F_INT_TRANSLATION_FAULT (BIT(0) | BIT(7)) 7915a01f4cSYong Wu #define F_INT_MAIN_MULTI_HIT_FAULT (BIT(1) | BIT(8)) 8015a01f4cSYong Wu #define F_INT_INVALID_PA_FAULT (BIT(2) | BIT(9)) 8115a01f4cSYong Wu #define F_INT_ENTRY_REPLACEMENT_FAULT (BIT(3) | BIT(10)) 8215a01f4cSYong Wu #define F_INT_TLB_MISS_FAULT (BIT(4) | BIT(11)) 8315a01f4cSYong Wu #define F_INT_MISS_TRANSACTION_FIFO_FAULT (BIT(5) | BIT(12)) 8415a01f4cSYong Wu #define F_INT_PRETETCH_TRANSATION_FIFO_FAULT (BIT(6) | BIT(13)) 850df4fabeSYong Wu 860df4fabeSYong Wu #define REG_MMU_CPE_DONE 0x12C 870df4fabeSYong Wu 880df4fabeSYong Wu #define REG_MMU_FAULT_ST1 0x134 8915a01f4cSYong Wu #define F_REG_MMU0_FAULT_MASK GENMASK(6, 0) 9015a01f4cSYong Wu #define F_REG_MMU1_FAULT_MASK GENMASK(13, 7) 910df4fabeSYong Wu 9215a01f4cSYong Wu #define REG_MMU0_FAULT_VA 0x13c 93ef0f0986SYong Wu #define F_MMU_INVAL_VA_31_12_MASK GENMASK(31, 12) 94ef0f0986SYong Wu #define F_MMU_INVAL_VA_34_32_MASK GENMASK(11, 9) 95ef0f0986SYong Wu #define F_MMU_INVAL_PA_34_32_MASK GENMASK(8, 6) 960df4fabeSYong Wu #define F_MMU_FAULT_VA_WRITE_BIT BIT(1) 970df4fabeSYong Wu #define F_MMU_FAULT_VA_LAYER_BIT BIT(0) 980df4fabeSYong Wu 9915a01f4cSYong Wu #define REG_MMU0_INVLD_PA 0x140 10015a01f4cSYong Wu #define REG_MMU1_FAULT_VA 0x144 10115a01f4cSYong Wu #define REG_MMU1_INVLD_PA 0x148 10215a01f4cSYong Wu #define REG_MMU0_INT_ID 0x150 10315a01f4cSYong Wu #define REG_MMU1_INT_ID 0x154 10437276e00SChao Hao #define F_MMU_INT_ID_COMM_ID(a) (((a) >> 9) & 0x7) 10537276e00SChao Hao #define F_MMU_INT_ID_SUB_COMM_ID(a) (((a) >> 7) & 0x3) 10615a01f4cSYong Wu #define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7) 10715a01f4cSYong Wu #define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f) 1080df4fabeSYong Wu 109829316b3SChao Hao #define MTK_PROTECT_PA_ALIGN 256 1100df4fabeSYong Wu 1116b717796SChao Hao #define HAS_4GB_MODE BIT(0) 1126b717796SChao Hao /* HW will use the EMI clock if there isn't the "bclk". */ 1136b717796SChao Hao #define HAS_BCLK BIT(1) 1146b717796SChao Hao #define HAS_VLD_PA_RNG BIT(2) 1156b717796SChao Hao #define RESET_AXI BIT(3) 1164bb2bf4cSChao Hao #define OUT_ORDER_WR_EN BIT(4) 11737276e00SChao Hao #define HAS_SUB_COMM BIT(5) 11835c1b48dSChao Hao #define WR_THROT_EN BIT(6) 119d1b5ef00SFabien Parent #define HAS_LEGACY_IVRP_PADDR BIT(7) 1202f317da4SYong Wu #define IOVA_34_EN BIT(8) 1216b717796SChao Hao 1226b717796SChao Hao #define MTK_IOMMU_HAS_FLAG(pdata, _x) \ 1236b717796SChao Hao ((((pdata)->flags) & (_x)) == (_x)) 1246b717796SChao Hao 1250df4fabeSYong Wu struct mtk_iommu_domain { 1260df4fabeSYong Wu struct io_pgtable_cfg cfg; 1270df4fabeSYong Wu struct io_pgtable_ops *iop; 1280df4fabeSYong Wu 129*08500c43SYong Wu struct mtk_iommu_data *data; 1300df4fabeSYong Wu struct iommu_domain domain; 1310df4fabeSYong Wu }; 1320df4fabeSYong Wu 133b65f5016SArvind Yadav static const struct iommu_ops mtk_iommu_ops; 1340df4fabeSYong Wu 1357f37a91dSYong Wu static int mtk_iommu_hw_init(const struct mtk_iommu_data *data); 1367f37a91dSYong Wu 137bfed8731SYong Wu #define MTK_IOMMU_TLB_ADDR(iova) ({ \ 138bfed8731SYong Wu dma_addr_t _addr = iova; \ 139bfed8731SYong Wu ((lower_32_bits(_addr) & GENMASK(31, 12)) | upper_32_bits(_addr));\ 140bfed8731SYong Wu }) 141bfed8731SYong Wu 14276ce6546SYong Wu /* 14376ce6546SYong Wu * In M4U 4GB mode, the physical address is remapped as below: 14476ce6546SYong Wu * 14576ce6546SYong Wu * CPU Physical address: 14676ce6546SYong Wu * ==================== 14776ce6546SYong Wu * 14876ce6546SYong Wu * 0 1G 2G 3G 4G 5G 14976ce6546SYong Wu * |---A---|---B---|---C---|---D---|---E---| 15076ce6546SYong Wu * +--I/O--+------------Memory-------------+ 15176ce6546SYong Wu * 15276ce6546SYong Wu * IOMMU output physical address: 15376ce6546SYong Wu * ============================= 15476ce6546SYong Wu * 15576ce6546SYong Wu * 4G 5G 6G 7G 8G 15676ce6546SYong Wu * |---E---|---B---|---C---|---D---| 15776ce6546SYong Wu * +------------Memory-------------+ 15876ce6546SYong Wu * 15976ce6546SYong Wu * The Region 'A'(I/O) can NOT be mapped by M4U; For Region 'B'/'C'/'D', the 16076ce6546SYong Wu * bit32 of the CPU physical address always is needed to set, and for Region 16176ce6546SYong Wu * 'E', the CPU physical address keep as is. 16276ce6546SYong Wu * Additionally, The iommu consumers always use the CPU phyiscal address. 16376ce6546SYong Wu */ 164b4dad40eSYong Wu #define MTK_IOMMU_4GB_MODE_REMAP_BASE 0x140000000UL 16576ce6546SYong Wu 1667c3a2ec0SYong Wu static LIST_HEAD(m4ulist); /* List all the M4U HWs */ 1677c3a2ec0SYong Wu 1687c3a2ec0SYong Wu #define for_each_m4u(data) list_for_each_entry(data, &m4ulist, list) 1697c3a2ec0SYong Wu 1707c3a2ec0SYong Wu /* 1717c3a2ec0SYong Wu * There may be 1 or 2 M4U HWs, But we always expect they are in the same domain 1727c3a2ec0SYong Wu * for the performance. 1737c3a2ec0SYong Wu * 1747c3a2ec0SYong Wu * Here always return the mtk_iommu_data of the first probed M4U where the 1757c3a2ec0SYong Wu * iommu domain information is recorded. 1767c3a2ec0SYong Wu */ 1777c3a2ec0SYong Wu static struct mtk_iommu_data *mtk_iommu_get_m4u_data(void) 1787c3a2ec0SYong Wu { 1797c3a2ec0SYong Wu struct mtk_iommu_data *data; 1807c3a2ec0SYong Wu 1817c3a2ec0SYong Wu for_each_m4u(data) 1827c3a2ec0SYong Wu return data; 1837c3a2ec0SYong Wu 1847c3a2ec0SYong Wu return NULL; 1857c3a2ec0SYong Wu } 1867c3a2ec0SYong Wu 1870df4fabeSYong Wu static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom) 1880df4fabeSYong Wu { 1890df4fabeSYong Wu return container_of(dom, struct mtk_iommu_domain, domain); 1900df4fabeSYong Wu } 1910df4fabeSYong Wu 1920954d61aSYong Wu static void mtk_iommu_tlb_flush_all(struct mtk_iommu_data *data) 1930df4fabeSYong Wu { 1947c3a2ec0SYong Wu for_each_m4u(data) { 195c0b57581SYong Wu if (pm_runtime_get_if_in_use(data->dev) <= 0) 196c0b57581SYong Wu continue; 197c0b57581SYong Wu 1987c3a2ec0SYong Wu writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, 199b053bc71SChao Hao data->base + data->plat_data->inv_sel_reg); 2000df4fabeSYong Wu writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE); 2010df4fabeSYong Wu wmb(); /* Make sure the tlb flush all done */ 202c0b57581SYong Wu 203c0b57581SYong Wu pm_runtime_put(data->dev); 2040df4fabeSYong Wu } 2057c3a2ec0SYong Wu } 2060df4fabeSYong Wu 2071f4fd624SYong Wu static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size, 2080954d61aSYong Wu size_t granule, 2090954d61aSYong Wu struct mtk_iommu_data *data) 2100df4fabeSYong Wu { 211c0b57581SYong Wu bool has_pm = !!data->dev->pm_domain; 2121f4fd624SYong Wu unsigned long flags; 2131f4fd624SYong Wu int ret; 2141f4fd624SYong Wu u32 tmp; 2150df4fabeSYong Wu 2167c3a2ec0SYong Wu for_each_m4u(data) { 217c0b57581SYong Wu if (has_pm) { 218c0b57581SYong Wu if (pm_runtime_get_if_in_use(data->dev) <= 0) 219c0b57581SYong Wu continue; 220c0b57581SYong Wu } 221c0b57581SYong Wu 2221f4fd624SYong Wu spin_lock_irqsave(&data->tlb_lock, flags); 2237c3a2ec0SYong Wu writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, 224b053bc71SChao Hao data->base + data->plat_data->inv_sel_reg); 2250df4fabeSYong Wu 226bfed8731SYong Wu writel_relaxed(MTK_IOMMU_TLB_ADDR(iova), 227bfed8731SYong Wu data->base + REG_MMU_INVLD_START_A); 228bfed8731SYong Wu writel_relaxed(MTK_IOMMU_TLB_ADDR(iova + size - 1), 2297c3a2ec0SYong Wu data->base + REG_MMU_INVLD_END_A); 2307c3a2ec0SYong Wu writel_relaxed(F_MMU_INV_RANGE, 2317c3a2ec0SYong Wu data->base + REG_MMU_INVALIDATE); 2320df4fabeSYong Wu 2331f4fd624SYong Wu /* tlb sync */ 2347c3a2ec0SYong Wu ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE, 235c90ae4a6SYong Wu tmp, tmp != 0, 10, 1000); 2360df4fabeSYong Wu if (ret) { 2370df4fabeSYong Wu dev_warn(data->dev, 2380df4fabeSYong Wu "Partial TLB flush timed out, falling back to full flush\n"); 2390954d61aSYong Wu mtk_iommu_tlb_flush_all(data); 2400df4fabeSYong Wu } 2410df4fabeSYong Wu /* Clear the CPE status */ 2420df4fabeSYong Wu writel_relaxed(0, data->base + REG_MMU_CPE_DONE); 243da3cc91bSYong Wu spin_unlock_irqrestore(&data->tlb_lock, flags); 244c0b57581SYong Wu 245c0b57581SYong Wu if (has_pm) 246c0b57581SYong Wu pm_runtime_put(data->dev); 2470df4fabeSYong Wu } 2487c3a2ec0SYong Wu } 2490df4fabeSYong Wu 2500df4fabeSYong Wu static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) 2510df4fabeSYong Wu { 2520df4fabeSYong Wu struct mtk_iommu_data *data = dev_id; 2530df4fabeSYong Wu struct mtk_iommu_domain *dom = data->m4u_dom; 25437276e00SChao Hao unsigned int fault_larb, fault_port, sub_comm = 0; 255ef0f0986SYong Wu u32 int_state, regval, va34_32, pa34_32; 256ef0f0986SYong Wu u64 fault_iova, fault_pa; 2570df4fabeSYong Wu bool layer, write; 2580df4fabeSYong Wu 2590df4fabeSYong Wu /* Read error info from registers */ 2600df4fabeSYong Wu int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST1); 26115a01f4cSYong Wu if (int_state & F_REG_MMU0_FAULT_MASK) { 26215a01f4cSYong Wu regval = readl_relaxed(data->base + REG_MMU0_INT_ID); 26315a01f4cSYong Wu fault_iova = readl_relaxed(data->base + REG_MMU0_FAULT_VA); 26415a01f4cSYong Wu fault_pa = readl_relaxed(data->base + REG_MMU0_INVLD_PA); 26515a01f4cSYong Wu } else { 26615a01f4cSYong Wu regval = readl_relaxed(data->base + REG_MMU1_INT_ID); 26715a01f4cSYong Wu fault_iova = readl_relaxed(data->base + REG_MMU1_FAULT_VA); 26815a01f4cSYong Wu fault_pa = readl_relaxed(data->base + REG_MMU1_INVLD_PA); 26915a01f4cSYong Wu } 2700df4fabeSYong Wu layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT; 2710df4fabeSYong Wu write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT; 272ef0f0986SYong Wu if (MTK_IOMMU_HAS_FLAG(data->plat_data, IOVA_34_EN)) { 273ef0f0986SYong Wu va34_32 = FIELD_GET(F_MMU_INVAL_VA_34_32_MASK, fault_iova); 274ef0f0986SYong Wu pa34_32 = FIELD_GET(F_MMU_INVAL_PA_34_32_MASK, fault_iova); 275ef0f0986SYong Wu fault_iova = fault_iova & F_MMU_INVAL_VA_31_12_MASK; 276ef0f0986SYong Wu fault_iova |= (u64)va34_32 << 32; 277ef0f0986SYong Wu fault_pa |= (u64)pa34_32 << 32; 278ef0f0986SYong Wu } 279ef0f0986SYong Wu 28015a01f4cSYong Wu fault_port = F_MMU_INT_ID_PORT_ID(regval); 28137276e00SChao Hao if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_SUB_COMM)) { 28237276e00SChao Hao fault_larb = F_MMU_INT_ID_COMM_ID(regval); 28337276e00SChao Hao sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval); 28437276e00SChao Hao } else { 28537276e00SChao Hao fault_larb = F_MMU_INT_ID_LARB_ID(regval); 28637276e00SChao Hao } 28737276e00SChao Hao fault_larb = data->plat_data->larbid_remap[fault_larb][sub_comm]; 288b3e5eee7SYong Wu 2890df4fabeSYong Wu if (report_iommu_fault(&dom->domain, data->dev, fault_iova, 2900df4fabeSYong Wu write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) { 2910df4fabeSYong Wu dev_err_ratelimited( 2920df4fabeSYong Wu data->dev, 293ef0f0986SYong Wu "fault type=0x%x iova=0x%llx pa=0x%llx larb=%d port=%d layer=%d %s\n", 2940df4fabeSYong Wu int_state, fault_iova, fault_pa, fault_larb, fault_port, 2950df4fabeSYong Wu layer, write ? "write" : "read"); 2960df4fabeSYong Wu } 2970df4fabeSYong Wu 2980df4fabeSYong Wu /* Interrupt clear */ 2990df4fabeSYong Wu regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL0); 3000df4fabeSYong Wu regval |= F_INT_CLR_BIT; 3010df4fabeSYong Wu writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0); 3020df4fabeSYong Wu 3030df4fabeSYong Wu mtk_iommu_tlb_flush_all(data); 3040df4fabeSYong Wu 3050df4fabeSYong Wu return IRQ_HANDLED; 3060df4fabeSYong Wu } 3070df4fabeSYong Wu 3080df4fabeSYong Wu static void mtk_iommu_config(struct mtk_iommu_data *data, 3090df4fabeSYong Wu struct device *dev, bool enable) 3100df4fabeSYong Wu { 3110df4fabeSYong Wu struct mtk_smi_larb_iommu *larb_mmu; 3120df4fabeSYong Wu unsigned int larbid, portid; 313a9bf2eecSJoerg Roedel struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 31458f0d1d5SRobin Murphy int i; 3150df4fabeSYong Wu 31658f0d1d5SRobin Murphy for (i = 0; i < fwspec->num_ids; ++i) { 31758f0d1d5SRobin Murphy larbid = MTK_M4U_TO_LARB(fwspec->ids[i]); 31858f0d1d5SRobin Murphy portid = MTK_M4U_TO_PORT(fwspec->ids[i]); 3191ee9feb2SYong Wu larb_mmu = &data->larb_imu[larbid]; 3200df4fabeSYong Wu 3210df4fabeSYong Wu dev_dbg(dev, "%s iommu port: %d\n", 3220df4fabeSYong Wu enable ? "enable" : "disable", portid); 3230df4fabeSYong Wu 3240df4fabeSYong Wu if (enable) 3250df4fabeSYong Wu larb_mmu->mmu |= MTK_SMI_MMU_EN(portid); 3260df4fabeSYong Wu else 3270df4fabeSYong Wu larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid); 3280df4fabeSYong Wu } 3290df4fabeSYong Wu } 3300df4fabeSYong Wu 3314b00f5acSYong Wu static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom) 3320df4fabeSYong Wu { 3334b00f5acSYong Wu struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); 3340df4fabeSYong Wu 3350df4fabeSYong Wu dom->cfg = (struct io_pgtable_cfg) { 3360df4fabeSYong Wu .quirks = IO_PGTABLE_QUIRK_ARM_NS | 3370df4fabeSYong Wu IO_PGTABLE_QUIRK_NO_PERMS | 338b4dad40eSYong Wu IO_PGTABLE_QUIRK_ARM_MTK_EXT, 3390df4fabeSYong Wu .pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap, 3402f317da4SYong Wu .ias = MTK_IOMMU_HAS_FLAG(data->plat_data, IOVA_34_EN) ? 34 : 32, 3410df4fabeSYong Wu .iommu_dev = data->dev, 3420df4fabeSYong Wu }; 3430df4fabeSYong Wu 3449bdfe4c1SYong Wu if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) 3459bdfe4c1SYong Wu dom->cfg.oas = data->enable_4GB ? 33 : 32; 3469bdfe4c1SYong Wu else 3479bdfe4c1SYong Wu dom->cfg.oas = 35; 3489bdfe4c1SYong Wu 3490df4fabeSYong Wu dom->iop = alloc_io_pgtable_ops(ARM_V7S, &dom->cfg, data); 3500df4fabeSYong Wu if (!dom->iop) { 3510df4fabeSYong Wu dev_err(data->dev, "Failed to alloc io pgtable\n"); 3520df4fabeSYong Wu return -EINVAL; 3530df4fabeSYong Wu } 3540df4fabeSYong Wu 355*08500c43SYong Wu dom->data = data; 3560df4fabeSYong Wu /* Update our support page sizes bitmap */ 357d16e0faaSRobin Murphy dom->domain.pgsize_bitmap = dom->cfg.pgsize_bitmap; 3580df4fabeSYong Wu return 0; 3590df4fabeSYong Wu } 3600df4fabeSYong Wu 3610df4fabeSYong Wu static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type) 3620df4fabeSYong Wu { 3630df4fabeSYong Wu struct mtk_iommu_domain *dom; 3640df4fabeSYong Wu 3650df4fabeSYong Wu if (type != IOMMU_DOMAIN_DMA) 3660df4fabeSYong Wu return NULL; 3670df4fabeSYong Wu 3680df4fabeSYong Wu dom = kzalloc(sizeof(*dom), GFP_KERNEL); 3690df4fabeSYong Wu if (!dom) 3700df4fabeSYong Wu return NULL; 3710df4fabeSYong Wu 3724b00f5acSYong Wu if (iommu_get_dma_cookie(&dom->domain)) 3734b00f5acSYong Wu goto free_dom; 3744b00f5acSYong Wu 3754b00f5acSYong Wu if (mtk_iommu_domain_finalise(dom)) 3764b00f5acSYong Wu goto put_dma_cookie; 3770df4fabeSYong Wu 3780df4fabeSYong Wu dom->domain.geometry.aperture_start = 0; 3790df4fabeSYong Wu dom->domain.geometry.aperture_end = DMA_BIT_MASK(32); 3800df4fabeSYong Wu dom->domain.geometry.force_aperture = true; 3810df4fabeSYong Wu 3820df4fabeSYong Wu return &dom->domain; 3834b00f5acSYong Wu 3844b00f5acSYong Wu put_dma_cookie: 3854b00f5acSYong Wu iommu_put_dma_cookie(&dom->domain); 3864b00f5acSYong Wu free_dom: 3874b00f5acSYong Wu kfree(dom); 3884b00f5acSYong Wu return NULL; 3890df4fabeSYong Wu } 3900df4fabeSYong Wu 3910df4fabeSYong Wu static void mtk_iommu_domain_free(struct iommu_domain *domain) 3920df4fabeSYong Wu { 3934b00f5acSYong Wu struct mtk_iommu_domain *dom = to_mtk_domain(domain); 3944b00f5acSYong Wu 3954b00f5acSYong Wu free_io_pgtable_ops(dom->iop); 3960df4fabeSYong Wu iommu_put_dma_cookie(domain); 3970df4fabeSYong Wu kfree(to_mtk_domain(domain)); 3980df4fabeSYong Wu } 3990df4fabeSYong Wu 4000df4fabeSYong Wu static int mtk_iommu_attach_device(struct iommu_domain *domain, 4010df4fabeSYong Wu struct device *dev) 4020df4fabeSYong Wu { 4033524b559SJoerg Roedel struct mtk_iommu_data *data = dev_iommu_priv_get(dev); 4040df4fabeSYong Wu struct mtk_iommu_domain *dom = to_mtk_domain(domain); 405c0b57581SYong Wu struct device *m4udev = data->dev; 4067f37a91dSYong Wu int ret; 4070df4fabeSYong Wu 4084b00f5acSYong Wu if (!data) 4090df4fabeSYong Wu return -ENODEV; 4100df4fabeSYong Wu 4117f37a91dSYong Wu if (!data->m4u_dom) { /* Initialize the M4U HW */ 412c0b57581SYong Wu ret = pm_runtime_resume_and_get(m4udev); 413c0b57581SYong Wu if (ret < 0) 4147f37a91dSYong Wu return ret; 415c0b57581SYong Wu 416c0b57581SYong Wu ret = mtk_iommu_hw_init(data); 417c0b57581SYong Wu if (ret) { 418c0b57581SYong Wu pm_runtime_put(m4udev); 419c0b57581SYong Wu return ret; 420c0b57581SYong Wu } 4210df4fabeSYong Wu data->m4u_dom = dom; 422d1e5f26fSRobin Murphy writel(dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, 4234b00f5acSYong Wu data->base + REG_MMU_PT_BASE_ADDR); 424c0b57581SYong Wu 425c0b57581SYong Wu pm_runtime_put(m4udev); 4260df4fabeSYong Wu } 4270df4fabeSYong Wu 4284b00f5acSYong Wu mtk_iommu_config(data, dev, true); 4290df4fabeSYong Wu return 0; 4300df4fabeSYong Wu } 4310df4fabeSYong Wu 4320df4fabeSYong Wu static void mtk_iommu_detach_device(struct iommu_domain *domain, 4330df4fabeSYong Wu struct device *dev) 4340df4fabeSYong Wu { 4353524b559SJoerg Roedel struct mtk_iommu_data *data = dev_iommu_priv_get(dev); 4360df4fabeSYong Wu 43758f0d1d5SRobin Murphy if (!data) 4380df4fabeSYong Wu return; 4390df4fabeSYong Wu 4400df4fabeSYong Wu mtk_iommu_config(data, dev, false); 4410df4fabeSYong Wu } 4420df4fabeSYong Wu 4430df4fabeSYong Wu static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova, 444781ca2deSTom Murphy phys_addr_t paddr, size_t size, int prot, gfp_t gfp) 4450df4fabeSYong Wu { 4460df4fabeSYong Wu struct mtk_iommu_domain *dom = to_mtk_domain(domain); 4470df4fabeSYong Wu 448b4dad40eSYong Wu /* The "4GB mode" M4U physically can not use the lower remap of Dram. */ 449*08500c43SYong Wu if (dom->data->enable_4GB) 450b4dad40eSYong Wu paddr |= BIT_ULL(32); 451b4dad40eSYong Wu 45260829b4dSYong Wu /* Synchronize with the tlb_lock */ 453f34ce7a7SBaolin Wang return dom->iop->map(dom->iop, iova, paddr, size, prot, gfp); 4540df4fabeSYong Wu } 4550df4fabeSYong Wu 4560df4fabeSYong Wu static size_t mtk_iommu_unmap(struct iommu_domain *domain, 45756f8af5eSWill Deacon unsigned long iova, size_t size, 45856f8af5eSWill Deacon struct iommu_iotlb_gather *gather) 4590df4fabeSYong Wu { 4600df4fabeSYong Wu struct mtk_iommu_domain *dom = to_mtk_domain(domain); 461f21ae3b1SYong Wu unsigned long end = iova + size - 1; 4620df4fabeSYong Wu 463f21ae3b1SYong Wu if (gather->start > iova) 464f21ae3b1SYong Wu gather->start = iova; 465f21ae3b1SYong Wu if (gather->end < end) 466f21ae3b1SYong Wu gather->end = end; 46760829b4dSYong Wu return dom->iop->unmap(dom->iop, iova, size, gather); 4680df4fabeSYong Wu } 4690df4fabeSYong Wu 47056f8af5eSWill Deacon static void mtk_iommu_flush_iotlb_all(struct iommu_domain *domain) 47156f8af5eSWill Deacon { 472*08500c43SYong Wu struct mtk_iommu_domain *dom = to_mtk_domain(domain); 473*08500c43SYong Wu 474*08500c43SYong Wu mtk_iommu_tlb_flush_all(dom->data); 47556f8af5eSWill Deacon } 47656f8af5eSWill Deacon 47756f8af5eSWill Deacon static void mtk_iommu_iotlb_sync(struct iommu_domain *domain, 47856f8af5eSWill Deacon struct iommu_iotlb_gather *gather) 4794d689b61SRobin Murphy { 480*08500c43SYong Wu struct mtk_iommu_domain *dom = to_mtk_domain(domain); 481862c3715SYong Wu size_t length = gather->end - gather->start + 1; 482da3cc91bSYong Wu 4831f4fd624SYong Wu mtk_iommu_tlb_flush_range_sync(gather->start, length, gather->pgsize, 484*08500c43SYong Wu dom->data); 4854d689b61SRobin Murphy } 4864d689b61SRobin Murphy 48720143451SYong Wu static void mtk_iommu_sync_map(struct iommu_domain *domain, unsigned long iova, 48820143451SYong Wu size_t size) 48920143451SYong Wu { 490*08500c43SYong Wu struct mtk_iommu_domain *dom = to_mtk_domain(domain); 49120143451SYong Wu 492*08500c43SYong Wu mtk_iommu_tlb_flush_range_sync(iova, size, size, dom->data); 49320143451SYong Wu } 49420143451SYong Wu 4950df4fabeSYong Wu static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain, 4960df4fabeSYong Wu dma_addr_t iova) 4970df4fabeSYong Wu { 4980df4fabeSYong Wu struct mtk_iommu_domain *dom = to_mtk_domain(domain); 4990df4fabeSYong Wu phys_addr_t pa; 5000df4fabeSYong Wu 5010df4fabeSYong Wu pa = dom->iop->iova_to_phys(dom->iop, iova); 502*08500c43SYong Wu if (dom->data->enable_4GB && pa >= MTK_IOMMU_4GB_MODE_REMAP_BASE) 503b4dad40eSYong Wu pa &= ~BIT_ULL(32); 50430e2fccfSYong Wu 5050df4fabeSYong Wu return pa; 5060df4fabeSYong Wu } 5070df4fabeSYong Wu 50880e4592aSJoerg Roedel static struct iommu_device *mtk_iommu_probe_device(struct device *dev) 5090df4fabeSYong Wu { 510a9bf2eecSJoerg Roedel struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 511b16c0170SJoerg Roedel struct mtk_iommu_data *data; 5120df4fabeSYong Wu 513a9bf2eecSJoerg Roedel if (!fwspec || fwspec->ops != &mtk_iommu_ops) 51480e4592aSJoerg Roedel return ERR_PTR(-ENODEV); /* Not a iommu client device */ 5150df4fabeSYong Wu 5163524b559SJoerg Roedel data = dev_iommu_priv_get(dev); 517b16c0170SJoerg Roedel 51880e4592aSJoerg Roedel return &data->iommu; 5190df4fabeSYong Wu } 5200df4fabeSYong Wu 52180e4592aSJoerg Roedel static void mtk_iommu_release_device(struct device *dev) 5220df4fabeSYong Wu { 523a9bf2eecSJoerg Roedel struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 524b16c0170SJoerg Roedel 525a9bf2eecSJoerg Roedel if (!fwspec || fwspec->ops != &mtk_iommu_ops) 5260df4fabeSYong Wu return; 5270df4fabeSYong Wu 52858f0d1d5SRobin Murphy iommu_fwspec_free(dev); 5290df4fabeSYong Wu } 5300df4fabeSYong Wu 5310df4fabeSYong Wu static struct iommu_group *mtk_iommu_device_group(struct device *dev) 5320df4fabeSYong Wu { 5337c3a2ec0SYong Wu struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); 5340df4fabeSYong Wu 53558f0d1d5SRobin Murphy if (!data) 5360df4fabeSYong Wu return ERR_PTR(-ENODEV); 5370df4fabeSYong Wu 5380df4fabeSYong Wu /* All the client devices are in the same m4u iommu-group */ 5390df4fabeSYong Wu if (!data->m4u_group) { 5400df4fabeSYong Wu data->m4u_group = iommu_group_alloc(); 5410df4fabeSYong Wu if (IS_ERR(data->m4u_group)) 5420df4fabeSYong Wu dev_err(dev, "Failed to allocate M4U IOMMU group\n"); 5433a8d40b6SRobin Murphy } else { 5443a8d40b6SRobin Murphy iommu_group_ref_get(data->m4u_group); 5450df4fabeSYong Wu } 5460df4fabeSYong Wu return data->m4u_group; 5470df4fabeSYong Wu } 5480df4fabeSYong Wu 5490df4fabeSYong Wu static int mtk_iommu_of_xlate(struct device *dev, struct of_phandle_args *args) 5500df4fabeSYong Wu { 5510df4fabeSYong Wu struct platform_device *m4updev; 5520df4fabeSYong Wu 5530df4fabeSYong Wu if (args->args_count != 1) { 5540df4fabeSYong Wu dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n", 5550df4fabeSYong Wu args->args_count); 5560df4fabeSYong Wu return -EINVAL; 5570df4fabeSYong Wu } 5580df4fabeSYong Wu 5593524b559SJoerg Roedel if (!dev_iommu_priv_get(dev)) { 5600df4fabeSYong Wu /* Get the m4u device */ 5610df4fabeSYong Wu m4updev = of_find_device_by_node(args->np); 5620df4fabeSYong Wu if (WARN_ON(!m4updev)) 5630df4fabeSYong Wu return -EINVAL; 5640df4fabeSYong Wu 5653524b559SJoerg Roedel dev_iommu_priv_set(dev, platform_get_drvdata(m4updev)); 5660df4fabeSYong Wu } 5670df4fabeSYong Wu 56858f0d1d5SRobin Murphy return iommu_fwspec_add_ids(dev, args->args, 1); 5690df4fabeSYong Wu } 5700df4fabeSYong Wu 571b65f5016SArvind Yadav static const struct iommu_ops mtk_iommu_ops = { 5720df4fabeSYong Wu .domain_alloc = mtk_iommu_domain_alloc, 5730df4fabeSYong Wu .domain_free = mtk_iommu_domain_free, 5740df4fabeSYong Wu .attach_dev = mtk_iommu_attach_device, 5750df4fabeSYong Wu .detach_dev = mtk_iommu_detach_device, 5760df4fabeSYong Wu .map = mtk_iommu_map, 5770df4fabeSYong Wu .unmap = mtk_iommu_unmap, 57856f8af5eSWill Deacon .flush_iotlb_all = mtk_iommu_flush_iotlb_all, 5794d689b61SRobin Murphy .iotlb_sync = mtk_iommu_iotlb_sync, 58020143451SYong Wu .iotlb_sync_map = mtk_iommu_sync_map, 5810df4fabeSYong Wu .iova_to_phys = mtk_iommu_iova_to_phys, 58280e4592aSJoerg Roedel .probe_device = mtk_iommu_probe_device, 58380e4592aSJoerg Roedel .release_device = mtk_iommu_release_device, 5840df4fabeSYong Wu .device_group = mtk_iommu_device_group, 5850df4fabeSYong Wu .of_xlate = mtk_iommu_of_xlate, 5860df4fabeSYong Wu .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M, 5870df4fabeSYong Wu }; 5880df4fabeSYong Wu 5890df4fabeSYong Wu static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) 5900df4fabeSYong Wu { 5910df4fabeSYong Wu u32 regval; 5920df4fabeSYong Wu int ret; 5930df4fabeSYong Wu 5940df4fabeSYong Wu ret = clk_prepare_enable(data->bclk); 5950df4fabeSYong Wu if (ret) { 5960df4fabeSYong Wu dev_err(data->dev, "Failed to enable iommu bclk(%d)\n", ret); 5970df4fabeSYong Wu return ret; 5980df4fabeSYong Wu } 5990df4fabeSYong Wu 60086444413SChao Hao if (data->plat_data->m4u_plat == M4U_MT8173) { 601acb3c92aSYong Wu regval = F_MMU_PREFETCH_RT_REPLACE_MOD | 602acb3c92aSYong Wu F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173; 60386444413SChao Hao } else { 60486444413SChao Hao regval = readl_relaxed(data->base + REG_MMU_CTRL_REG); 60586444413SChao Hao regval |= F_MMU_TF_PROT_TO_PROGRAM_ADDR; 60686444413SChao Hao } 6070df4fabeSYong Wu writel_relaxed(regval, data->base + REG_MMU_CTRL_REG); 6080df4fabeSYong Wu 6090df4fabeSYong Wu regval = F_L2_MULIT_HIT_EN | 6100df4fabeSYong Wu F_TABLE_WALK_FAULT_INT_EN | 6110df4fabeSYong Wu F_PREETCH_FIFO_OVERFLOW_INT_EN | 6120df4fabeSYong Wu F_MISS_FIFO_OVERFLOW_INT_EN | 6130df4fabeSYong Wu F_PREFETCH_FIFO_ERR_INT_EN | 6140df4fabeSYong Wu F_MISS_FIFO_ERR_INT_EN; 6150df4fabeSYong Wu writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0); 6160df4fabeSYong Wu 6170df4fabeSYong Wu regval = F_INT_TRANSLATION_FAULT | 6180df4fabeSYong Wu F_INT_MAIN_MULTI_HIT_FAULT | 6190df4fabeSYong Wu F_INT_INVALID_PA_FAULT | 6200df4fabeSYong Wu F_INT_ENTRY_REPLACEMENT_FAULT | 6210df4fabeSYong Wu F_INT_TLB_MISS_FAULT | 6220df4fabeSYong Wu F_INT_MISS_TRANSACTION_FIFO_FAULT | 6230df4fabeSYong Wu F_INT_PRETETCH_TRANSATION_FIFO_FAULT; 6240df4fabeSYong Wu writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL); 6250df4fabeSYong Wu 626d1b5ef00SFabien Parent if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_LEGACY_IVRP_PADDR)) 62770ca608bSYong Wu regval = (data->protect_base >> 1) | (data->enable_4GB << 31); 62870ca608bSYong Wu else 62970ca608bSYong Wu regval = lower_32_bits(data->protect_base) | 63070ca608bSYong Wu upper_32_bits(data->protect_base); 63170ca608bSYong Wu writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR); 63270ca608bSYong Wu 6336b717796SChao Hao if (data->enable_4GB && 6346b717796SChao Hao MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_VLD_PA_RNG)) { 63530e2fccfSYong Wu /* 63630e2fccfSYong Wu * If 4GB mode is enabled, the validate PA range is from 63730e2fccfSYong Wu * 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30]. 63830e2fccfSYong Wu */ 63930e2fccfSYong Wu regval = F_MMU_VLD_PA_RNG(7, 4); 64030e2fccfSYong Wu writel_relaxed(regval, data->base + REG_MMU_VLD_PA_RNG); 64130e2fccfSYong Wu } 6420df4fabeSYong Wu writel_relaxed(0, data->base + REG_MMU_DCM_DIS); 64335c1b48dSChao Hao if (MTK_IOMMU_HAS_FLAG(data->plat_data, WR_THROT_EN)) { 64435c1b48dSChao Hao /* write command throttling mode */ 64535c1b48dSChao Hao regval = readl_relaxed(data->base + REG_MMU_WR_LEN_CTRL); 64635c1b48dSChao Hao regval &= ~F_MMU_WR_THROT_DIS_MASK; 64735c1b48dSChao Hao writel_relaxed(regval, data->base + REG_MMU_WR_LEN_CTRL); 64835c1b48dSChao Hao } 649e6dec923SYong Wu 6506b717796SChao Hao if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) { 65175eed350SChao Hao /* The register is called STANDARD_AXI_MODE in this case */ 6524bb2bf4cSChao Hao regval = 0; 6534bb2bf4cSChao Hao } else { 6544bb2bf4cSChao Hao regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL); 6554bb2bf4cSChao Hao regval &= ~F_MMU_STANDARD_AXI_MODE_MASK; 6564bb2bf4cSChao Hao if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_WR_EN)) 6574bb2bf4cSChao Hao regval &= ~F_MMU_IN_ORDER_WR_EN_MASK; 65875eed350SChao Hao } 6594bb2bf4cSChao Hao writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL); 6600df4fabeSYong Wu 6610df4fabeSYong Wu if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0, 6620df4fabeSYong Wu dev_name(data->dev), (void *)data)) { 6630df4fabeSYong Wu writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR); 6640df4fabeSYong Wu clk_disable_unprepare(data->bclk); 6650df4fabeSYong Wu dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq); 6660df4fabeSYong Wu return -ENODEV; 6670df4fabeSYong Wu } 6680df4fabeSYong Wu 6690df4fabeSYong Wu return 0; 6700df4fabeSYong Wu } 6710df4fabeSYong Wu 6720df4fabeSYong Wu static const struct component_master_ops mtk_iommu_com_ops = { 6730df4fabeSYong Wu .bind = mtk_iommu_bind, 6740df4fabeSYong Wu .unbind = mtk_iommu_unbind, 6750df4fabeSYong Wu }; 6760df4fabeSYong Wu 6770df4fabeSYong Wu static int mtk_iommu_probe(struct platform_device *pdev) 6780df4fabeSYong Wu { 6790df4fabeSYong Wu struct mtk_iommu_data *data; 6800df4fabeSYong Wu struct device *dev = &pdev->dev; 681baf94e6eSYong Wu struct device_node *larbnode, *smicomm_node; 682baf94e6eSYong Wu struct platform_device *plarbdev; 683baf94e6eSYong Wu struct device_link *link; 6840df4fabeSYong Wu struct resource *res; 685b16c0170SJoerg Roedel resource_size_t ioaddr; 6860df4fabeSYong Wu struct component_match *match = NULL; 687c2c59456SMiles Chen struct regmap *infracfg; 6880df4fabeSYong Wu void *protect; 6890b6c0ad3SAndrzej Hajda int i, larb_nr, ret; 690c2c59456SMiles Chen u32 val; 691c2c59456SMiles Chen char *p; 6920df4fabeSYong Wu 6930df4fabeSYong Wu data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 6940df4fabeSYong Wu if (!data) 6950df4fabeSYong Wu return -ENOMEM; 6960df4fabeSYong Wu data->dev = dev; 697cecdce9dSYong Wu data->plat_data = of_device_get_match_data(dev); 6980df4fabeSYong Wu 6990df4fabeSYong Wu /* Protect memory. HW will access here while translation fault.*/ 7000df4fabeSYong Wu protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2, GFP_KERNEL); 7010df4fabeSYong Wu if (!protect) 7020df4fabeSYong Wu return -ENOMEM; 7030df4fabeSYong Wu data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN); 7040df4fabeSYong Wu 705c2c59456SMiles Chen if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) { 706c2c59456SMiles Chen switch (data->plat_data->m4u_plat) { 707c2c59456SMiles Chen case M4U_MT2712: 708c2c59456SMiles Chen p = "mediatek,mt2712-infracfg"; 709c2c59456SMiles Chen break; 710c2c59456SMiles Chen case M4U_MT8173: 711c2c59456SMiles Chen p = "mediatek,mt8173-infracfg"; 712c2c59456SMiles Chen break; 713c2c59456SMiles Chen default: 714c2c59456SMiles Chen p = NULL; 715c2c59456SMiles Chen } 716c2c59456SMiles Chen 717c2c59456SMiles Chen infracfg = syscon_regmap_lookup_by_compatible(p); 718c2c59456SMiles Chen 719c2c59456SMiles Chen if (IS_ERR(infracfg)) 720c2c59456SMiles Chen return PTR_ERR(infracfg); 721c2c59456SMiles Chen 722c2c59456SMiles Chen ret = regmap_read(infracfg, REG_INFRA_MISC, &val); 723c2c59456SMiles Chen if (ret) 724c2c59456SMiles Chen return ret; 725c2c59456SMiles Chen data->enable_4GB = !!(val & F_DDR_4GB_SUPPORT_EN); 726c2c59456SMiles Chen } 72701e23c93SYong Wu 7280df4fabeSYong Wu res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 7290df4fabeSYong Wu data->base = devm_ioremap_resource(dev, res); 7300df4fabeSYong Wu if (IS_ERR(data->base)) 7310df4fabeSYong Wu return PTR_ERR(data->base); 732b16c0170SJoerg Roedel ioaddr = res->start; 7330df4fabeSYong Wu 7340df4fabeSYong Wu data->irq = platform_get_irq(pdev, 0); 7350df4fabeSYong Wu if (data->irq < 0) 7360df4fabeSYong Wu return data->irq; 7370df4fabeSYong Wu 7386b717796SChao Hao if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_BCLK)) { 7390df4fabeSYong Wu data->bclk = devm_clk_get(dev, "bclk"); 7400df4fabeSYong Wu if (IS_ERR(data->bclk)) 7410df4fabeSYong Wu return PTR_ERR(data->bclk); 7422aa4c259SYong Wu } 7430df4fabeSYong Wu 7440df4fabeSYong Wu larb_nr = of_count_phandle_with_args(dev->of_node, 7450df4fabeSYong Wu "mediatek,larbs", NULL); 7460df4fabeSYong Wu if (larb_nr < 0) 7470df4fabeSYong Wu return larb_nr; 7480df4fabeSYong Wu 7490df4fabeSYong Wu for (i = 0; i < larb_nr; i++) { 750e6dec923SYong Wu u32 id; 7510df4fabeSYong Wu 7520df4fabeSYong Wu larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i); 7530df4fabeSYong Wu if (!larbnode) 7540df4fabeSYong Wu return -EINVAL; 7550df4fabeSYong Wu 7561eb8e4e2SWen Yang if (!of_device_is_available(larbnode)) { 7571eb8e4e2SWen Yang of_node_put(larbnode); 7580df4fabeSYong Wu continue; 7591eb8e4e2SWen Yang } 7600df4fabeSYong Wu 761e6dec923SYong Wu ret = of_property_read_u32(larbnode, "mediatek,larb-id", &id); 762e6dec923SYong Wu if (ret)/* The id is consecutive if there is no this property */ 763e6dec923SYong Wu id = i; 764e6dec923SYong Wu 7650df4fabeSYong Wu plarbdev = of_find_device_by_node(larbnode); 7661eb8e4e2SWen Yang if (!plarbdev) { 7671eb8e4e2SWen Yang of_node_put(larbnode); 7680df4fabeSYong Wu return -EPROBE_DEFER; 7691eb8e4e2SWen Yang } 7701ee9feb2SYong Wu data->larb_imu[id].dev = &plarbdev->dev; 7710df4fabeSYong Wu 77200c7c81fSRussell King component_match_add_release(dev, &match, release_of, 77300c7c81fSRussell King compare_of, larbnode); 7740df4fabeSYong Wu } 7750df4fabeSYong Wu 776baf94e6eSYong Wu /* Get smi-common dev from the last larb. */ 777baf94e6eSYong Wu smicomm_node = of_parse_phandle(larbnode, "mediatek,smi", 0); 778baf94e6eSYong Wu if (!smicomm_node) 779baf94e6eSYong Wu return -EINVAL; 780baf94e6eSYong Wu 781baf94e6eSYong Wu plarbdev = of_find_device_by_node(smicomm_node); 782baf94e6eSYong Wu of_node_put(smicomm_node); 783baf94e6eSYong Wu data->smicomm_dev = &plarbdev->dev; 784baf94e6eSYong Wu 785c0b57581SYong Wu pm_runtime_enable(dev); 786c0b57581SYong Wu 787baf94e6eSYong Wu link = device_link_add(data->smicomm_dev, dev, 788baf94e6eSYong Wu DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME); 789baf94e6eSYong Wu if (!link) { 790baf94e6eSYong Wu dev_err(dev, "Unable link %s.\n", dev_name(data->smicomm_dev)); 791c0b57581SYong Wu goto out_runtime_disable; 792baf94e6eSYong Wu } 793baf94e6eSYong Wu 7940df4fabeSYong Wu platform_set_drvdata(pdev, data); 7950df4fabeSYong Wu 796b16c0170SJoerg Roedel ret = iommu_device_sysfs_add(&data->iommu, dev, NULL, 797b16c0170SJoerg Roedel "mtk-iommu.%pa", &ioaddr); 798b16c0170SJoerg Roedel if (ret) 799baf94e6eSYong Wu goto out_link_remove; 800b16c0170SJoerg Roedel 801b16c0170SJoerg Roedel iommu_device_set_ops(&data->iommu, &mtk_iommu_ops); 802b16c0170SJoerg Roedel iommu_device_set_fwnode(&data->iommu, &pdev->dev.of_node->fwnode); 803b16c0170SJoerg Roedel 804b16c0170SJoerg Roedel ret = iommu_device_register(&data->iommu); 805b16c0170SJoerg Roedel if (ret) 806986d9ec5SYong Wu goto out_sysfs_remove; 807b16c0170SJoerg Roedel 808da3cc91bSYong Wu spin_lock_init(&data->tlb_lock); 8097c3a2ec0SYong Wu list_add_tail(&data->list, &m4ulist); 8107c3a2ec0SYong Wu 811986d9ec5SYong Wu if (!iommu_present(&platform_bus_type)) { 812986d9ec5SYong Wu ret = bus_set_iommu(&platform_bus_type, &mtk_iommu_ops); 813986d9ec5SYong Wu if (ret) 814986d9ec5SYong Wu goto out_list_del; 815986d9ec5SYong Wu } 8160df4fabeSYong Wu 817986d9ec5SYong Wu ret = component_master_add_with_match(dev, &mtk_iommu_com_ops, match); 818986d9ec5SYong Wu if (ret) 819986d9ec5SYong Wu goto out_bus_set_null; 820986d9ec5SYong Wu return ret; 821986d9ec5SYong Wu 822986d9ec5SYong Wu out_bus_set_null: 823986d9ec5SYong Wu bus_set_iommu(&platform_bus_type, NULL); 824986d9ec5SYong Wu out_list_del: 825986d9ec5SYong Wu list_del(&data->list); 826986d9ec5SYong Wu iommu_device_unregister(&data->iommu); 827986d9ec5SYong Wu out_sysfs_remove: 828986d9ec5SYong Wu iommu_device_sysfs_remove(&data->iommu); 829baf94e6eSYong Wu out_link_remove: 830baf94e6eSYong Wu device_link_remove(data->smicomm_dev, dev); 831c0b57581SYong Wu out_runtime_disable: 832c0b57581SYong Wu pm_runtime_disable(dev); 833986d9ec5SYong Wu return ret; 8340df4fabeSYong Wu } 8350df4fabeSYong Wu 8360df4fabeSYong Wu static int mtk_iommu_remove(struct platform_device *pdev) 8370df4fabeSYong Wu { 8380df4fabeSYong Wu struct mtk_iommu_data *data = platform_get_drvdata(pdev); 8390df4fabeSYong Wu 840b16c0170SJoerg Roedel iommu_device_sysfs_remove(&data->iommu); 841b16c0170SJoerg Roedel iommu_device_unregister(&data->iommu); 842b16c0170SJoerg Roedel 8430df4fabeSYong Wu if (iommu_present(&platform_bus_type)) 8440df4fabeSYong Wu bus_set_iommu(&platform_bus_type, NULL); 8450df4fabeSYong Wu 8460df4fabeSYong Wu clk_disable_unprepare(data->bclk); 847baf94e6eSYong Wu device_link_remove(data->smicomm_dev, &pdev->dev); 848c0b57581SYong Wu pm_runtime_disable(&pdev->dev); 8490df4fabeSYong Wu devm_free_irq(&pdev->dev, data->irq, data); 8500df4fabeSYong Wu component_master_del(&pdev->dev, &mtk_iommu_com_ops); 8510df4fabeSYong Wu return 0; 8520df4fabeSYong Wu } 8530df4fabeSYong Wu 85434665c79SYong Wu static int __maybe_unused mtk_iommu_runtime_suspend(struct device *dev) 8550df4fabeSYong Wu { 8560df4fabeSYong Wu struct mtk_iommu_data *data = dev_get_drvdata(dev); 8570df4fabeSYong Wu struct mtk_iommu_suspend_reg *reg = &data->reg; 8580df4fabeSYong Wu void __iomem *base = data->base; 8590df4fabeSYong Wu 86035c1b48dSChao Hao reg->wr_len_ctrl = readl_relaxed(base + REG_MMU_WR_LEN_CTRL); 86175eed350SChao Hao reg->misc_ctrl = readl_relaxed(base + REG_MMU_MISC_CTRL); 8620df4fabeSYong Wu reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS); 8630df4fabeSYong Wu reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG); 8640df4fabeSYong Wu reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL0); 8650df4fabeSYong Wu reg->int_main_control = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL); 86670ca608bSYong Wu reg->ivrp_paddr = readl_relaxed(base + REG_MMU_IVRP_PADDR); 867b9475b34SYong Wu reg->vld_pa_rng = readl_relaxed(base + REG_MMU_VLD_PA_RNG); 8686254b64fSYong Wu clk_disable_unprepare(data->bclk); 8690df4fabeSYong Wu return 0; 8700df4fabeSYong Wu } 8710df4fabeSYong Wu 87234665c79SYong Wu static int __maybe_unused mtk_iommu_runtime_resume(struct device *dev) 8730df4fabeSYong Wu { 8740df4fabeSYong Wu struct mtk_iommu_data *data = dev_get_drvdata(dev); 8750df4fabeSYong Wu struct mtk_iommu_suspend_reg *reg = &data->reg; 876907ba6a1SYong Wu struct mtk_iommu_domain *m4u_dom = data->m4u_dom; 8770df4fabeSYong Wu void __iomem *base = data->base; 8786254b64fSYong Wu int ret; 8790df4fabeSYong Wu 880c0b57581SYong Wu /* Avoid first resume to affect the default value of registers below. */ 881c0b57581SYong Wu if (!m4u_dom) 882c0b57581SYong Wu return 0; 8836254b64fSYong Wu ret = clk_prepare_enable(data->bclk); 8846254b64fSYong Wu if (ret) { 8856254b64fSYong Wu dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret); 8866254b64fSYong Wu return ret; 8876254b64fSYong Wu } 88835c1b48dSChao Hao writel_relaxed(reg->wr_len_ctrl, base + REG_MMU_WR_LEN_CTRL); 88975eed350SChao Hao writel_relaxed(reg->misc_ctrl, base + REG_MMU_MISC_CTRL); 8900df4fabeSYong Wu writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS); 8910df4fabeSYong Wu writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG); 8920df4fabeSYong Wu writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0); 8930df4fabeSYong Wu writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL); 89470ca608bSYong Wu writel_relaxed(reg->ivrp_paddr, base + REG_MMU_IVRP_PADDR); 895b9475b34SYong Wu writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG); 896c0b57581SYong Wu writel(m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, base + REG_MMU_PT_BASE_ADDR); 8970df4fabeSYong Wu return 0; 8980df4fabeSYong Wu } 8990df4fabeSYong Wu 900e6dec923SYong Wu static const struct dev_pm_ops mtk_iommu_pm_ops = { 90134665c79SYong Wu SET_RUNTIME_PM_OPS(mtk_iommu_runtime_suspend, mtk_iommu_runtime_resume, NULL) 90234665c79SYong Wu SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 90334665c79SYong Wu pm_runtime_force_resume) 9040df4fabeSYong Wu }; 9050df4fabeSYong Wu 906cecdce9dSYong Wu static const struct mtk_iommu_plat_data mt2712_data = { 907cecdce9dSYong Wu .m4u_plat = M4U_MT2712, 9086b717796SChao Hao .flags = HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG, 909b053bc71SChao Hao .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 91037276e00SChao Hao .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}}, 911cecdce9dSYong Wu }; 912cecdce9dSYong Wu 913068c86e9SChao Hao static const struct mtk_iommu_plat_data mt6779_data = { 914068c86e9SChao Hao .m4u_plat = M4U_MT6779, 915068c86e9SChao Hao .flags = HAS_SUB_COMM | OUT_ORDER_WR_EN | WR_THROT_EN, 916068c86e9SChao Hao .inv_sel_reg = REG_MMU_INV_SEL_GEN2, 917068c86e9SChao Hao .larbid_remap = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}}, 918cecdce9dSYong Wu }; 919cecdce9dSYong Wu 9203c213562SFabien Parent static const struct mtk_iommu_plat_data mt8167_data = { 9213c213562SFabien Parent .m4u_plat = M4U_MT8167, 9223c213562SFabien Parent .flags = RESET_AXI | HAS_LEGACY_IVRP_PADDR, 9233c213562SFabien Parent .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 9243c213562SFabien Parent .larbid_remap = {{0}, {1}, {2}}, /* Linear mapping. */ 9253c213562SFabien Parent }; 9263c213562SFabien Parent 927cecdce9dSYong Wu static const struct mtk_iommu_plat_data mt8173_data = { 928cecdce9dSYong Wu .m4u_plat = M4U_MT8173, 929d1b5ef00SFabien Parent .flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI | 930d1b5ef00SFabien Parent HAS_LEGACY_IVRP_PADDR, 931b053bc71SChao Hao .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 93237276e00SChao Hao .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */ 933cecdce9dSYong Wu }; 934cecdce9dSYong Wu 935907ba6a1SYong Wu static const struct mtk_iommu_plat_data mt8183_data = { 936907ba6a1SYong Wu .m4u_plat = M4U_MT8183, 9376b717796SChao Hao .flags = RESET_AXI, 938b053bc71SChao Hao .inv_sel_reg = REG_MMU_INV_SEL_GEN1, 93937276e00SChao Hao .larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}}, 940907ba6a1SYong Wu }; 941907ba6a1SYong Wu 9420df4fabeSYong Wu static const struct of_device_id mtk_iommu_of_ids[] = { 943cecdce9dSYong Wu { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data}, 944068c86e9SChao Hao { .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data}, 9453c213562SFabien Parent { .compatible = "mediatek,mt8167-m4u", .data = &mt8167_data}, 946cecdce9dSYong Wu { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data}, 947907ba6a1SYong Wu { .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data}, 9480df4fabeSYong Wu {} 9490df4fabeSYong Wu }; 9500df4fabeSYong Wu 9510df4fabeSYong Wu static struct platform_driver mtk_iommu_driver = { 9520df4fabeSYong Wu .probe = mtk_iommu_probe, 9530df4fabeSYong Wu .remove = mtk_iommu_remove, 9540df4fabeSYong Wu .driver = { 9550df4fabeSYong Wu .name = "mtk-iommu", 956f53dd978SKrzysztof Kozlowski .of_match_table = mtk_iommu_of_ids, 9570df4fabeSYong Wu .pm = &mtk_iommu_pm_ops, 9580df4fabeSYong Wu } 9590df4fabeSYong Wu }; 9600df4fabeSYong Wu 961e6dec923SYong Wu static int __init mtk_iommu_init(void) 9620df4fabeSYong Wu { 9630df4fabeSYong Wu int ret; 9640df4fabeSYong Wu 9650df4fabeSYong Wu ret = platform_driver_register(&mtk_iommu_driver); 966e6dec923SYong Wu if (ret != 0) 967e6dec923SYong Wu pr_err("Failed to register MTK IOMMU driver\n"); 968e6dec923SYong Wu 9690df4fabeSYong Wu return ret; 9700df4fabeSYong Wu } 9710df4fabeSYong Wu 972e6dec923SYong Wu subsys_initcall(mtk_iommu_init) 973