xref: /linux/drivers/iommu/iommu-priv.h (revision a1ff5a7d78a036d6c2178ee5acd6ba4946243800)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES.
3  */
4 #ifndef __LINUX_IOMMU_PRIV_H
5 #define __LINUX_IOMMU_PRIV_H
6 
7 #include <linux/iommu.h>
8 
dev_iommu_ops(struct device * dev)9 static inline const struct iommu_ops *dev_iommu_ops(struct device *dev)
10 {
11 	/*
12 	 * Assume that valid ops must be installed if iommu_probe_device()
13 	 * has succeeded. The device ops are essentially for internal use
14 	 * within the IOMMU subsystem itself, so we should be able to trust
15 	 * ourselves not to misuse the helper.
16 	 */
17 	return dev->iommu->iommu_dev->ops;
18 }
19 
20 const struct iommu_ops *iommu_ops_from_fwnode(const struct fwnode_handle *fwnode);
21 
iommu_fwspec_ops(struct iommu_fwspec * fwspec)22 static inline const struct iommu_ops *iommu_fwspec_ops(struct iommu_fwspec *fwspec)
23 {
24 	return iommu_ops_from_fwnode(fwspec ? fwspec->iommu_fwnode : NULL);
25 }
26 
27 int iommu_group_replace_domain(struct iommu_group *group,
28 			       struct iommu_domain *new_domain);
29 
30 int iommu_device_register_bus(struct iommu_device *iommu,
31 			      const struct iommu_ops *ops,
32 			      const struct bus_type *bus,
33 			      struct notifier_block *nb);
34 void iommu_device_unregister_bus(struct iommu_device *iommu,
35 				 const struct bus_type *bus,
36 				 struct notifier_block *nb);
37 
38 struct iommu_attach_handle *iommu_attach_handle_get(struct iommu_group *group,
39 						    ioasid_t pasid,
40 						    unsigned int type);
41 int iommu_attach_group_handle(struct iommu_domain *domain,
42 			      struct iommu_group *group,
43 			      struct iommu_attach_handle *handle);
44 void iommu_detach_group_handle(struct iommu_domain *domain,
45 			       struct iommu_group *group);
46 int iommu_replace_group_handle(struct iommu_group *group,
47 			       struct iommu_domain *new_domain,
48 			       struct iommu_attach_handle *handle);
49 #endif /* __LINUX_IOMMU_PRIV_H */
50