1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 * $Id: mthca_dev.h 1349 2004-12-16 21:09:43Z roland $ 33 */ 34 35 #ifndef MTHCA_DEV_H 36 #define MTHCA_DEV_H 37 38 #include <linux/spinlock.h> 39 #include <linux/kernel.h> 40 #include <linux/pci.h> 41 #include <linux/dma-mapping.h> 42 #include <asm/semaphore.h> 43 44 #include "mthca_provider.h" 45 #include "mthca_doorbell.h" 46 47 #define DRV_NAME "ib_mthca" 48 #define PFX DRV_NAME ": " 49 #define DRV_VERSION "0.06-pre" 50 #define DRV_RELDATE "November 8, 2004" 51 52 enum { 53 MTHCA_FLAG_DDR_HIDDEN = 1 << 1, 54 MTHCA_FLAG_SRQ = 1 << 2, 55 MTHCA_FLAG_MSI = 1 << 3, 56 MTHCA_FLAG_MSI_X = 1 << 4, 57 MTHCA_FLAG_NO_LAM = 1 << 5, 58 MTHCA_FLAG_FMR = 1 << 6, 59 MTHCA_FLAG_MEMFREE = 1 << 7, 60 MTHCA_FLAG_PCIE = 1 << 8 61 }; 62 63 enum { 64 MTHCA_MAX_PORTS = 2 65 }; 66 67 enum { 68 MTHCA_EQ_CONTEXT_SIZE = 0x40, 69 MTHCA_CQ_CONTEXT_SIZE = 0x40, 70 MTHCA_QP_CONTEXT_SIZE = 0x200, 71 MTHCA_RDB_ENTRY_SIZE = 0x20, 72 MTHCA_AV_SIZE = 0x20, 73 MTHCA_MGM_ENTRY_SIZE = 0x40, 74 75 /* Arbel FW gives us these, but we need them for Tavor */ 76 MTHCA_MPT_ENTRY_SIZE = 0x40, 77 MTHCA_MTT_SEG_SIZE = 0x40, 78 }; 79 80 enum { 81 MTHCA_EQ_CMD, 82 MTHCA_EQ_ASYNC, 83 MTHCA_EQ_COMP, 84 MTHCA_NUM_EQ 85 }; 86 87 enum { 88 MTHCA_OPCODE_NOP = 0x00, 89 MTHCA_OPCODE_RDMA_WRITE = 0x08, 90 MTHCA_OPCODE_RDMA_WRITE_IMM = 0x09, 91 MTHCA_OPCODE_SEND = 0x0a, 92 MTHCA_OPCODE_SEND_IMM = 0x0b, 93 MTHCA_OPCODE_RDMA_READ = 0x10, 94 MTHCA_OPCODE_ATOMIC_CS = 0x11, 95 MTHCA_OPCODE_ATOMIC_FA = 0x12, 96 MTHCA_OPCODE_BIND_MW = 0x18, 97 MTHCA_OPCODE_INVALID = 0xff 98 }; 99 100 struct mthca_cmd { 101 int use_events; 102 struct semaphore hcr_sem; 103 struct semaphore poll_sem; 104 struct semaphore event_sem; 105 int max_cmds; 106 spinlock_t context_lock; 107 int free_head; 108 struct mthca_cmd_context *context; 109 u16 token_mask; 110 }; 111 112 struct mthca_limits { 113 int num_ports; 114 int vl_cap; 115 int mtu_cap; 116 int gid_table_len; 117 int pkey_table_len; 118 int local_ca_ack_delay; 119 int num_uars; 120 int max_sg; 121 int num_qps; 122 int reserved_qps; 123 int num_srqs; 124 int reserved_srqs; 125 int num_eecs; 126 int reserved_eecs; 127 int num_cqs; 128 int reserved_cqs; 129 int num_eqs; 130 int reserved_eqs; 131 int num_mpts; 132 int num_mtt_segs; 133 int fmr_reserved_mtts; 134 int reserved_mtts; 135 int reserved_mrws; 136 int reserved_uars; 137 int num_mgms; 138 int num_amgms; 139 int reserved_mcgs; 140 int num_pds; 141 int reserved_pds; 142 }; 143 144 struct mthca_alloc { 145 u32 last; 146 u32 top; 147 u32 max; 148 u32 mask; 149 spinlock_t lock; 150 unsigned long *table; 151 }; 152 153 struct mthca_array { 154 struct { 155 void **page; 156 int used; 157 } *page_list; 158 }; 159 160 struct mthca_uar_table { 161 struct mthca_alloc alloc; 162 u64 uarc_base; 163 int uarc_size; 164 }; 165 166 struct mthca_pd_table { 167 struct mthca_alloc alloc; 168 }; 169 170 struct mthca_buddy { 171 unsigned long **bits; 172 int max_order; 173 spinlock_t lock; 174 }; 175 176 struct mthca_mr_table { 177 struct mthca_alloc mpt_alloc; 178 struct mthca_buddy mtt_buddy; 179 struct mthca_buddy *fmr_mtt_buddy; 180 u64 mtt_base; 181 u64 mpt_base; 182 struct mthca_icm_table *mtt_table; 183 struct mthca_icm_table *mpt_table; 184 struct { 185 void __iomem *mpt_base; 186 void __iomem *mtt_base; 187 struct mthca_buddy mtt_buddy; 188 } tavor_fmr; 189 }; 190 191 struct mthca_eq_table { 192 struct mthca_alloc alloc; 193 void __iomem *clr_int; 194 u32 clr_mask; 195 u32 arm_mask; 196 struct mthca_eq eq[MTHCA_NUM_EQ]; 197 u64 icm_virt; 198 struct page *icm_page; 199 dma_addr_t icm_dma; 200 int have_irq; 201 u8 inta_pin; 202 }; 203 204 struct mthca_cq_table { 205 struct mthca_alloc alloc; 206 spinlock_t lock; 207 struct mthca_array cq; 208 struct mthca_icm_table *table; 209 }; 210 211 struct mthca_qp_table { 212 struct mthca_alloc alloc; 213 u32 rdb_base; 214 int rdb_shift; 215 int sqp_start; 216 spinlock_t lock; 217 struct mthca_array qp; 218 struct mthca_icm_table *qp_table; 219 struct mthca_icm_table *eqp_table; 220 struct mthca_icm_table *rdb_table; 221 }; 222 223 struct mthca_av_table { 224 struct pci_pool *pool; 225 int num_ddr_avs; 226 u64 ddr_av_base; 227 void __iomem *av_map; 228 struct mthca_alloc alloc; 229 }; 230 231 struct mthca_mcg_table { 232 struct semaphore sem; 233 struct mthca_alloc alloc; 234 struct mthca_icm_table *table; 235 }; 236 237 struct mthca_dev { 238 struct ib_device ib_dev; 239 struct pci_dev *pdev; 240 241 int hca_type; 242 unsigned long mthca_flags; 243 unsigned long device_cap_flags; 244 245 u32 rev_id; 246 247 /* firmware info */ 248 u64 fw_ver; 249 union { 250 struct { 251 u64 fw_start; 252 u64 fw_end; 253 } tavor; 254 struct { 255 u64 clr_int_base; 256 u64 eq_arm_base; 257 u64 eq_set_ci_base; 258 struct mthca_icm *fw_icm; 259 struct mthca_icm *aux_icm; 260 u16 fw_pages; 261 } arbel; 262 } fw; 263 264 u64 ddr_start; 265 u64 ddr_end; 266 267 MTHCA_DECLARE_DOORBELL_LOCK(doorbell_lock) 268 struct semaphore cap_mask_mutex; 269 270 void __iomem *hcr; 271 void __iomem *kar; 272 void __iomem *clr_base; 273 union { 274 struct { 275 void __iomem *ecr_base; 276 } tavor; 277 struct { 278 void __iomem *eq_arm; 279 void __iomem *eq_set_ci_base; 280 } arbel; 281 } eq_regs; 282 283 struct mthca_cmd cmd; 284 struct mthca_limits limits; 285 286 struct mthca_uar_table uar_table; 287 struct mthca_pd_table pd_table; 288 struct mthca_mr_table mr_table; 289 struct mthca_eq_table eq_table; 290 struct mthca_cq_table cq_table; 291 struct mthca_qp_table qp_table; 292 struct mthca_av_table av_table; 293 struct mthca_mcg_table mcg_table; 294 295 struct mthca_uar driver_uar; 296 struct mthca_db_table *db_tab; 297 struct mthca_pd driver_pd; 298 struct mthca_mr driver_mr; 299 300 struct ib_mad_agent *send_agent[MTHCA_MAX_PORTS][2]; 301 struct ib_ah *sm_ah[MTHCA_MAX_PORTS]; 302 spinlock_t sm_lock; 303 }; 304 305 #define mthca_dbg(mdev, format, arg...) \ 306 dev_dbg(&mdev->pdev->dev, format, ## arg) 307 #define mthca_err(mdev, format, arg...) \ 308 dev_err(&mdev->pdev->dev, format, ## arg) 309 #define mthca_info(mdev, format, arg...) \ 310 dev_info(&mdev->pdev->dev, format, ## arg) 311 #define mthca_warn(mdev, format, arg...) \ 312 dev_warn(&mdev->pdev->dev, format, ## arg) 313 314 extern void __buggy_use_of_MTHCA_GET(void); 315 extern void __buggy_use_of_MTHCA_PUT(void); 316 317 #define MTHCA_GET(dest, source, offset) \ 318 do { \ 319 void *__p = (char *) (source) + (offset); \ 320 switch (sizeof (dest)) { \ 321 case 1: (dest) = *(u8 *) __p; break; \ 322 case 2: (dest) = be16_to_cpup(__p); break; \ 323 case 4: (dest) = be32_to_cpup(__p); break; \ 324 case 8: (dest) = be64_to_cpup(__p); break; \ 325 default: __buggy_use_of_MTHCA_GET(); \ 326 } \ 327 } while (0) 328 329 #define MTHCA_PUT(dest, source, offset) \ 330 do { \ 331 __typeof__(source) *__p = \ 332 (__typeof__(source) *) ((char *) (dest) + (offset)); \ 333 switch (sizeof(source)) { \ 334 case 1: *__p = (source); break; \ 335 case 2: *__p = cpu_to_be16(source); break; \ 336 case 4: *__p = cpu_to_be32(source); break; \ 337 case 8: *__p = cpu_to_be64(source); break; \ 338 default: __buggy_use_of_MTHCA_PUT(); \ 339 } \ 340 } while (0) 341 342 int mthca_reset(struct mthca_dev *mdev); 343 344 u32 mthca_alloc(struct mthca_alloc *alloc); 345 void mthca_free(struct mthca_alloc *alloc, u32 obj); 346 int mthca_alloc_init(struct mthca_alloc *alloc, u32 num, u32 mask, 347 u32 reserved); 348 void mthca_alloc_cleanup(struct mthca_alloc *alloc); 349 void *mthca_array_get(struct mthca_array *array, int index); 350 int mthca_array_set(struct mthca_array *array, int index, void *value); 351 void mthca_array_clear(struct mthca_array *array, int index); 352 int mthca_array_init(struct mthca_array *array, int nent); 353 void mthca_array_cleanup(struct mthca_array *array, int nent); 354 355 int mthca_init_uar_table(struct mthca_dev *dev); 356 int mthca_init_pd_table(struct mthca_dev *dev); 357 int mthca_init_mr_table(struct mthca_dev *dev); 358 int mthca_init_eq_table(struct mthca_dev *dev); 359 int mthca_init_cq_table(struct mthca_dev *dev); 360 int mthca_init_qp_table(struct mthca_dev *dev); 361 int mthca_init_av_table(struct mthca_dev *dev); 362 int mthca_init_mcg_table(struct mthca_dev *dev); 363 364 void mthca_cleanup_uar_table(struct mthca_dev *dev); 365 void mthca_cleanup_pd_table(struct mthca_dev *dev); 366 void mthca_cleanup_mr_table(struct mthca_dev *dev); 367 void mthca_cleanup_eq_table(struct mthca_dev *dev); 368 void mthca_cleanup_cq_table(struct mthca_dev *dev); 369 void mthca_cleanup_qp_table(struct mthca_dev *dev); 370 void mthca_cleanup_av_table(struct mthca_dev *dev); 371 void mthca_cleanup_mcg_table(struct mthca_dev *dev); 372 373 int mthca_register_device(struct mthca_dev *dev); 374 void mthca_unregister_device(struct mthca_dev *dev); 375 376 int mthca_uar_alloc(struct mthca_dev *dev, struct mthca_uar *uar); 377 void mthca_uar_free(struct mthca_dev *dev, struct mthca_uar *uar); 378 379 int mthca_pd_alloc(struct mthca_dev *dev, struct mthca_pd *pd); 380 void mthca_pd_free(struct mthca_dev *dev, struct mthca_pd *pd); 381 382 int mthca_mr_alloc_notrans(struct mthca_dev *dev, u32 pd, 383 u32 access, struct mthca_mr *mr); 384 int mthca_mr_alloc_phys(struct mthca_dev *dev, u32 pd, 385 u64 *buffer_list, int buffer_size_shift, 386 int list_len, u64 iova, u64 total_size, 387 u32 access, struct mthca_mr *mr); 388 void mthca_free_mr(struct mthca_dev *dev, struct mthca_mr *mr); 389 390 int mthca_fmr_alloc(struct mthca_dev *dev, u32 pd, 391 u32 access, struct mthca_fmr *fmr); 392 int mthca_tavor_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list, 393 int list_len, u64 iova); 394 void mthca_tavor_fmr_unmap(struct mthca_dev *dev, struct mthca_fmr *fmr); 395 int mthca_arbel_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list, 396 int list_len, u64 iova); 397 void mthca_arbel_fmr_unmap(struct mthca_dev *dev, struct mthca_fmr *fmr); 398 int mthca_free_fmr(struct mthca_dev *dev, struct mthca_fmr *fmr); 399 400 int mthca_map_eq_icm(struct mthca_dev *dev, u64 icm_virt); 401 void mthca_unmap_eq_icm(struct mthca_dev *dev); 402 403 int mthca_poll_cq(struct ib_cq *ibcq, int num_entries, 404 struct ib_wc *entry); 405 int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify); 406 int mthca_arbel_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify); 407 int mthca_init_cq(struct mthca_dev *dev, int nent, 408 struct mthca_cq *cq); 409 void mthca_free_cq(struct mthca_dev *dev, 410 struct mthca_cq *cq); 411 void mthca_cq_event(struct mthca_dev *dev, u32 cqn); 412 void mthca_cq_clean(struct mthca_dev *dev, u32 cqn, u32 qpn); 413 414 void mthca_qp_event(struct mthca_dev *dev, u32 qpn, 415 enum ib_event_type event_type); 416 int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask); 417 int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 418 struct ib_send_wr **bad_wr); 419 int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr, 420 struct ib_recv_wr **bad_wr); 421 int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 422 struct ib_send_wr **bad_wr); 423 int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr, 424 struct ib_recv_wr **bad_wr); 425 int mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send, 426 int index, int *dbd, u32 *new_wqe); 427 int mthca_alloc_qp(struct mthca_dev *dev, 428 struct mthca_pd *pd, 429 struct mthca_cq *send_cq, 430 struct mthca_cq *recv_cq, 431 enum ib_qp_type type, 432 enum ib_sig_type send_policy, 433 struct mthca_qp *qp); 434 int mthca_alloc_sqp(struct mthca_dev *dev, 435 struct mthca_pd *pd, 436 struct mthca_cq *send_cq, 437 struct mthca_cq *recv_cq, 438 enum ib_sig_type send_policy, 439 int qpn, 440 int port, 441 struct mthca_sqp *sqp); 442 void mthca_free_qp(struct mthca_dev *dev, struct mthca_qp *qp); 443 int mthca_create_ah(struct mthca_dev *dev, 444 struct mthca_pd *pd, 445 struct ib_ah_attr *ah_attr, 446 struct mthca_ah *ah); 447 int mthca_destroy_ah(struct mthca_dev *dev, struct mthca_ah *ah); 448 int mthca_read_ah(struct mthca_dev *dev, struct mthca_ah *ah, 449 struct ib_ud_header *header); 450 451 int mthca_multicast_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid); 452 int mthca_multicast_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid); 453 454 int mthca_process_mad(struct ib_device *ibdev, 455 int mad_flags, 456 u8 port_num, 457 struct ib_wc *in_wc, 458 struct ib_grh *in_grh, 459 struct ib_mad *in_mad, 460 struct ib_mad *out_mad); 461 int mthca_create_agents(struct mthca_dev *dev); 462 void mthca_free_agents(struct mthca_dev *dev); 463 464 static inline struct mthca_dev *to_mdev(struct ib_device *ibdev) 465 { 466 return container_of(ibdev, struct mthca_dev, ib_dev); 467 } 468 469 static inline int mthca_is_memfree(struct mthca_dev *dev) 470 { 471 return dev->mthca_flags & MTHCA_FLAG_MEMFREE; 472 } 473 474 #endif /* MTHCA_DEV_H */ 475