1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. 4 * Copyright (c) 2005, 2006 Cisco Systems, Inc. All rights reserved. 5 * Copyright (c) 2005 Mellanox Technologies. All rights reserved. 6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved. 7 * 8 * This software is available to you under a choice of one of two 9 * licenses. You may choose to be licensed under the terms of the GNU 10 * General Public License (GPL) Version 2, available from the file 11 * COPYING in the main directory of this source tree, or the 12 * OpenIB.org BSD license below: 13 * 14 * Redistribution and use in source and binary forms, with or 15 * without modification, are permitted provided that the following 16 * conditions are met: 17 * 18 * - Redistributions of source code must retain the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer. 21 * 22 * - Redistributions in binary form must reproduce the above 23 * copyright notice, this list of conditions and the following 24 * disclaimer in the documentation and/or other materials 25 * provided with the distribution. 26 * 27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 34 * SOFTWARE. 35 * 36 * $Id: mthca_cq.c 1369 2004-12-20 16:17:07Z roland $ 37 */ 38 39 #include <linux/init.h> 40 #include <linux/hardirq.h> 41 42 #include <rdma/ib_pack.h> 43 44 #include "mthca_dev.h" 45 #include "mthca_cmd.h" 46 #include "mthca_memfree.h" 47 48 enum { 49 MTHCA_MAX_DIRECT_CQ_SIZE = 4 * PAGE_SIZE 50 }; 51 52 enum { 53 MTHCA_CQ_ENTRY_SIZE = 0x20 54 }; 55 56 /* 57 * Must be packed because start is 64 bits but only aligned to 32 bits. 58 */ 59 struct mthca_cq_context { 60 __be32 flags; 61 __be64 start; 62 __be32 logsize_usrpage; 63 __be32 error_eqn; /* Tavor only */ 64 __be32 comp_eqn; 65 __be32 pd; 66 __be32 lkey; 67 __be32 last_notified_index; 68 __be32 solicit_producer_index; 69 __be32 consumer_index; 70 __be32 producer_index; 71 __be32 cqn; 72 __be32 ci_db; /* Arbel only */ 73 __be32 state_db; /* Arbel only */ 74 u32 reserved; 75 } __attribute__((packed)); 76 77 #define MTHCA_CQ_STATUS_OK ( 0 << 28) 78 #define MTHCA_CQ_STATUS_OVERFLOW ( 9 << 28) 79 #define MTHCA_CQ_STATUS_WRITE_FAIL (10 << 28) 80 #define MTHCA_CQ_FLAG_TR ( 1 << 18) 81 #define MTHCA_CQ_FLAG_OI ( 1 << 17) 82 #define MTHCA_CQ_STATE_DISARMED ( 0 << 8) 83 #define MTHCA_CQ_STATE_ARMED ( 1 << 8) 84 #define MTHCA_CQ_STATE_ARMED_SOL ( 4 << 8) 85 #define MTHCA_EQ_STATE_FIRED (10 << 8) 86 87 enum { 88 MTHCA_ERROR_CQE_OPCODE_MASK = 0xfe 89 }; 90 91 enum { 92 SYNDROME_LOCAL_LENGTH_ERR = 0x01, 93 SYNDROME_LOCAL_QP_OP_ERR = 0x02, 94 SYNDROME_LOCAL_EEC_OP_ERR = 0x03, 95 SYNDROME_LOCAL_PROT_ERR = 0x04, 96 SYNDROME_WR_FLUSH_ERR = 0x05, 97 SYNDROME_MW_BIND_ERR = 0x06, 98 SYNDROME_BAD_RESP_ERR = 0x10, 99 SYNDROME_LOCAL_ACCESS_ERR = 0x11, 100 SYNDROME_REMOTE_INVAL_REQ_ERR = 0x12, 101 SYNDROME_REMOTE_ACCESS_ERR = 0x13, 102 SYNDROME_REMOTE_OP_ERR = 0x14, 103 SYNDROME_RETRY_EXC_ERR = 0x15, 104 SYNDROME_RNR_RETRY_EXC_ERR = 0x16, 105 SYNDROME_LOCAL_RDD_VIOL_ERR = 0x20, 106 SYNDROME_REMOTE_INVAL_RD_REQ_ERR = 0x21, 107 SYNDROME_REMOTE_ABORTED_ERR = 0x22, 108 SYNDROME_INVAL_EECN_ERR = 0x23, 109 SYNDROME_INVAL_EEC_STATE_ERR = 0x24 110 }; 111 112 struct mthca_cqe { 113 __be32 my_qpn; 114 __be32 my_ee; 115 __be32 rqpn; 116 __be16 sl_g_mlpath; 117 __be16 rlid; 118 __be32 imm_etype_pkey_eec; 119 __be32 byte_cnt; 120 __be32 wqe; 121 u8 opcode; 122 u8 is_send; 123 u8 reserved; 124 u8 owner; 125 }; 126 127 struct mthca_err_cqe { 128 __be32 my_qpn; 129 u32 reserved1[3]; 130 u8 syndrome; 131 u8 vendor_err; 132 __be16 db_cnt; 133 u32 reserved2; 134 __be32 wqe; 135 u8 opcode; 136 u8 reserved3[2]; 137 u8 owner; 138 }; 139 140 #define MTHCA_CQ_ENTRY_OWNER_SW (0 << 7) 141 #define MTHCA_CQ_ENTRY_OWNER_HW (1 << 7) 142 143 #define MTHCA_TAVOR_CQ_DB_INC_CI (1 << 24) 144 #define MTHCA_TAVOR_CQ_DB_REQ_NOT (2 << 24) 145 #define MTHCA_TAVOR_CQ_DB_REQ_NOT_SOL (3 << 24) 146 #define MTHCA_TAVOR_CQ_DB_SET_CI (4 << 24) 147 #define MTHCA_TAVOR_CQ_DB_REQ_NOT_MULT (5 << 24) 148 149 #define MTHCA_ARBEL_CQ_DB_REQ_NOT_SOL (1 << 24) 150 #define MTHCA_ARBEL_CQ_DB_REQ_NOT (2 << 24) 151 #define MTHCA_ARBEL_CQ_DB_REQ_NOT_MULT (3 << 24) 152 153 static inline struct mthca_cqe *get_cqe_from_buf(struct mthca_cq_buf *buf, 154 int entry) 155 { 156 if (buf->is_direct) 157 return buf->queue.direct.buf + (entry * MTHCA_CQ_ENTRY_SIZE); 158 else 159 return buf->queue.page_list[entry * MTHCA_CQ_ENTRY_SIZE / PAGE_SIZE].buf 160 + (entry * MTHCA_CQ_ENTRY_SIZE) % PAGE_SIZE; 161 } 162 163 static inline struct mthca_cqe *get_cqe(struct mthca_cq *cq, int entry) 164 { 165 return get_cqe_from_buf(&cq->buf, entry); 166 } 167 168 static inline struct mthca_cqe *cqe_sw(struct mthca_cqe *cqe) 169 { 170 return MTHCA_CQ_ENTRY_OWNER_HW & cqe->owner ? NULL : cqe; 171 } 172 173 static inline struct mthca_cqe *next_cqe_sw(struct mthca_cq *cq) 174 { 175 return cqe_sw(get_cqe(cq, cq->cons_index & cq->ibcq.cqe)); 176 } 177 178 static inline void set_cqe_hw(struct mthca_cqe *cqe) 179 { 180 cqe->owner = MTHCA_CQ_ENTRY_OWNER_HW; 181 } 182 183 static void dump_cqe(struct mthca_dev *dev, void *cqe_ptr) 184 { 185 __be32 *cqe = cqe_ptr; 186 187 (void) cqe; /* avoid warning if mthca_dbg compiled away... */ 188 mthca_dbg(dev, "CQE contents %08x %08x %08x %08x %08x %08x %08x %08x\n", 189 be32_to_cpu(cqe[0]), be32_to_cpu(cqe[1]), be32_to_cpu(cqe[2]), 190 be32_to_cpu(cqe[3]), be32_to_cpu(cqe[4]), be32_to_cpu(cqe[5]), 191 be32_to_cpu(cqe[6]), be32_to_cpu(cqe[7])); 192 } 193 194 /* 195 * incr is ignored in native Arbel (mem-free) mode, so cq->cons_index 196 * should be correct before calling update_cons_index(). 197 */ 198 static inline void update_cons_index(struct mthca_dev *dev, struct mthca_cq *cq, 199 int incr) 200 { 201 __be32 doorbell[2]; 202 203 if (mthca_is_memfree(dev)) { 204 *cq->set_ci_db = cpu_to_be32(cq->cons_index); 205 wmb(); 206 } else { 207 doorbell[0] = cpu_to_be32(MTHCA_TAVOR_CQ_DB_INC_CI | cq->cqn); 208 doorbell[1] = cpu_to_be32(incr - 1); 209 210 mthca_write64(doorbell, 211 dev->kar + MTHCA_CQ_DOORBELL, 212 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); 213 } 214 } 215 216 void mthca_cq_completion(struct mthca_dev *dev, u32 cqn) 217 { 218 struct mthca_cq *cq; 219 220 cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1)); 221 222 if (!cq) { 223 mthca_warn(dev, "Completion event for bogus CQ %08x\n", cqn); 224 return; 225 } 226 227 ++cq->arm_sn; 228 229 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context); 230 } 231 232 void mthca_cq_event(struct mthca_dev *dev, u32 cqn, 233 enum ib_event_type event_type) 234 { 235 struct mthca_cq *cq; 236 struct ib_event event; 237 238 spin_lock(&dev->cq_table.lock); 239 240 cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1)); 241 if (cq) 242 ++cq->refcount; 243 244 spin_unlock(&dev->cq_table.lock); 245 246 if (!cq) { 247 mthca_warn(dev, "Async event for bogus CQ %08x\n", cqn); 248 return; 249 } 250 251 event.device = &dev->ib_dev; 252 event.event = event_type; 253 event.element.cq = &cq->ibcq; 254 if (cq->ibcq.event_handler) 255 cq->ibcq.event_handler(&event, cq->ibcq.cq_context); 256 257 spin_lock(&dev->cq_table.lock); 258 if (!--cq->refcount) 259 wake_up(&cq->wait); 260 spin_unlock(&dev->cq_table.lock); 261 } 262 263 static inline int is_recv_cqe(struct mthca_cqe *cqe) 264 { 265 if ((cqe->opcode & MTHCA_ERROR_CQE_OPCODE_MASK) == 266 MTHCA_ERROR_CQE_OPCODE_MASK) 267 return !(cqe->opcode & 0x01); 268 else 269 return !(cqe->is_send & 0x80); 270 } 271 272 void mthca_cq_clean(struct mthca_dev *dev, struct mthca_cq *cq, u32 qpn, 273 struct mthca_srq *srq) 274 { 275 struct mthca_cqe *cqe; 276 u32 prod_index; 277 int nfreed = 0; 278 279 spin_lock_irq(&cq->lock); 280 281 /* 282 * First we need to find the current producer index, so we 283 * know where to start cleaning from. It doesn't matter if HW 284 * adds new entries after this loop -- the QP we're worried 285 * about is already in RESET, so the new entries won't come 286 * from our QP and therefore don't need to be checked. 287 */ 288 for (prod_index = cq->cons_index; 289 cqe_sw(get_cqe(cq, prod_index & cq->ibcq.cqe)); 290 ++prod_index) 291 if (prod_index == cq->cons_index + cq->ibcq.cqe) 292 break; 293 294 if (0) 295 mthca_dbg(dev, "Cleaning QPN %06x from CQN %06x; ci %d, pi %d\n", 296 qpn, cq->cqn, cq->cons_index, prod_index); 297 298 /* 299 * Now sweep backwards through the CQ, removing CQ entries 300 * that match our QP by copying older entries on top of them. 301 */ 302 while ((int) --prod_index - (int) cq->cons_index >= 0) { 303 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe); 304 if (cqe->my_qpn == cpu_to_be32(qpn)) { 305 if (srq && is_recv_cqe(cqe)) 306 mthca_free_srq_wqe(srq, be32_to_cpu(cqe->wqe)); 307 ++nfreed; 308 } else if (nfreed) 309 memcpy(get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe), 310 cqe, MTHCA_CQ_ENTRY_SIZE); 311 } 312 313 if (nfreed) { 314 wmb(); 315 cq->cons_index += nfreed; 316 update_cons_index(dev, cq, nfreed); 317 } 318 319 spin_unlock_irq(&cq->lock); 320 } 321 322 void mthca_cq_resize_copy_cqes(struct mthca_cq *cq) 323 { 324 int i; 325 326 /* 327 * In Tavor mode, the hardware keeps the consumer and producer 328 * indices mod the CQ size. Since we might be making the CQ 329 * bigger, we need to deal with the case where the producer 330 * index wrapped around before the CQ was resized. 331 */ 332 if (!mthca_is_memfree(to_mdev(cq->ibcq.device)) && 333 cq->ibcq.cqe < cq->resize_buf->cqe) { 334 cq->cons_index &= cq->ibcq.cqe; 335 if (cqe_sw(get_cqe(cq, cq->ibcq.cqe))) 336 cq->cons_index -= cq->ibcq.cqe + 1; 337 } 338 339 for (i = cq->cons_index; cqe_sw(get_cqe(cq, i & cq->ibcq.cqe)); ++i) 340 memcpy(get_cqe_from_buf(&cq->resize_buf->buf, 341 i & cq->resize_buf->cqe), 342 get_cqe(cq, i & cq->ibcq.cqe), MTHCA_CQ_ENTRY_SIZE); 343 } 344 345 int mthca_alloc_cq_buf(struct mthca_dev *dev, struct mthca_cq_buf *buf, int nent) 346 { 347 int ret; 348 int i; 349 350 ret = mthca_buf_alloc(dev, nent * MTHCA_CQ_ENTRY_SIZE, 351 MTHCA_MAX_DIRECT_CQ_SIZE, 352 &buf->queue, &buf->is_direct, 353 &dev->driver_pd, 1, &buf->mr); 354 if (ret) 355 return ret; 356 357 for (i = 0; i < nent; ++i) 358 set_cqe_hw(get_cqe_from_buf(buf, i)); 359 360 return 0; 361 } 362 363 void mthca_free_cq_buf(struct mthca_dev *dev, struct mthca_cq_buf *buf, int cqe) 364 { 365 mthca_buf_free(dev, (cqe + 1) * MTHCA_CQ_ENTRY_SIZE, &buf->queue, 366 buf->is_direct, &buf->mr); 367 } 368 369 static void handle_error_cqe(struct mthca_dev *dev, struct mthca_cq *cq, 370 struct mthca_qp *qp, int wqe_index, int is_send, 371 struct mthca_err_cqe *cqe, 372 struct ib_wc *entry, int *free_cqe) 373 { 374 int dbd; 375 __be32 new_wqe; 376 377 if (cqe->syndrome == SYNDROME_LOCAL_QP_OP_ERR) { 378 mthca_dbg(dev, "local QP operation err " 379 "(QPN %06x, WQE @ %08x, CQN %06x, index %d)\n", 380 be32_to_cpu(cqe->my_qpn), be32_to_cpu(cqe->wqe), 381 cq->cqn, cq->cons_index); 382 dump_cqe(dev, cqe); 383 } 384 385 /* 386 * For completions in error, only work request ID, status, vendor error 387 * (and freed resource count for RD) have to be set. 388 */ 389 switch (cqe->syndrome) { 390 case SYNDROME_LOCAL_LENGTH_ERR: 391 entry->status = IB_WC_LOC_LEN_ERR; 392 break; 393 case SYNDROME_LOCAL_QP_OP_ERR: 394 entry->status = IB_WC_LOC_QP_OP_ERR; 395 break; 396 case SYNDROME_LOCAL_EEC_OP_ERR: 397 entry->status = IB_WC_LOC_EEC_OP_ERR; 398 break; 399 case SYNDROME_LOCAL_PROT_ERR: 400 entry->status = IB_WC_LOC_PROT_ERR; 401 break; 402 case SYNDROME_WR_FLUSH_ERR: 403 entry->status = IB_WC_WR_FLUSH_ERR; 404 break; 405 case SYNDROME_MW_BIND_ERR: 406 entry->status = IB_WC_MW_BIND_ERR; 407 break; 408 case SYNDROME_BAD_RESP_ERR: 409 entry->status = IB_WC_BAD_RESP_ERR; 410 break; 411 case SYNDROME_LOCAL_ACCESS_ERR: 412 entry->status = IB_WC_LOC_ACCESS_ERR; 413 break; 414 case SYNDROME_REMOTE_INVAL_REQ_ERR: 415 entry->status = IB_WC_REM_INV_REQ_ERR; 416 break; 417 case SYNDROME_REMOTE_ACCESS_ERR: 418 entry->status = IB_WC_REM_ACCESS_ERR; 419 break; 420 case SYNDROME_REMOTE_OP_ERR: 421 entry->status = IB_WC_REM_OP_ERR; 422 break; 423 case SYNDROME_RETRY_EXC_ERR: 424 entry->status = IB_WC_RETRY_EXC_ERR; 425 break; 426 case SYNDROME_RNR_RETRY_EXC_ERR: 427 entry->status = IB_WC_RNR_RETRY_EXC_ERR; 428 break; 429 case SYNDROME_LOCAL_RDD_VIOL_ERR: 430 entry->status = IB_WC_LOC_RDD_VIOL_ERR; 431 break; 432 case SYNDROME_REMOTE_INVAL_RD_REQ_ERR: 433 entry->status = IB_WC_REM_INV_RD_REQ_ERR; 434 break; 435 case SYNDROME_REMOTE_ABORTED_ERR: 436 entry->status = IB_WC_REM_ABORT_ERR; 437 break; 438 case SYNDROME_INVAL_EECN_ERR: 439 entry->status = IB_WC_INV_EECN_ERR; 440 break; 441 case SYNDROME_INVAL_EEC_STATE_ERR: 442 entry->status = IB_WC_INV_EEC_STATE_ERR; 443 break; 444 default: 445 entry->status = IB_WC_GENERAL_ERR; 446 break; 447 } 448 449 entry->vendor_err = cqe->vendor_err; 450 451 /* 452 * Mem-free HCAs always generate one CQE per WQE, even in the 453 * error case, so we don't have to check the doorbell count, etc. 454 */ 455 if (mthca_is_memfree(dev)) 456 return; 457 458 mthca_free_err_wqe(dev, qp, is_send, wqe_index, &dbd, &new_wqe); 459 460 /* 461 * If we're at the end of the WQE chain, or we've used up our 462 * doorbell count, free the CQE. Otherwise just update it for 463 * the next poll operation. 464 */ 465 if (!(new_wqe & cpu_to_be32(0x3f)) || (!cqe->db_cnt && dbd)) 466 return; 467 468 cqe->db_cnt = cpu_to_be16(be16_to_cpu(cqe->db_cnt) - dbd); 469 cqe->wqe = new_wqe; 470 cqe->syndrome = SYNDROME_WR_FLUSH_ERR; 471 472 *free_cqe = 0; 473 } 474 475 static inline int mthca_poll_one(struct mthca_dev *dev, 476 struct mthca_cq *cq, 477 struct mthca_qp **cur_qp, 478 int *freed, 479 struct ib_wc *entry) 480 { 481 struct mthca_wq *wq; 482 struct mthca_cqe *cqe; 483 int wqe_index; 484 int is_error; 485 int is_send; 486 int free_cqe = 1; 487 int err = 0; 488 489 cqe = next_cqe_sw(cq); 490 if (!cqe) 491 return -EAGAIN; 492 493 /* 494 * Make sure we read CQ entry contents after we've checked the 495 * ownership bit. 496 */ 497 rmb(); 498 499 if (0) { 500 mthca_dbg(dev, "%x/%d: CQE -> QPN %06x, WQE @ %08x\n", 501 cq->cqn, cq->cons_index, be32_to_cpu(cqe->my_qpn), 502 be32_to_cpu(cqe->wqe)); 503 dump_cqe(dev, cqe); 504 } 505 506 is_error = (cqe->opcode & MTHCA_ERROR_CQE_OPCODE_MASK) == 507 MTHCA_ERROR_CQE_OPCODE_MASK; 508 is_send = is_error ? cqe->opcode & 0x01 : cqe->is_send & 0x80; 509 510 if (!*cur_qp || be32_to_cpu(cqe->my_qpn) != (*cur_qp)->qpn) { 511 /* 512 * We do not have to take the QP table lock here, 513 * because CQs will be locked while QPs are removed 514 * from the table. 515 */ 516 *cur_qp = mthca_array_get(&dev->qp_table.qp, 517 be32_to_cpu(cqe->my_qpn) & 518 (dev->limits.num_qps - 1)); 519 if (!*cur_qp) { 520 mthca_warn(dev, "CQ entry for unknown QP %06x\n", 521 be32_to_cpu(cqe->my_qpn) & 0xffffff); 522 err = -EINVAL; 523 goto out; 524 } 525 } 526 527 entry->qp_num = (*cur_qp)->qpn; 528 529 if (is_send) { 530 wq = &(*cur_qp)->sq; 531 wqe_index = ((be32_to_cpu(cqe->wqe) - (*cur_qp)->send_wqe_offset) 532 >> wq->wqe_shift); 533 entry->wr_id = (*cur_qp)->wrid[wqe_index + 534 (*cur_qp)->rq.max]; 535 } else if ((*cur_qp)->ibqp.srq) { 536 struct mthca_srq *srq = to_msrq((*cur_qp)->ibqp.srq); 537 u32 wqe = be32_to_cpu(cqe->wqe); 538 wq = NULL; 539 wqe_index = wqe >> srq->wqe_shift; 540 entry->wr_id = srq->wrid[wqe_index]; 541 mthca_free_srq_wqe(srq, wqe); 542 } else { 543 s32 wqe; 544 wq = &(*cur_qp)->rq; 545 wqe = be32_to_cpu(cqe->wqe); 546 wqe_index = wqe >> wq->wqe_shift; 547 /* 548 * WQE addr == base - 1 might be reported in receive completion 549 * with error instead of (rq size - 1) by Sinai FW 1.0.800 and 550 * Arbel FW 5.1.400. This bug should be fixed in later FW revs. 551 */ 552 if (unlikely(wqe_index < 0)) 553 wqe_index = wq->max - 1; 554 entry->wr_id = (*cur_qp)->wrid[wqe_index]; 555 } 556 557 if (wq) { 558 if (wq->last_comp < wqe_index) 559 wq->tail += wqe_index - wq->last_comp; 560 else 561 wq->tail += wqe_index + wq->max - wq->last_comp; 562 563 wq->last_comp = wqe_index; 564 } 565 566 if (is_error) { 567 handle_error_cqe(dev, cq, *cur_qp, wqe_index, is_send, 568 (struct mthca_err_cqe *) cqe, 569 entry, &free_cqe); 570 goto out; 571 } 572 573 if (is_send) { 574 entry->wc_flags = 0; 575 switch (cqe->opcode) { 576 case MTHCA_OPCODE_RDMA_WRITE: 577 entry->opcode = IB_WC_RDMA_WRITE; 578 break; 579 case MTHCA_OPCODE_RDMA_WRITE_IMM: 580 entry->opcode = IB_WC_RDMA_WRITE; 581 entry->wc_flags |= IB_WC_WITH_IMM; 582 break; 583 case MTHCA_OPCODE_SEND: 584 entry->opcode = IB_WC_SEND; 585 break; 586 case MTHCA_OPCODE_SEND_IMM: 587 entry->opcode = IB_WC_SEND; 588 entry->wc_flags |= IB_WC_WITH_IMM; 589 break; 590 case MTHCA_OPCODE_RDMA_READ: 591 entry->opcode = IB_WC_RDMA_READ; 592 entry->byte_len = be32_to_cpu(cqe->byte_cnt); 593 break; 594 case MTHCA_OPCODE_ATOMIC_CS: 595 entry->opcode = IB_WC_COMP_SWAP; 596 entry->byte_len = be32_to_cpu(cqe->byte_cnt); 597 break; 598 case MTHCA_OPCODE_ATOMIC_FA: 599 entry->opcode = IB_WC_FETCH_ADD; 600 entry->byte_len = be32_to_cpu(cqe->byte_cnt); 601 break; 602 case MTHCA_OPCODE_BIND_MW: 603 entry->opcode = IB_WC_BIND_MW; 604 break; 605 default: 606 entry->opcode = MTHCA_OPCODE_INVALID; 607 break; 608 } 609 } else { 610 entry->byte_len = be32_to_cpu(cqe->byte_cnt); 611 switch (cqe->opcode & 0x1f) { 612 case IB_OPCODE_SEND_LAST_WITH_IMMEDIATE: 613 case IB_OPCODE_SEND_ONLY_WITH_IMMEDIATE: 614 entry->wc_flags = IB_WC_WITH_IMM; 615 entry->imm_data = cqe->imm_etype_pkey_eec; 616 entry->opcode = IB_WC_RECV; 617 break; 618 case IB_OPCODE_RDMA_WRITE_LAST_WITH_IMMEDIATE: 619 case IB_OPCODE_RDMA_WRITE_ONLY_WITH_IMMEDIATE: 620 entry->wc_flags = IB_WC_WITH_IMM; 621 entry->imm_data = cqe->imm_etype_pkey_eec; 622 entry->opcode = IB_WC_RECV_RDMA_WITH_IMM; 623 break; 624 default: 625 entry->wc_flags = 0; 626 entry->opcode = IB_WC_RECV; 627 break; 628 } 629 entry->slid = be16_to_cpu(cqe->rlid); 630 entry->sl = be16_to_cpu(cqe->sl_g_mlpath) >> 12; 631 entry->src_qp = be32_to_cpu(cqe->rqpn) & 0xffffff; 632 entry->dlid_path_bits = be16_to_cpu(cqe->sl_g_mlpath) & 0x7f; 633 entry->pkey_index = be32_to_cpu(cqe->imm_etype_pkey_eec) >> 16; 634 entry->wc_flags |= be16_to_cpu(cqe->sl_g_mlpath) & 0x80 ? 635 IB_WC_GRH : 0; 636 } 637 638 entry->status = IB_WC_SUCCESS; 639 640 out: 641 if (likely(free_cqe)) { 642 set_cqe_hw(cqe); 643 ++(*freed); 644 ++cq->cons_index; 645 } 646 647 return err; 648 } 649 650 int mthca_poll_cq(struct ib_cq *ibcq, int num_entries, 651 struct ib_wc *entry) 652 { 653 struct mthca_dev *dev = to_mdev(ibcq->device); 654 struct mthca_cq *cq = to_mcq(ibcq); 655 struct mthca_qp *qp = NULL; 656 unsigned long flags; 657 int err = 0; 658 int freed = 0; 659 int npolled; 660 661 spin_lock_irqsave(&cq->lock, flags); 662 663 npolled = 0; 664 repoll: 665 while (npolled < num_entries) { 666 err = mthca_poll_one(dev, cq, &qp, 667 &freed, entry + npolled); 668 if (err) 669 break; 670 ++npolled; 671 } 672 673 if (freed) { 674 wmb(); 675 update_cons_index(dev, cq, freed); 676 } 677 678 /* 679 * If a CQ resize is in progress and we discovered that the 680 * old buffer is empty, then peek in the new buffer, and if 681 * it's not empty, switch to the new buffer and continue 682 * polling there. 683 */ 684 if (unlikely(err == -EAGAIN && cq->resize_buf && 685 cq->resize_buf->state == CQ_RESIZE_READY)) { 686 /* 687 * In Tavor mode, the hardware keeps the producer 688 * index modulo the CQ size. Since we might be making 689 * the CQ bigger, we need to mask our consumer index 690 * using the size of the old CQ buffer before looking 691 * in the new CQ buffer. 692 */ 693 if (!mthca_is_memfree(dev)) 694 cq->cons_index &= cq->ibcq.cqe; 695 696 if (cqe_sw(get_cqe_from_buf(&cq->resize_buf->buf, 697 cq->cons_index & cq->resize_buf->cqe))) { 698 struct mthca_cq_buf tbuf; 699 int tcqe; 700 701 tbuf = cq->buf; 702 tcqe = cq->ibcq.cqe; 703 cq->buf = cq->resize_buf->buf; 704 cq->ibcq.cqe = cq->resize_buf->cqe; 705 706 cq->resize_buf->buf = tbuf; 707 cq->resize_buf->cqe = tcqe; 708 cq->resize_buf->state = CQ_RESIZE_SWAPPED; 709 710 goto repoll; 711 } 712 } 713 714 spin_unlock_irqrestore(&cq->lock, flags); 715 716 return err == 0 || err == -EAGAIN ? npolled : err; 717 } 718 719 int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify) 720 { 721 __be32 doorbell[2]; 722 723 doorbell[0] = cpu_to_be32((notify == IB_CQ_SOLICITED ? 724 MTHCA_TAVOR_CQ_DB_REQ_NOT_SOL : 725 MTHCA_TAVOR_CQ_DB_REQ_NOT) | 726 to_mcq(cq)->cqn); 727 doorbell[1] = (__force __be32) 0xffffffff; 728 729 mthca_write64(doorbell, 730 to_mdev(cq->device)->kar + MTHCA_CQ_DOORBELL, 731 MTHCA_GET_DOORBELL_LOCK(&to_mdev(cq->device)->doorbell_lock)); 732 733 return 0; 734 } 735 736 int mthca_arbel_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify notify) 737 { 738 struct mthca_cq *cq = to_mcq(ibcq); 739 __be32 doorbell[2]; 740 u32 sn; 741 __be32 ci; 742 743 sn = cq->arm_sn & 3; 744 ci = cpu_to_be32(cq->cons_index); 745 746 doorbell[0] = ci; 747 doorbell[1] = cpu_to_be32((cq->cqn << 8) | (2 << 5) | (sn << 3) | 748 (notify == IB_CQ_SOLICITED ? 1 : 2)); 749 750 mthca_write_db_rec(doorbell, cq->arm_db); 751 752 /* 753 * Make sure that the doorbell record in host memory is 754 * written before ringing the doorbell via PCI MMIO. 755 */ 756 wmb(); 757 758 doorbell[0] = cpu_to_be32((sn << 28) | 759 (notify == IB_CQ_SOLICITED ? 760 MTHCA_ARBEL_CQ_DB_REQ_NOT_SOL : 761 MTHCA_ARBEL_CQ_DB_REQ_NOT) | 762 cq->cqn); 763 doorbell[1] = ci; 764 765 mthca_write64(doorbell, 766 to_mdev(ibcq->device)->kar + MTHCA_CQ_DOORBELL, 767 MTHCA_GET_DOORBELL_LOCK(&to_mdev(ibcq->device)->doorbell_lock)); 768 769 return 0; 770 } 771 772 int mthca_init_cq(struct mthca_dev *dev, int nent, 773 struct mthca_ucontext *ctx, u32 pdn, 774 struct mthca_cq *cq) 775 { 776 struct mthca_mailbox *mailbox; 777 struct mthca_cq_context *cq_context; 778 int err = -ENOMEM; 779 u8 status; 780 781 cq->ibcq.cqe = nent - 1; 782 cq->is_kernel = !ctx; 783 784 cq->cqn = mthca_alloc(&dev->cq_table.alloc); 785 if (cq->cqn == -1) 786 return -ENOMEM; 787 788 if (mthca_is_memfree(dev)) { 789 err = mthca_table_get(dev, dev->cq_table.table, cq->cqn); 790 if (err) 791 goto err_out; 792 793 if (cq->is_kernel) { 794 cq->arm_sn = 1; 795 796 err = -ENOMEM; 797 798 cq->set_ci_db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_CQ_SET_CI, 799 cq->cqn, &cq->set_ci_db); 800 if (cq->set_ci_db_index < 0) 801 goto err_out_icm; 802 803 cq->arm_db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_CQ_ARM, 804 cq->cqn, &cq->arm_db); 805 if (cq->arm_db_index < 0) 806 goto err_out_ci; 807 } 808 } 809 810 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 811 if (IS_ERR(mailbox)) 812 goto err_out_arm; 813 814 cq_context = mailbox->buf; 815 816 if (cq->is_kernel) { 817 err = mthca_alloc_cq_buf(dev, &cq->buf, nent); 818 if (err) 819 goto err_out_mailbox; 820 } 821 822 spin_lock_init(&cq->lock); 823 cq->refcount = 1; 824 init_waitqueue_head(&cq->wait); 825 mutex_init(&cq->mutex); 826 827 memset(cq_context, 0, sizeof *cq_context); 828 cq_context->flags = cpu_to_be32(MTHCA_CQ_STATUS_OK | 829 MTHCA_CQ_STATE_DISARMED | 830 MTHCA_CQ_FLAG_TR); 831 cq_context->logsize_usrpage = cpu_to_be32((ffs(nent) - 1) << 24); 832 if (ctx) 833 cq_context->logsize_usrpage |= cpu_to_be32(ctx->uar.index); 834 else 835 cq_context->logsize_usrpage |= cpu_to_be32(dev->driver_uar.index); 836 cq_context->error_eqn = cpu_to_be32(dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn); 837 cq_context->comp_eqn = cpu_to_be32(dev->eq_table.eq[MTHCA_EQ_COMP].eqn); 838 cq_context->pd = cpu_to_be32(pdn); 839 cq_context->lkey = cpu_to_be32(cq->buf.mr.ibmr.lkey); 840 cq_context->cqn = cpu_to_be32(cq->cqn); 841 842 if (mthca_is_memfree(dev)) { 843 cq_context->ci_db = cpu_to_be32(cq->set_ci_db_index); 844 cq_context->state_db = cpu_to_be32(cq->arm_db_index); 845 } 846 847 err = mthca_SW2HW_CQ(dev, mailbox, cq->cqn, &status); 848 if (err) { 849 mthca_warn(dev, "SW2HW_CQ failed (%d)\n", err); 850 goto err_out_free_mr; 851 } 852 853 if (status) { 854 mthca_warn(dev, "SW2HW_CQ returned status 0x%02x\n", 855 status); 856 err = -EINVAL; 857 goto err_out_free_mr; 858 } 859 860 spin_lock_irq(&dev->cq_table.lock); 861 if (mthca_array_set(&dev->cq_table.cq, 862 cq->cqn & (dev->limits.num_cqs - 1), 863 cq)) { 864 spin_unlock_irq(&dev->cq_table.lock); 865 goto err_out_free_mr; 866 } 867 spin_unlock_irq(&dev->cq_table.lock); 868 869 cq->cons_index = 0; 870 871 mthca_free_mailbox(dev, mailbox); 872 873 return 0; 874 875 err_out_free_mr: 876 if (cq->is_kernel) 877 mthca_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe); 878 879 err_out_mailbox: 880 mthca_free_mailbox(dev, mailbox); 881 882 err_out_arm: 883 if (cq->is_kernel && mthca_is_memfree(dev)) 884 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_ARM, cq->arm_db_index); 885 886 err_out_ci: 887 if (cq->is_kernel && mthca_is_memfree(dev)) 888 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_SET_CI, cq->set_ci_db_index); 889 890 err_out_icm: 891 mthca_table_put(dev, dev->cq_table.table, cq->cqn); 892 893 err_out: 894 mthca_free(&dev->cq_table.alloc, cq->cqn); 895 896 return err; 897 } 898 899 static inline int get_cq_refcount(struct mthca_dev *dev, struct mthca_cq *cq) 900 { 901 int c; 902 903 spin_lock_irq(&dev->cq_table.lock); 904 c = cq->refcount; 905 spin_unlock_irq(&dev->cq_table.lock); 906 907 return c; 908 } 909 910 void mthca_free_cq(struct mthca_dev *dev, 911 struct mthca_cq *cq) 912 { 913 struct mthca_mailbox *mailbox; 914 int err; 915 u8 status; 916 917 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 918 if (IS_ERR(mailbox)) { 919 mthca_warn(dev, "No memory for mailbox to free CQ.\n"); 920 return; 921 } 922 923 err = mthca_HW2SW_CQ(dev, mailbox, cq->cqn, &status); 924 if (err) 925 mthca_warn(dev, "HW2SW_CQ failed (%d)\n", err); 926 else if (status) 927 mthca_warn(dev, "HW2SW_CQ returned status 0x%02x\n", status); 928 929 if (0) { 930 __be32 *ctx = mailbox->buf; 931 int j; 932 933 printk(KERN_ERR "context for CQN %x (cons index %x, next sw %d)\n", 934 cq->cqn, cq->cons_index, 935 cq->is_kernel ? !!next_cqe_sw(cq) : 0); 936 for (j = 0; j < 16; ++j) 937 printk(KERN_ERR "[%2x] %08x\n", j * 4, be32_to_cpu(ctx[j])); 938 } 939 940 spin_lock_irq(&dev->cq_table.lock); 941 mthca_array_clear(&dev->cq_table.cq, 942 cq->cqn & (dev->limits.num_cqs - 1)); 943 --cq->refcount; 944 spin_unlock_irq(&dev->cq_table.lock); 945 946 if (dev->mthca_flags & MTHCA_FLAG_MSI_X) 947 synchronize_irq(dev->eq_table.eq[MTHCA_EQ_COMP].msi_x_vector); 948 else 949 synchronize_irq(dev->pdev->irq); 950 951 wait_event(cq->wait, !get_cq_refcount(dev, cq)); 952 953 if (cq->is_kernel) { 954 mthca_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe); 955 if (mthca_is_memfree(dev)) { 956 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_ARM, cq->arm_db_index); 957 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_SET_CI, cq->set_ci_db_index); 958 } 959 } 960 961 mthca_table_put(dev, dev->cq_table.table, cq->cqn); 962 mthca_free(&dev->cq_table.alloc, cq->cqn); 963 mthca_free_mailbox(dev, mailbox); 964 } 965 966 int __devinit mthca_init_cq_table(struct mthca_dev *dev) 967 { 968 int err; 969 970 spin_lock_init(&dev->cq_table.lock); 971 972 err = mthca_alloc_init(&dev->cq_table.alloc, 973 dev->limits.num_cqs, 974 (1 << 24) - 1, 975 dev->limits.reserved_cqs); 976 if (err) 977 return err; 978 979 err = mthca_array_init(&dev->cq_table.cq, 980 dev->limits.num_cqs); 981 if (err) 982 mthca_alloc_cleanup(&dev->cq_table.alloc); 983 984 return err; 985 } 986 987 void mthca_cleanup_cq_table(struct mthca_dev *dev) 988 { 989 mthca_array_cleanup(&dev->cq_table.cq, dev->limits.num_cqs); 990 mthca_alloc_cleanup(&dev->cq_table.alloc); 991 } 992