1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 3 /* Authors: Cheng Xu <chengyou@linux.alibaba.com> */ 4 /* Kai Shen <kaishen@linux.alibaba.com> */ 5 /* Copyright (c) 2020-2022, Alibaba Group. */ 6 7 #ifndef __ERDMA_HW_H__ 8 #define __ERDMA_HW_H__ 9 10 #include <linux/kernel.h> 11 #include <linux/types.h> 12 13 /* PCIe device related definition. */ 14 #define ERDMA_PCI_WIDTH 64 15 #define ERDMA_FUNC_BAR 0 16 #define ERDMA_MISX_BAR 2 17 18 #define ERDMA_BAR_MASK (BIT(ERDMA_FUNC_BAR) | BIT(ERDMA_MISX_BAR)) 19 20 /* MSI-X related. */ 21 #define ERDMA_NUM_MSIX_VEC 32U 22 #define ERDMA_MSIX_VECTOR_CMDQ 0 23 24 /* PCIe Bar0 Registers. */ 25 #define ERDMA_REGS_VERSION_REG 0x0 26 #define ERDMA_REGS_DEV_CTRL_REG 0x10 27 #define ERDMA_REGS_DEV_ST_REG 0x14 28 #define ERDMA_REGS_NETDEV_MAC_L_REG 0x18 29 #define ERDMA_REGS_NETDEV_MAC_H_REG 0x1C 30 #define ERDMA_REGS_CMDQ_SQ_ADDR_L_REG 0x20 31 #define ERDMA_REGS_CMDQ_SQ_ADDR_H_REG 0x24 32 #define ERDMA_REGS_CMDQ_CQ_ADDR_L_REG 0x28 33 #define ERDMA_REGS_CMDQ_CQ_ADDR_H_REG 0x2C 34 #define ERDMA_REGS_CMDQ_DEPTH_REG 0x30 35 #define ERDMA_REGS_CMDQ_EQ_DEPTH_REG 0x34 36 #define ERDMA_REGS_CMDQ_EQ_ADDR_L_REG 0x38 37 #define ERDMA_REGS_CMDQ_EQ_ADDR_H_REG 0x3C 38 #define ERDMA_REGS_AEQ_ADDR_L_REG 0x40 39 #define ERDMA_REGS_AEQ_ADDR_H_REG 0x44 40 #define ERDMA_REGS_AEQ_DEPTH_REG 0x48 41 #define ERDMA_REGS_GRP_NUM_REG 0x4c 42 #define ERDMA_REGS_AEQ_DB_REG 0x50 43 #define ERDMA_CMDQ_SQ_DB_HOST_ADDR_REG 0x60 44 #define ERDMA_CMDQ_CQ_DB_HOST_ADDR_REG 0x68 45 #define ERDMA_CMDQ_EQ_DB_HOST_ADDR_REG 0x70 46 #define ERDMA_AEQ_DB_HOST_ADDR_REG 0x78 47 #define ERDMA_REGS_STATS_TSO_IN_PKTS_REG 0x80 48 #define ERDMA_REGS_STATS_TSO_OUT_PKTS_REG 0x88 49 #define ERDMA_REGS_STATS_TSO_OUT_BYTES_REG 0x90 50 #define ERDMA_REGS_STATS_TX_DROP_PKTS_REG 0x98 51 #define ERDMA_REGS_STATS_TX_BPS_METER_DROP_PKTS_REG 0xa0 52 #define ERDMA_REGS_STATS_TX_PPS_METER_DROP_PKTS_REG 0xa8 53 #define ERDMA_REGS_STATS_RX_PKTS_REG 0xc0 54 #define ERDMA_REGS_STATS_RX_BYTES_REG 0xc8 55 #define ERDMA_REGS_STATS_RX_DROP_PKTS_REG 0xd0 56 #define ERDMA_REGS_STATS_RX_BPS_METER_DROP_PKTS_REG 0xd8 57 #define ERDMA_REGS_STATS_RX_PPS_METER_DROP_PKTS_REG 0xe0 58 #define ERDMA_REGS_CEQ_DB_BASE_REG 0x100 59 #define ERDMA_CMDQ_SQDB_REG 0x200 60 #define ERDMA_CMDQ_CQDB_REG 0x300 61 62 /* DEV_CTRL_REG details. */ 63 #define ERDMA_REG_DEV_CTRL_RESET_MASK 0x00000001 64 #define ERDMA_REG_DEV_CTRL_INIT_MASK 0x00000002 65 66 /* DEV_ST_REG details. */ 67 #define ERDMA_REG_DEV_ST_RESET_DONE_MASK 0x00000001U 68 #define ERDMA_REG_DEV_ST_INIT_DONE_MASK 0x00000002U 69 70 /* eRDMA PCIe DBs definition. */ 71 #define ERDMA_BAR_DB_SPACE_BASE 4096 72 73 #define ERDMA_BAR_SQDB_SPACE_OFFSET ERDMA_BAR_DB_SPACE_BASE 74 #define ERDMA_BAR_SQDB_SPACE_SIZE (384 * 1024) 75 76 #define ERDMA_BAR_RQDB_SPACE_OFFSET \ 77 (ERDMA_BAR_SQDB_SPACE_OFFSET + ERDMA_BAR_SQDB_SPACE_SIZE) 78 #define ERDMA_BAR_RQDB_SPACE_SIZE (96 * 1024) 79 80 #define ERDMA_BAR_CQDB_SPACE_OFFSET \ 81 (ERDMA_BAR_RQDB_SPACE_OFFSET + ERDMA_BAR_RQDB_SPACE_SIZE) 82 83 #define ERDMA_SDB_SHARED_PAGE_INDEX 95 84 85 /* Doorbell related. */ 86 #define ERDMA_DB_SIZE 8 87 88 #define ERDMA_CQDB_IDX_MASK GENMASK_ULL(63, 56) 89 #define ERDMA_CQDB_CQN_MASK GENMASK_ULL(55, 32) 90 #define ERDMA_CQDB_ARM_MASK BIT_ULL(31) 91 #define ERDMA_CQDB_SOL_MASK BIT_ULL(30) 92 #define ERDMA_CQDB_CMDSN_MASK GENMASK_ULL(29, 28) 93 #define ERDMA_CQDB_CI_MASK GENMASK_ULL(23, 0) 94 95 #define ERDMA_EQDB_ARM_MASK BIT(31) 96 #define ERDMA_EQDB_CI_MASK GENMASK_ULL(23, 0) 97 98 #define ERDMA_PAGE_SIZE_SUPPORT 0x7FFFF000 99 100 /* Hardware page size definition */ 101 #define ERDMA_HW_PAGE_SHIFT 12 102 #define ERDMA_HW_PAGE_SIZE 4096 103 104 /* WQE related. */ 105 #define EQE_SIZE 16 106 #define EQE_SHIFT 4 107 #define RQE_SIZE 32 108 #define RQE_SHIFT 5 109 #define CQE_SIZE 32 110 #define CQE_SHIFT 5 111 #define SQEBB_SIZE 32 112 #define SQEBB_SHIFT 5 113 #define SQEBB_MASK (~(SQEBB_SIZE - 1)) 114 #define SQEBB_ALIGN(size) ((size + SQEBB_SIZE - 1) & SQEBB_MASK) 115 #define SQEBB_COUNT(size) (SQEBB_ALIGN(size) >> SQEBB_SHIFT) 116 117 #define ERDMA_MAX_SQE_SIZE 128 118 #define ERDMA_MAX_WQEBB_PER_SQE 4 119 120 /* CMDQ related. */ 121 #define ERDMA_CMDQ_MAX_OUTSTANDING 128 122 #define ERDMA_CMDQ_SQE_SIZE 128 123 124 /* cmdq sub module definition. */ 125 enum CMDQ_WQE_SUB_MOD { 126 CMDQ_SUBMOD_RDMA = 0, 127 CMDQ_SUBMOD_COMMON = 1 128 }; 129 130 enum CMDQ_RDMA_OPCODE { 131 CMDQ_OPCODE_QUERY_DEVICE = 0, 132 CMDQ_OPCODE_CREATE_QP = 1, 133 CMDQ_OPCODE_DESTROY_QP = 2, 134 CMDQ_OPCODE_MODIFY_QP = 3, 135 CMDQ_OPCODE_CREATE_CQ = 4, 136 CMDQ_OPCODE_DESTROY_CQ = 5, 137 CMDQ_OPCODE_REFLUSH = 6, 138 CMDQ_OPCODE_REG_MR = 8, 139 CMDQ_OPCODE_DEREG_MR = 9 140 }; 141 142 enum CMDQ_COMMON_OPCODE { 143 CMDQ_OPCODE_CREATE_EQ = 0, 144 CMDQ_OPCODE_DESTROY_EQ = 1, 145 CMDQ_OPCODE_QUERY_FW_INFO = 2, 146 CMDQ_OPCODE_CONF_MTU = 3, 147 CMDQ_OPCODE_CONF_DEVICE = 5, 148 CMDQ_OPCODE_ALLOC_DB = 8, 149 CMDQ_OPCODE_FREE_DB = 9, 150 }; 151 152 /* cmdq-SQE HDR */ 153 #define ERDMA_CMD_HDR_WQEBB_CNT_MASK GENMASK_ULL(54, 52) 154 #define ERDMA_CMD_HDR_CONTEXT_COOKIE_MASK GENMASK_ULL(47, 32) 155 #define ERDMA_CMD_HDR_SUB_MOD_MASK GENMASK_ULL(25, 24) 156 #define ERDMA_CMD_HDR_OPCODE_MASK GENMASK_ULL(23, 16) 157 #define ERDMA_CMD_HDR_WQEBB_INDEX_MASK GENMASK_ULL(15, 0) 158 159 struct erdma_cmdq_destroy_cq_req { 160 u64 hdr; 161 u32 cqn; 162 }; 163 164 #define ERDMA_EQ_TYPE_AEQ 0 165 #define ERDMA_EQ_TYPE_CEQ 1 166 167 struct erdma_cmdq_create_eq_req { 168 u64 hdr; 169 u64 qbuf_addr; 170 u8 vector_idx; 171 u8 eqn; 172 u8 depth; 173 u8 qtype; 174 u32 db_dma_addr_l; 175 u32 db_dma_addr_h; 176 }; 177 178 struct erdma_cmdq_destroy_eq_req { 179 u64 hdr; 180 u64 rsvd0; 181 u8 vector_idx; 182 u8 eqn; 183 u8 rsvd1; 184 u8 qtype; 185 }; 186 187 /* config device cfg */ 188 #define ERDMA_CMD_CONFIG_DEVICE_PS_EN_MASK BIT(31) 189 #define ERDMA_CMD_CONFIG_DEVICE_PGSHIFT_MASK GENMASK(4, 0) 190 191 struct erdma_cmdq_config_device_req { 192 u64 hdr; 193 u32 cfg; 194 u32 rsvd[5]; 195 }; 196 197 struct erdma_cmdq_config_mtu_req { 198 u64 hdr; 199 u32 mtu; 200 }; 201 202 /* ext db requests(alloc and free) cfg */ 203 #define ERDMA_CMD_EXT_DB_CQ_EN_MASK BIT(2) 204 #define ERDMA_CMD_EXT_DB_RQ_EN_MASK BIT(1) 205 #define ERDMA_CMD_EXT_DB_SQ_EN_MASK BIT(0) 206 207 struct erdma_cmdq_ext_db_req { 208 u64 hdr; 209 u32 cfg; 210 u16 rdb_off; 211 u16 sdb_off; 212 u16 rsvd0; 213 u16 cdb_off; 214 u32 rsvd1[3]; 215 }; 216 217 /* alloc db response qword 0 definition */ 218 #define ERDMA_CMD_ALLOC_DB_RESP_RDB_MASK GENMASK_ULL(63, 48) 219 #define ERDMA_CMD_ALLOC_DB_RESP_CDB_MASK GENMASK_ULL(47, 32) 220 #define ERDMA_CMD_ALLOC_DB_RESP_SDB_MASK GENMASK_ULL(15, 0) 221 222 /* create_cq cfg0 */ 223 #define ERDMA_CMD_CREATE_CQ_DEPTH_MASK GENMASK(31, 24) 224 #define ERDMA_CMD_CREATE_CQ_PAGESIZE_MASK GENMASK(23, 20) 225 #define ERDMA_CMD_CREATE_CQ_CQN_MASK GENMASK(19, 0) 226 227 /* create_cq cfg1 */ 228 #define ERDMA_CMD_CREATE_CQ_MTT_CNT_MASK GENMASK(31, 16) 229 #define ERDMA_CMD_CREATE_CQ_MTT_LEVEL_MASK BIT(15) 230 #define ERDMA_CMD_CREATE_CQ_MTT_DB_CFG_MASK BIT(11) 231 #define ERDMA_CMD_CREATE_CQ_EQN_MASK GENMASK(9, 0) 232 233 /* create_cq cfg2 */ 234 #define ERDMA_CMD_CREATE_CQ_DB_CFG_MASK GENMASK(15, 0) 235 236 struct erdma_cmdq_create_cq_req { 237 u64 hdr; 238 u32 cfg0; 239 u32 qbuf_addr_l; 240 u32 qbuf_addr_h; 241 u32 cfg1; 242 u64 cq_db_info_addr; 243 u32 first_page_offset; 244 u32 cfg2; 245 }; 246 247 /* regmr/deregmr cfg0 */ 248 #define ERDMA_CMD_MR_VALID_MASK BIT(31) 249 #define ERDMA_CMD_MR_VERSION_MASK GENMASK(30, 28) 250 #define ERDMA_CMD_MR_KEY_MASK GENMASK(27, 20) 251 #define ERDMA_CMD_MR_MPT_IDX_MASK GENMASK(19, 0) 252 253 /* regmr cfg1 */ 254 #define ERDMA_CMD_REGMR_PD_MASK GENMASK(31, 12) 255 #define ERDMA_CMD_REGMR_TYPE_MASK GENMASK(7, 6) 256 #define ERDMA_CMD_REGMR_RIGHT_MASK GENMASK(5, 1) 257 258 /* regmr cfg2 */ 259 #define ERDMA_CMD_REGMR_PAGESIZE_MASK GENMASK(31, 27) 260 #define ERDMA_CMD_REGMR_MTT_PAGESIZE_MASK GENMASK(26, 24) 261 #define ERDMA_CMD_REGMR_MTT_LEVEL_MASK GENMASK(21, 20) 262 #define ERDMA_CMD_REGMR_MTT_CNT_MASK GENMASK(19, 0) 263 264 struct erdma_cmdq_reg_mr_req { 265 u64 hdr; 266 u32 cfg0; 267 u32 cfg1; 268 u64 start_va; 269 u32 size; 270 u32 cfg2; 271 union { 272 u64 phy_addr[4]; 273 struct { 274 u64 rsvd; 275 u32 size_h; 276 u32 mtt_cnt_h; 277 }; 278 }; 279 }; 280 281 struct erdma_cmdq_dereg_mr_req { 282 u64 hdr; 283 u32 cfg; 284 }; 285 286 /* modify qp cfg */ 287 #define ERDMA_CMD_MODIFY_QP_STATE_MASK GENMASK(31, 24) 288 #define ERDMA_CMD_MODIFY_QP_CC_MASK GENMASK(23, 20) 289 #define ERDMA_CMD_MODIFY_QP_QPN_MASK GENMASK(19, 0) 290 291 struct erdma_cmdq_modify_qp_req { 292 u64 hdr; 293 u32 cfg; 294 u32 cookie; 295 __be32 dip; 296 __be32 sip; 297 __be16 sport; 298 __be16 dport; 299 u32 send_nxt; 300 u32 recv_nxt; 301 }; 302 303 /* create qp cfg0 */ 304 #define ERDMA_CMD_CREATE_QP_SQ_DEPTH_MASK GENMASK(31, 20) 305 #define ERDMA_CMD_CREATE_QP_QPN_MASK GENMASK(19, 0) 306 307 /* create qp cfg1 */ 308 #define ERDMA_CMD_CREATE_QP_RQ_DEPTH_MASK GENMASK(31, 20) 309 #define ERDMA_CMD_CREATE_QP_PD_MASK GENMASK(19, 0) 310 311 /* create qp cqn_mtt_cfg */ 312 #define ERDMA_CMD_CREATE_QP_PAGE_SIZE_MASK GENMASK(31, 28) 313 #define ERDMA_CMD_CREATE_QP_DB_CFG_MASK BIT(25) 314 #define ERDMA_CMD_CREATE_QP_CQN_MASK GENMASK(23, 0) 315 316 /* create qp mtt_cfg */ 317 #define ERDMA_CMD_CREATE_QP_PAGE_OFFSET_MASK GENMASK(31, 12) 318 #define ERDMA_CMD_CREATE_QP_MTT_CNT_MASK GENMASK(11, 1) 319 #define ERDMA_CMD_CREATE_QP_MTT_LEVEL_MASK BIT(0) 320 321 /* create qp db cfg */ 322 #define ERDMA_CMD_CREATE_QP_SQDB_CFG_MASK GENMASK(31, 16) 323 #define ERDMA_CMD_CREATE_QP_RQDB_CFG_MASK GENMASK(15, 0) 324 325 #define ERDMA_CMDQ_CREATE_QP_RESP_COOKIE_MASK GENMASK_ULL(31, 0) 326 327 struct erdma_cmdq_create_qp_req { 328 u64 hdr; 329 u32 cfg0; 330 u32 cfg1; 331 u32 sq_cqn_mtt_cfg; 332 u32 rq_cqn_mtt_cfg; 333 u64 sq_buf_addr; 334 u64 rq_buf_addr; 335 u32 sq_mtt_cfg; 336 u32 rq_mtt_cfg; 337 u64 sq_db_info_dma_addr; 338 u64 rq_db_info_dma_addr; 339 340 u64 sq_mtt_entry[3]; 341 u64 rq_mtt_entry[3]; 342 343 u32 db_cfg; 344 }; 345 346 struct erdma_cmdq_destroy_qp_req { 347 u64 hdr; 348 u32 qpn; 349 }; 350 351 struct erdma_cmdq_reflush_req { 352 u64 hdr; 353 u32 qpn; 354 u32 sq_pi; 355 u32 rq_pi; 356 }; 357 358 /* cap qword 0 definition */ 359 #define ERDMA_CMD_DEV_CAP_MAX_CQE_MASK GENMASK_ULL(47, 40) 360 #define ERDMA_CMD_DEV_CAP_FLAGS_MASK GENMASK_ULL(31, 24) 361 #define ERDMA_CMD_DEV_CAP_MAX_RECV_WR_MASK GENMASK_ULL(23, 16) 362 #define ERDMA_CMD_DEV_CAP_MAX_MR_SIZE_MASK GENMASK_ULL(7, 0) 363 364 /* cap qword 1 definition */ 365 #define ERDMA_CMD_DEV_CAP_DMA_LOCAL_KEY_MASK GENMASK_ULL(63, 32) 366 #define ERDMA_CMD_DEV_CAP_DEFAULT_CC_MASK GENMASK_ULL(31, 28) 367 #define ERDMA_CMD_DEV_CAP_QBLOCK_MASK GENMASK_ULL(27, 16) 368 #define ERDMA_CMD_DEV_CAP_MAX_MW_MASK GENMASK_ULL(7, 0) 369 370 #define ERDMA_NQP_PER_QBLOCK 1024 371 372 enum { 373 ERDMA_DEV_CAP_FLAGS_ATOMIC = 1 << 7, 374 ERDMA_DEV_CAP_FLAGS_MTT_VA = 1 << 5, 375 ERDMA_DEV_CAP_FLAGS_EXTEND_DB = 1 << 3, 376 }; 377 378 #define ERDMA_CMD_INFO0_FW_VER_MASK GENMASK_ULL(31, 0) 379 380 /* CQE hdr */ 381 #define ERDMA_CQE_HDR_OWNER_MASK BIT(31) 382 #define ERDMA_CQE_HDR_OPCODE_MASK GENMASK(23, 16) 383 #define ERDMA_CQE_HDR_QTYPE_MASK GENMASK(15, 8) 384 #define ERDMA_CQE_HDR_SYNDROME_MASK GENMASK(7, 0) 385 386 #define ERDMA_CQE_QTYPE_SQ 0 387 #define ERDMA_CQE_QTYPE_RQ 1 388 #define ERDMA_CQE_QTYPE_CMDQ 2 389 390 struct erdma_cqe { 391 __be32 hdr; 392 __be32 qe_idx; 393 __be32 qpn; 394 union { 395 __le32 imm_data; 396 __be32 inv_rkey; 397 }; 398 __be32 size; 399 __be32 rsvd[3]; 400 }; 401 402 struct erdma_sge { 403 __aligned_le64 addr; 404 __le32 length; 405 __le32 key; 406 }; 407 408 /* Receive Queue Element */ 409 struct erdma_rqe { 410 __le16 qe_idx; 411 __le16 rsvd0; 412 __le32 qpn; 413 __le32 rsvd1; 414 __le32 rsvd2; 415 __le64 to; 416 __le32 length; 417 __le32 stag; 418 }; 419 420 /* SQE */ 421 #define ERDMA_SQE_HDR_SGL_LEN_MASK GENMASK_ULL(63, 56) 422 #define ERDMA_SQE_HDR_WQEBB_CNT_MASK GENMASK_ULL(54, 52) 423 #define ERDMA_SQE_HDR_QPN_MASK GENMASK_ULL(51, 32) 424 #define ERDMA_SQE_HDR_OPCODE_MASK GENMASK_ULL(31, 27) 425 #define ERDMA_SQE_HDR_DWQE_MASK BIT_ULL(26) 426 #define ERDMA_SQE_HDR_INLINE_MASK BIT_ULL(25) 427 #define ERDMA_SQE_HDR_FENCE_MASK BIT_ULL(24) 428 #define ERDMA_SQE_HDR_SE_MASK BIT_ULL(23) 429 #define ERDMA_SQE_HDR_CE_MASK BIT_ULL(22) 430 #define ERDMA_SQE_HDR_WQEBB_INDEX_MASK GENMASK_ULL(15, 0) 431 432 /* REG MR attrs */ 433 #define ERDMA_SQE_MR_ACCESS_MASK GENMASK(5, 1) 434 #define ERDMA_SQE_MR_MTT_TYPE_MASK GENMASK(7, 6) 435 #define ERDMA_SQE_MR_MTT_CNT_MASK GENMASK(31, 12) 436 437 struct erdma_write_sqe { 438 __le64 hdr; 439 __be32 imm_data; 440 __le32 length; 441 442 __le32 sink_stag; 443 __le32 sink_to_l; 444 __le32 sink_to_h; 445 446 __le32 rsvd; 447 448 struct erdma_sge sgl[]; 449 }; 450 451 struct erdma_send_sqe { 452 __le64 hdr; 453 union { 454 __be32 imm_data; 455 __le32 invalid_stag; 456 }; 457 458 __le32 length; 459 struct erdma_sge sgl[]; 460 }; 461 462 struct erdma_readreq_sqe { 463 __le64 hdr; 464 __le32 invalid_stag; 465 __le32 length; 466 __le32 sink_stag; 467 __le32 sink_to_l; 468 __le32 sink_to_h; 469 __le32 rsvd; 470 }; 471 472 struct erdma_atomic_sqe { 473 __le64 hdr; 474 __le64 rsvd; 475 __le64 fetchadd_swap_data; 476 __le64 cmp_data; 477 478 struct erdma_sge remote; 479 struct erdma_sge sgl; 480 }; 481 482 struct erdma_reg_mr_sqe { 483 __le64 hdr; 484 __le64 addr; 485 __le32 length; 486 __le32 stag; 487 __le32 attrs; 488 __le32 rsvd; 489 }; 490 491 /* EQ related. */ 492 #define ERDMA_DEFAULT_EQ_DEPTH 4096 493 494 /* ceqe */ 495 #define ERDMA_CEQE_HDR_DB_MASK BIT_ULL(63) 496 #define ERDMA_CEQE_HDR_PI_MASK GENMASK_ULL(55, 32) 497 #define ERDMA_CEQE_HDR_O_MASK BIT_ULL(31) 498 #define ERDMA_CEQE_HDR_CQN_MASK GENMASK_ULL(19, 0) 499 500 /* aeqe */ 501 #define ERDMA_AEQE_HDR_O_MASK BIT(31) 502 #define ERDMA_AEQE_HDR_TYPE_MASK GENMASK(23, 16) 503 #define ERDMA_AEQE_HDR_SUBTYPE_MASK GENMASK(7, 0) 504 505 #define ERDMA_AE_TYPE_QP_FATAL_EVENT 0 506 #define ERDMA_AE_TYPE_QP_ERQ_ERR_EVENT 1 507 #define ERDMA_AE_TYPE_ACC_ERR_EVENT 2 508 #define ERDMA_AE_TYPE_CQ_ERR 3 509 #define ERDMA_AE_TYPE_OTHER_ERROR 4 510 511 struct erdma_aeqe { 512 __le32 hdr; 513 __le32 event_data0; 514 __le32 event_data1; 515 __le32 rsvd; 516 }; 517 518 enum erdma_opcode { 519 ERDMA_OP_WRITE = 0, 520 ERDMA_OP_READ = 1, 521 ERDMA_OP_SEND = 2, 522 ERDMA_OP_SEND_WITH_IMM = 3, 523 524 ERDMA_OP_RECEIVE = 4, 525 ERDMA_OP_RECV_IMM = 5, 526 ERDMA_OP_RECV_INV = 6, 527 528 ERDMA_OP_RSVD0 = 7, 529 ERDMA_OP_RSVD1 = 8, 530 ERDMA_OP_WRITE_WITH_IMM = 9, 531 532 ERDMA_OP_RSVD2 = 10, 533 ERDMA_OP_RSVD3 = 11, 534 535 ERDMA_OP_RSP_SEND_IMM = 12, 536 ERDMA_OP_SEND_WITH_INV = 13, 537 538 ERDMA_OP_REG_MR = 14, 539 ERDMA_OP_LOCAL_INV = 15, 540 ERDMA_OP_READ_WITH_INV = 16, 541 ERDMA_OP_ATOMIC_CAS = 17, 542 ERDMA_OP_ATOMIC_FAA = 18, 543 ERDMA_NUM_OPCODES = 19, 544 ERDMA_OP_INVALID = ERDMA_NUM_OPCODES + 1 545 }; 546 547 enum erdma_wc_status { 548 ERDMA_WC_SUCCESS = 0, 549 ERDMA_WC_GENERAL_ERR = 1, 550 ERDMA_WC_RECV_WQE_FORMAT_ERR = 2, 551 ERDMA_WC_RECV_STAG_INVALID_ERR = 3, 552 ERDMA_WC_RECV_ADDR_VIOLATION_ERR = 4, 553 ERDMA_WC_RECV_RIGHT_VIOLATION_ERR = 5, 554 ERDMA_WC_RECV_PDID_ERR = 6, 555 ERDMA_WC_RECV_WARRPING_ERR = 7, 556 ERDMA_WC_SEND_WQE_FORMAT_ERR = 8, 557 ERDMA_WC_SEND_WQE_ORD_EXCEED = 9, 558 ERDMA_WC_SEND_STAG_INVALID_ERR = 10, 559 ERDMA_WC_SEND_ADDR_VIOLATION_ERR = 11, 560 ERDMA_WC_SEND_RIGHT_VIOLATION_ERR = 12, 561 ERDMA_WC_SEND_PDID_ERR = 13, 562 ERDMA_WC_SEND_WARRPING_ERR = 14, 563 ERDMA_WC_FLUSH_ERR = 15, 564 ERDMA_WC_RETRY_EXC_ERR = 16, 565 ERDMA_NUM_WC_STATUS 566 }; 567 568 enum erdma_vendor_err { 569 ERDMA_WC_VENDOR_NO_ERR = 0, 570 ERDMA_WC_VENDOR_INVALID_RQE = 1, 571 ERDMA_WC_VENDOR_RQE_INVALID_STAG = 2, 572 ERDMA_WC_VENDOR_RQE_ADDR_VIOLATION = 3, 573 ERDMA_WC_VENDOR_RQE_ACCESS_RIGHT_ERR = 4, 574 ERDMA_WC_VENDOR_RQE_INVALID_PD = 5, 575 ERDMA_WC_VENDOR_RQE_WRAP_ERR = 6, 576 ERDMA_WC_VENDOR_INVALID_SQE = 0x20, 577 ERDMA_WC_VENDOR_ZERO_ORD = 0x21, 578 ERDMA_WC_VENDOR_SQE_INVALID_STAG = 0x30, 579 ERDMA_WC_VENDOR_SQE_ADDR_VIOLATION = 0x31, 580 ERDMA_WC_VENDOR_SQE_ACCESS_ERR = 0x32, 581 ERDMA_WC_VENDOR_SQE_INVALID_PD = 0x33, 582 ERDMA_WC_VENDOR_SQE_WARP_ERR = 0x34 583 }; 584 585 #endif 586