1 /* 2 * Xilinx XADC driver 3 * 4 * Copyright 2013-2014 Analog Devices Inc. 5 * Author: Lars-Peter Clauen <lars@metafoo.de> 6 * 7 * Licensed under the GPL-2. 8 * 9 * Documentation for the parts can be found at: 10 * - XADC hardmacro: Xilinx UG480 11 * - ZYNQ XADC interface: Xilinx UG585 12 * - AXI XADC interface: Xilinx PG019 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/device.h> 17 #include <linux/err.h> 18 #include <linux/interrupt.h> 19 #include <linux/io.h> 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/platform_device.h> 24 #include <linux/slab.h> 25 #include <linux/sysfs.h> 26 27 #include <linux/iio/buffer.h> 28 #include <linux/iio/events.h> 29 #include <linux/iio/iio.h> 30 #include <linux/iio/sysfs.h> 31 #include <linux/iio/trigger.h> 32 #include <linux/iio/trigger_consumer.h> 33 #include <linux/iio/triggered_buffer.h> 34 35 #include "xilinx-xadc.h" 36 37 static const unsigned int XADC_ZYNQ_UNMASK_TIMEOUT = 500; 38 39 /* ZYNQ register definitions */ 40 #define XADC_ZYNQ_REG_CFG 0x00 41 #define XADC_ZYNQ_REG_INTSTS 0x04 42 #define XADC_ZYNQ_REG_INTMSK 0x08 43 #define XADC_ZYNQ_REG_STATUS 0x0c 44 #define XADC_ZYNQ_REG_CFIFO 0x10 45 #define XADC_ZYNQ_REG_DFIFO 0x14 46 #define XADC_ZYNQ_REG_CTL 0x18 47 48 #define XADC_ZYNQ_CFG_ENABLE BIT(31) 49 #define XADC_ZYNQ_CFG_CFIFOTH_MASK (0xf << 20) 50 #define XADC_ZYNQ_CFG_CFIFOTH_OFFSET 20 51 #define XADC_ZYNQ_CFG_DFIFOTH_MASK (0xf << 16) 52 #define XADC_ZYNQ_CFG_DFIFOTH_OFFSET 16 53 #define XADC_ZYNQ_CFG_WEDGE BIT(13) 54 #define XADC_ZYNQ_CFG_REDGE BIT(12) 55 #define XADC_ZYNQ_CFG_TCKRATE_MASK (0x3 << 8) 56 #define XADC_ZYNQ_CFG_TCKRATE_DIV2 (0x0 << 8) 57 #define XADC_ZYNQ_CFG_TCKRATE_DIV4 (0x1 << 8) 58 #define XADC_ZYNQ_CFG_TCKRATE_DIV8 (0x2 << 8) 59 #define XADC_ZYNQ_CFG_TCKRATE_DIV16 (0x3 << 8) 60 #define XADC_ZYNQ_CFG_IGAP_MASK 0x1f 61 #define XADC_ZYNQ_CFG_IGAP(x) (x) 62 63 #define XADC_ZYNQ_INT_CFIFO_LTH BIT(9) 64 #define XADC_ZYNQ_INT_DFIFO_GTH BIT(8) 65 #define XADC_ZYNQ_INT_ALARM_MASK 0xff 66 #define XADC_ZYNQ_INT_ALARM_OFFSET 0 67 68 #define XADC_ZYNQ_STATUS_CFIFO_LVL_MASK (0xf << 16) 69 #define XADC_ZYNQ_STATUS_CFIFO_LVL_OFFSET 16 70 #define XADC_ZYNQ_STATUS_DFIFO_LVL_MASK (0xf << 12) 71 #define XADC_ZYNQ_STATUS_DFIFO_LVL_OFFSET 12 72 #define XADC_ZYNQ_STATUS_CFIFOF BIT(11) 73 #define XADC_ZYNQ_STATUS_CFIFOE BIT(10) 74 #define XADC_ZYNQ_STATUS_DFIFOF BIT(9) 75 #define XADC_ZYNQ_STATUS_DFIFOE BIT(8) 76 #define XADC_ZYNQ_STATUS_OT BIT(7) 77 #define XADC_ZYNQ_STATUS_ALM(x) BIT(x) 78 79 #define XADC_ZYNQ_CTL_RESET BIT(4) 80 81 #define XADC_ZYNQ_CMD_NOP 0x00 82 #define XADC_ZYNQ_CMD_READ 0x01 83 #define XADC_ZYNQ_CMD_WRITE 0x02 84 85 #define XADC_ZYNQ_CMD(cmd, addr, data) (((cmd) << 26) | ((addr) << 16) | (data)) 86 87 /* AXI register definitions */ 88 #define XADC_AXI_REG_RESET 0x00 89 #define XADC_AXI_REG_STATUS 0x04 90 #define XADC_AXI_REG_ALARM_STATUS 0x08 91 #define XADC_AXI_REG_CONVST 0x0c 92 #define XADC_AXI_REG_XADC_RESET 0x10 93 #define XADC_AXI_REG_GIER 0x5c 94 #define XADC_AXI_REG_IPISR 0x60 95 #define XADC_AXI_REG_IPIER 0x68 96 #define XADC_AXI_ADC_REG_OFFSET 0x200 97 98 #define XADC_AXI_RESET_MAGIC 0xa 99 #define XADC_AXI_GIER_ENABLE BIT(31) 100 101 #define XADC_AXI_INT_EOS BIT(4) 102 #define XADC_AXI_INT_ALARM_MASK 0x3c0f 103 104 #define XADC_FLAGS_BUFFERED BIT(0) 105 106 static void xadc_write_reg(struct xadc *xadc, unsigned int reg, 107 uint32_t val) 108 { 109 writel(val, xadc->base + reg); 110 } 111 112 static void xadc_read_reg(struct xadc *xadc, unsigned int reg, 113 uint32_t *val) 114 { 115 *val = readl(xadc->base + reg); 116 } 117 118 /* 119 * The ZYNQ interface uses two asynchronous FIFOs for communication with the 120 * XADC. Reads and writes to the XADC register are performed by submitting a 121 * request to the command FIFO (CFIFO), once the request has been completed the 122 * result can be read from the data FIFO (DFIFO). The method currently used in 123 * this driver is to submit the request for a read/write operation, then go to 124 * sleep and wait for an interrupt that signals that a response is available in 125 * the data FIFO. 126 */ 127 128 static void xadc_zynq_write_fifo(struct xadc *xadc, uint32_t *cmd, 129 unsigned int n) 130 { 131 unsigned int i; 132 133 for (i = 0; i < n; i++) 134 xadc_write_reg(xadc, XADC_ZYNQ_REG_CFIFO, cmd[i]); 135 } 136 137 static void xadc_zynq_drain_fifo(struct xadc *xadc) 138 { 139 uint32_t status, tmp; 140 141 xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &status); 142 143 while (!(status & XADC_ZYNQ_STATUS_DFIFOE)) { 144 xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &tmp); 145 xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &status); 146 } 147 } 148 149 static void xadc_zynq_update_intmsk(struct xadc *xadc, unsigned int mask, 150 unsigned int val) 151 { 152 xadc->zynq_intmask &= ~mask; 153 xadc->zynq_intmask |= val; 154 155 xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK, 156 xadc->zynq_intmask | xadc->zynq_masked_alarm); 157 } 158 159 static int xadc_zynq_write_adc_reg(struct xadc *xadc, unsigned int reg, 160 uint16_t val) 161 { 162 uint32_t cmd[1]; 163 uint32_t tmp; 164 int ret; 165 166 spin_lock_irq(&xadc->lock); 167 xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 168 XADC_ZYNQ_INT_DFIFO_GTH); 169 170 reinit_completion(&xadc->completion); 171 172 cmd[0] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_WRITE, reg, val); 173 xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd)); 174 xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp); 175 tmp &= ~XADC_ZYNQ_CFG_DFIFOTH_MASK; 176 tmp |= 0 << XADC_ZYNQ_CFG_DFIFOTH_OFFSET; 177 xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp); 178 179 xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0); 180 spin_unlock_irq(&xadc->lock); 181 182 ret = wait_for_completion_interruptible_timeout(&xadc->completion, HZ); 183 if (ret == 0) 184 ret = -EIO; 185 else 186 ret = 0; 187 188 xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &tmp); 189 190 return ret; 191 } 192 193 static int xadc_zynq_read_adc_reg(struct xadc *xadc, unsigned int reg, 194 uint16_t *val) 195 { 196 uint32_t cmd[2]; 197 uint32_t resp, tmp; 198 int ret; 199 200 cmd[0] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_READ, reg, 0); 201 cmd[1] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_NOP, 0, 0); 202 203 spin_lock_irq(&xadc->lock); 204 xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 205 XADC_ZYNQ_INT_DFIFO_GTH); 206 xadc_zynq_drain_fifo(xadc); 207 reinit_completion(&xadc->completion); 208 209 xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd)); 210 xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp); 211 tmp &= ~XADC_ZYNQ_CFG_DFIFOTH_MASK; 212 tmp |= 1 << XADC_ZYNQ_CFG_DFIFOTH_OFFSET; 213 xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp); 214 215 xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0); 216 spin_unlock_irq(&xadc->lock); 217 ret = wait_for_completion_interruptible_timeout(&xadc->completion, HZ); 218 if (ret == 0) 219 ret = -EIO; 220 if (ret < 0) 221 return ret; 222 223 xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &resp); 224 xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &resp); 225 226 *val = resp & 0xffff; 227 228 return 0; 229 } 230 231 static unsigned int xadc_zynq_transform_alarm(unsigned int alarm) 232 { 233 return ((alarm & 0x80) >> 4) | 234 ((alarm & 0x78) << 1) | 235 (alarm & 0x07); 236 } 237 238 /* 239 * The ZYNQ threshold interrupts are level sensitive. Since we can't make the 240 * threshold condition go way from within the interrupt handler, this means as 241 * soon as a threshold condition is present we would enter the interrupt handler 242 * again and again. To work around this we mask all active thresholds interrupts 243 * in the interrupt handler and start a timer. In this timer we poll the 244 * interrupt status and only if the interrupt is inactive we unmask it again. 245 */ 246 static void xadc_zynq_unmask_worker(struct work_struct *work) 247 { 248 struct xadc *xadc = container_of(work, struct xadc, zynq_unmask_work.work); 249 unsigned int misc_sts, unmask; 250 251 xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &misc_sts); 252 253 misc_sts &= XADC_ZYNQ_INT_ALARM_MASK; 254 255 spin_lock_irq(&xadc->lock); 256 257 /* Clear those bits which are not active anymore */ 258 unmask = (xadc->zynq_masked_alarm ^ misc_sts) & xadc->zynq_masked_alarm; 259 xadc->zynq_masked_alarm &= misc_sts; 260 261 /* Also clear those which are masked out anyway */ 262 xadc->zynq_masked_alarm &= ~xadc->zynq_intmask; 263 264 /* Clear the interrupts before we unmask them */ 265 xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, unmask); 266 267 xadc_zynq_update_intmsk(xadc, 0, 0); 268 269 spin_unlock_irq(&xadc->lock); 270 271 /* if still pending some alarm re-trigger the timer */ 272 if (xadc->zynq_masked_alarm) { 273 schedule_delayed_work(&xadc->zynq_unmask_work, 274 msecs_to_jiffies(XADC_ZYNQ_UNMASK_TIMEOUT)); 275 } 276 277 } 278 279 static irqreturn_t xadc_zynq_interrupt_handler(int irq, void *devid) 280 { 281 struct iio_dev *indio_dev = devid; 282 struct xadc *xadc = iio_priv(indio_dev); 283 uint32_t status; 284 285 xadc_read_reg(xadc, XADC_ZYNQ_REG_INTSTS, &status); 286 287 status &= ~(xadc->zynq_intmask | xadc->zynq_masked_alarm); 288 289 if (!status) 290 return IRQ_NONE; 291 292 spin_lock(&xadc->lock); 293 294 xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, status); 295 296 if (status & XADC_ZYNQ_INT_DFIFO_GTH) { 297 xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 298 XADC_ZYNQ_INT_DFIFO_GTH); 299 complete(&xadc->completion); 300 } 301 302 status &= XADC_ZYNQ_INT_ALARM_MASK; 303 if (status) { 304 xadc->zynq_masked_alarm |= status; 305 /* 306 * mask the current event interrupt, 307 * unmask it when the interrupt is no more active. 308 */ 309 xadc_zynq_update_intmsk(xadc, 0, 0); 310 311 xadc_handle_events(indio_dev, 312 xadc_zynq_transform_alarm(status)); 313 314 /* unmask the required interrupts in timer. */ 315 schedule_delayed_work(&xadc->zynq_unmask_work, 316 msecs_to_jiffies(XADC_ZYNQ_UNMASK_TIMEOUT)); 317 } 318 spin_unlock(&xadc->lock); 319 320 return IRQ_HANDLED; 321 } 322 323 #define XADC_ZYNQ_TCK_RATE_MAX 50000000 324 #define XADC_ZYNQ_IGAP_DEFAULT 20 325 #define XADC_ZYNQ_PCAP_RATE_MAX 200000000 326 327 static int xadc_zynq_setup(struct platform_device *pdev, 328 struct iio_dev *indio_dev, int irq) 329 { 330 struct xadc *xadc = iio_priv(indio_dev); 331 unsigned long pcap_rate; 332 unsigned int tck_div; 333 unsigned int div; 334 unsigned int igap; 335 unsigned int tck_rate; 336 int ret; 337 338 /* TODO: Figure out how to make igap and tck_rate configurable */ 339 igap = XADC_ZYNQ_IGAP_DEFAULT; 340 tck_rate = XADC_ZYNQ_TCK_RATE_MAX; 341 342 xadc->zynq_intmask = ~0; 343 344 pcap_rate = clk_get_rate(xadc->clk); 345 if (!pcap_rate) 346 return -EINVAL; 347 348 if (pcap_rate > XADC_ZYNQ_PCAP_RATE_MAX) { 349 ret = clk_set_rate(xadc->clk, 350 (unsigned long)XADC_ZYNQ_PCAP_RATE_MAX); 351 if (ret) 352 return ret; 353 } 354 355 if (tck_rate > pcap_rate / 2) { 356 div = 2; 357 } else { 358 div = pcap_rate / tck_rate; 359 if (pcap_rate / div > XADC_ZYNQ_TCK_RATE_MAX) 360 div++; 361 } 362 363 if (div <= 3) 364 tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV2; 365 else if (div <= 7) 366 tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV4; 367 else if (div <= 15) 368 tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV8; 369 else 370 tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV16; 371 372 xadc_write_reg(xadc, XADC_ZYNQ_REG_CTL, XADC_ZYNQ_CTL_RESET); 373 xadc_write_reg(xadc, XADC_ZYNQ_REG_CTL, 0); 374 xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, ~0); 375 xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK, xadc->zynq_intmask); 376 xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, XADC_ZYNQ_CFG_ENABLE | 377 XADC_ZYNQ_CFG_REDGE | XADC_ZYNQ_CFG_WEDGE | 378 tck_div | XADC_ZYNQ_CFG_IGAP(igap)); 379 380 if (pcap_rate > XADC_ZYNQ_PCAP_RATE_MAX) { 381 ret = clk_set_rate(xadc->clk, pcap_rate); 382 if (ret) 383 return ret; 384 } 385 386 return 0; 387 } 388 389 static unsigned long xadc_zynq_get_dclk_rate(struct xadc *xadc) 390 { 391 unsigned int div; 392 uint32_t val; 393 394 xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &val); 395 396 switch (val & XADC_ZYNQ_CFG_TCKRATE_MASK) { 397 case XADC_ZYNQ_CFG_TCKRATE_DIV4: 398 div = 4; 399 break; 400 case XADC_ZYNQ_CFG_TCKRATE_DIV8: 401 div = 8; 402 break; 403 case XADC_ZYNQ_CFG_TCKRATE_DIV16: 404 div = 16; 405 break; 406 default: 407 div = 2; 408 break; 409 } 410 411 return clk_get_rate(xadc->clk) / div; 412 } 413 414 static void xadc_zynq_update_alarm(struct xadc *xadc, unsigned int alarm) 415 { 416 unsigned long flags; 417 uint32_t status; 418 419 /* Move OT to bit 7 */ 420 alarm = ((alarm & 0x08) << 4) | ((alarm & 0xf0) >> 1) | (alarm & 0x07); 421 422 spin_lock_irqsave(&xadc->lock, flags); 423 424 /* Clear previous interrupts if any. */ 425 xadc_read_reg(xadc, XADC_ZYNQ_REG_INTSTS, &status); 426 xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, status & alarm); 427 428 xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_ALARM_MASK, 429 ~alarm & XADC_ZYNQ_INT_ALARM_MASK); 430 431 spin_unlock_irqrestore(&xadc->lock, flags); 432 } 433 434 static const struct xadc_ops xadc_zynq_ops = { 435 .read = xadc_zynq_read_adc_reg, 436 .write = xadc_zynq_write_adc_reg, 437 .setup = xadc_zynq_setup, 438 .get_dclk_rate = xadc_zynq_get_dclk_rate, 439 .interrupt_handler = xadc_zynq_interrupt_handler, 440 .update_alarm = xadc_zynq_update_alarm, 441 }; 442 443 static int xadc_axi_read_adc_reg(struct xadc *xadc, unsigned int reg, 444 uint16_t *val) 445 { 446 uint32_t val32; 447 448 xadc_read_reg(xadc, XADC_AXI_ADC_REG_OFFSET + reg * 4, &val32); 449 *val = val32 & 0xffff; 450 451 return 0; 452 } 453 454 static int xadc_axi_write_adc_reg(struct xadc *xadc, unsigned int reg, 455 uint16_t val) 456 { 457 xadc_write_reg(xadc, XADC_AXI_ADC_REG_OFFSET + reg * 4, val); 458 459 return 0; 460 } 461 462 static int xadc_axi_setup(struct platform_device *pdev, 463 struct iio_dev *indio_dev, int irq) 464 { 465 struct xadc *xadc = iio_priv(indio_dev); 466 467 xadc_write_reg(xadc, XADC_AXI_REG_RESET, XADC_AXI_RESET_MAGIC); 468 xadc_write_reg(xadc, XADC_AXI_REG_GIER, XADC_AXI_GIER_ENABLE); 469 470 return 0; 471 } 472 473 static irqreturn_t xadc_axi_interrupt_handler(int irq, void *devid) 474 { 475 struct iio_dev *indio_dev = devid; 476 struct xadc *xadc = iio_priv(indio_dev); 477 uint32_t status, mask; 478 unsigned int events; 479 480 xadc_read_reg(xadc, XADC_AXI_REG_IPISR, &status); 481 xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &mask); 482 status &= mask; 483 484 if (!status) 485 return IRQ_NONE; 486 487 if ((status & XADC_AXI_INT_EOS) && xadc->trigger) 488 iio_trigger_poll(xadc->trigger); 489 490 if (status & XADC_AXI_INT_ALARM_MASK) { 491 /* 492 * The order of the bits in the AXI-XADC status register does 493 * not match the order of the bits in the XADC alarm enable 494 * register. xadc_handle_events() expects the events to be in 495 * the same order as the XADC alarm enable register. 496 */ 497 events = (status & 0x000e) >> 1; 498 events |= (status & 0x0001) << 3; 499 events |= (status & 0x3c00) >> 6; 500 xadc_handle_events(indio_dev, events); 501 } 502 503 xadc_write_reg(xadc, XADC_AXI_REG_IPISR, status); 504 505 return IRQ_HANDLED; 506 } 507 508 static void xadc_axi_update_alarm(struct xadc *xadc, unsigned int alarm) 509 { 510 uint32_t val; 511 unsigned long flags; 512 513 /* 514 * The order of the bits in the AXI-XADC status register does not match 515 * the order of the bits in the XADC alarm enable register. We get 516 * passed the alarm mask in the same order as in the XADC alarm enable 517 * register. 518 */ 519 alarm = ((alarm & 0x07) << 1) | ((alarm & 0x08) >> 3) | 520 ((alarm & 0xf0) << 6); 521 522 spin_lock_irqsave(&xadc->lock, flags); 523 xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val); 524 val &= ~XADC_AXI_INT_ALARM_MASK; 525 val |= alarm; 526 xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val); 527 spin_unlock_irqrestore(&xadc->lock, flags); 528 } 529 530 static unsigned long xadc_axi_get_dclk(struct xadc *xadc) 531 { 532 return clk_get_rate(xadc->clk); 533 } 534 535 static const struct xadc_ops xadc_axi_ops = { 536 .read = xadc_axi_read_adc_reg, 537 .write = xadc_axi_write_adc_reg, 538 .setup = xadc_axi_setup, 539 .get_dclk_rate = xadc_axi_get_dclk, 540 .update_alarm = xadc_axi_update_alarm, 541 .interrupt_handler = xadc_axi_interrupt_handler, 542 .flags = XADC_FLAGS_BUFFERED, 543 }; 544 545 static int _xadc_update_adc_reg(struct xadc *xadc, unsigned int reg, 546 uint16_t mask, uint16_t val) 547 { 548 uint16_t tmp; 549 int ret; 550 551 ret = _xadc_read_adc_reg(xadc, reg, &tmp); 552 if (ret) 553 return ret; 554 555 return _xadc_write_adc_reg(xadc, reg, (tmp & ~mask) | val); 556 } 557 558 static int xadc_update_adc_reg(struct xadc *xadc, unsigned int reg, 559 uint16_t mask, uint16_t val) 560 { 561 int ret; 562 563 mutex_lock(&xadc->mutex); 564 ret = _xadc_update_adc_reg(xadc, reg, mask, val); 565 mutex_unlock(&xadc->mutex); 566 567 return ret; 568 } 569 570 static unsigned long xadc_get_dclk_rate(struct xadc *xadc) 571 { 572 return xadc->ops->get_dclk_rate(xadc); 573 } 574 575 static int xadc_update_scan_mode(struct iio_dev *indio_dev, 576 const unsigned long *mask) 577 { 578 struct xadc *xadc = iio_priv(indio_dev); 579 unsigned int n; 580 581 n = bitmap_weight(mask, indio_dev->masklength); 582 583 kfree(xadc->data); 584 xadc->data = kcalloc(n, sizeof(*xadc->data), GFP_KERNEL); 585 if (!xadc->data) 586 return -ENOMEM; 587 588 return 0; 589 } 590 591 static unsigned int xadc_scan_index_to_channel(unsigned int scan_index) 592 { 593 switch (scan_index) { 594 case 5: 595 return XADC_REG_VCCPINT; 596 case 6: 597 return XADC_REG_VCCPAUX; 598 case 7: 599 return XADC_REG_VCCO_DDR; 600 case 8: 601 return XADC_REG_TEMP; 602 case 9: 603 return XADC_REG_VCCINT; 604 case 10: 605 return XADC_REG_VCCAUX; 606 case 11: 607 return XADC_REG_VPVN; 608 case 12: 609 return XADC_REG_VREFP; 610 case 13: 611 return XADC_REG_VREFN; 612 case 14: 613 return XADC_REG_VCCBRAM; 614 default: 615 return XADC_REG_VAUX(scan_index - 16); 616 } 617 } 618 619 static irqreturn_t xadc_trigger_handler(int irq, void *p) 620 { 621 struct iio_poll_func *pf = p; 622 struct iio_dev *indio_dev = pf->indio_dev; 623 struct xadc *xadc = iio_priv(indio_dev); 624 unsigned int chan; 625 int i, j; 626 627 if (!xadc->data) 628 goto out; 629 630 j = 0; 631 for_each_set_bit(i, indio_dev->active_scan_mask, 632 indio_dev->masklength) { 633 chan = xadc_scan_index_to_channel(i); 634 xadc_read_adc_reg(xadc, chan, &xadc->data[j]); 635 j++; 636 } 637 638 iio_push_to_buffers(indio_dev, xadc->data); 639 640 out: 641 iio_trigger_notify_done(indio_dev->trig); 642 643 return IRQ_HANDLED; 644 } 645 646 static int xadc_trigger_set_state(struct iio_trigger *trigger, bool state) 647 { 648 struct xadc *xadc = iio_trigger_get_drvdata(trigger); 649 unsigned long flags; 650 unsigned int convst; 651 unsigned int val; 652 int ret = 0; 653 654 mutex_lock(&xadc->mutex); 655 656 if (state) { 657 /* Only one of the two triggers can be active at the a time. */ 658 if (xadc->trigger != NULL) { 659 ret = -EBUSY; 660 goto err_out; 661 } else { 662 xadc->trigger = trigger; 663 if (trigger == xadc->convst_trigger) 664 convst = XADC_CONF0_EC; 665 else 666 convst = 0; 667 } 668 ret = _xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF0_EC, 669 convst); 670 if (ret) 671 goto err_out; 672 } else { 673 xadc->trigger = NULL; 674 } 675 676 spin_lock_irqsave(&xadc->lock, flags); 677 xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val); 678 xadc_write_reg(xadc, XADC_AXI_REG_IPISR, val & XADC_AXI_INT_EOS); 679 if (state) 680 val |= XADC_AXI_INT_EOS; 681 else 682 val &= ~XADC_AXI_INT_EOS; 683 xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val); 684 spin_unlock_irqrestore(&xadc->lock, flags); 685 686 err_out: 687 mutex_unlock(&xadc->mutex); 688 689 return ret; 690 } 691 692 static const struct iio_trigger_ops xadc_trigger_ops = { 693 .set_trigger_state = &xadc_trigger_set_state, 694 }; 695 696 static struct iio_trigger *xadc_alloc_trigger(struct iio_dev *indio_dev, 697 const char *name) 698 { 699 struct iio_trigger *trig; 700 int ret; 701 702 trig = iio_trigger_alloc("%s%d-%s", indio_dev->name, 703 indio_dev->id, name); 704 if (trig == NULL) 705 return ERR_PTR(-ENOMEM); 706 707 trig->dev.parent = indio_dev->dev.parent; 708 trig->ops = &xadc_trigger_ops; 709 iio_trigger_set_drvdata(trig, iio_priv(indio_dev)); 710 711 ret = iio_trigger_register(trig); 712 if (ret) 713 goto error_free_trig; 714 715 return trig; 716 717 error_free_trig: 718 iio_trigger_free(trig); 719 return ERR_PTR(ret); 720 } 721 722 static int xadc_power_adc_b(struct xadc *xadc, unsigned int seq_mode) 723 { 724 uint16_t val; 725 726 switch (seq_mode) { 727 case XADC_CONF1_SEQ_SIMULTANEOUS: 728 case XADC_CONF1_SEQ_INDEPENDENT: 729 val = XADC_CONF2_PD_ADC_B; 730 break; 731 default: 732 val = 0; 733 break; 734 } 735 736 return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_PD_MASK, 737 val); 738 } 739 740 static int xadc_get_seq_mode(struct xadc *xadc, unsigned long scan_mode) 741 { 742 unsigned int aux_scan_mode = scan_mode >> 16; 743 744 if (xadc->external_mux_mode == XADC_EXTERNAL_MUX_DUAL) 745 return XADC_CONF1_SEQ_SIMULTANEOUS; 746 747 if ((aux_scan_mode & 0xff00) == 0 || 748 (aux_scan_mode & 0x00ff) == 0) 749 return XADC_CONF1_SEQ_CONTINUOUS; 750 751 return XADC_CONF1_SEQ_SIMULTANEOUS; 752 } 753 754 static int xadc_postdisable(struct iio_dev *indio_dev) 755 { 756 struct xadc *xadc = iio_priv(indio_dev); 757 unsigned long scan_mask; 758 int ret; 759 int i; 760 761 scan_mask = 1; /* Run calibration as part of the sequence */ 762 for (i = 0; i < indio_dev->num_channels; i++) 763 scan_mask |= BIT(indio_dev->channels[i].scan_index); 764 765 /* Enable all channels and calibration */ 766 ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(0), scan_mask & 0xffff); 767 if (ret) 768 return ret; 769 770 ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(1), scan_mask >> 16); 771 if (ret) 772 return ret; 773 774 ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK, 775 XADC_CONF1_SEQ_CONTINUOUS); 776 if (ret) 777 return ret; 778 779 return xadc_power_adc_b(xadc, XADC_CONF1_SEQ_CONTINUOUS); 780 } 781 782 static int xadc_preenable(struct iio_dev *indio_dev) 783 { 784 struct xadc *xadc = iio_priv(indio_dev); 785 unsigned long scan_mask; 786 int seq_mode; 787 int ret; 788 789 ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK, 790 XADC_CONF1_SEQ_DEFAULT); 791 if (ret) 792 goto err; 793 794 scan_mask = *indio_dev->active_scan_mask; 795 seq_mode = xadc_get_seq_mode(xadc, scan_mask); 796 797 ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(0), scan_mask & 0xffff); 798 if (ret) 799 goto err; 800 801 ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(1), scan_mask >> 16); 802 if (ret) 803 goto err; 804 805 ret = xadc_power_adc_b(xadc, seq_mode); 806 if (ret) 807 goto err; 808 809 ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK, 810 seq_mode); 811 if (ret) 812 goto err; 813 814 return 0; 815 err: 816 xadc_postdisable(indio_dev); 817 return ret; 818 } 819 820 static const struct iio_buffer_setup_ops xadc_buffer_ops = { 821 .preenable = &xadc_preenable, 822 .postenable = &iio_triggered_buffer_postenable, 823 .predisable = &iio_triggered_buffer_predisable, 824 .postdisable = &xadc_postdisable, 825 }; 826 827 static int xadc_read_raw(struct iio_dev *indio_dev, 828 struct iio_chan_spec const *chan, int *val, int *val2, long info) 829 { 830 struct xadc *xadc = iio_priv(indio_dev); 831 unsigned int div; 832 uint16_t val16; 833 int ret; 834 835 switch (info) { 836 case IIO_CHAN_INFO_RAW: 837 if (iio_buffer_enabled(indio_dev)) 838 return -EBUSY; 839 ret = xadc_read_adc_reg(xadc, chan->address, &val16); 840 if (ret < 0) 841 return ret; 842 843 val16 >>= 4; 844 if (chan->scan_type.sign == 'u') 845 *val = val16; 846 else 847 *val = sign_extend32(val16, 11); 848 849 return IIO_VAL_INT; 850 case IIO_CHAN_INFO_SCALE: 851 switch (chan->type) { 852 case IIO_VOLTAGE: 853 /* V = (val * 3.0) / 4096 */ 854 switch (chan->address) { 855 case XADC_REG_VCCINT: 856 case XADC_REG_VCCAUX: 857 case XADC_REG_VREFP: 858 case XADC_REG_VREFN: 859 case XADC_REG_VCCBRAM: 860 case XADC_REG_VCCPINT: 861 case XADC_REG_VCCPAUX: 862 case XADC_REG_VCCO_DDR: 863 *val = 3000; 864 break; 865 default: 866 *val = 1000; 867 break; 868 } 869 *val2 = 12; 870 return IIO_VAL_FRACTIONAL_LOG2; 871 case IIO_TEMP: 872 /* Temp in C = (val * 503.975) / 4096 - 273.15 */ 873 *val = 503975; 874 *val2 = 12; 875 return IIO_VAL_FRACTIONAL_LOG2; 876 default: 877 return -EINVAL; 878 } 879 case IIO_CHAN_INFO_OFFSET: 880 /* Only the temperature channel has an offset */ 881 *val = -((273150 << 12) / 503975); 882 return IIO_VAL_INT; 883 case IIO_CHAN_INFO_SAMP_FREQ: 884 ret = xadc_read_adc_reg(xadc, XADC_REG_CONF2, &val16); 885 if (ret) 886 return ret; 887 888 div = (val16 & XADC_CONF2_DIV_MASK) >> XADC_CONF2_DIV_OFFSET; 889 if (div < 2) 890 div = 2; 891 892 *val = xadc_get_dclk_rate(xadc) / div / 26; 893 894 return IIO_VAL_INT; 895 default: 896 return -EINVAL; 897 } 898 } 899 900 static int xadc_write_raw(struct iio_dev *indio_dev, 901 struct iio_chan_spec const *chan, int val, int val2, long info) 902 { 903 struct xadc *xadc = iio_priv(indio_dev); 904 unsigned long clk_rate = xadc_get_dclk_rate(xadc); 905 unsigned int div; 906 907 if (!clk_rate) 908 return -EINVAL; 909 910 if (info != IIO_CHAN_INFO_SAMP_FREQ) 911 return -EINVAL; 912 913 if (val <= 0) 914 return -EINVAL; 915 916 /* Max. 150 kSPS */ 917 if (val > 150000) 918 val = 150000; 919 920 val *= 26; 921 922 /* Min 1MHz */ 923 if (val < 1000000) 924 val = 1000000; 925 926 /* 927 * We want to round down, but only if we do not exceed the 150 kSPS 928 * limit. 929 */ 930 div = clk_rate / val; 931 if (clk_rate / div / 26 > 150000) 932 div++; 933 if (div < 2) 934 div = 2; 935 else if (div > 0xff) 936 div = 0xff; 937 938 return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_DIV_MASK, 939 div << XADC_CONF2_DIV_OFFSET); 940 } 941 942 static const struct iio_event_spec xadc_temp_events[] = { 943 { 944 .type = IIO_EV_TYPE_THRESH, 945 .dir = IIO_EV_DIR_RISING, 946 .mask_separate = BIT(IIO_EV_INFO_ENABLE) | 947 BIT(IIO_EV_INFO_VALUE) | 948 BIT(IIO_EV_INFO_HYSTERESIS), 949 }, 950 }; 951 952 /* Separate values for upper and lower thresholds, but only a shared enabled */ 953 static const struct iio_event_spec xadc_voltage_events[] = { 954 { 955 .type = IIO_EV_TYPE_THRESH, 956 .dir = IIO_EV_DIR_RISING, 957 .mask_separate = BIT(IIO_EV_INFO_VALUE), 958 }, { 959 .type = IIO_EV_TYPE_THRESH, 960 .dir = IIO_EV_DIR_FALLING, 961 .mask_separate = BIT(IIO_EV_INFO_VALUE), 962 }, { 963 .type = IIO_EV_TYPE_THRESH, 964 .dir = IIO_EV_DIR_EITHER, 965 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 966 }, 967 }; 968 969 #define XADC_CHAN_TEMP(_chan, _scan_index, _addr) { \ 970 .type = IIO_TEMP, \ 971 .indexed = 1, \ 972 .channel = (_chan), \ 973 .address = (_addr), \ 974 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 975 BIT(IIO_CHAN_INFO_SCALE) | \ 976 BIT(IIO_CHAN_INFO_OFFSET), \ 977 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 978 .event_spec = xadc_temp_events, \ 979 .num_event_specs = ARRAY_SIZE(xadc_temp_events), \ 980 .scan_index = (_scan_index), \ 981 .scan_type = { \ 982 .sign = 'u', \ 983 .realbits = 12, \ 984 .storagebits = 16, \ 985 .shift = 4, \ 986 .endianness = IIO_CPU, \ 987 }, \ 988 } 989 990 #define XADC_CHAN_VOLTAGE(_chan, _scan_index, _addr, _ext, _alarm) { \ 991 .type = IIO_VOLTAGE, \ 992 .indexed = 1, \ 993 .channel = (_chan), \ 994 .address = (_addr), \ 995 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 996 BIT(IIO_CHAN_INFO_SCALE), \ 997 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 998 .event_spec = (_alarm) ? xadc_voltage_events : NULL, \ 999 .num_event_specs = (_alarm) ? ARRAY_SIZE(xadc_voltage_events) : 0, \ 1000 .scan_index = (_scan_index), \ 1001 .scan_type = { \ 1002 .sign = ((_addr) == XADC_REG_VREFN) ? 's' : 'u', \ 1003 .realbits = 12, \ 1004 .storagebits = 16, \ 1005 .shift = 4, \ 1006 .endianness = IIO_CPU, \ 1007 }, \ 1008 .extend_name = _ext, \ 1009 } 1010 1011 static const struct iio_chan_spec xadc_channels[] = { 1012 XADC_CHAN_TEMP(0, 8, XADC_REG_TEMP), 1013 XADC_CHAN_VOLTAGE(0, 9, XADC_REG_VCCINT, "vccint", true), 1014 XADC_CHAN_VOLTAGE(1, 10, XADC_REG_VCCAUX, "vccaux", true), 1015 XADC_CHAN_VOLTAGE(2, 14, XADC_REG_VCCBRAM, "vccbram", true), 1016 XADC_CHAN_VOLTAGE(3, 5, XADC_REG_VCCPINT, "vccpint", true), 1017 XADC_CHAN_VOLTAGE(4, 6, XADC_REG_VCCPAUX, "vccpaux", true), 1018 XADC_CHAN_VOLTAGE(5, 7, XADC_REG_VCCO_DDR, "vccoddr", true), 1019 XADC_CHAN_VOLTAGE(6, 12, XADC_REG_VREFP, "vrefp", false), 1020 XADC_CHAN_VOLTAGE(7, 13, XADC_REG_VREFN, "vrefn", false), 1021 XADC_CHAN_VOLTAGE(8, 11, XADC_REG_VPVN, NULL, false), 1022 XADC_CHAN_VOLTAGE(9, 16, XADC_REG_VAUX(0), NULL, false), 1023 XADC_CHAN_VOLTAGE(10, 17, XADC_REG_VAUX(1), NULL, false), 1024 XADC_CHAN_VOLTAGE(11, 18, XADC_REG_VAUX(2), NULL, false), 1025 XADC_CHAN_VOLTAGE(12, 19, XADC_REG_VAUX(3), NULL, false), 1026 XADC_CHAN_VOLTAGE(13, 20, XADC_REG_VAUX(4), NULL, false), 1027 XADC_CHAN_VOLTAGE(14, 21, XADC_REG_VAUX(5), NULL, false), 1028 XADC_CHAN_VOLTAGE(15, 22, XADC_REG_VAUX(6), NULL, false), 1029 XADC_CHAN_VOLTAGE(16, 23, XADC_REG_VAUX(7), NULL, false), 1030 XADC_CHAN_VOLTAGE(17, 24, XADC_REG_VAUX(8), NULL, false), 1031 XADC_CHAN_VOLTAGE(18, 25, XADC_REG_VAUX(9), NULL, false), 1032 XADC_CHAN_VOLTAGE(19, 26, XADC_REG_VAUX(10), NULL, false), 1033 XADC_CHAN_VOLTAGE(20, 27, XADC_REG_VAUX(11), NULL, false), 1034 XADC_CHAN_VOLTAGE(21, 28, XADC_REG_VAUX(12), NULL, false), 1035 XADC_CHAN_VOLTAGE(22, 29, XADC_REG_VAUX(13), NULL, false), 1036 XADC_CHAN_VOLTAGE(23, 30, XADC_REG_VAUX(14), NULL, false), 1037 XADC_CHAN_VOLTAGE(24, 31, XADC_REG_VAUX(15), NULL, false), 1038 }; 1039 1040 static const struct iio_info xadc_info = { 1041 .read_raw = &xadc_read_raw, 1042 .write_raw = &xadc_write_raw, 1043 .read_event_config = &xadc_read_event_config, 1044 .write_event_config = &xadc_write_event_config, 1045 .read_event_value = &xadc_read_event_value, 1046 .write_event_value = &xadc_write_event_value, 1047 .update_scan_mode = &xadc_update_scan_mode, 1048 }; 1049 1050 static const struct of_device_id xadc_of_match_table[] = { 1051 { .compatible = "xlnx,zynq-xadc-1.00.a", (void *)&xadc_zynq_ops }, 1052 { .compatible = "xlnx,axi-xadc-1.00.a", (void *)&xadc_axi_ops }, 1053 { }, 1054 }; 1055 MODULE_DEVICE_TABLE(of, xadc_of_match_table); 1056 1057 static int xadc_parse_dt(struct iio_dev *indio_dev, struct device_node *np, 1058 unsigned int *conf) 1059 { 1060 struct xadc *xadc = iio_priv(indio_dev); 1061 struct iio_chan_spec *channels, *chan; 1062 struct device_node *chan_node, *child; 1063 unsigned int num_channels; 1064 const char *external_mux; 1065 u32 ext_mux_chan; 1066 u32 reg; 1067 int ret; 1068 1069 *conf = 0; 1070 1071 ret = of_property_read_string(np, "xlnx,external-mux", &external_mux); 1072 if (ret < 0 || strcasecmp(external_mux, "none") == 0) 1073 xadc->external_mux_mode = XADC_EXTERNAL_MUX_NONE; 1074 else if (strcasecmp(external_mux, "single") == 0) 1075 xadc->external_mux_mode = XADC_EXTERNAL_MUX_SINGLE; 1076 else if (strcasecmp(external_mux, "dual") == 0) 1077 xadc->external_mux_mode = XADC_EXTERNAL_MUX_DUAL; 1078 else 1079 return -EINVAL; 1080 1081 if (xadc->external_mux_mode != XADC_EXTERNAL_MUX_NONE) { 1082 ret = of_property_read_u32(np, "xlnx,external-mux-channel", 1083 &ext_mux_chan); 1084 if (ret < 0) 1085 return ret; 1086 1087 if (xadc->external_mux_mode == XADC_EXTERNAL_MUX_SINGLE) { 1088 if (ext_mux_chan == 0) 1089 ext_mux_chan = XADC_REG_VPVN; 1090 else if (ext_mux_chan <= 16) 1091 ext_mux_chan = XADC_REG_VAUX(ext_mux_chan - 1); 1092 else 1093 return -EINVAL; 1094 } else { 1095 if (ext_mux_chan > 0 && ext_mux_chan <= 8) 1096 ext_mux_chan = XADC_REG_VAUX(ext_mux_chan - 1); 1097 else 1098 return -EINVAL; 1099 } 1100 1101 *conf |= XADC_CONF0_MUX | XADC_CONF0_CHAN(ext_mux_chan); 1102 } 1103 1104 channels = kmemdup(xadc_channels, sizeof(xadc_channels), GFP_KERNEL); 1105 if (!channels) 1106 return -ENOMEM; 1107 1108 num_channels = 9; 1109 chan = &channels[9]; 1110 1111 chan_node = of_get_child_by_name(np, "xlnx,channels"); 1112 if (chan_node) { 1113 for_each_child_of_node(chan_node, child) { 1114 if (num_channels >= ARRAY_SIZE(xadc_channels)) { 1115 of_node_put(child); 1116 break; 1117 } 1118 1119 ret = of_property_read_u32(child, "reg", ®); 1120 if (ret || reg > 16) 1121 continue; 1122 1123 if (of_property_read_bool(child, "xlnx,bipolar")) 1124 chan->scan_type.sign = 's'; 1125 1126 if (reg == 0) { 1127 chan->scan_index = 11; 1128 chan->address = XADC_REG_VPVN; 1129 } else { 1130 chan->scan_index = 15 + reg; 1131 chan->address = XADC_REG_VAUX(reg - 1); 1132 } 1133 num_channels++; 1134 chan++; 1135 } 1136 } 1137 of_node_put(chan_node); 1138 1139 indio_dev->num_channels = num_channels; 1140 indio_dev->channels = krealloc(channels, sizeof(*channels) * 1141 num_channels, GFP_KERNEL); 1142 /* If we can't resize the channels array, just use the original */ 1143 if (!indio_dev->channels) 1144 indio_dev->channels = channels; 1145 1146 return 0; 1147 } 1148 1149 static int xadc_probe(struct platform_device *pdev) 1150 { 1151 const struct of_device_id *id; 1152 struct iio_dev *indio_dev; 1153 unsigned int bipolar_mask; 1154 struct resource *mem; 1155 unsigned int conf0; 1156 struct xadc *xadc; 1157 int ret; 1158 int irq; 1159 int i; 1160 1161 if (!pdev->dev.of_node) 1162 return -ENODEV; 1163 1164 id = of_match_node(xadc_of_match_table, pdev->dev.of_node); 1165 if (!id) 1166 return -EINVAL; 1167 1168 irq = platform_get_irq(pdev, 0); 1169 if (irq <= 0) 1170 return -ENXIO; 1171 1172 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*xadc)); 1173 if (!indio_dev) 1174 return -ENOMEM; 1175 1176 xadc = iio_priv(indio_dev); 1177 xadc->ops = id->data; 1178 xadc->irq = irq; 1179 init_completion(&xadc->completion); 1180 mutex_init(&xadc->mutex); 1181 spin_lock_init(&xadc->lock); 1182 INIT_DELAYED_WORK(&xadc->zynq_unmask_work, xadc_zynq_unmask_worker); 1183 1184 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1185 xadc->base = devm_ioremap_resource(&pdev->dev, mem); 1186 if (IS_ERR(xadc->base)) 1187 return PTR_ERR(xadc->base); 1188 1189 indio_dev->dev.parent = &pdev->dev; 1190 indio_dev->dev.of_node = pdev->dev.of_node; 1191 indio_dev->name = "xadc"; 1192 indio_dev->modes = INDIO_DIRECT_MODE; 1193 indio_dev->info = &xadc_info; 1194 1195 ret = xadc_parse_dt(indio_dev, pdev->dev.of_node, &conf0); 1196 if (ret) 1197 goto err_device_free; 1198 1199 if (xadc->ops->flags & XADC_FLAGS_BUFFERED) { 1200 ret = iio_triggered_buffer_setup(indio_dev, 1201 &iio_pollfunc_store_time, &xadc_trigger_handler, 1202 &xadc_buffer_ops); 1203 if (ret) 1204 goto err_device_free; 1205 1206 xadc->convst_trigger = xadc_alloc_trigger(indio_dev, "convst"); 1207 if (IS_ERR(xadc->convst_trigger)) { 1208 ret = PTR_ERR(xadc->convst_trigger); 1209 goto err_triggered_buffer_cleanup; 1210 } 1211 xadc->samplerate_trigger = xadc_alloc_trigger(indio_dev, 1212 "samplerate"); 1213 if (IS_ERR(xadc->samplerate_trigger)) { 1214 ret = PTR_ERR(xadc->samplerate_trigger); 1215 goto err_free_convst_trigger; 1216 } 1217 } 1218 1219 xadc->clk = devm_clk_get(&pdev->dev, NULL); 1220 if (IS_ERR(xadc->clk)) { 1221 ret = PTR_ERR(xadc->clk); 1222 goto err_free_samplerate_trigger; 1223 } 1224 1225 ret = clk_prepare_enable(xadc->clk); 1226 if (ret) 1227 goto err_free_samplerate_trigger; 1228 1229 ret = request_irq(xadc->irq, xadc->ops->interrupt_handler, 0, 1230 dev_name(&pdev->dev), indio_dev); 1231 if (ret) 1232 goto err_clk_disable_unprepare; 1233 1234 ret = xadc->ops->setup(pdev, indio_dev, xadc->irq); 1235 if (ret) 1236 goto err_free_irq; 1237 1238 for (i = 0; i < 16; i++) 1239 xadc_read_adc_reg(xadc, XADC_REG_THRESHOLD(i), 1240 &xadc->threshold[i]); 1241 1242 ret = xadc_write_adc_reg(xadc, XADC_REG_CONF0, conf0); 1243 if (ret) 1244 goto err_free_irq; 1245 1246 bipolar_mask = 0; 1247 for (i = 0; i < indio_dev->num_channels; i++) { 1248 if (indio_dev->channels[i].scan_type.sign == 's') 1249 bipolar_mask |= BIT(indio_dev->channels[i].scan_index); 1250 } 1251 1252 ret = xadc_write_adc_reg(xadc, XADC_REG_INPUT_MODE(0), bipolar_mask); 1253 if (ret) 1254 goto err_free_irq; 1255 ret = xadc_write_adc_reg(xadc, XADC_REG_INPUT_MODE(1), 1256 bipolar_mask >> 16); 1257 if (ret) 1258 goto err_free_irq; 1259 1260 /* Disable all alarms */ 1261 ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_ALARM_MASK, 1262 XADC_CONF1_ALARM_MASK); 1263 if (ret) 1264 goto err_free_irq; 1265 1266 /* Set thresholds to min/max */ 1267 for (i = 0; i < 16; i++) { 1268 /* 1269 * Set max voltage threshold and both temperature thresholds to 1270 * 0xffff, min voltage threshold to 0. 1271 */ 1272 if (i % 8 < 4 || i == 7) 1273 xadc->threshold[i] = 0xffff; 1274 else 1275 xadc->threshold[i] = 0; 1276 xadc_write_adc_reg(xadc, XADC_REG_THRESHOLD(i), 1277 xadc->threshold[i]); 1278 } 1279 1280 /* Go to non-buffered mode */ 1281 xadc_postdisable(indio_dev); 1282 1283 ret = iio_device_register(indio_dev); 1284 if (ret) 1285 goto err_free_irq; 1286 1287 platform_set_drvdata(pdev, indio_dev); 1288 1289 return 0; 1290 1291 err_free_irq: 1292 free_irq(xadc->irq, indio_dev); 1293 err_clk_disable_unprepare: 1294 clk_disable_unprepare(xadc->clk); 1295 err_free_samplerate_trigger: 1296 if (xadc->ops->flags & XADC_FLAGS_BUFFERED) 1297 iio_trigger_free(xadc->samplerate_trigger); 1298 err_free_convst_trigger: 1299 if (xadc->ops->flags & XADC_FLAGS_BUFFERED) 1300 iio_trigger_free(xadc->convst_trigger); 1301 err_triggered_buffer_cleanup: 1302 if (xadc->ops->flags & XADC_FLAGS_BUFFERED) 1303 iio_triggered_buffer_cleanup(indio_dev); 1304 err_device_free: 1305 kfree(indio_dev->channels); 1306 1307 return ret; 1308 } 1309 1310 static int xadc_remove(struct platform_device *pdev) 1311 { 1312 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 1313 struct xadc *xadc = iio_priv(indio_dev); 1314 1315 iio_device_unregister(indio_dev); 1316 if (xadc->ops->flags & XADC_FLAGS_BUFFERED) { 1317 iio_trigger_free(xadc->samplerate_trigger); 1318 iio_trigger_free(xadc->convst_trigger); 1319 iio_triggered_buffer_cleanup(indio_dev); 1320 } 1321 free_irq(xadc->irq, indio_dev); 1322 clk_disable_unprepare(xadc->clk); 1323 cancel_delayed_work(&xadc->zynq_unmask_work); 1324 kfree(xadc->data); 1325 kfree(indio_dev->channels); 1326 1327 return 0; 1328 } 1329 1330 static struct platform_driver xadc_driver = { 1331 .probe = xadc_probe, 1332 .remove = xadc_remove, 1333 .driver = { 1334 .name = "xadc", 1335 .of_match_table = xadc_of_match_table, 1336 }, 1337 }; 1338 module_platform_driver(xadc_driver); 1339 1340 MODULE_LICENSE("GPL v2"); 1341 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); 1342 MODULE_DESCRIPTION("Xilinx XADC IIO driver"); 1343