1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * SPI ADC driver for Analog Devices Inc. AD4695 and similar chips 4 * 5 * https://www.analog.com/en/products/ad4695.html 6 * https://www.analog.com/en/products/ad4696.html 7 * https://www.analog.com/en/products/ad4697.html 8 * https://www.analog.com/en/products/ad4698.html 9 * 10 * Copyright 2024 Analog Devices Inc. 11 * Copyright 2024 BayLibre, SAS 12 */ 13 14 #include <linux/bitfield.h> 15 #include <linux/bits.h> 16 #include <linux/compiler.h> 17 #include <linux/delay.h> 18 #include <linux/device.h> 19 #include <linux/err.h> 20 #include <linux/gpio/consumer.h> 21 #include <linux/iio/iio.h> 22 #include <linux/property.h> 23 #include <linux/regmap.h> 24 #include <linux/regulator/consumer.h> 25 #include <linux/spi/spi.h> 26 #include <linux/units.h> 27 28 #include <dt-bindings/iio/adi,ad4695.h> 29 30 /* AD4695 registers */ 31 #define AD4695_REG_SPI_CONFIG_A 0x0000 32 #define AD4695_REG_SPI_CONFIG_A_SW_RST (BIT(7) | BIT(0)) 33 #define AD4695_REG_SPI_CONFIG_B 0x0001 34 #define AD4695_REG_SPI_CONFIG_B_INST_MODE BIT(7) 35 #define AD4695_REG_DEVICE_TYPE 0x0003 36 #define AD4695_REG_SCRATCH_PAD 0x000A 37 #define AD4695_REG_VENDOR_L 0x000C 38 #define AD4695_REG_VENDOR_H 0x000D 39 #define AD4695_REG_LOOP_MODE 0x000E 40 #define AD4695_REG_SPI_CONFIG_C 0x0010 41 #define AD4695_REG_SPI_CONFIG_C_MB_STRICT BIT(7) 42 #define AD4695_REG_SPI_STATUS 0x0011 43 #define AD4695_REG_STATUS 0x0014 44 #define AD4695_REG_ALERT_STATUS1 0x0015 45 #define AD4695_REG_ALERT_STATUS2 0x0016 46 #define AD4695_REG_CLAMP_STATUS 0x001A 47 #define AD4695_REG_SETUP 0x0020 48 #define AD4695_REG_SETUP_LDO_EN BIT(4) 49 #define AD4695_REG_SETUP_SPI_MODE BIT(2) 50 #define AD4695_REG_SETUP_SPI_CYC_CTRL BIT(1) 51 #define AD4695_REG_REF_CTRL 0x0021 52 #define AD4695_REG_REF_CTRL_OV_MODE BIT(7) 53 #define AD4695_REG_REF_CTRL_VREF_SET GENMASK(4, 2) 54 #define AD4695_REG_REF_CTRL_REFHIZ_EN BIT(1) 55 #define AD4695_REG_REF_CTRL_REFBUF_EN BIT(0) 56 #define AD4695_REG_SEQ_CTRL 0x0022 57 #define AD4695_REG_SEQ_CTRL_STD_SEQ_EN BIT(7) 58 #define AD4695_REG_SEQ_CTRL_NUM_SLOTS_AS GENMASK(6, 0) 59 #define AD4695_REG_AC_CTRL 0x0023 60 #define AD4695_REG_STD_SEQ_CONFIG 0x0024 61 #define AD4695_REG_GPIO_CTRL 0x0026 62 #define AD4695_REG_GP_MODE 0x0027 63 #define AD4695_REG_TEMP_CTRL 0x0029 64 #define AD4695_REG_CONFIG_IN(n) (0x0030 | (n)) 65 #define AD4695_REG_CONFIG_IN_MODE BIT(6) 66 #define AD4695_REG_CONFIG_IN_PAIR GENMASK(5, 4) 67 #define AD4695_REG_CONFIG_IN_AINHIGHZ_EN BIT(3) 68 #define AD4695_REG_UPPER_IN(n) (0x0040 | (2 * (n))) 69 #define AD4695_REG_LOWER_IN(n) (0x0060 | (2 * (n))) 70 #define AD4695_REG_HYST_IN(n) (0x0080 | (2 * (n))) 71 #define AD4695_REG_OFFSET_IN(n) (0x00A0 | (2 * (n))) 72 #define AD4695_REG_GAIN_IN(n) (0x00C0 | (2 * (n))) 73 #define AD4695_REG_AS_SLOT(n) (0x0100 | (n)) 74 #define AD4695_REG_AS_SLOT_INX GENMASK(3, 0) 75 #define AD4695_MAX_REG 0x017F 76 77 /* Conversion mode commands */ 78 #define AD4695_CMD_EXIT_CNV_MODE 0x0A 79 #define AD4695_CMD_TEMP_CHAN 0x0F 80 #define AD4695_CMD_VOLTAGE_CHAN(n) (0x10 | (n)) 81 82 /* timing specs */ 83 #define AD4695_T_CONVERT_NS 415 84 #define AD4695_T_WAKEUP_HW_MS 3 85 #define AD4695_T_WAKEUP_SW_MS 3 86 #define AD4695_T_REFBUF_MS 100 87 #define AD4695_REG_ACCESS_SCLK_HZ (10 * MEGA) 88 89 #define AD4695_MAX_CHANNELS 16 90 91 enum ad4695_in_pair { 92 AD4695_IN_PAIR_REFGND, 93 AD4695_IN_PAIR_COM, 94 AD4695_IN_PAIR_EVEN_ODD, 95 }; 96 97 struct ad4695_chip_info { 98 const char *name; 99 int max_sample_rate; 100 u8 num_voltage_inputs; 101 }; 102 103 struct ad4695_channel_config { 104 unsigned int channel; 105 bool highz_en; 106 bool bipolar; 107 enum ad4695_in_pair pin_pairing; 108 unsigned int common_mode_mv; 109 }; 110 111 struct ad4695_state { 112 struct spi_device *spi; 113 struct regmap *regmap; 114 struct gpio_desc *reset_gpio; 115 struct iio_chan_spec iio_chan[AD4695_MAX_CHANNELS + 1]; 116 struct ad4695_channel_config channels_cfg[AD4695_MAX_CHANNELS]; 117 const struct ad4695_chip_info *chip_info; 118 /* Reference voltage. */ 119 unsigned int vref_mv; 120 /* Common mode input pin voltage. */ 121 unsigned int com_mv; 122 /* Raw conversion data received. */ 123 u16 raw_data __aligned(IIO_DMA_MINALIGN); 124 /* Commands to send for single conversion. */ 125 u16 cnv_cmd; 126 u8 cnv_cmd2; 127 }; 128 129 static const struct regmap_range ad4695_regmap_rd_ranges[] = { 130 regmap_reg_range(AD4695_REG_SPI_CONFIG_A, AD4695_REG_SPI_CONFIG_B), 131 regmap_reg_range(AD4695_REG_DEVICE_TYPE, AD4695_REG_DEVICE_TYPE), 132 regmap_reg_range(AD4695_REG_SCRATCH_PAD, AD4695_REG_SCRATCH_PAD), 133 regmap_reg_range(AD4695_REG_VENDOR_L, AD4695_REG_LOOP_MODE), 134 regmap_reg_range(AD4695_REG_SPI_CONFIG_C, AD4695_REG_SPI_STATUS), 135 regmap_reg_range(AD4695_REG_STATUS, AD4695_REG_ALERT_STATUS2), 136 regmap_reg_range(AD4695_REG_CLAMP_STATUS, AD4695_REG_CLAMP_STATUS), 137 regmap_reg_range(AD4695_REG_SETUP, AD4695_REG_TEMP_CTRL), 138 regmap_reg_range(AD4695_REG_CONFIG_IN(0), AD4695_MAX_REG), 139 }; 140 141 static const struct regmap_access_table ad4695_regmap_rd_table = { 142 .yes_ranges = ad4695_regmap_rd_ranges, 143 .n_yes_ranges = ARRAY_SIZE(ad4695_regmap_rd_ranges), 144 }; 145 146 static const struct regmap_range ad4695_regmap_wr_ranges[] = { 147 regmap_reg_range(AD4695_REG_SPI_CONFIG_A, AD4695_REG_SPI_CONFIG_B), 148 regmap_reg_range(AD4695_REG_SCRATCH_PAD, AD4695_REG_SCRATCH_PAD), 149 regmap_reg_range(AD4695_REG_LOOP_MODE, AD4695_REG_LOOP_MODE), 150 regmap_reg_range(AD4695_REG_SPI_CONFIG_C, AD4695_REG_SPI_STATUS), 151 regmap_reg_range(AD4695_REG_SETUP, AD4695_REG_TEMP_CTRL), 152 regmap_reg_range(AD4695_REG_CONFIG_IN(0), AD4695_MAX_REG), 153 }; 154 155 static const struct regmap_access_table ad4695_regmap_wr_table = { 156 .yes_ranges = ad4695_regmap_wr_ranges, 157 .n_yes_ranges = ARRAY_SIZE(ad4695_regmap_wr_ranges), 158 }; 159 160 static const struct regmap_config ad4695_regmap_config = { 161 .name = "ad4695", 162 .reg_bits = 16, 163 .val_bits = 8, 164 .max_register = AD4695_MAX_REG, 165 .rd_table = &ad4695_regmap_rd_table, 166 .wr_table = &ad4695_regmap_wr_table, 167 .can_multi_write = true, 168 }; 169 170 static const struct iio_chan_spec ad4695_channel_template = { 171 .type = IIO_VOLTAGE, 172 .indexed = 1, 173 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 174 BIT(IIO_CHAN_INFO_SCALE) | 175 BIT(IIO_CHAN_INFO_OFFSET), 176 .scan_type = { 177 .sign = 'u', 178 .realbits = 16, 179 .storagebits = 16, 180 }, 181 }; 182 183 static const struct iio_chan_spec ad4695_temp_channel_template = { 184 .address = AD4695_CMD_TEMP_CHAN, 185 .type = IIO_TEMP, 186 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 187 BIT(IIO_CHAN_INFO_SCALE) | 188 BIT(IIO_CHAN_INFO_OFFSET), 189 .scan_type = { 190 .sign = 's', 191 .realbits = 16, 192 .storagebits = 16, 193 }, 194 }; 195 196 static const char * const ad4695_power_supplies[] = { 197 "avdd", "vio" 198 }; 199 200 static const struct ad4695_chip_info ad4695_chip_info = { 201 .name = "ad4695", 202 .max_sample_rate = 500 * KILO, 203 .num_voltage_inputs = 16, 204 }; 205 206 static const struct ad4695_chip_info ad4696_chip_info = { 207 .name = "ad4696", 208 .max_sample_rate = 1 * MEGA, 209 .num_voltage_inputs = 16, 210 }; 211 212 static const struct ad4695_chip_info ad4697_chip_info = { 213 .name = "ad4697", 214 .max_sample_rate = 500 * KILO, 215 .num_voltage_inputs = 8, 216 }; 217 218 static const struct ad4695_chip_info ad4698_chip_info = { 219 .name = "ad4698", 220 .max_sample_rate = 1 * MEGA, 221 .num_voltage_inputs = 8, 222 }; 223 224 /** 225 * ad4695_set_single_cycle_mode - Set the device in single cycle mode 226 * @st: The AD4695 state 227 * @channel: The first channel to read 228 * 229 * As per the datasheet, to enable single cycle mode, we need to set 230 * STD_SEQ_EN=0, NUM_SLOTS_AS=0 and CYC_CTRL=1 (Table 15). Setting SPI_MODE=1 231 * triggers the first conversion using the channel in AS_SLOT0. 232 * 233 * Context: can sleep, must be called with iio_device_claim_direct held 234 * Return: 0 on success, a negative error code on failure 235 */ 236 static int ad4695_set_single_cycle_mode(struct ad4695_state *st, 237 unsigned int channel) 238 { 239 int ret; 240 241 ret = regmap_clear_bits(st->regmap, AD4695_REG_SEQ_CTRL, 242 AD4695_REG_SEQ_CTRL_STD_SEQ_EN | 243 AD4695_REG_SEQ_CTRL_NUM_SLOTS_AS); 244 if (ret) 245 return ret; 246 247 ret = regmap_write(st->regmap, AD4695_REG_AS_SLOT(0), 248 FIELD_PREP(AD4695_REG_AS_SLOT_INX, channel)); 249 if (ret) 250 return ret; 251 252 return regmap_set_bits(st->regmap, AD4695_REG_SETUP, 253 AD4695_REG_SETUP_SPI_MODE | 254 AD4695_REG_SETUP_SPI_CYC_CTRL); 255 } 256 257 static int ad4695_set_ref_voltage(struct ad4695_state *st, int vref_mv) 258 { 259 u8 val; 260 261 if (vref_mv >= 2400 && vref_mv <= 2750) 262 val = 0; 263 else if (vref_mv > 2750 && vref_mv <= 3250) 264 val = 1; 265 else if (vref_mv > 3250 && vref_mv <= 3750) 266 val = 2; 267 else if (vref_mv > 3750 && vref_mv <= 4500) 268 val = 3; 269 else if (vref_mv > 4500 && vref_mv <= 5100) 270 val = 4; 271 else 272 return -EINVAL; 273 274 return regmap_update_bits(st->regmap, AD4695_REG_REF_CTRL, 275 AD4695_REG_REF_CTRL_VREF_SET, 276 FIELD_PREP(AD4695_REG_REF_CTRL_VREF_SET, val)); 277 } 278 279 static int ad4695_write_chn_cfg(struct ad4695_state *st, 280 struct ad4695_channel_config *cfg) 281 { 282 u32 mask, val; 283 284 mask = AD4695_REG_CONFIG_IN_MODE; 285 val = FIELD_PREP(AD4695_REG_CONFIG_IN_MODE, cfg->bipolar ? 1 : 0); 286 287 mask |= AD4695_REG_CONFIG_IN_PAIR; 288 val |= FIELD_PREP(AD4695_REG_CONFIG_IN_PAIR, cfg->pin_pairing); 289 290 mask |= AD4695_REG_CONFIG_IN_AINHIGHZ_EN; 291 val |= FIELD_PREP(AD4695_REG_CONFIG_IN_AINHIGHZ_EN, 292 cfg->highz_en ? 1 : 0); 293 294 return regmap_update_bits(st->regmap, 295 AD4695_REG_CONFIG_IN(cfg->channel), 296 mask, val); 297 } 298 299 /** 300 * ad4695_read_one_sample - Read a single sample using single-cycle mode 301 * @st: The AD4695 state 302 * @address: The address of the channel to read 303 * 304 * Upon successful return, the sample will be stored in `st->raw_data`. 305 * 306 * Context: can sleep, must be called with iio_device_claim_direct held 307 * Return: 0 on success, a negative error code on failure 308 */ 309 static int ad4695_read_one_sample(struct ad4695_state *st, unsigned int address) 310 { 311 struct spi_transfer xfer[2] = { }; 312 int ret, i = 0; 313 314 ret = ad4695_set_single_cycle_mode(st, address); 315 if (ret) 316 return ret; 317 318 /* 319 * Setting the first channel to the temperature channel isn't supported 320 * in single-cycle mode, so we have to do an extra xfer to read the 321 * temperature. 322 */ 323 if (address == AD4695_CMD_TEMP_CHAN) { 324 /* We aren't reading, so we can make this a short xfer. */ 325 st->cnv_cmd2 = AD4695_CMD_TEMP_CHAN << 3; 326 xfer[0].tx_buf = &st->cnv_cmd2; 327 xfer[0].len = 1; 328 xfer[0].cs_change = 1; 329 xfer[0].cs_change_delay.value = AD4695_T_CONVERT_NS; 330 xfer[0].cs_change_delay.unit = SPI_DELAY_UNIT_NSECS; 331 332 i = 1; 333 } 334 335 /* Then read the result and exit conversion mode. */ 336 st->cnv_cmd = AD4695_CMD_EXIT_CNV_MODE << 11; 337 xfer[i].bits_per_word = 16; 338 xfer[i].tx_buf = &st->cnv_cmd; 339 xfer[i].rx_buf = &st->raw_data; 340 xfer[i].len = 2; 341 342 return spi_sync_transfer(st->spi, xfer, i + 1); 343 } 344 345 static int ad4695_read_raw(struct iio_dev *indio_dev, 346 struct iio_chan_spec const *chan, 347 int *val, int *val2, long mask) 348 { 349 struct ad4695_state *st = iio_priv(indio_dev); 350 struct ad4695_channel_config *cfg = &st->channels_cfg[chan->scan_index]; 351 u8 realbits = chan->scan_type.realbits; 352 int ret; 353 354 switch (mask) { 355 case IIO_CHAN_INFO_RAW: 356 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) { 357 ret = ad4695_read_one_sample(st, chan->address); 358 if (ret) 359 return ret; 360 361 if (chan->scan_type.sign == 's') 362 *val = sign_extend32(st->raw_data, realbits - 1); 363 else 364 *val = st->raw_data; 365 366 return IIO_VAL_INT; 367 } 368 unreachable(); 369 case IIO_CHAN_INFO_SCALE: 370 switch (chan->type) { 371 case IIO_VOLTAGE: 372 *val = st->vref_mv; 373 *val2 = chan->scan_type.realbits; 374 return IIO_VAL_FRACTIONAL_LOG2; 375 case IIO_TEMP: 376 /* T_scale (°C) = raw * V_REF (mV) / (-1.8 mV/°C * 2^16) */ 377 *val = st->vref_mv * -556; 378 *val2 = 16; 379 return IIO_VAL_FRACTIONAL_LOG2; 380 default: 381 return -EINVAL; 382 } 383 case IIO_CHAN_INFO_OFFSET: 384 switch (chan->type) { 385 case IIO_VOLTAGE: 386 if (cfg->pin_pairing == AD4695_IN_PAIR_COM) 387 *val = st->com_mv * (1 << realbits) / st->vref_mv; 388 else if (cfg->pin_pairing == AD4695_IN_PAIR_EVEN_ODD) 389 *val = cfg->common_mode_mv * (1 << realbits) / st->vref_mv; 390 else 391 *val = 0; 392 393 return IIO_VAL_INT; 394 case IIO_TEMP: 395 /* T_offset (°C) = -725 mV / (-1.8 mV/°C) */ 396 /* T_offset (raw) = T_offset (°C) * (-1.8 mV/°C) * 2^16 / V_REF (mV) */ 397 *val = -47513600; 398 *val2 = st->vref_mv; 399 return IIO_VAL_FRACTIONAL; 400 default: 401 return -EINVAL; 402 } 403 default: 404 return -EINVAL; 405 } 406 } 407 408 static int ad4695_debugfs_reg_access(struct iio_dev *indio_dev, 409 unsigned int reg, 410 unsigned int writeval, 411 unsigned int *readval) 412 { 413 struct ad4695_state *st = iio_priv(indio_dev); 414 415 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) { 416 if (readval) 417 return regmap_read(st->regmap, reg, readval); 418 419 return regmap_write(st->regmap, reg, writeval); 420 } 421 422 unreachable(); 423 } 424 425 static const struct iio_info ad4695_info = { 426 .read_raw = &ad4695_read_raw, 427 .debugfs_reg_access = &ad4695_debugfs_reg_access, 428 }; 429 430 static int ad4695_parse_channel_cfg(struct ad4695_state *st) 431 { 432 struct device *dev = &st->spi->dev; 433 struct ad4695_channel_config *chan_cfg; 434 struct iio_chan_spec *iio_chan; 435 int ret, i; 436 437 /* populate defaults */ 438 for (i = 0; i < st->chip_info->num_voltage_inputs; i++) { 439 chan_cfg = &st->channels_cfg[i]; 440 iio_chan = &st->iio_chan[i]; 441 442 chan_cfg->highz_en = true; 443 chan_cfg->channel = i; 444 445 *iio_chan = ad4695_channel_template; 446 iio_chan->channel = i; 447 iio_chan->scan_index = i; 448 iio_chan->address = AD4695_CMD_VOLTAGE_CHAN(i); 449 } 450 451 /* modify based on firmware description */ 452 device_for_each_child_node_scoped(dev, child) { 453 u32 reg, val; 454 455 ret = fwnode_property_read_u32(child, "reg", ®); 456 if (ret) 457 return dev_err_probe(dev, ret, 458 "failed to read reg property (%s)\n", 459 fwnode_get_name(child)); 460 461 if (reg >= st->chip_info->num_voltage_inputs) 462 return dev_err_probe(dev, -EINVAL, 463 "reg out of range (%s)\n", 464 fwnode_get_name(child)); 465 466 iio_chan = &st->iio_chan[reg]; 467 chan_cfg = &st->channels_cfg[reg]; 468 469 chan_cfg->highz_en = 470 !fwnode_property_read_bool(child, "adi,no-high-z"); 471 chan_cfg->bipolar = fwnode_property_read_bool(child, "bipolar"); 472 473 ret = fwnode_property_read_u32(child, "common-mode-channel", 474 &val); 475 if (ret && ret != -EINVAL) 476 return dev_err_probe(dev, ret, 477 "failed to read common-mode-channel (%s)\n", 478 fwnode_get_name(child)); 479 480 if (ret == -EINVAL || val == AD4695_COMMON_MODE_REFGND) 481 chan_cfg->pin_pairing = AD4695_IN_PAIR_REFGND; 482 else if (val == AD4695_COMMON_MODE_COM) 483 chan_cfg->pin_pairing = AD4695_IN_PAIR_COM; 484 else 485 chan_cfg->pin_pairing = AD4695_IN_PAIR_EVEN_ODD; 486 487 if (chan_cfg->pin_pairing == AD4695_IN_PAIR_EVEN_ODD && 488 val % 2 == 0) 489 return dev_err_probe(dev, -EINVAL, 490 "common-mode-channel must be odd number (%s)\n", 491 fwnode_get_name(child)); 492 493 if (chan_cfg->pin_pairing == AD4695_IN_PAIR_EVEN_ODD && 494 val != reg + 1) 495 return dev_err_probe(dev, -EINVAL, 496 "common-mode-channel must be next consecutive channel (%s)\n", 497 fwnode_get_name(child)); 498 499 if (chan_cfg->pin_pairing == AD4695_IN_PAIR_EVEN_ODD) { 500 char name[5]; 501 502 snprintf(name, sizeof(name), "in%d", reg + 1); 503 504 ret = devm_regulator_get_enable_read_voltage(dev, name); 505 if (ret < 0) 506 return dev_err_probe(dev, ret, 507 "failed to get %s voltage (%s)\n", 508 name, fwnode_get_name(child)); 509 510 chan_cfg->common_mode_mv = ret / 1000; 511 } 512 513 if (chan_cfg->bipolar && 514 chan_cfg->pin_pairing == AD4695_IN_PAIR_REFGND) 515 return dev_err_probe(dev, -EINVAL, 516 "bipolar mode is not available for inputs paired with REFGND (%s).\n", 517 fwnode_get_name(child)); 518 519 if (chan_cfg->bipolar) 520 iio_chan->scan_type.sign = 's'; 521 522 ret = ad4695_write_chn_cfg(st, chan_cfg); 523 if (ret) 524 return ret; 525 } 526 527 /* Temperature channel must be next scan index after voltage channels. */ 528 st->iio_chan[i] = ad4695_temp_channel_template; 529 st->iio_chan[i].scan_index = i; 530 531 return 0; 532 } 533 534 static int ad4695_probe(struct spi_device *spi) 535 { 536 struct device *dev = &spi->dev; 537 struct ad4695_state *st; 538 struct iio_dev *indio_dev; 539 struct gpio_desc *cnv_gpio; 540 bool use_internal_ldo_supply; 541 bool use_internal_ref_buffer; 542 int ret; 543 544 cnv_gpio = devm_gpiod_get_optional(dev, "cnv", GPIOD_OUT_LOW); 545 if (IS_ERR(cnv_gpio)) 546 return dev_err_probe(dev, PTR_ERR(cnv_gpio), 547 "Failed to get CNV GPIO\n"); 548 549 /* Driver currently requires CNV pin to be connected to SPI CS */ 550 if (cnv_gpio) 551 return dev_err_probe(dev, -ENODEV, 552 "CNV GPIO is not supported\n"); 553 554 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 555 if (!indio_dev) 556 return -ENOMEM; 557 558 st = iio_priv(indio_dev); 559 st->spi = spi; 560 561 st->chip_info = spi_get_device_match_data(spi); 562 if (!st->chip_info) 563 return -EINVAL; 564 565 /* Registers cannot be read at the max allowable speed */ 566 spi->max_speed_hz = AD4695_REG_ACCESS_SCLK_HZ; 567 568 st->regmap = devm_regmap_init_spi(spi, &ad4695_regmap_config); 569 if (IS_ERR(st->regmap)) 570 return dev_err_probe(dev, PTR_ERR(st->regmap), 571 "Failed to initialize regmap\n"); 572 573 ret = devm_regulator_bulk_get_enable(dev, 574 ARRAY_SIZE(ad4695_power_supplies), 575 ad4695_power_supplies); 576 if (ret) 577 return dev_err_probe(dev, ret, 578 "Failed to enable power supplies\n"); 579 580 /* If LDO_IN supply is present, then we are using internal LDO. */ 581 ret = devm_regulator_get_enable_optional(dev, "ldo-in"); 582 if (ret < 0 && ret != -ENODEV) 583 return dev_err_probe(dev, ret, 584 "Failed to enable LDO_IN supply\n"); 585 586 use_internal_ldo_supply = ret == 0; 587 588 if (!use_internal_ldo_supply) { 589 /* Otherwise we need an external VDD supply. */ 590 ret = devm_regulator_get_enable(dev, "vdd"); 591 if (ret < 0) 592 return dev_err_probe(dev, ret, 593 "Failed to enable VDD supply\n"); 594 } 595 596 /* If REFIN supply is given, then we are using internal buffer */ 597 ret = devm_regulator_get_enable_read_voltage(dev, "refin"); 598 if (ret < 0 && ret != -ENODEV) 599 return dev_err_probe(dev, ret, "Failed to get REFIN voltage\n"); 600 601 if (ret != -ENODEV) { 602 st->vref_mv = ret / 1000; 603 use_internal_ref_buffer = true; 604 } else { 605 /* Otherwise, we need an external reference. */ 606 ret = devm_regulator_get_enable_read_voltage(dev, "ref"); 607 if (ret < 0) 608 return dev_err_probe(dev, ret, 609 "Failed to get REF voltage\n"); 610 611 st->vref_mv = ret / 1000; 612 use_internal_ref_buffer = false; 613 } 614 615 ret = devm_regulator_get_enable_read_voltage(dev, "com"); 616 if (ret < 0 && ret != -ENODEV) 617 return dev_err_probe(dev, ret, "Failed to get COM voltage\n"); 618 619 st->com_mv = ret == -ENODEV ? 0 : ret / 1000; 620 621 /* 622 * Reset the device using hardware reset if available or fall back to 623 * software reset. 624 */ 625 626 st->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); 627 if (IS_ERR(st->reset_gpio)) 628 return PTR_ERR(st->reset_gpio); 629 630 if (st->reset_gpio) { 631 gpiod_set_value(st->reset_gpio, 0); 632 msleep(AD4695_T_WAKEUP_HW_MS); 633 } else { 634 ret = regmap_write(st->regmap, AD4695_REG_SPI_CONFIG_A, 635 AD4695_REG_SPI_CONFIG_A_SW_RST); 636 if (ret) 637 return ret; 638 639 msleep(AD4695_T_WAKEUP_SW_MS); 640 } 641 642 /* Needed for debugfs since it only access registers 1 byte at a time. */ 643 ret = regmap_set_bits(st->regmap, AD4695_REG_SPI_CONFIG_C, 644 AD4695_REG_SPI_CONFIG_C_MB_STRICT); 645 if (ret) 646 return ret; 647 648 /* Disable internal LDO if it isn't needed. */ 649 ret = regmap_update_bits(st->regmap, AD4695_REG_SETUP, 650 AD4695_REG_SETUP_LDO_EN, 651 FIELD_PREP(AD4695_REG_SETUP_LDO_EN, 652 use_internal_ldo_supply ? 1 : 0)); 653 if (ret) 654 return ret; 655 656 /* configure reference supply */ 657 658 if (device_property_present(dev, "adi,no-ref-current-limit")) { 659 ret = regmap_set_bits(st->regmap, AD4695_REG_REF_CTRL, 660 AD4695_REG_REF_CTRL_OV_MODE); 661 if (ret) 662 return ret; 663 } 664 665 if (device_property_present(dev, "adi,no-ref-high-z")) { 666 if (use_internal_ref_buffer) 667 return dev_err_probe(dev, -EINVAL, 668 "Cannot disable high-Z mode for internal reference buffer\n"); 669 670 ret = regmap_clear_bits(st->regmap, AD4695_REG_REF_CTRL, 671 AD4695_REG_REF_CTRL_REFHIZ_EN); 672 if (ret) 673 return ret; 674 } 675 676 ret = ad4695_set_ref_voltage(st, st->vref_mv); 677 if (ret) 678 return ret; 679 680 if (use_internal_ref_buffer) { 681 ret = regmap_set_bits(st->regmap, AD4695_REG_REF_CTRL, 682 AD4695_REG_REF_CTRL_REFBUF_EN); 683 if (ret) 684 return ret; 685 686 /* Give the capacitor some time to charge up. */ 687 msleep(AD4695_T_REFBUF_MS); 688 } 689 690 ret = ad4695_parse_channel_cfg(st); 691 if (ret) 692 return ret; 693 694 indio_dev->name = st->chip_info->name; 695 indio_dev->info = &ad4695_info; 696 indio_dev->modes = INDIO_DIRECT_MODE; 697 indio_dev->channels = st->iio_chan; 698 indio_dev->num_channels = st->chip_info->num_voltage_inputs + 1; 699 700 return devm_iio_device_register(dev, indio_dev); 701 } 702 703 static const struct spi_device_id ad4695_spi_id_table[] = { 704 { .name = "ad4695", .driver_data = (kernel_ulong_t)&ad4695_chip_info }, 705 { .name = "ad4696", .driver_data = (kernel_ulong_t)&ad4696_chip_info }, 706 { .name = "ad4697", .driver_data = (kernel_ulong_t)&ad4697_chip_info }, 707 { .name = "ad4698", .driver_data = (kernel_ulong_t)&ad4698_chip_info }, 708 { } 709 }; 710 MODULE_DEVICE_TABLE(spi, ad4695_spi_id_table); 711 712 static const struct of_device_id ad4695_of_match_table[] = { 713 { .compatible = "adi,ad4695", .data = &ad4695_chip_info, }, 714 { .compatible = "adi,ad4696", .data = &ad4696_chip_info, }, 715 { .compatible = "adi,ad4697", .data = &ad4697_chip_info, }, 716 { .compatible = "adi,ad4698", .data = &ad4698_chip_info, }, 717 { } 718 }; 719 MODULE_DEVICE_TABLE(of, ad4695_of_match_table); 720 721 static struct spi_driver ad4695_driver = { 722 .driver = { 723 .name = "ad4695", 724 .of_match_table = ad4695_of_match_table, 725 }, 726 .probe = ad4695_probe, 727 .id_table = ad4695_spi_id_table, 728 }; 729 module_spi_driver(ad4695_driver); 730 731 MODULE_AUTHOR("Ramona Gradinariu <ramona.gradinariu@analog.com>"); 732 MODULE_AUTHOR("David Lechner <dlechner@baylibre.com>"); 733 MODULE_DESCRIPTION("Analog Devices AD4695 ADC driver"); 734 MODULE_LICENSE("GPL"); 735