1 /* 2 Copyright (c) 2001,2002 Christer Weinigel <wingel@nano-system.com> 3 4 National Semiconductor SCx200 ACCESS.bus support 5 Also supports the AMD CS5535 and AMD CS5536 6 7 Based on i2c-keywest.c which is: 8 Copyright (c) 2001 Benjamin Herrenschmidt <benh@kernel.crashing.org> 9 Copyright (c) 2000 Philip Edelbrock <phil@stimpy.netroedge.com> 10 11 This program is free software; you can redistribute it and/or 12 modify it under the terms of the GNU General Public License as 13 published by the Free Software Foundation; either version 2 of the 14 License, or (at your option) any later version. 15 16 This program is distributed in the hope that it will be useful, 17 but WITHOUT ANY WARRANTY; without even the implied warranty of 18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 General Public License for more details. 20 21 You should have received a copy of the GNU General Public License 22 along with this program; if not, write to the Free Software 23 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 24 */ 25 26 #include <linux/module.h> 27 #include <linux/errno.h> 28 #include <linux/kernel.h> 29 #include <linux/init.h> 30 #include <linux/i2c.h> 31 #include <linux/smp_lock.h> 32 #include <linux/pci.h> 33 #include <linux/delay.h> 34 #include <linux/mutex.h> 35 #include <asm/io.h> 36 #include <asm/msr.h> 37 38 #include <linux/scx200.h> 39 40 #define NAME "scx200_acb" 41 42 MODULE_AUTHOR("Christer Weinigel <wingel@nano-system.com>"); 43 MODULE_DESCRIPTION("NatSemi SCx200 ACCESS.bus Driver"); 44 MODULE_LICENSE("GPL"); 45 46 #define MAX_DEVICES 4 47 static int base[MAX_DEVICES] = { 0x820, 0x840 }; 48 module_param_array(base, int, NULL, 0); 49 MODULE_PARM_DESC(base, "Base addresses for the ACCESS.bus controllers"); 50 51 #define POLL_TIMEOUT (HZ/5) 52 53 enum scx200_acb_state { 54 state_idle, 55 state_address, 56 state_command, 57 state_repeat_start, 58 state_quick, 59 state_read, 60 state_write, 61 }; 62 63 static const char *scx200_acb_state_name[] = { 64 "idle", 65 "address", 66 "command", 67 "repeat_start", 68 "quick", 69 "read", 70 "write", 71 }; 72 73 /* Physical interface */ 74 struct scx200_acb_iface { 75 struct scx200_acb_iface *next; 76 struct i2c_adapter adapter; 77 unsigned base; 78 struct mutex mutex; 79 80 /* State machine data */ 81 enum scx200_acb_state state; 82 int result; 83 u8 address_byte; 84 u8 command; 85 u8 *ptr; 86 char needs_reset; 87 unsigned len; 88 }; 89 90 /* Register Definitions */ 91 #define ACBSDA (iface->base + 0) 92 #define ACBST (iface->base + 1) 93 #define ACBST_SDAST 0x40 /* SDA Status */ 94 #define ACBST_BER 0x20 95 #define ACBST_NEGACK 0x10 /* Negative Acknowledge */ 96 #define ACBST_STASTR 0x08 /* Stall After Start */ 97 #define ACBST_MASTER 0x02 98 #define ACBCST (iface->base + 2) 99 #define ACBCST_BB 0x02 100 #define ACBCTL1 (iface->base + 3) 101 #define ACBCTL1_STASTRE 0x80 102 #define ACBCTL1_NMINTE 0x40 103 #define ACBCTL1_ACK 0x10 104 #define ACBCTL1_STOP 0x02 105 #define ACBCTL1_START 0x01 106 #define ACBADDR (iface->base + 4) 107 #define ACBCTL2 (iface->base + 5) 108 #define ACBCTL2_ENABLE 0x01 109 110 /************************************************************************/ 111 112 static void scx200_acb_machine(struct scx200_acb_iface *iface, u8 status) 113 { 114 const char *errmsg; 115 116 dev_dbg(&iface->adapter.dev, "state %s, status = 0x%02x\n", 117 scx200_acb_state_name[iface->state], status); 118 119 if (status & ACBST_BER) { 120 errmsg = "bus error"; 121 goto error; 122 } 123 if (!(status & ACBST_MASTER)) { 124 errmsg = "not master"; 125 goto error; 126 } 127 if (status & ACBST_NEGACK) { 128 dev_dbg(&iface->adapter.dev, "negative ack in state %s\n", 129 scx200_acb_state_name[iface->state]); 130 131 iface->state = state_idle; 132 iface->result = -ENXIO; 133 134 outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1); 135 outb(ACBST_STASTR | ACBST_NEGACK, ACBST); 136 return; 137 } 138 139 switch (iface->state) { 140 case state_idle: 141 dev_warn(&iface->adapter.dev, "interrupt in idle state\n"); 142 break; 143 144 case state_address: 145 /* Do a pointer write first */ 146 outb(iface->address_byte & ~1, ACBSDA); 147 148 iface->state = state_command; 149 break; 150 151 case state_command: 152 outb(iface->command, ACBSDA); 153 154 if (iface->address_byte & 1) 155 iface->state = state_repeat_start; 156 else 157 iface->state = state_write; 158 break; 159 160 case state_repeat_start: 161 outb(inb(ACBCTL1) | ACBCTL1_START, ACBCTL1); 162 /* fallthrough */ 163 164 case state_quick: 165 if (iface->address_byte & 1) { 166 if (iface->len == 1) 167 outb(inb(ACBCTL1) | ACBCTL1_ACK, ACBCTL1); 168 else 169 outb(inb(ACBCTL1) & ~ACBCTL1_ACK, ACBCTL1); 170 outb(iface->address_byte, ACBSDA); 171 172 iface->state = state_read; 173 } else { 174 outb(iface->address_byte, ACBSDA); 175 176 iface->state = state_write; 177 } 178 break; 179 180 case state_read: 181 /* Set ACK if receiving the last byte */ 182 if (iface->len == 1) 183 outb(inb(ACBCTL1) | ACBCTL1_ACK, ACBCTL1); 184 else 185 outb(inb(ACBCTL1) & ~ACBCTL1_ACK, ACBCTL1); 186 187 *iface->ptr++ = inb(ACBSDA); 188 --iface->len; 189 190 if (iface->len == 0) { 191 iface->result = 0; 192 iface->state = state_idle; 193 outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1); 194 } 195 196 break; 197 198 case state_write: 199 if (iface->len == 0) { 200 iface->result = 0; 201 iface->state = state_idle; 202 outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1); 203 break; 204 } 205 206 outb(*iface->ptr++, ACBSDA); 207 --iface->len; 208 209 break; 210 } 211 212 return; 213 214 error: 215 dev_err(&iface->adapter.dev, "%s in state %s\n", errmsg, 216 scx200_acb_state_name[iface->state]); 217 218 iface->state = state_idle; 219 iface->result = -EIO; 220 iface->needs_reset = 1; 221 } 222 223 static void scx200_acb_poll(struct scx200_acb_iface *iface) 224 { 225 u8 status; 226 unsigned long timeout; 227 228 timeout = jiffies + POLL_TIMEOUT; 229 while (time_before(jiffies, timeout)) { 230 status = inb(ACBST); 231 if ((status & (ACBST_SDAST|ACBST_BER|ACBST_NEGACK)) != 0) { 232 scx200_acb_machine(iface, status); 233 return; 234 } 235 yield(); 236 } 237 238 dev_err(&iface->adapter.dev, "timeout in state %s\n", 239 scx200_acb_state_name[iface->state]); 240 241 iface->state = state_idle; 242 iface->result = -EIO; 243 iface->needs_reset = 1; 244 } 245 246 static void scx200_acb_reset(struct scx200_acb_iface *iface) 247 { 248 /* Disable the ACCESS.bus device and Configure the SCL 249 frequency: 16 clock cycles */ 250 outb(0x70, ACBCTL2); 251 /* Polling mode */ 252 outb(0, ACBCTL1); 253 /* Disable slave address */ 254 outb(0, ACBADDR); 255 /* Enable the ACCESS.bus device */ 256 outb(inb(ACBCTL2) | ACBCTL2_ENABLE, ACBCTL2); 257 /* Free STALL after START */ 258 outb(inb(ACBCTL1) & ~(ACBCTL1_STASTRE | ACBCTL1_NMINTE), ACBCTL1); 259 /* Send a STOP */ 260 outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1); 261 /* Clear BER, NEGACK and STASTR bits */ 262 outb(ACBST_BER | ACBST_NEGACK | ACBST_STASTR, ACBST); 263 /* Clear BB bit */ 264 outb(inb(ACBCST) | ACBCST_BB, ACBCST); 265 } 266 267 static s32 scx200_acb_smbus_xfer(struct i2c_adapter *adapter, 268 u16 address, unsigned short flags, 269 char rw, u8 command, int size, 270 union i2c_smbus_data *data) 271 { 272 struct scx200_acb_iface *iface = i2c_get_adapdata(adapter); 273 int len; 274 u8 *buffer; 275 u16 cur_word; 276 int rc; 277 278 switch (size) { 279 case I2C_SMBUS_QUICK: 280 len = 0; 281 buffer = NULL; 282 break; 283 284 case I2C_SMBUS_BYTE: 285 len = 1; 286 buffer = rw ? &data->byte : &command; 287 break; 288 289 case I2C_SMBUS_BYTE_DATA: 290 len = 1; 291 buffer = &data->byte; 292 break; 293 294 case I2C_SMBUS_WORD_DATA: 295 len = 2; 296 cur_word = cpu_to_le16(data->word); 297 buffer = (u8 *)&cur_word; 298 break; 299 300 case I2C_SMBUS_BLOCK_DATA: 301 len = data->block[0]; 302 buffer = &data->block[1]; 303 break; 304 305 default: 306 return -EINVAL; 307 } 308 309 dev_dbg(&adapter->dev, 310 "size=%d, address=0x%x, command=0x%x, len=%d, read=%d\n", 311 size, address, command, len, rw); 312 313 if (!len && rw == I2C_SMBUS_READ) { 314 dev_dbg(&adapter->dev, "zero length read\n"); 315 return -EINVAL; 316 } 317 318 mutex_lock(&iface->mutex); 319 320 iface->address_byte = (address << 1) | rw; 321 iface->command = command; 322 iface->ptr = buffer; 323 iface->len = len; 324 iface->result = -EINVAL; 325 iface->needs_reset = 0; 326 327 outb(inb(ACBCTL1) | ACBCTL1_START, ACBCTL1); 328 329 if (size == I2C_SMBUS_QUICK || size == I2C_SMBUS_BYTE) 330 iface->state = state_quick; 331 else 332 iface->state = state_address; 333 334 while (iface->state != state_idle) 335 scx200_acb_poll(iface); 336 337 if (iface->needs_reset) 338 scx200_acb_reset(iface); 339 340 rc = iface->result; 341 342 mutex_unlock(&iface->mutex); 343 344 if (rc == 0 && size == I2C_SMBUS_WORD_DATA && rw == I2C_SMBUS_READ) 345 data->word = le16_to_cpu(cur_word); 346 347 #ifdef DEBUG 348 dev_dbg(&adapter->dev, "transfer done, result: %d", rc); 349 if (buffer) { 350 int i; 351 printk(" data:"); 352 for (i = 0; i < len; ++i) 353 printk(" %02x", buffer[i]); 354 } 355 printk("\n"); 356 #endif 357 358 return rc; 359 } 360 361 static u32 scx200_acb_func(struct i2c_adapter *adapter) 362 { 363 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 364 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 365 I2C_FUNC_SMBUS_BLOCK_DATA; 366 } 367 368 /* For now, we only handle combined mode (smbus) */ 369 static struct i2c_algorithm scx200_acb_algorithm = { 370 .smbus_xfer = scx200_acb_smbus_xfer, 371 .functionality = scx200_acb_func, 372 }; 373 374 static struct scx200_acb_iface *scx200_acb_list; 375 static DECLARE_MUTEX(scx200_acb_list_mutex); 376 377 static int scx200_acb_probe(struct scx200_acb_iface *iface) 378 { 379 u8 val; 380 381 /* Disable the ACCESS.bus device and Configure the SCL 382 frequency: 16 clock cycles */ 383 outb(0x70, ACBCTL2); 384 385 if (inb(ACBCTL2) != 0x70) { 386 pr_debug(NAME ": ACBCTL2 readback failed\n"); 387 return -ENXIO; 388 } 389 390 outb(inb(ACBCTL1) | ACBCTL1_NMINTE, ACBCTL1); 391 392 val = inb(ACBCTL1); 393 if (val) { 394 pr_debug(NAME ": disabled, but ACBCTL1=0x%02x\n", 395 val); 396 return -ENXIO; 397 } 398 399 outb(inb(ACBCTL2) | ACBCTL2_ENABLE, ACBCTL2); 400 401 outb(inb(ACBCTL1) | ACBCTL1_NMINTE, ACBCTL1); 402 403 val = inb(ACBCTL1); 404 if ((val & ACBCTL1_NMINTE) != ACBCTL1_NMINTE) { 405 pr_debug(NAME ": enabled, but NMINTE won't be set, " 406 "ACBCTL1=0x%02x\n", val); 407 return -ENXIO; 408 } 409 410 return 0; 411 } 412 413 static int __init scx200_acb_create(const char *text, int base, int index) 414 { 415 struct scx200_acb_iface *iface; 416 struct i2c_adapter *adapter; 417 int rc; 418 char description[64]; 419 420 iface = kzalloc(sizeof(*iface), GFP_KERNEL); 421 if (!iface) { 422 printk(KERN_ERR NAME ": can't allocate memory\n"); 423 rc = -ENOMEM; 424 goto errout; 425 } 426 427 adapter = &iface->adapter; 428 i2c_set_adapdata(adapter, iface); 429 snprintf(adapter->name, I2C_NAME_SIZE, "%s ACB%d", text, index); 430 adapter->owner = THIS_MODULE; 431 adapter->id = I2C_HW_SMBUS_SCX200; 432 adapter->algo = &scx200_acb_algorithm; 433 adapter->class = I2C_CLASS_HWMON; 434 435 mutex_init(&iface->mutex); 436 437 snprintf(description, sizeof(description), "%s ACCESS.bus [%s]", 438 text, adapter->name); 439 440 if (request_region(base, 8, description) == 0) { 441 printk(KERN_ERR NAME ": can't allocate io 0x%x-0x%x\n", 442 base, base + 8-1); 443 rc = -EBUSY; 444 goto errout_free; 445 } 446 iface->base = base; 447 448 rc = scx200_acb_probe(iface); 449 if (rc) { 450 printk(KERN_WARNING NAME ": probe failed\n"); 451 goto errout_release; 452 } 453 454 scx200_acb_reset(iface); 455 456 if (i2c_add_adapter(adapter) < 0) { 457 printk(KERN_ERR NAME ": failed to register\n"); 458 rc = -ENODEV; 459 goto errout_release; 460 } 461 462 down(&scx200_acb_list_mutex); 463 iface->next = scx200_acb_list; 464 scx200_acb_list = iface; 465 up(&scx200_acb_list_mutex); 466 467 return 0; 468 469 errout_release: 470 release_region(iface->base, 8); 471 errout_free: 472 kfree(iface); 473 errout: 474 return rc; 475 } 476 477 static struct pci_device_id scx200[] = { 478 { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SCx200_BRIDGE) }, 479 { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SC1100_BRIDGE) }, 480 { }, 481 }; 482 483 static struct pci_device_id divil_pci[] = { 484 { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_CS5535_ISA) }, 485 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA) }, 486 { } /* NULL entry */ 487 }; 488 489 #define MSR_LBAR_SMB 0x5140000B 490 491 static int scx200_add_cs553x(void) 492 { 493 u32 low, hi; 494 u32 smb_base; 495 496 /* Grab & reserve the SMB I/O range */ 497 rdmsr(MSR_LBAR_SMB, low, hi); 498 499 /* Check the IO mask and whether SMB is enabled */ 500 if (hi != 0x0000F001) { 501 printk(KERN_WARNING NAME ": SMBus not enabled\n"); 502 return -ENODEV; 503 } 504 505 /* SMBus IO size is 8 bytes */ 506 smb_base = low & 0x0000FFF8; 507 508 return scx200_acb_create("CS5535", smb_base, 0); 509 } 510 511 static int __init scx200_acb_init(void) 512 { 513 int i; 514 int rc = -ENODEV; 515 516 pr_debug(NAME ": NatSemi SCx200 ACCESS.bus Driver\n"); 517 518 /* Verify that this really is a SCx200 processor */ 519 if (pci_dev_present(scx200)) { 520 for (i = 0; i < MAX_DEVICES; ++i) { 521 if (base[i] > 0) 522 rc = scx200_acb_create("SCx200", base[i], i); 523 } 524 } else if (pci_dev_present(divil_pci)) 525 rc = scx200_add_cs553x(); 526 527 return rc; 528 } 529 530 static void __exit scx200_acb_cleanup(void) 531 { 532 struct scx200_acb_iface *iface; 533 534 down(&scx200_acb_list_mutex); 535 while ((iface = scx200_acb_list) != NULL) { 536 scx200_acb_list = iface->next; 537 up(&scx200_acb_list_mutex); 538 539 i2c_del_adapter(&iface->adapter); 540 release_region(iface->base, 8); 541 kfree(iface); 542 down(&scx200_acb_list_mutex); 543 } 544 up(&scx200_acb_list_mutex); 545 } 546 547 module_init(scx200_acb_init); 548 module_exit(scx200_acb_cleanup); 549