1 /* 2 * i2c-au1550.c: SMBus (i2c) adapter for Alchemy PSC interface 3 * Copyright (C) 2004 Embedded Edge, LLC <dan@embeddededge.com> 4 * 5 * 2.6 port by Matt Porter <mporter@kernel.crashing.org> 6 * 7 * The documentation describes this as an SMBus controller, but it doesn't 8 * understand any of the SMBus protocol in hardware. It's really an I2C 9 * controller that could emulate most of the SMBus in software. 10 * 11 * This is just a skeleton adapter to use with the Au1550 PSC 12 * algorithm. It was developed for the Pb1550, but will work with 13 * any Au1550 board that has a similar PSC configuration. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License 17 * as published by the Free Software Foundation; either version 2 18 * of the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 28 */ 29 30 #include <linux/delay.h> 31 #include <linux/kernel.h> 32 #include <linux/module.h> 33 #include <linux/init.h> 34 #include <linux/errno.h> 35 #include <linux/i2c.h> 36 37 #include <asm/mach-au1x00/au1xxx.h> 38 #include <asm/mach-au1x00/au1xxx_psc.h> 39 40 #include "i2c-au1550.h" 41 42 static int 43 wait_xfer_done(struct i2c_au1550_data *adap) 44 { 45 u32 stat; 46 int i; 47 volatile psc_smb_t *sp; 48 49 sp = (volatile psc_smb_t *)(adap->psc_base); 50 51 /* Wait for Tx Buffer Empty 52 */ 53 for (i = 0; i < adap->xfer_timeout; i++) { 54 stat = sp->psc_smbstat; 55 au_sync(); 56 if ((stat & PSC_SMBSTAT_TE) != 0) 57 return 0; 58 59 udelay(1); 60 } 61 62 return -ETIMEDOUT; 63 } 64 65 static int 66 wait_ack(struct i2c_au1550_data *adap) 67 { 68 u32 stat; 69 volatile psc_smb_t *sp; 70 71 if (wait_xfer_done(adap)) 72 return -ETIMEDOUT; 73 74 sp = (volatile psc_smb_t *)(adap->psc_base); 75 76 stat = sp->psc_smbevnt; 77 au_sync(); 78 79 if ((stat & (PSC_SMBEVNT_DN | PSC_SMBEVNT_AN | PSC_SMBEVNT_AL)) != 0) 80 return -ETIMEDOUT; 81 82 return 0; 83 } 84 85 static int 86 wait_master_done(struct i2c_au1550_data *adap) 87 { 88 u32 stat; 89 int i; 90 volatile psc_smb_t *sp; 91 92 sp = (volatile psc_smb_t *)(adap->psc_base); 93 94 /* Wait for Master Done. 95 */ 96 for (i = 0; i < adap->xfer_timeout; i++) { 97 stat = sp->psc_smbevnt; 98 au_sync(); 99 if ((stat & PSC_SMBEVNT_MD) != 0) 100 return 0; 101 udelay(1); 102 } 103 104 return -ETIMEDOUT; 105 } 106 107 static int 108 do_address(struct i2c_au1550_data *adap, unsigned int addr, int rd) 109 { 110 volatile psc_smb_t *sp; 111 u32 stat; 112 113 sp = (volatile psc_smb_t *)(adap->psc_base); 114 115 /* Reset the FIFOs, clear events. 116 */ 117 stat = sp->psc_smbstat; 118 sp->psc_smbevnt = PSC_SMBEVNT_ALLCLR; 119 au_sync(); 120 121 if (!(stat & PSC_SMBSTAT_TE) || !(stat & PSC_SMBSTAT_RE)) { 122 sp->psc_smbpcr = PSC_SMBPCR_DC; 123 au_sync(); 124 do { 125 stat = sp->psc_smbpcr; 126 au_sync(); 127 } while ((stat & PSC_SMBPCR_DC) != 0); 128 udelay(50); 129 } 130 131 /* Write out the i2c chip address and specify operation 132 */ 133 addr <<= 1; 134 if (rd) 135 addr |= 1; 136 137 /* Put byte into fifo, start up master. 138 */ 139 sp->psc_smbtxrx = addr; 140 au_sync(); 141 sp->psc_smbpcr = PSC_SMBPCR_MS; 142 au_sync(); 143 if (wait_ack(adap)) 144 return -EIO; 145 return 0; 146 } 147 148 static u32 149 wait_for_rx_byte(struct i2c_au1550_data *adap, u32 *ret_data) 150 { 151 int j; 152 u32 data, stat; 153 volatile psc_smb_t *sp; 154 155 if (wait_xfer_done(adap)) 156 return -EIO; 157 158 sp = (volatile psc_smb_t *)(adap->psc_base); 159 160 j = adap->xfer_timeout * 100; 161 do { 162 j--; 163 if (j <= 0) 164 return -EIO; 165 166 stat = sp->psc_smbstat; 167 au_sync(); 168 if ((stat & PSC_SMBSTAT_RE) == 0) 169 j = 0; 170 else 171 udelay(1); 172 } while (j > 0); 173 data = sp->psc_smbtxrx; 174 au_sync(); 175 *ret_data = data; 176 177 return 0; 178 } 179 180 static int 181 i2c_read(struct i2c_au1550_data *adap, unsigned char *buf, 182 unsigned int len) 183 { 184 int i; 185 u32 data; 186 volatile psc_smb_t *sp; 187 188 if (len == 0) 189 return 0; 190 191 /* A read is performed by stuffing the transmit fifo with 192 * zero bytes for timing, waiting for bytes to appear in the 193 * receive fifo, then reading the bytes. 194 */ 195 196 sp = (volatile psc_smb_t *)(adap->psc_base); 197 198 i = 0; 199 while (i < (len-1)) { 200 sp->psc_smbtxrx = 0; 201 au_sync(); 202 if (wait_for_rx_byte(adap, &data)) 203 return -EIO; 204 205 buf[i] = data; 206 i++; 207 } 208 209 /* The last byte has to indicate transfer done. 210 */ 211 sp->psc_smbtxrx = PSC_SMBTXRX_STP; 212 au_sync(); 213 if (wait_master_done(adap)) 214 return -EIO; 215 216 data = sp->psc_smbtxrx; 217 au_sync(); 218 buf[i] = data; 219 return 0; 220 } 221 222 static int 223 i2c_write(struct i2c_au1550_data *adap, unsigned char *buf, 224 unsigned int len) 225 { 226 int i; 227 u32 data; 228 volatile psc_smb_t *sp; 229 230 if (len == 0) 231 return 0; 232 233 sp = (volatile psc_smb_t *)(adap->psc_base); 234 235 i = 0; 236 while (i < (len-1)) { 237 data = buf[i]; 238 sp->psc_smbtxrx = data; 239 au_sync(); 240 if (wait_ack(adap)) 241 return -EIO; 242 i++; 243 } 244 245 /* The last byte has to indicate transfer done. 246 */ 247 data = buf[i]; 248 data |= PSC_SMBTXRX_STP; 249 sp->psc_smbtxrx = data; 250 au_sync(); 251 if (wait_master_done(adap)) 252 return -EIO; 253 return 0; 254 } 255 256 static int 257 au1550_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num) 258 { 259 struct i2c_au1550_data *adap = i2c_adap->algo_data; 260 struct i2c_msg *p; 261 int i, err = 0; 262 263 for (i = 0; !err && i < num; i++) { 264 p = &msgs[i]; 265 err = do_address(adap, p->addr, p->flags & I2C_M_RD); 266 if (err || !p->len) 267 continue; 268 if (p->flags & I2C_M_RD) 269 err = i2c_read(adap, p->buf, p->len); 270 else 271 err = i2c_write(adap, p->buf, p->len); 272 } 273 274 /* Return the number of messages processed, or the error code. 275 */ 276 if (err == 0) 277 err = num; 278 return err; 279 } 280 281 static u32 282 au1550_func(struct i2c_adapter *adap) 283 { 284 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 285 } 286 287 static const struct i2c_algorithm au1550_algo = { 288 .master_xfer = au1550_xfer, 289 .functionality = au1550_func, 290 }; 291 292 /* 293 * registering functions to load algorithms at runtime 294 * Prior to calling us, the 50MHz clock frequency and routing 295 * must have been set up for the PSC indicated by the adapter. 296 */ 297 int 298 i2c_au1550_add_bus(struct i2c_adapter *i2c_adap) 299 { 300 struct i2c_au1550_data *adap = i2c_adap->algo_data; 301 volatile psc_smb_t *sp; 302 u32 stat; 303 304 i2c_adap->algo = &au1550_algo; 305 306 /* Now, set up the PSC for SMBus PIO mode. 307 */ 308 sp = (volatile psc_smb_t *)(adap->psc_base); 309 sp->psc_ctrl = PSC_CTRL_DISABLE; 310 au_sync(); 311 sp->psc_sel = PSC_SEL_PS_SMBUSMODE; 312 sp->psc_smbcfg = 0; 313 au_sync(); 314 sp->psc_ctrl = PSC_CTRL_ENABLE; 315 au_sync(); 316 do { 317 stat = sp->psc_smbstat; 318 au_sync(); 319 } while ((stat & PSC_SMBSTAT_SR) == 0); 320 321 sp->psc_smbcfg = (PSC_SMBCFG_RT_FIFO8 | PSC_SMBCFG_TT_FIFO8 | 322 PSC_SMBCFG_DD_DISABLE); 323 324 /* Divide by 8 to get a 6.25 MHz clock. The later protocol 325 * timings are based on this clock. 326 */ 327 sp->psc_smbcfg |= PSC_SMBCFG_SET_DIV(PSC_SMBCFG_DIV8); 328 sp->psc_smbmsk = PSC_SMBMSK_ALLMASK; 329 au_sync(); 330 331 /* Set the protocol timer values. See Table 71 in the 332 * Au1550 Data Book for standard timing values. 333 */ 334 sp->psc_smbtmr = PSC_SMBTMR_SET_TH(0) | PSC_SMBTMR_SET_PS(15) | \ 335 PSC_SMBTMR_SET_PU(15) | PSC_SMBTMR_SET_SH(15) | \ 336 PSC_SMBTMR_SET_SU(15) | PSC_SMBTMR_SET_CL(15) | \ 337 PSC_SMBTMR_SET_CH(15); 338 au_sync(); 339 340 sp->psc_smbcfg |= PSC_SMBCFG_DE_ENABLE; 341 do { 342 stat = sp->psc_smbstat; 343 au_sync(); 344 } while ((stat & PSC_SMBSTAT_DR) == 0); 345 346 return i2c_add_adapter(i2c_adap); 347 } 348 349 350 int 351 i2c_au1550_del_bus(struct i2c_adapter *adap) 352 { 353 return i2c_del_adapter(adap); 354 } 355 356 static int 357 pb1550_reg(struct i2c_client *client) 358 { 359 return 0; 360 } 361 362 static int 363 pb1550_unreg(struct i2c_client *client) 364 { 365 return 0; 366 } 367 368 static struct i2c_au1550_data pb1550_i2c_info = { 369 SMBUS_PSC_BASE, 200, 200 370 }; 371 372 static struct i2c_adapter pb1550_board_adapter = { 373 name: "pb1550 adapter", 374 id: I2C_HW_AU1550_PSC, 375 algo: NULL, 376 algo_data: &pb1550_i2c_info, 377 client_register: pb1550_reg, 378 client_unregister: pb1550_unreg, 379 }; 380 381 /* BIG hack to support the control interface on the Wolfson WM8731 382 * audio codec on the Pb1550 board. We get an address and two data 383 * bytes to write, create an i2c message, and send it across the 384 * i2c transfer function. We do this here because we have access to 385 * the i2c adapter structure. 386 */ 387 static struct i2c_msg wm_i2c_msg; /* We don't want this stuff on the stack */ 388 static u8 i2cbuf[2]; 389 390 int 391 pb1550_wm_codec_write(u8 addr, u8 reg, u8 val) 392 { 393 wm_i2c_msg.addr = addr; 394 wm_i2c_msg.flags = 0; 395 wm_i2c_msg.buf = i2cbuf; 396 wm_i2c_msg.len = 2; 397 i2cbuf[0] = reg; 398 i2cbuf[1] = val; 399 400 return pb1550_board_adapter.algo->master_xfer(&pb1550_board_adapter, &wm_i2c_msg, 1); 401 } 402 403 static int __init 404 i2c_au1550_init(void) 405 { 406 printk(KERN_INFO "Au1550 I2C: "); 407 408 /* This is where we would set up a 50MHz clock source 409 * and routing. On the Pb1550, the SMBus is PSC2, which 410 * uses a shared clock with USB. This has been already 411 * configured by Yamon as a 48MHz clock, close enough 412 * for our work. 413 */ 414 if (i2c_au1550_add_bus(&pb1550_board_adapter) < 0) { 415 printk("failed to initialize.\n"); 416 return -ENODEV; 417 } 418 419 printk("initialized.\n"); 420 return 0; 421 } 422 423 static void __exit 424 i2c_au1550_exit(void) 425 { 426 i2c_au1550_del_bus(&pb1550_board_adapter); 427 } 428 429 MODULE_AUTHOR("Dan Malek, Embedded Edge, LLC."); 430 MODULE_DESCRIPTION("SMBus adapter Alchemy pb1550"); 431 MODULE_LICENSE("GPL"); 432 433 module_init (i2c_au1550_init); 434 module_exit (i2c_au1550_exit); 435