xref: /linux/drivers/hwmon/asus-ec-sensors.c (revision 3b9dfd9e59367eff5f65ef2a850f2df674f1f1c5)
1d0ddfd24SEugene Shalygin // SPDX-License-Identifier: GPL-2.0+
2d0ddfd24SEugene Shalygin /*
3d0ddfd24SEugene Shalygin  * HWMON driver for ASUS motherboards that publish some sensor values
4d0ddfd24SEugene Shalygin  * via the embedded controller registers.
5d0ddfd24SEugene Shalygin  *
6d0ddfd24SEugene Shalygin  * Copyright (C) 2021 Eugene Shalygin <eugene.shalygin@gmail.com>
7d0ddfd24SEugene Shalygin 
8d0ddfd24SEugene Shalygin  * EC provides:
9d0ddfd24SEugene Shalygin  * - Chipset temperature
10d0ddfd24SEugene Shalygin  * - CPU temperature
11d0ddfd24SEugene Shalygin  * - Motherboard temperature
12d0ddfd24SEugene Shalygin  * - T_Sensor temperature
13d0ddfd24SEugene Shalygin  * - VRM temperature
14d0ddfd24SEugene Shalygin  * - Water In temperature
15d0ddfd24SEugene Shalygin  * - Water Out temperature
16d0ddfd24SEugene Shalygin  * - CPU Optional fan RPM
17d0ddfd24SEugene Shalygin  * - Chipset fan RPM
18d0ddfd24SEugene Shalygin  * - VRM Heat Sink fan RPM
19d0ddfd24SEugene Shalygin  * - Water Flow fan RPM
20d0ddfd24SEugene Shalygin  * - CPU current
21f545a2fdSEugene Shalygin  * - CPU core voltage
22d0ddfd24SEugene Shalygin  */
23d0ddfd24SEugene Shalygin 
24d0ddfd24SEugene Shalygin #include <linux/acpi.h>
25d0ddfd24SEugene Shalygin #include <linux/bitops.h>
26d0ddfd24SEugene Shalygin #include <linux/dev_printk.h>
27d0ddfd24SEugene Shalygin #include <linux/dmi.h>
28d0ddfd24SEugene Shalygin #include <linux/hwmon.h>
29d0ddfd24SEugene Shalygin #include <linux/init.h>
30d0ddfd24SEugene Shalygin #include <linux/jiffies.h>
31d0ddfd24SEugene Shalygin #include <linux/kernel.h>
32d0ddfd24SEugene Shalygin #include <linux/module.h>
33d0ddfd24SEugene Shalygin #include <linux/platform_device.h>
34d0ddfd24SEugene Shalygin #include <linux/sort.h>
35d0ddfd24SEugene Shalygin #include <linux/units.h>
36d0ddfd24SEugene Shalygin 
37d0ddfd24SEugene Shalygin #include <asm/unaligned.h>
38d0ddfd24SEugene Shalygin 
39d0ddfd24SEugene Shalygin static char *mutex_path_override;
40d0ddfd24SEugene Shalygin 
41d0ddfd24SEugene Shalygin /* Writing to this EC register switches EC bank */
42d0ddfd24SEugene Shalygin #define ASUS_EC_BANK_REGISTER	0xff
43d0ddfd24SEugene Shalygin #define SENSOR_LABEL_LEN	16
44d0ddfd24SEugene Shalygin 
45d0ddfd24SEugene Shalygin /*
46d0ddfd24SEugene Shalygin  * Arbitrary set max. allowed bank number. Required for sorting banks and
47d0ddfd24SEugene Shalygin  * currently is overkill with just 2 banks used at max, but for the sake
48d0ddfd24SEugene Shalygin  * of alignment let's set it to a higher value.
49d0ddfd24SEugene Shalygin  */
50d0ddfd24SEugene Shalygin #define ASUS_EC_MAX_BANK	3
51d0ddfd24SEugene Shalygin 
52d0ddfd24SEugene Shalygin #define ACPI_LOCK_DELAY_MS	500
53d0ddfd24SEugene Shalygin 
54d0ddfd24SEugene Shalygin /* ACPI mutex for locking access to the EC for the firmware */
55d0ddfd24SEugene Shalygin #define ASUS_HW_ACCESS_MUTEX_ASMX	"\\AMW0.ASMX"
56d0ddfd24SEugene Shalygin 
57bae26b80SShady Nawara #define ASUS_HW_ACCESS_MUTEX_RMTW_ASMX	"\\RMTW.ASMX"
58bae26b80SShady Nawara 
599992b19dSUrs Schroffenegger #define ASUS_HW_ACCESS_MUTEX_SB_PCI0_SBRG_SIO1_MUT0 "\\_SB_.PCI0.SBRG.SIO1.MUT0"
609992b19dSUrs Schroffenegger 
615b4285c5SEugene Shalygin #define MAX_IDENTICAL_BOARD_VARIATIONS	3
62d0ddfd24SEugene Shalygin 
63de8fbac5SEugene Shalygin /* Moniker for the ACPI global lock (':' is not allowed in ASL identifiers) */
64de8fbac5SEugene Shalygin #define ACPI_GLOBAL_LOCK_PSEUDO_PATH	":GLOBAL_LOCK"
65de8fbac5SEugene Shalygin 
66d0ddfd24SEugene Shalygin typedef union {
67d0ddfd24SEugene Shalygin 	u32 value;
68d0ddfd24SEugene Shalygin 	struct {
69d0ddfd24SEugene Shalygin 		u8 index;
70d0ddfd24SEugene Shalygin 		u8 bank;
71d0ddfd24SEugene Shalygin 		u8 size;
72d0ddfd24SEugene Shalygin 		u8 dummy;
73d0ddfd24SEugene Shalygin 	} components;
74d0ddfd24SEugene Shalygin } sensor_address;
75d0ddfd24SEugene Shalygin 
76d0ddfd24SEugene Shalygin #define MAKE_SENSOR_ADDRESS(size, bank, index) {                               \
77d0ddfd24SEugene Shalygin 		.value = (size << 16) + (bank << 8) + index                    \
78d0ddfd24SEugene Shalygin 	}
79d0ddfd24SEugene Shalygin 
80d0ddfd24SEugene Shalygin static u32 hwmon_attributes[hwmon_max] = {
81d0ddfd24SEugene Shalygin 	[hwmon_chip] = HWMON_C_REGISTER_TZ,
82d0ddfd24SEugene Shalygin 	[hwmon_temp] = HWMON_T_INPUT | HWMON_T_LABEL,
83d0ddfd24SEugene Shalygin 	[hwmon_in] = HWMON_I_INPUT | HWMON_I_LABEL,
84d0ddfd24SEugene Shalygin 	[hwmon_curr] = HWMON_C_INPUT | HWMON_C_LABEL,
85d0ddfd24SEugene Shalygin 	[hwmon_fan] = HWMON_F_INPUT | HWMON_F_LABEL,
86d0ddfd24SEugene Shalygin };
87d0ddfd24SEugene Shalygin 
88d0ddfd24SEugene Shalygin struct ec_sensor_info {
89d0ddfd24SEugene Shalygin 	char label[SENSOR_LABEL_LEN];
90d0ddfd24SEugene Shalygin 	enum hwmon_sensor_types type;
91d0ddfd24SEugene Shalygin 	sensor_address addr;
92d0ddfd24SEugene Shalygin };
93d0ddfd24SEugene Shalygin 
94d0ddfd24SEugene Shalygin #define EC_SENSOR(sensor_label, sensor_type, size, bank, index) {              \
95d0ddfd24SEugene Shalygin 		.label = sensor_label, .type = sensor_type,                    \
96d0ddfd24SEugene Shalygin 		.addr = MAKE_SENSOR_ADDRESS(size, bank, index),                \
97d0ddfd24SEugene Shalygin 	}
98d0ddfd24SEugene Shalygin 
99d0ddfd24SEugene Shalygin enum ec_sensors {
100d0ddfd24SEugene Shalygin 	/* chipset temperature [℃] */
101d0ddfd24SEugene Shalygin 	ec_sensor_temp_chipset,
102d0ddfd24SEugene Shalygin 	/* CPU temperature [℃] */
103d0ddfd24SEugene Shalygin 	ec_sensor_temp_cpu,
104790dec13SMichael Carns 	/* CPU package temperature [℃] */
105790dec13SMichael Carns 	ec_sensor_temp_cpu_package,
106d0ddfd24SEugene Shalygin 	/* motherboard temperature [℃] */
107d0ddfd24SEugene Shalygin 	ec_sensor_temp_mb,
108d0ddfd24SEugene Shalygin 	/* "T_Sensor" temperature sensor reading [℃] */
109d0ddfd24SEugene Shalygin 	ec_sensor_temp_t_sensor,
110d0ddfd24SEugene Shalygin 	/* VRM temperature [℃] */
111d0ddfd24SEugene Shalygin 	ec_sensor_temp_vrm,
112f545a2fdSEugene Shalygin 	/* CPU Core voltage [mV] */
113f545a2fdSEugene Shalygin 	ec_sensor_in_cpu_core,
114d0ddfd24SEugene Shalygin 	/* CPU_Opt fan [RPM] */
115d0ddfd24SEugene Shalygin 	ec_sensor_fan_cpu_opt,
116d0ddfd24SEugene Shalygin 	/* VRM heat sink fan [RPM] */
117d0ddfd24SEugene Shalygin 	ec_sensor_fan_vrm_hs,
118d0ddfd24SEugene Shalygin 	/* Chipset fan [RPM] */
119d0ddfd24SEugene Shalygin 	ec_sensor_fan_chipset,
120d0ddfd24SEugene Shalygin 	/* Water flow sensor reading [RPM] */
121d0ddfd24SEugene Shalygin 	ec_sensor_fan_water_flow,
122d0ddfd24SEugene Shalygin 	/* CPU current [A] */
123d0ddfd24SEugene Shalygin 	ec_sensor_curr_cpu,
124d0ddfd24SEugene Shalygin 	/* "Water_In" temperature sensor reading [℃] */
125d0ddfd24SEugene Shalygin 	ec_sensor_temp_water_in,
126d0ddfd24SEugene Shalygin 	/* "Water_Out" temperature sensor reading [℃] */
127d0ddfd24SEugene Shalygin 	ec_sensor_temp_water_out,
1289992b19dSUrs Schroffenegger 	/* "Water_Block_In" temperature sensor reading [℃] */
1299992b19dSUrs Schroffenegger 	ec_sensor_temp_water_block_in,
1309992b19dSUrs Schroffenegger 	/* "Water_Block_Out" temperature sensor reading [℃] */
1319992b19dSUrs Schroffenegger 	ec_sensor_temp_water_block_out,
1329992b19dSUrs Schroffenegger 	/* "T_sensor_2" temperature sensor reading [℃] */
1339992b19dSUrs Schroffenegger 	ec_sensor_temp_t_sensor_2,
1349992b19dSUrs Schroffenegger 	/* "Extra_1" temperature sensor reading [℃] */
1359992b19dSUrs Schroffenegger 	ec_sensor_temp_sensor_extra_1,
1369992b19dSUrs Schroffenegger 	/* "Extra_2" temperature sensor reading [℃] */
1379992b19dSUrs Schroffenegger 	ec_sensor_temp_sensor_extra_2,
1389992b19dSUrs Schroffenegger 	/* "Extra_3" temperature sensor reading [℃] */
1399992b19dSUrs Schroffenegger 	ec_sensor_temp_sensor_extra_3,
140d0ddfd24SEugene Shalygin };
141d0ddfd24SEugene Shalygin 
142d0ddfd24SEugene Shalygin #define SENSOR_TEMP_CHIPSET BIT(ec_sensor_temp_chipset)
143d0ddfd24SEugene Shalygin #define SENSOR_TEMP_CPU BIT(ec_sensor_temp_cpu)
144790dec13SMichael Carns #define SENSOR_TEMP_CPU_PACKAGE BIT(ec_sensor_temp_cpu_package)
145d0ddfd24SEugene Shalygin #define SENSOR_TEMP_MB BIT(ec_sensor_temp_mb)
146d0ddfd24SEugene Shalygin #define SENSOR_TEMP_T_SENSOR BIT(ec_sensor_temp_t_sensor)
147d0ddfd24SEugene Shalygin #define SENSOR_TEMP_VRM BIT(ec_sensor_temp_vrm)
148f545a2fdSEugene Shalygin #define SENSOR_IN_CPU_CORE BIT(ec_sensor_in_cpu_core)
149d0ddfd24SEugene Shalygin #define SENSOR_FAN_CPU_OPT BIT(ec_sensor_fan_cpu_opt)
150d0ddfd24SEugene Shalygin #define SENSOR_FAN_VRM_HS BIT(ec_sensor_fan_vrm_hs)
151d0ddfd24SEugene Shalygin #define SENSOR_FAN_CHIPSET BIT(ec_sensor_fan_chipset)
152d0ddfd24SEugene Shalygin #define SENSOR_FAN_WATER_FLOW BIT(ec_sensor_fan_water_flow)
153d0ddfd24SEugene Shalygin #define SENSOR_CURR_CPU BIT(ec_sensor_curr_cpu)
154d0ddfd24SEugene Shalygin #define SENSOR_TEMP_WATER_IN BIT(ec_sensor_temp_water_in)
155d0ddfd24SEugene Shalygin #define SENSOR_TEMP_WATER_OUT BIT(ec_sensor_temp_water_out)
1569992b19dSUrs Schroffenegger #define SENSOR_TEMP_WATER_BLOCK_IN BIT(ec_sensor_temp_water_block_in)
1579992b19dSUrs Schroffenegger #define SENSOR_TEMP_WATER_BLOCK_OUT BIT(ec_sensor_temp_water_block_out)
1589992b19dSUrs Schroffenegger #define SENSOR_TEMP_T_SENSOR_2 BIT(ec_sensor_temp_t_sensor_2)
1599992b19dSUrs Schroffenegger #define SENSOR_TEMP_SENSOR_EXTRA_1 BIT(ec_sensor_temp_sensor_extra_1)
1609992b19dSUrs Schroffenegger #define SENSOR_TEMP_SENSOR_EXTRA_2 BIT(ec_sensor_temp_sensor_extra_2)
1619992b19dSUrs Schroffenegger #define SENSOR_TEMP_SENSOR_EXTRA_3 BIT(ec_sensor_temp_sensor_extra_3)
162d0ddfd24SEugene Shalygin 
16345934e4aSEugene Shalygin enum board_family {
16445934e4aSEugene Shalygin 	family_unknown,
1657cc44e5aSEugene Shalygin 	family_amd_400_series,
16645934e4aSEugene Shalygin 	family_amd_500_series,
167790dec13SMichael Carns 	family_amd_600_series,
1688f9eb10fSMichael Carns 	family_intel_300_series,
169bae26b80SShady Nawara 	family_intel_600_series
17045934e4aSEugene Shalygin };
17145934e4aSEugene Shalygin 
172d0ddfd24SEugene Shalygin /* All the known sensors for ASUS EC controllers */
1737cc44e5aSEugene Shalygin static const struct ec_sensor_info sensors_family_amd_400[] = {
1747cc44e5aSEugene Shalygin 	[ec_sensor_temp_chipset] =
1757cc44e5aSEugene Shalygin 		EC_SENSOR("Chipset", hwmon_temp, 1, 0x00, 0x3a),
1767cc44e5aSEugene Shalygin 	[ec_sensor_temp_cpu] =
1777cc44e5aSEugene Shalygin 		EC_SENSOR("CPU", hwmon_temp, 1, 0x00, 0x3b),
1787cc44e5aSEugene Shalygin 	[ec_sensor_temp_mb] =
1797cc44e5aSEugene Shalygin 		EC_SENSOR("Motherboard", hwmon_temp, 1, 0x00, 0x3c),
1807cc44e5aSEugene Shalygin 	[ec_sensor_temp_t_sensor] =
1817cc44e5aSEugene Shalygin 		EC_SENSOR("T_Sensor", hwmon_temp, 1, 0x00, 0x3d),
1827cc44e5aSEugene Shalygin 	[ec_sensor_temp_vrm] =
1837cc44e5aSEugene Shalygin 		EC_SENSOR("VRM", hwmon_temp, 1, 0x00, 0x3e),
1847cc44e5aSEugene Shalygin 	[ec_sensor_in_cpu_core] =
1857cc44e5aSEugene Shalygin 		EC_SENSOR("CPU Core", hwmon_in, 2, 0x00, 0xa2),
1867cc44e5aSEugene Shalygin 	[ec_sensor_fan_cpu_opt] =
1877cc44e5aSEugene Shalygin 		EC_SENSOR("CPU_Opt", hwmon_fan, 2, 0x00, 0xbc),
1887cc44e5aSEugene Shalygin 	[ec_sensor_fan_vrm_hs] =
1897cc44e5aSEugene Shalygin 		EC_SENSOR("VRM HS", hwmon_fan, 2, 0x00, 0xb2),
1907cc44e5aSEugene Shalygin 	[ec_sensor_fan_chipset] =
1917cc44e5aSEugene Shalygin 		/* no chipset fans in this generation */
1927cc44e5aSEugene Shalygin 		EC_SENSOR("Chipset", hwmon_fan, 0, 0x00, 0x00),
1937cc44e5aSEugene Shalygin 	[ec_sensor_fan_water_flow] =
1947cc44e5aSEugene Shalygin 		EC_SENSOR("Water_Flow", hwmon_fan, 2, 0x00, 0xb4),
1957cc44e5aSEugene Shalygin 	[ec_sensor_curr_cpu] =
1967cc44e5aSEugene Shalygin 		EC_SENSOR("CPU", hwmon_curr, 1, 0x00, 0xf4),
1977cc44e5aSEugene Shalygin 	[ec_sensor_temp_water_in] =
1987cc44e5aSEugene Shalygin 		EC_SENSOR("Water_In", hwmon_temp, 1, 0x01, 0x0d),
1997cc44e5aSEugene Shalygin 	[ec_sensor_temp_water_out] =
2007cc44e5aSEugene Shalygin 		EC_SENSOR("Water_Out", hwmon_temp, 1, 0x01, 0x0b),
2017cc44e5aSEugene Shalygin };
2027cc44e5aSEugene Shalygin 
20345934e4aSEugene Shalygin static const struct ec_sensor_info sensors_family_amd_500[] = {
204d0ddfd24SEugene Shalygin 	[ec_sensor_temp_chipset] =
205d0ddfd24SEugene Shalygin 		EC_SENSOR("Chipset", hwmon_temp, 1, 0x00, 0x3a),
206d0ddfd24SEugene Shalygin 	[ec_sensor_temp_cpu] = EC_SENSOR("CPU", hwmon_temp, 1, 0x00, 0x3b),
207d0ddfd24SEugene Shalygin 	[ec_sensor_temp_mb] =
208d0ddfd24SEugene Shalygin 		EC_SENSOR("Motherboard", hwmon_temp, 1, 0x00, 0x3c),
209d0ddfd24SEugene Shalygin 	[ec_sensor_temp_t_sensor] =
210d0ddfd24SEugene Shalygin 		EC_SENSOR("T_Sensor", hwmon_temp, 1, 0x00, 0x3d),
211d0ddfd24SEugene Shalygin 	[ec_sensor_temp_vrm] = EC_SENSOR("VRM", hwmon_temp, 1, 0x00, 0x3e),
212f545a2fdSEugene Shalygin 	[ec_sensor_in_cpu_core] =
213f545a2fdSEugene Shalygin 		EC_SENSOR("CPU Core", hwmon_in, 2, 0x00, 0xa2),
214d0ddfd24SEugene Shalygin 	[ec_sensor_fan_cpu_opt] =
215d0ddfd24SEugene Shalygin 		EC_SENSOR("CPU_Opt", hwmon_fan, 2, 0x00, 0xb0),
216d0ddfd24SEugene Shalygin 	[ec_sensor_fan_vrm_hs] = EC_SENSOR("VRM HS", hwmon_fan, 2, 0x00, 0xb2),
217d0ddfd24SEugene Shalygin 	[ec_sensor_fan_chipset] =
218d0ddfd24SEugene Shalygin 		EC_SENSOR("Chipset", hwmon_fan, 2, 0x00, 0xb4),
219d0ddfd24SEugene Shalygin 	[ec_sensor_fan_water_flow] =
220d0ddfd24SEugene Shalygin 		EC_SENSOR("Water_Flow", hwmon_fan, 2, 0x00, 0xbc),
221d0ddfd24SEugene Shalygin 	[ec_sensor_curr_cpu] = EC_SENSOR("CPU", hwmon_curr, 1, 0x00, 0xf4),
222d0ddfd24SEugene Shalygin 	[ec_sensor_temp_water_in] =
223d0ddfd24SEugene Shalygin 		EC_SENSOR("Water_In", hwmon_temp, 1, 0x01, 0x00),
224d0ddfd24SEugene Shalygin 	[ec_sensor_temp_water_out] =
225d0ddfd24SEugene Shalygin 		EC_SENSOR("Water_Out", hwmon_temp, 1, 0x01, 0x01),
2269992b19dSUrs Schroffenegger 	[ec_sensor_temp_water_block_in] =
2279992b19dSUrs Schroffenegger 		EC_SENSOR("Water_Block_In", hwmon_temp, 1, 0x01, 0x02),
2289992b19dSUrs Schroffenegger 	[ec_sensor_temp_water_block_out] =
2299992b19dSUrs Schroffenegger 		EC_SENSOR("Water_Block_Out", hwmon_temp, 1, 0x01, 0x03),
2309992b19dSUrs Schroffenegger 	[ec_sensor_temp_sensor_extra_1] =
2319992b19dSUrs Schroffenegger 		EC_SENSOR("Extra_1", hwmon_temp, 1, 0x01, 0x09),
2329992b19dSUrs Schroffenegger 	[ec_sensor_temp_t_sensor_2] =
2339992b19dSUrs Schroffenegger 		EC_SENSOR("T_sensor_2", hwmon_temp, 1, 0x01, 0x0a),
2349992b19dSUrs Schroffenegger 	[ec_sensor_temp_sensor_extra_2] =
2359992b19dSUrs Schroffenegger 		EC_SENSOR("Extra_2", hwmon_temp, 1, 0x01, 0x0b),
2369992b19dSUrs Schroffenegger 	[ec_sensor_temp_sensor_extra_3] =
2379992b19dSUrs Schroffenegger 		EC_SENSOR("Extra_3", hwmon_temp, 1, 0x01, 0x0c),
238d0ddfd24SEugene Shalygin };
239d0ddfd24SEugene Shalygin 
240790dec13SMichael Carns static const struct ec_sensor_info sensors_family_amd_600[] = {
241790dec13SMichael Carns 	[ec_sensor_temp_cpu] = EC_SENSOR("CPU", hwmon_temp, 1, 0x00, 0x30),
242790dec13SMichael Carns 	[ec_sensor_temp_cpu_package] = EC_SENSOR("CPU Package", hwmon_temp, 1, 0x00, 0x31),
243790dec13SMichael Carns 	[ec_sensor_temp_mb] =
244790dec13SMichael Carns 	EC_SENSOR("Motherboard", hwmon_temp, 1, 0x00, 0x32),
245790dec13SMichael Carns 	[ec_sensor_temp_vrm] =
246790dec13SMichael Carns 		EC_SENSOR("VRM", hwmon_temp, 1, 0x00, 0x33),
247f7ac3020SEllie Hermaszewska 	[ec_sensor_temp_t_sensor] =
248f7ac3020SEllie Hermaszewska 		EC_SENSOR("T_Sensor", hwmon_temp, 1, 0x00, 0x36),
249790dec13SMichael Carns 	[ec_sensor_temp_water_in] =
250790dec13SMichael Carns 		EC_SENSOR("Water_In", hwmon_temp, 1, 0x01, 0x00),
251790dec13SMichael Carns 	[ec_sensor_temp_water_out] =
252790dec13SMichael Carns 		EC_SENSOR("Water_Out", hwmon_temp, 1, 0x01, 0x01),
253790dec13SMichael Carns };
254790dec13SMichael Carns 
2558f9eb10fSMichael Carns static const struct ec_sensor_info sensors_family_intel_300[] = {
2568f9eb10fSMichael Carns 	[ec_sensor_temp_chipset] =
2578f9eb10fSMichael Carns 		EC_SENSOR("Chipset", hwmon_temp, 1, 0x00, 0x3a),
2588f9eb10fSMichael Carns 	[ec_sensor_temp_cpu] = EC_SENSOR("CPU", hwmon_temp, 1, 0x00, 0x3b),
2598f9eb10fSMichael Carns 	[ec_sensor_temp_mb] =
2608f9eb10fSMichael Carns 		EC_SENSOR("Motherboard", hwmon_temp, 1, 0x00, 0x3c),
2618f9eb10fSMichael Carns 	[ec_sensor_temp_t_sensor] =
2628f9eb10fSMichael Carns 		EC_SENSOR("T_Sensor", hwmon_temp, 1, 0x00, 0x3d),
2638f9eb10fSMichael Carns 	[ec_sensor_temp_vrm] = EC_SENSOR("VRM", hwmon_temp, 1, 0x00, 0x3e),
2648f9eb10fSMichael Carns 	[ec_sensor_fan_cpu_opt] =
2658f9eb10fSMichael Carns 		EC_SENSOR("CPU_Opt", hwmon_fan, 2, 0x00, 0xb0),
2668f9eb10fSMichael Carns 	[ec_sensor_fan_vrm_hs] = EC_SENSOR("VRM HS", hwmon_fan, 2, 0x00, 0xb2),
2678f9eb10fSMichael Carns 	[ec_sensor_fan_water_flow] =
2688f9eb10fSMichael Carns 		EC_SENSOR("Water_Flow", hwmon_fan, 2, 0x00, 0xbc),
2698f9eb10fSMichael Carns 	[ec_sensor_temp_water_in] =
2708f9eb10fSMichael Carns 		EC_SENSOR("Water_In", hwmon_temp, 1, 0x01, 0x00),
2718f9eb10fSMichael Carns 	[ec_sensor_temp_water_out] =
2728f9eb10fSMichael Carns 		EC_SENSOR("Water_Out", hwmon_temp, 1, 0x01, 0x01),
2738f9eb10fSMichael Carns };
2748f9eb10fSMichael Carns 
275bae26b80SShady Nawara static const struct ec_sensor_info sensors_family_intel_600[] = {
276bae26b80SShady Nawara 	[ec_sensor_temp_t_sensor] =
277bae26b80SShady Nawara 		EC_SENSOR("T_Sensor", hwmon_temp, 1, 0x00, 0x3d),
278bae26b80SShady Nawara 	[ec_sensor_temp_vrm] = EC_SENSOR("VRM", hwmon_temp, 1, 0x00, 0x3e),
279bae26b80SShady Nawara };
280bae26b80SShady Nawara 
281d0ddfd24SEugene Shalygin /* Shortcuts for common combinations */
282d0ddfd24SEugene Shalygin #define SENSOR_SET_TEMP_CHIPSET_CPU_MB                                         \
283d0ddfd24SEugene Shalygin 	(SENSOR_TEMP_CHIPSET | SENSOR_TEMP_CPU | SENSOR_TEMP_MB)
284d0ddfd24SEugene Shalygin #define SENSOR_SET_TEMP_WATER (SENSOR_TEMP_WATER_IN | SENSOR_TEMP_WATER_OUT)
2859992b19dSUrs Schroffenegger #define SENSOR_SET_WATER_BLOCK                                                 \
2869992b19dSUrs Schroffenegger 	(SENSOR_TEMP_WATER_BLOCK_IN | SENSOR_TEMP_WATER_BLOCK_OUT)
2879992b19dSUrs Schroffenegger 
2885cd29012SEugene Shalygin struct ec_board_info {
2895cd29012SEugene Shalygin 	unsigned long sensors;
290de8fbac5SEugene Shalygin 	/*
291de8fbac5SEugene Shalygin 	 * Defines which mutex to use for guarding access to the state and the
292de8fbac5SEugene Shalygin 	 * hardware. Can be either a full path to an AML mutex or the
293de8fbac5SEugene Shalygin 	 * pseudo-path ACPI_GLOBAL_LOCK_PSEUDO_PATH to use the global ACPI lock,
294de8fbac5SEugene Shalygin 	 * or left empty to use a regular mutex object, in which case access to
295de8fbac5SEugene Shalygin 	 * the hardware is not guarded.
296de8fbac5SEugene Shalygin 	 */
297de8fbac5SEugene Shalygin 	const char *mutex_path;
29845934e4aSEugene Shalygin 	enum board_family family;
2995cd29012SEugene Shalygin };
300d0ddfd24SEugene Shalygin 
30188700d13SEugene Shalygin static const struct ec_board_info board_info_prime_x470_pro = {
3027cc44e5aSEugene Shalygin 	.sensors = SENSOR_SET_TEMP_CHIPSET_CPU_MB |
3037cc44e5aSEugene Shalygin 		SENSOR_TEMP_T_SENSOR | SENSOR_TEMP_VRM |
3047cc44e5aSEugene Shalygin 		SENSOR_FAN_CPU_OPT |
3057cc44e5aSEugene Shalygin 		SENSOR_CURR_CPU | SENSOR_IN_CPU_CORE,
3067cc44e5aSEugene Shalygin 	.mutex_path = ACPI_GLOBAL_LOCK_PSEUDO_PATH,
3077cc44e5aSEugene Shalygin 	.family = family_amd_400_series,
30888700d13SEugene Shalygin };
30988700d13SEugene Shalygin 
31088700d13SEugene Shalygin static const struct ec_board_info board_info_prime_x570_pro = {
3115cd29012SEugene Shalygin 	.sensors = SENSOR_SET_TEMP_CHIPSET_CPU_MB | SENSOR_TEMP_VRM |
3125cd29012SEugene Shalygin 		SENSOR_TEMP_T_SENSOR | SENSOR_FAN_CHIPSET,
313de8fbac5SEugene Shalygin 	.mutex_path = ASUS_HW_ACCESS_MUTEX_ASMX,
31445934e4aSEugene Shalygin 	.family = family_amd_500_series,
31588700d13SEugene Shalygin };
31688700d13SEugene Shalygin 
31788700d13SEugene Shalygin static const struct ec_board_info board_info_pro_art_x570_creator_wifi = {
3185cd29012SEugene Shalygin 	.sensors = SENSOR_SET_TEMP_CHIPSET_CPU_MB | SENSOR_TEMP_VRM |
319d7cc063fSEugene Shalygin 		SENSOR_TEMP_T_SENSOR | SENSOR_FAN_CPU_OPT |
3205cd29012SEugene Shalygin 		SENSOR_CURR_CPU | SENSOR_IN_CPU_CORE,
321e2de0e6aSEugene Shalygin 	.mutex_path = ASUS_HW_ACCESS_MUTEX_ASMX,
32288700d13SEugene Shalygin 	.family = family_amd_500_series,
32388700d13SEugene Shalygin };
32488700d13SEugene Shalygin 
32571ac69e0SEugene Shalygin static const struct ec_board_info board_info_pro_art_x670E_creator_wifi = {
32671ac69e0SEugene Shalygin 	.sensors = SENSOR_TEMP_CPU | SENSOR_TEMP_CPU_PACKAGE |
32771ac69e0SEugene Shalygin 		SENSOR_TEMP_MB | SENSOR_TEMP_VRM |
32871ac69e0SEugene Shalygin 		SENSOR_TEMP_T_SENSOR,
32971ac69e0SEugene Shalygin 	.mutex_path = ACPI_GLOBAL_LOCK_PSEUDO_PATH,
33071ac69e0SEugene Shalygin 	.family = family_amd_600_series,
33171ac69e0SEugene Shalygin };
33271ac69e0SEugene Shalygin 
333c7ba3e26Sfireflame90051 static const struct ec_board_info board_info_pro_art_b550_creator = {
334c7ba3e26Sfireflame90051 	.sensors = SENSOR_SET_TEMP_CHIPSET_CPU_MB |
335c7ba3e26Sfireflame90051 		SENSOR_TEMP_T_SENSOR |
336c7ba3e26Sfireflame90051 		SENSOR_FAN_CPU_OPT,
337c7ba3e26Sfireflame90051 	.mutex_path = ASUS_HW_ACCESS_MUTEX_ASMX,
338c7ba3e26Sfireflame90051 	.family = family_amd_500_series,
339c7ba3e26Sfireflame90051 };
340c7ba3e26Sfireflame90051 
34188700d13SEugene Shalygin static const struct ec_board_info board_info_pro_ws_x570_ace = {
3425cd29012SEugene Shalygin 	.sensors = SENSOR_SET_TEMP_CHIPSET_CPU_MB | SENSOR_TEMP_VRM |
343ab9ac6dfSWei Shuyu 		SENSOR_TEMP_T_SENSOR | SENSOR_FAN_CHIPSET |
3445cd29012SEugene Shalygin 		SENSOR_CURR_CPU | SENSOR_IN_CPU_CORE,
345de8fbac5SEugene Shalygin 	.mutex_path = ASUS_HW_ACCESS_MUTEX_ASMX,
34645934e4aSEugene Shalygin 	.family = family_amd_500_series,
34788700d13SEugene Shalygin };
34888700d13SEugene Shalygin 
349790dec13SMichael Carns static const struct ec_board_info board_info_crosshair_x670e_hero = {
350790dec13SMichael Carns 	.sensors = SENSOR_TEMP_CPU | SENSOR_TEMP_CPU_PACKAGE |
351790dec13SMichael Carns 		SENSOR_TEMP_MB | SENSOR_TEMP_VRM |
352790dec13SMichael Carns 		SENSOR_SET_TEMP_WATER,
3539c53fb0aSEugene Shalygin 	.mutex_path = ACPI_GLOBAL_LOCK_PSEUDO_PATH,
354790dec13SMichael Carns 	.family = family_amd_600_series,
355790dec13SMichael Carns };
356790dec13SMichael Carns 
357f7ac3020SEllie Hermaszewska static const struct ec_board_info board_info_crosshair_x670e_gene = {
358f7ac3020SEllie Hermaszewska 	.sensors = SENSOR_TEMP_CPU | SENSOR_TEMP_CPU_PACKAGE |
359f7ac3020SEllie Hermaszewska 		SENSOR_TEMP_T_SENSOR |
360f7ac3020SEllie Hermaszewska 		SENSOR_TEMP_MB | SENSOR_TEMP_VRM,
361f7ac3020SEllie Hermaszewska 	.mutex_path = ACPI_GLOBAL_LOCK_PSEUDO_PATH,
362f7ac3020SEllie Hermaszewska 	.family = family_amd_600_series,
363f7ac3020SEllie Hermaszewska };
364f7ac3020SEllie Hermaszewska 
36588700d13SEugene Shalygin static const struct ec_board_info board_info_crosshair_viii_dark_hero = {
3665cd29012SEugene Shalygin 	.sensors = SENSOR_SET_TEMP_CHIPSET_CPU_MB |
3675cd29012SEugene Shalygin 		SENSOR_TEMP_T_SENSOR |
368d0ddfd24SEugene Shalygin 		SENSOR_TEMP_VRM | SENSOR_SET_TEMP_WATER |
369f545a2fdSEugene Shalygin 		SENSOR_FAN_CPU_OPT | SENSOR_FAN_WATER_FLOW |
3705cd29012SEugene Shalygin 		SENSOR_CURR_CPU | SENSOR_IN_CPU_CORE,
371de8fbac5SEugene Shalygin 	.mutex_path = ASUS_HW_ACCESS_MUTEX_ASMX,
37245934e4aSEugene Shalygin 	.family = family_amd_500_series,
37388700d13SEugene Shalygin };
37488700d13SEugene Shalygin 
37588700d13SEugene Shalygin static const struct ec_board_info board_info_crosshair_viii_hero = {
3765cd29012SEugene Shalygin 	.sensors = SENSOR_SET_TEMP_CHIPSET_CPU_MB |
3775cd29012SEugene Shalygin 		SENSOR_TEMP_T_SENSOR |
3782f66cb5bSEugene Shalygin 		SENSOR_TEMP_VRM | SENSOR_SET_TEMP_WATER |
3792f66cb5bSEugene Shalygin 		SENSOR_FAN_CPU_OPT | SENSOR_FAN_CHIPSET |
3805cd29012SEugene Shalygin 		SENSOR_FAN_WATER_FLOW | SENSOR_CURR_CPU |
3815cd29012SEugene Shalygin 		SENSOR_IN_CPU_CORE,
382de8fbac5SEugene Shalygin 	.mutex_path = ASUS_HW_ACCESS_MUTEX_ASMX,
38345934e4aSEugene Shalygin 	.family = family_amd_500_series,
38488700d13SEugene Shalygin };
38588700d13SEugene Shalygin 
38688700d13SEugene Shalygin static const struct ec_board_info board_info_maximus_xi_hero = {
3878f9eb10fSMichael Carns 	.sensors = SENSOR_SET_TEMP_CHIPSET_CPU_MB |
3888f9eb10fSMichael Carns 		SENSOR_TEMP_T_SENSOR |
3898f9eb10fSMichael Carns 		SENSOR_TEMP_VRM | SENSOR_SET_TEMP_WATER |
3908f9eb10fSMichael Carns 		SENSOR_FAN_CPU_OPT | SENSOR_FAN_WATER_FLOW,
3918f9eb10fSMichael Carns 	.mutex_path = ASUS_HW_ACCESS_MUTEX_ASMX,
3928f9eb10fSMichael Carns 	.family = family_intel_300_series,
39388700d13SEugene Shalygin };
39488700d13SEugene Shalygin 
39588700d13SEugene Shalygin static const struct ec_board_info board_info_crosshair_viii_impact = {
3965cd29012SEugene Shalygin 	.sensors = SENSOR_SET_TEMP_CHIPSET_CPU_MB |
3975cd29012SEugene Shalygin 		SENSOR_TEMP_T_SENSOR | SENSOR_TEMP_VRM |
3985cd29012SEugene Shalygin 		SENSOR_FAN_CHIPSET | SENSOR_CURR_CPU |
3995cd29012SEugene Shalygin 		SENSOR_IN_CPU_CORE,
400de8fbac5SEugene Shalygin 	.mutex_path = ASUS_HW_ACCESS_MUTEX_ASMX,
40145934e4aSEugene Shalygin 	.family = family_amd_500_series,
40288700d13SEugene Shalygin };
40388700d13SEugene Shalygin 
40488700d13SEugene Shalygin static const struct ec_board_info board_info_strix_b550_e_gaming = {
4055cd29012SEugene Shalygin 	.sensors = SENSOR_SET_TEMP_CHIPSET_CPU_MB |
4065cd29012SEugene Shalygin 		SENSOR_TEMP_T_SENSOR | SENSOR_TEMP_VRM |
4075cd29012SEugene Shalygin 		SENSOR_FAN_CPU_OPT,
408de8fbac5SEugene Shalygin 	.mutex_path = ASUS_HW_ACCESS_MUTEX_ASMX,
40945934e4aSEugene Shalygin 	.family = family_amd_500_series,
41088700d13SEugene Shalygin };
41188700d13SEugene Shalygin 
41288700d13SEugene Shalygin static const struct ec_board_info board_info_strix_b550_i_gaming = {
4135cd29012SEugene Shalygin 	.sensors = SENSOR_SET_TEMP_CHIPSET_CPU_MB |
4145cd29012SEugene Shalygin 		SENSOR_TEMP_T_SENSOR | SENSOR_TEMP_VRM |
4155cd29012SEugene Shalygin 		SENSOR_FAN_VRM_HS | SENSOR_CURR_CPU |
4165cd29012SEugene Shalygin 		SENSOR_IN_CPU_CORE,
417de8fbac5SEugene Shalygin 	.mutex_path = ASUS_HW_ACCESS_MUTEX_ASMX,
41845934e4aSEugene Shalygin 	.family = family_amd_500_series,
41988700d13SEugene Shalygin };
42088700d13SEugene Shalygin 
42188700d13SEugene Shalygin static const struct ec_board_info board_info_strix_x570_e_gaming = {
4225cd29012SEugene Shalygin 	.sensors = SENSOR_SET_TEMP_CHIPSET_CPU_MB |
423*9efaebc0SRoss Brown 		SENSOR_TEMP_T_SENSOR |
4245cd29012SEugene Shalygin 		SENSOR_FAN_CHIPSET | SENSOR_CURR_CPU |
4255cd29012SEugene Shalygin 		SENSOR_IN_CPU_CORE,
426de8fbac5SEugene Shalygin 	.mutex_path = ASUS_HW_ACCESS_MUTEX_ASMX,
42745934e4aSEugene Shalygin 	.family = family_amd_500_series,
42888700d13SEugene Shalygin };
42988700d13SEugene Shalygin 
43088700d13SEugene Shalygin static const struct ec_board_info board_info_strix_x570_e_gaming_wifi_ii = {
4319ccafe46SDebabrata Banerjee 	.sensors = SENSOR_SET_TEMP_CHIPSET_CPU_MB |
4329ccafe46SDebabrata Banerjee 		SENSOR_TEMP_T_SENSOR | SENSOR_CURR_CPU |
4339ccafe46SDebabrata Banerjee 		SENSOR_IN_CPU_CORE,
4349ccafe46SDebabrata Banerjee 	.mutex_path = ASUS_HW_ACCESS_MUTEX_ASMX,
4359ccafe46SDebabrata Banerjee 	.family = family_amd_500_series,
43688700d13SEugene Shalygin };
43788700d13SEugene Shalygin 
43888700d13SEugene Shalygin static const struct ec_board_info board_info_strix_x570_f_gaming = {
4395cd29012SEugene Shalygin 	.sensors = SENSOR_SET_TEMP_CHIPSET_CPU_MB |
4405cd29012SEugene Shalygin 		SENSOR_TEMP_T_SENSOR | SENSOR_FAN_CHIPSET,
441de8fbac5SEugene Shalygin 	.mutex_path = ASUS_HW_ACCESS_MUTEX_ASMX,
44245934e4aSEugene Shalygin 	.family = family_amd_500_series,
44388700d13SEugene Shalygin };
44488700d13SEugene Shalygin 
44588700d13SEugene Shalygin static const struct ec_board_info board_info_strix_x570_i_gaming = {
4461c4e4f4aSEugene Shalygin 	.sensors = SENSOR_TEMP_CHIPSET | SENSOR_TEMP_VRM |
4471c4e4f4aSEugene Shalygin 		SENSOR_TEMP_T_SENSOR |
4481c4e4f4aSEugene Shalygin 		SENSOR_FAN_VRM_HS | SENSOR_FAN_CHIPSET |
4491c4e4f4aSEugene Shalygin 		SENSOR_CURR_CPU | SENSOR_IN_CPU_CORE,
450de8fbac5SEugene Shalygin 	.mutex_path = ASUS_HW_ACCESS_MUTEX_ASMX,
45145934e4aSEugene Shalygin 	.family = family_amd_500_series,
45288700d13SEugene Shalygin };
45388700d13SEugene Shalygin 
4543a31e092SEugene Shalygin static const struct ec_board_info board_info_strix_z390_f_gaming = {
4553a31e092SEugene Shalygin 	.sensors = SENSOR_TEMP_CHIPSET | SENSOR_TEMP_VRM |
4563a31e092SEugene Shalygin 		SENSOR_TEMP_T_SENSOR |
4573a31e092SEugene Shalygin 		SENSOR_FAN_CPU_OPT,
4583a31e092SEugene Shalygin 	.mutex_path = ASUS_HW_ACCESS_MUTEX_ASMX,
4593a31e092SEugene Shalygin 	.family = family_intel_300_series,
4603a31e092SEugene Shalygin };
4613a31e092SEugene Shalygin 
46288700d13SEugene Shalygin static const struct ec_board_info board_info_strix_z690_a_gaming_wifi_d4 = {
463bae26b80SShady Nawara 	.sensors = SENSOR_TEMP_T_SENSOR | SENSOR_TEMP_VRM,
464bae26b80SShady Nawara 	.mutex_path = ASUS_HW_ACCESS_MUTEX_RMTW_ASMX,
465bae26b80SShady Nawara 	.family = family_intel_600_series,
46688700d13SEugene Shalygin };
46788700d13SEugene Shalygin 
46888700d13SEugene Shalygin static const struct ec_board_info board_info_zenith_ii_extreme = {
4699992b19dSUrs Schroffenegger 	.sensors = SENSOR_SET_TEMP_CHIPSET_CPU_MB | SENSOR_TEMP_T_SENSOR |
4709992b19dSUrs Schroffenegger 		SENSOR_TEMP_VRM | SENSOR_SET_TEMP_WATER |
4719992b19dSUrs Schroffenegger 		SENSOR_FAN_CPU_OPT | SENSOR_FAN_CHIPSET | SENSOR_FAN_VRM_HS |
4729992b19dSUrs Schroffenegger 		SENSOR_FAN_WATER_FLOW | SENSOR_CURR_CPU | SENSOR_IN_CPU_CORE |
4739992b19dSUrs Schroffenegger 		SENSOR_SET_WATER_BLOCK |
4749992b19dSUrs Schroffenegger 		SENSOR_TEMP_T_SENSOR_2 | SENSOR_TEMP_SENSOR_EXTRA_1 |
4759992b19dSUrs Schroffenegger 		SENSOR_TEMP_SENSOR_EXTRA_2 | SENSOR_TEMP_SENSOR_EXTRA_3,
4769992b19dSUrs Schroffenegger 	.mutex_path = ASUS_HW_ACCESS_MUTEX_SB_PCI0_SBRG_SIO1_MUT0,
4779992b19dSUrs Schroffenegger 	.family = family_amd_500_series,
47888700d13SEugene Shalygin };
47988700d13SEugene Shalygin 
48088700d13SEugene Shalygin #define DMI_EXACT_MATCH_ASUS_BOARD_NAME(name, board_info)                      \
48188700d13SEugene Shalygin 	{                                                                      \
48288700d13SEugene Shalygin 		.matches = {                                                   \
48388700d13SEugene Shalygin 			DMI_EXACT_MATCH(DMI_BOARD_VENDOR,                      \
48488700d13SEugene Shalygin 					"ASUSTeK COMPUTER INC."),              \
48588700d13SEugene Shalygin 			DMI_EXACT_MATCH(DMI_BOARD_NAME, name),                 \
48688700d13SEugene Shalygin 		},                                                             \
48788700d13SEugene Shalygin 		.driver_data = (void *)board_info,                              \
48888700d13SEugene Shalygin 	}
48988700d13SEugene Shalygin 
49088700d13SEugene Shalygin static const struct dmi_system_id dmi_table[] = {
49188700d13SEugene Shalygin 	DMI_EXACT_MATCH_ASUS_BOARD_NAME("PRIME X470-PRO",
49288700d13SEugene Shalygin 					&board_info_prime_x470_pro),
49388700d13SEugene Shalygin 	DMI_EXACT_MATCH_ASUS_BOARD_NAME("PRIME X570-PRO",
49488700d13SEugene Shalygin 					&board_info_prime_x570_pro),
49588700d13SEugene Shalygin 	DMI_EXACT_MATCH_ASUS_BOARD_NAME("ProArt X570-CREATOR WIFI",
49688700d13SEugene Shalygin 					&board_info_pro_art_x570_creator_wifi),
49771ac69e0SEugene Shalygin 	DMI_EXACT_MATCH_ASUS_BOARD_NAME("ProArt X670E-CREATOR WIFI",
49871ac69e0SEugene Shalygin 					&board_info_pro_art_x670E_creator_wifi),
499c7ba3e26Sfireflame90051 	DMI_EXACT_MATCH_ASUS_BOARD_NAME("ProArt B550-CREATOR",
500c7ba3e26Sfireflame90051 					&board_info_pro_art_b550_creator),
50188700d13SEugene Shalygin 	DMI_EXACT_MATCH_ASUS_BOARD_NAME("Pro WS X570-ACE",
50288700d13SEugene Shalygin 					&board_info_pro_ws_x570_ace),
50388700d13SEugene Shalygin 	DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG CROSSHAIR VIII DARK HERO",
50488700d13SEugene Shalygin 					&board_info_crosshair_viii_dark_hero),
50588700d13SEugene Shalygin 	DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG CROSSHAIR VIII FORMULA",
50688700d13SEugene Shalygin 					&board_info_crosshair_viii_hero),
50788700d13SEugene Shalygin 	DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG CROSSHAIR VIII HERO",
50888700d13SEugene Shalygin 					&board_info_crosshair_viii_hero),
50988700d13SEugene Shalygin 	DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG CROSSHAIR VIII HERO (WI-FI)",
51088700d13SEugene Shalygin 					&board_info_crosshair_viii_hero),
511790dec13SMichael Carns 	DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG CROSSHAIR X670E HERO",
512790dec13SMichael Carns 					&board_info_crosshair_x670e_hero),
513f7ac3020SEllie Hermaszewska 	DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG CROSSHAIR X670E GENE",
514f7ac3020SEllie Hermaszewska 					&board_info_crosshair_x670e_gene),
51588700d13SEugene Shalygin 	DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG MAXIMUS XI HERO",
51688700d13SEugene Shalygin 					&board_info_maximus_xi_hero),
51788700d13SEugene Shalygin 	DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG MAXIMUS XI HERO (WI-FI)",
51888700d13SEugene Shalygin 					&board_info_maximus_xi_hero),
51988700d13SEugene Shalygin 	DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG CROSSHAIR VIII IMPACT",
52088700d13SEugene Shalygin 					&board_info_crosshair_viii_impact),
52188700d13SEugene Shalygin 	DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG STRIX B550-E GAMING",
52288700d13SEugene Shalygin 					&board_info_strix_b550_e_gaming),
52388700d13SEugene Shalygin 	DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG STRIX B550-I GAMING",
52488700d13SEugene Shalygin 					&board_info_strix_b550_i_gaming),
52588700d13SEugene Shalygin 	DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG STRIX X570-E GAMING",
52688700d13SEugene Shalygin 					&board_info_strix_x570_e_gaming),
52788700d13SEugene Shalygin 	DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG STRIX X570-E GAMING WIFI II",
52888700d13SEugene Shalygin 					&board_info_strix_x570_e_gaming_wifi_ii),
52988700d13SEugene Shalygin 	DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG STRIX X570-F GAMING",
53088700d13SEugene Shalygin 					&board_info_strix_x570_f_gaming),
53188700d13SEugene Shalygin 	DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG STRIX X570-I GAMING",
53288700d13SEugene Shalygin 					&board_info_strix_x570_i_gaming),
5333a31e092SEugene Shalygin 	DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG STRIX Z390-F GAMING",
5343a31e092SEugene Shalygin 					&board_info_strix_z390_f_gaming),
53588700d13SEugene Shalygin 	DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG STRIX Z690-A GAMING WIFI D4",
53688700d13SEugene Shalygin 					&board_info_strix_z690_a_gaming_wifi_d4),
53788700d13SEugene Shalygin 	DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG ZENITH II EXTREME",
53888700d13SEugene Shalygin 					&board_info_zenith_ii_extreme),
539195f46e5SEric Nguyen 	DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG ZENITH II EXTREME ALPHA",
540195f46e5SEric Nguyen 					&board_info_zenith_ii_extreme),
54188700d13SEugene Shalygin 	{},
542d0ddfd24SEugene Shalygin };
543d0ddfd24SEugene Shalygin 
544d0ddfd24SEugene Shalygin struct ec_sensor {
545d0ddfd24SEugene Shalygin 	unsigned int info_index;
546339f8a99SEugene Shalygin 	s32 cached_value;
547d0ddfd24SEugene Shalygin };
548d0ddfd24SEugene Shalygin 
549de8fbac5SEugene Shalygin struct lock_data {
550de8fbac5SEugene Shalygin 	union {
551de8fbac5SEugene Shalygin 		acpi_handle aml;
552de8fbac5SEugene Shalygin 		/* global lock handle */
553de8fbac5SEugene Shalygin 		u32 glk;
554de8fbac5SEugene Shalygin 	} mutex;
555de8fbac5SEugene Shalygin 	bool (*lock)(struct lock_data *data);
556de8fbac5SEugene Shalygin 	bool (*unlock)(struct lock_data *data);
557de8fbac5SEugene Shalygin };
558de8fbac5SEugene Shalygin 
559de8fbac5SEugene Shalygin /*
560de8fbac5SEugene Shalygin  * The next function pairs implement options for locking access to the
561de8fbac5SEugene Shalygin  * state and the EC
562de8fbac5SEugene Shalygin  */
lock_via_acpi_mutex(struct lock_data * data)563de8fbac5SEugene Shalygin static bool lock_via_acpi_mutex(struct lock_data *data)
564de8fbac5SEugene Shalygin {
565de8fbac5SEugene Shalygin 	/*
566de8fbac5SEugene Shalygin 	 * ASUS DSDT does not specify that access to the EC has to be guarded,
567de8fbac5SEugene Shalygin 	 * but firmware does access it via ACPI
568de8fbac5SEugene Shalygin 	 */
569de8fbac5SEugene Shalygin 	return ACPI_SUCCESS(acpi_acquire_mutex(data->mutex.aml,
570de8fbac5SEugene Shalygin 					       NULL, ACPI_LOCK_DELAY_MS));
571de8fbac5SEugene Shalygin }
572de8fbac5SEugene Shalygin 
unlock_acpi_mutex(struct lock_data * data)573de8fbac5SEugene Shalygin static bool unlock_acpi_mutex(struct lock_data *data)
574de8fbac5SEugene Shalygin {
575de8fbac5SEugene Shalygin 	return ACPI_SUCCESS(acpi_release_mutex(data->mutex.aml, NULL));
576de8fbac5SEugene Shalygin }
577de8fbac5SEugene Shalygin 
lock_via_global_acpi_lock(struct lock_data * data)578de8fbac5SEugene Shalygin static bool lock_via_global_acpi_lock(struct lock_data *data)
579de8fbac5SEugene Shalygin {
580de8fbac5SEugene Shalygin 	return ACPI_SUCCESS(acpi_acquire_global_lock(ACPI_LOCK_DELAY_MS,
581de8fbac5SEugene Shalygin 						     &data->mutex.glk));
582de8fbac5SEugene Shalygin }
583de8fbac5SEugene Shalygin 
unlock_global_acpi_lock(struct lock_data * data)584de8fbac5SEugene Shalygin static bool unlock_global_acpi_lock(struct lock_data *data)
585de8fbac5SEugene Shalygin {
586de8fbac5SEugene Shalygin 	return ACPI_SUCCESS(acpi_release_global_lock(data->mutex.glk));
587de8fbac5SEugene Shalygin }
588de8fbac5SEugene Shalygin 
589d0ddfd24SEugene Shalygin struct ec_sensors_data {
5905cd29012SEugene Shalygin 	const struct ec_board_info *board_info;
59145934e4aSEugene Shalygin 	const struct ec_sensor_info *sensors_info;
592d0ddfd24SEugene Shalygin 	struct ec_sensor *sensors;
593d0ddfd24SEugene Shalygin 	/* EC registers to read from */
594d0ddfd24SEugene Shalygin 	u16 *registers;
595d0ddfd24SEugene Shalygin 	u8 *read_buffer;
596d0ddfd24SEugene Shalygin 	/* sorted list of unique register banks */
597d0ddfd24SEugene Shalygin 	u8 banks[ASUS_EC_MAX_BANK + 1];
598d0ddfd24SEugene Shalygin 	/* in jiffies */
599d0ddfd24SEugene Shalygin 	unsigned long last_updated;
600de8fbac5SEugene Shalygin 	struct lock_data lock_data;
601d0ddfd24SEugene Shalygin 	/* number of board EC sensors */
602d0ddfd24SEugene Shalygin 	u8 nr_sensors;
603d0ddfd24SEugene Shalygin 	/*
604d0ddfd24SEugene Shalygin 	 * number of EC registers to read
605d0ddfd24SEugene Shalygin 	 * (sensor might span more than 1 register)
606d0ddfd24SEugene Shalygin 	 */
607d0ddfd24SEugene Shalygin 	u8 nr_registers;
608d0ddfd24SEugene Shalygin 	/* number of unique register banks */
609d0ddfd24SEugene Shalygin 	u8 nr_banks;
610d0ddfd24SEugene Shalygin };
611d0ddfd24SEugene Shalygin 
register_bank(u16 reg)612d0ddfd24SEugene Shalygin static u8 register_bank(u16 reg)
613d0ddfd24SEugene Shalygin {
614d0ddfd24SEugene Shalygin 	return reg >> 8;
615d0ddfd24SEugene Shalygin }
616d0ddfd24SEugene Shalygin 
register_index(u16 reg)617d0ddfd24SEugene Shalygin static u8 register_index(u16 reg)
618d0ddfd24SEugene Shalygin {
619d0ddfd24SEugene Shalygin 	return reg & 0x00ff;
620d0ddfd24SEugene Shalygin }
621d0ddfd24SEugene Shalygin 
is_sensor_data_signed(const struct ec_sensor_info * si)6228aba9ca6SEugene Shalygin static bool is_sensor_data_signed(const struct ec_sensor_info *si)
6238aba9ca6SEugene Shalygin {
6248aba9ca6SEugene Shalygin 	/*
6258aba9ca6SEugene Shalygin 	 * guessed from WMI functions in DSDT code for boards
6268aba9ca6SEugene Shalygin 	 * of the X470 generation
6278aba9ca6SEugene Shalygin 	 */
6288aba9ca6SEugene Shalygin 	return si->type == hwmon_temp;
6298aba9ca6SEugene Shalygin }
6308aba9ca6SEugene Shalygin 
631d0ddfd24SEugene Shalygin static const struct ec_sensor_info *
get_sensor_info(const struct ec_sensors_data * state,int index)632d0ddfd24SEugene Shalygin get_sensor_info(const struct ec_sensors_data *state, int index)
633d0ddfd24SEugene Shalygin {
63445934e4aSEugene Shalygin 	return state->sensors_info + state->sensors[index].info_index;
635d0ddfd24SEugene Shalygin }
636d0ddfd24SEugene Shalygin 
find_ec_sensor_index(const struct ec_sensors_data * ec,enum hwmon_sensor_types type,int channel)637d0ddfd24SEugene Shalygin static int find_ec_sensor_index(const struct ec_sensors_data *ec,
638d0ddfd24SEugene Shalygin 				enum hwmon_sensor_types type, int channel)
639d0ddfd24SEugene Shalygin {
640d0ddfd24SEugene Shalygin 	unsigned int i;
641d0ddfd24SEugene Shalygin 
642d0ddfd24SEugene Shalygin 	for (i = 0; i < ec->nr_sensors; i++) {
643d0ddfd24SEugene Shalygin 		if (get_sensor_info(ec, i)->type == type) {
644d0ddfd24SEugene Shalygin 			if (channel == 0)
645d0ddfd24SEugene Shalygin 				return i;
646d0ddfd24SEugene Shalygin 			channel--;
647d0ddfd24SEugene Shalygin 		}
648d0ddfd24SEugene Shalygin 	}
649d0ddfd24SEugene Shalygin 	return -ENOENT;
650d0ddfd24SEugene Shalygin }
651d0ddfd24SEugene Shalygin 
bank_compare(const void * a,const void * b)65288700d13SEugene Shalygin static int bank_compare(const void *a, const void *b)
653d0ddfd24SEugene Shalygin {
654d0ddfd24SEugene Shalygin 	return *((const s8 *)a) - *((const s8 *)b);
655d0ddfd24SEugene Shalygin }
656d0ddfd24SEugene Shalygin 
setup_sensor_data(struct ec_sensors_data * ec)65788700d13SEugene Shalygin static void setup_sensor_data(struct ec_sensors_data *ec)
658d0ddfd24SEugene Shalygin {
659d0ddfd24SEugene Shalygin 	struct ec_sensor *s = ec->sensors;
660d0ddfd24SEugene Shalygin 	bool bank_found;
661d0ddfd24SEugene Shalygin 	int i, j;
662d0ddfd24SEugene Shalygin 	u8 bank;
663d0ddfd24SEugene Shalygin 
664d0ddfd24SEugene Shalygin 	ec->nr_banks = 0;
665d0ddfd24SEugene Shalygin 	ec->nr_registers = 0;
666d0ddfd24SEugene Shalygin 
6675cd29012SEugene Shalygin 	for_each_set_bit(i, &ec->board_info->sensors,
6685cd29012SEugene Shalygin 			 BITS_PER_TYPE(ec->board_info->sensors)) {
669d0ddfd24SEugene Shalygin 		s->info_index = i;
670d0ddfd24SEugene Shalygin 		s->cached_value = 0;
671d0ddfd24SEugene Shalygin 		ec->nr_registers +=
67245934e4aSEugene Shalygin 			ec->sensors_info[s->info_index].addr.components.size;
673d0ddfd24SEugene Shalygin 		bank_found = false;
67445934e4aSEugene Shalygin 		bank = ec->sensors_info[s->info_index].addr.components.bank;
675d0ddfd24SEugene Shalygin 		for (j = 0; j < ec->nr_banks; j++) {
676d0ddfd24SEugene Shalygin 			if (ec->banks[j] == bank) {
677d0ddfd24SEugene Shalygin 				bank_found = true;
678d0ddfd24SEugene Shalygin 				break;
679d0ddfd24SEugene Shalygin 			}
680d0ddfd24SEugene Shalygin 		}
681d0ddfd24SEugene Shalygin 		if (!bank_found) {
682d0ddfd24SEugene Shalygin 			ec->banks[ec->nr_banks++] = bank;
683d0ddfd24SEugene Shalygin 		}
684d0ddfd24SEugene Shalygin 		s++;
685d0ddfd24SEugene Shalygin 	}
686d0ddfd24SEugene Shalygin 	sort(ec->banks, ec->nr_banks, 1, bank_compare, NULL);
687d0ddfd24SEugene Shalygin }
688d0ddfd24SEugene Shalygin 
fill_ec_registers(struct ec_sensors_data * ec)68988700d13SEugene Shalygin static void fill_ec_registers(struct ec_sensors_data *ec)
690d0ddfd24SEugene Shalygin {
691d0ddfd24SEugene Shalygin 	const struct ec_sensor_info *si;
692d0ddfd24SEugene Shalygin 	unsigned int i, j, register_idx = 0;
693d0ddfd24SEugene Shalygin 
694d0ddfd24SEugene Shalygin 	for (i = 0; i < ec->nr_sensors; ++i) {
695d0ddfd24SEugene Shalygin 		si = get_sensor_info(ec, i);
696d0ddfd24SEugene Shalygin 		for (j = 0; j < si->addr.components.size; ++j, ++register_idx) {
697d0ddfd24SEugene Shalygin 			ec->registers[register_idx] =
698d0ddfd24SEugene Shalygin 				(si->addr.components.bank << 8) +
699d0ddfd24SEugene Shalygin 				si->addr.components.index + j;
700d0ddfd24SEugene Shalygin 		}
701d0ddfd24SEugene Shalygin 	}
702d0ddfd24SEugene Shalygin }
703d0ddfd24SEugene Shalygin 
setup_lock_data(struct device * dev)70488700d13SEugene Shalygin static int setup_lock_data(struct device *dev)
705d0ddfd24SEugene Shalygin {
706d0ddfd24SEugene Shalygin 	const char *mutex_path;
707d0ddfd24SEugene Shalygin 	int status;
708de8fbac5SEugene Shalygin 	struct ec_sensors_data *state = dev_get_drvdata(dev);
709d0ddfd24SEugene Shalygin 
710d0ddfd24SEugene Shalygin 	mutex_path = mutex_path_override ?
711de8fbac5SEugene Shalygin 		mutex_path_override : state->board_info->mutex_path;
712d0ddfd24SEugene Shalygin 
713de8fbac5SEugene Shalygin 	if (!mutex_path || !strlen(mutex_path)) {
714de8fbac5SEugene Shalygin 		dev_err(dev, "Hardware access guard mutex name is empty");
715de8fbac5SEugene Shalygin 		return -EINVAL;
716de8fbac5SEugene Shalygin 	}
717de8fbac5SEugene Shalygin 	if (!strcmp(mutex_path, ACPI_GLOBAL_LOCK_PSEUDO_PATH)) {
718de8fbac5SEugene Shalygin 		state->lock_data.mutex.glk = 0;
719de8fbac5SEugene Shalygin 		state->lock_data.lock = lock_via_global_acpi_lock;
720de8fbac5SEugene Shalygin 		state->lock_data.unlock = unlock_global_acpi_lock;
721de8fbac5SEugene Shalygin 	} else {
722de8fbac5SEugene Shalygin 		status = acpi_get_handle(NULL, (acpi_string)mutex_path,
723de8fbac5SEugene Shalygin 					 &state->lock_data.mutex.aml);
724d0ddfd24SEugene Shalygin 		if (ACPI_FAILURE(status)) {
725d0ddfd24SEugene Shalygin 			dev_err(dev,
726de8fbac5SEugene Shalygin 				"Failed to get hardware access guard AML mutex '%s': error %d",
727d0ddfd24SEugene Shalygin 				mutex_path, status);
728de8fbac5SEugene Shalygin 			return -ENOENT;
729d0ddfd24SEugene Shalygin 		}
730de8fbac5SEugene Shalygin 		state->lock_data.lock = lock_via_acpi_mutex;
731de8fbac5SEugene Shalygin 		state->lock_data.unlock = unlock_acpi_mutex;
732de8fbac5SEugene Shalygin 	}
733de8fbac5SEugene Shalygin 	return 0;
734d0ddfd24SEugene Shalygin }
735d0ddfd24SEugene Shalygin 
asus_ec_bank_switch(u8 bank,u8 * old)736d0ddfd24SEugene Shalygin static int asus_ec_bank_switch(u8 bank, u8 *old)
737d0ddfd24SEugene Shalygin {
738d0ddfd24SEugene Shalygin 	int status = 0;
739d0ddfd24SEugene Shalygin 
740d0ddfd24SEugene Shalygin 	if (old) {
741d0ddfd24SEugene Shalygin 		status = ec_read(ASUS_EC_BANK_REGISTER, old);
742d0ddfd24SEugene Shalygin 	}
743d0ddfd24SEugene Shalygin 	if (status || (old && (*old == bank)))
744d0ddfd24SEugene Shalygin 		return status;
745d0ddfd24SEugene Shalygin 	return ec_write(ASUS_EC_BANK_REGISTER, bank);
746d0ddfd24SEugene Shalygin }
747d0ddfd24SEugene Shalygin 
asus_ec_block_read(const struct device * dev,struct ec_sensors_data * ec)748d0ddfd24SEugene Shalygin static int asus_ec_block_read(const struct device *dev,
749d0ddfd24SEugene Shalygin 			      struct ec_sensors_data *ec)
750d0ddfd24SEugene Shalygin {
751d0ddfd24SEugene Shalygin 	int ireg, ibank, status;
752d0ddfd24SEugene Shalygin 	u8 bank, reg_bank, prev_bank;
753d0ddfd24SEugene Shalygin 
754d0ddfd24SEugene Shalygin 	bank = 0;
755d0ddfd24SEugene Shalygin 	status = asus_ec_bank_switch(bank, &prev_bank);
756d0ddfd24SEugene Shalygin 	if (status) {
757d0ddfd24SEugene Shalygin 		dev_warn(dev, "EC bank switch failed");
758d0ddfd24SEugene Shalygin 		return status;
759d0ddfd24SEugene Shalygin 	}
760d0ddfd24SEugene Shalygin 
761d0ddfd24SEugene Shalygin 	if (prev_bank) {
762d0ddfd24SEugene Shalygin 		/* oops... somebody else is working with the EC too */
763d0ddfd24SEugene Shalygin 		dev_warn(dev,
764d0ddfd24SEugene Shalygin 			"Concurrent access to the ACPI EC detected.\nRace condition possible.");
765d0ddfd24SEugene Shalygin 	}
766d0ddfd24SEugene Shalygin 
767d0ddfd24SEugene Shalygin 	/* read registers minimizing bank switches. */
768d0ddfd24SEugene Shalygin 	for (ibank = 0; ibank < ec->nr_banks; ibank++) {
769d0ddfd24SEugene Shalygin 		if (bank != ec->banks[ibank]) {
770d0ddfd24SEugene Shalygin 			bank = ec->banks[ibank];
771d0ddfd24SEugene Shalygin 			if (asus_ec_bank_switch(bank, NULL)) {
772d0ddfd24SEugene Shalygin 				dev_warn(dev, "EC bank switch to %d failed",
773d0ddfd24SEugene Shalygin 					 bank);
774d0ddfd24SEugene Shalygin 				break;
775d0ddfd24SEugene Shalygin 			}
776d0ddfd24SEugene Shalygin 		}
777d0ddfd24SEugene Shalygin 		for (ireg = 0; ireg < ec->nr_registers; ireg++) {
778d0ddfd24SEugene Shalygin 			reg_bank = register_bank(ec->registers[ireg]);
779d0ddfd24SEugene Shalygin 			if (reg_bank < bank) {
780d0ddfd24SEugene Shalygin 				continue;
781d0ddfd24SEugene Shalygin 			}
782d0ddfd24SEugene Shalygin 			ec_read(register_index(ec->registers[ireg]),
783d0ddfd24SEugene Shalygin 				ec->read_buffer + ireg);
784d0ddfd24SEugene Shalygin 		}
785d0ddfd24SEugene Shalygin 	}
786d0ddfd24SEugene Shalygin 
787d0ddfd24SEugene Shalygin 	status = asus_ec_bank_switch(prev_bank, NULL);
788d0ddfd24SEugene Shalygin 	return status;
789d0ddfd24SEugene Shalygin }
790d0ddfd24SEugene Shalygin 
get_sensor_value(const struct ec_sensor_info * si,u8 * data)791339f8a99SEugene Shalygin static inline s32 get_sensor_value(const struct ec_sensor_info *si, u8 *data)
792d0ddfd24SEugene Shalygin {
7938aba9ca6SEugene Shalygin 	if (is_sensor_data_signed(si)) {
794d0ddfd24SEugene Shalygin 		switch (si->addr.components.size) {
795d0ddfd24SEugene Shalygin 		case 1:
796339f8a99SEugene Shalygin 			return (s8)*data;
797d0ddfd24SEugene Shalygin 		case 2:
798339f8a99SEugene Shalygin 			return (s16)get_unaligned_be16(data);
799d0ddfd24SEugene Shalygin 		case 4:
800339f8a99SEugene Shalygin 			return (s32)get_unaligned_be32(data);
801d0ddfd24SEugene Shalygin 		default:
802d0ddfd24SEugene Shalygin 			return 0;
803d0ddfd24SEugene Shalygin 		}
8048aba9ca6SEugene Shalygin 	} else {
8058aba9ca6SEugene Shalygin 		switch (si->addr.components.size) {
8068aba9ca6SEugene Shalygin 		case 1:
8078aba9ca6SEugene Shalygin 			return *data;
8088aba9ca6SEugene Shalygin 		case 2:
8098aba9ca6SEugene Shalygin 			return get_unaligned_be16(data);
8108aba9ca6SEugene Shalygin 		case 4:
8118aba9ca6SEugene Shalygin 			return get_unaligned_be32(data);
8128aba9ca6SEugene Shalygin 		default:
8138aba9ca6SEugene Shalygin 			return 0;
8148aba9ca6SEugene Shalygin 		}
8158aba9ca6SEugene Shalygin 	}
816d0ddfd24SEugene Shalygin }
817d0ddfd24SEugene Shalygin 
update_sensor_values(struct ec_sensors_data * ec,u8 * data)818d0ddfd24SEugene Shalygin static void update_sensor_values(struct ec_sensors_data *ec, u8 *data)
819d0ddfd24SEugene Shalygin {
820d0ddfd24SEugene Shalygin 	const struct ec_sensor_info *si;
8215cd29012SEugene Shalygin 	struct ec_sensor *s, *sensor_end;
822d0ddfd24SEugene Shalygin 
8235cd29012SEugene Shalygin 	sensor_end = ec->sensors + ec->nr_sensors;
8245cd29012SEugene Shalygin 	for (s = ec->sensors; s != sensor_end; s++) {
82545934e4aSEugene Shalygin 		si = ec->sensors_info + s->info_index;
826d0ddfd24SEugene Shalygin 		s->cached_value = get_sensor_value(si, data);
827d0ddfd24SEugene Shalygin 		data += si->addr.components.size;
828d0ddfd24SEugene Shalygin 	}
829d0ddfd24SEugene Shalygin }
830d0ddfd24SEugene Shalygin 
update_ec_sensors(const struct device * dev,struct ec_sensors_data * ec)831d0ddfd24SEugene Shalygin static int update_ec_sensors(const struct device *dev,
832d0ddfd24SEugene Shalygin 			     struct ec_sensors_data *ec)
833d0ddfd24SEugene Shalygin {
834d0ddfd24SEugene Shalygin 	int status;
835d0ddfd24SEugene Shalygin 
836de8fbac5SEugene Shalygin 	if (!ec->lock_data.lock(&ec->lock_data)) {
837de8fbac5SEugene Shalygin 		dev_warn(dev, "Failed to acquire mutex");
838de8fbac5SEugene Shalygin 		return -EBUSY;
839d0ddfd24SEugene Shalygin 	}
840d0ddfd24SEugene Shalygin 
841d0ddfd24SEugene Shalygin 	status = asus_ec_block_read(dev, ec);
842d0ddfd24SEugene Shalygin 
843d0ddfd24SEugene Shalygin 	if (!status) {
844d0ddfd24SEugene Shalygin 		update_sensor_values(ec, ec->read_buffer);
845d0ddfd24SEugene Shalygin 	}
846de8fbac5SEugene Shalygin 
847de8fbac5SEugene Shalygin 	if (!ec->lock_data.unlock(&ec->lock_data))
848de8fbac5SEugene Shalygin 		dev_err(dev, "Failed to release mutex");
849de8fbac5SEugene Shalygin 
850d0ddfd24SEugene Shalygin 	return status;
851d0ddfd24SEugene Shalygin }
852d0ddfd24SEugene Shalygin 
scale_sensor_value(s32 value,int data_type)853339f8a99SEugene Shalygin static long scale_sensor_value(s32 value, int data_type)
854d0ddfd24SEugene Shalygin {
855d0ddfd24SEugene Shalygin 	switch (data_type) {
856d0ddfd24SEugene Shalygin 	case hwmon_curr:
857d0ddfd24SEugene Shalygin 	case hwmon_temp:
858d0ddfd24SEugene Shalygin 		return value * MILLI;
859d0ddfd24SEugene Shalygin 	default:
860d0ddfd24SEugene Shalygin 		return value;
861d0ddfd24SEugene Shalygin 	}
862d0ddfd24SEugene Shalygin }
863d0ddfd24SEugene Shalygin 
get_cached_value_or_update(const struct device * dev,int sensor_index,struct ec_sensors_data * state,s32 * value)864d0ddfd24SEugene Shalygin static int get_cached_value_or_update(const struct device *dev,
865d0ddfd24SEugene Shalygin 				      int sensor_index,
866339f8a99SEugene Shalygin 				      struct ec_sensors_data *state, s32 *value)
867d0ddfd24SEugene Shalygin {
868d0ddfd24SEugene Shalygin 	if (time_after(jiffies, state->last_updated + HZ)) {
869d0ddfd24SEugene Shalygin 		if (update_ec_sensors(dev, state)) {
870d0ddfd24SEugene Shalygin 			dev_err(dev, "update_ec_sensors() failure\n");
871d0ddfd24SEugene Shalygin 			return -EIO;
872d0ddfd24SEugene Shalygin 		}
873d0ddfd24SEugene Shalygin 
874d0ddfd24SEugene Shalygin 		state->last_updated = jiffies;
875d0ddfd24SEugene Shalygin 	}
876d0ddfd24SEugene Shalygin 
877d0ddfd24SEugene Shalygin 	*value = state->sensors[sensor_index].cached_value;
878d0ddfd24SEugene Shalygin 	return 0;
879d0ddfd24SEugene Shalygin }
880d0ddfd24SEugene Shalygin 
881d0ddfd24SEugene Shalygin /*
882d0ddfd24SEugene Shalygin  * Now follow the functions that implement the hwmon interface
883d0ddfd24SEugene Shalygin  */
884d0ddfd24SEugene Shalygin 
asus_ec_hwmon_read(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long * val)885d0ddfd24SEugene Shalygin static int asus_ec_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
886d0ddfd24SEugene Shalygin 			      u32 attr, int channel, long *val)
887d0ddfd24SEugene Shalygin {
888d0ddfd24SEugene Shalygin 	int ret;
889339f8a99SEugene Shalygin 	s32 value = 0;
890d0ddfd24SEugene Shalygin 
891d0ddfd24SEugene Shalygin 	struct ec_sensors_data *state = dev_get_drvdata(dev);
892d0ddfd24SEugene Shalygin 	int sidx = find_ec_sensor_index(state, type, channel);
893d0ddfd24SEugene Shalygin 
894d0ddfd24SEugene Shalygin 	if (sidx < 0) {
895d0ddfd24SEugene Shalygin 		return sidx;
896d0ddfd24SEugene Shalygin 	}
897d0ddfd24SEugene Shalygin 
898d0ddfd24SEugene Shalygin 	ret = get_cached_value_or_update(dev, sidx, state, &value);
899d0ddfd24SEugene Shalygin 	if (!ret) {
900d0ddfd24SEugene Shalygin 		*val = scale_sensor_value(value,
901d0ddfd24SEugene Shalygin 					  get_sensor_info(state, sidx)->type);
902d0ddfd24SEugene Shalygin 	}
903d0ddfd24SEugene Shalygin 
904d0ddfd24SEugene Shalygin 	return ret;
905d0ddfd24SEugene Shalygin }
906d0ddfd24SEugene Shalygin 
asus_ec_hwmon_read_string(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,const char ** str)907d0ddfd24SEugene Shalygin static int asus_ec_hwmon_read_string(struct device *dev,
908d0ddfd24SEugene Shalygin 				     enum hwmon_sensor_types type, u32 attr,
909d0ddfd24SEugene Shalygin 				     int channel, const char **str)
910d0ddfd24SEugene Shalygin {
911d0ddfd24SEugene Shalygin 	struct ec_sensors_data *state = dev_get_drvdata(dev);
912d0ddfd24SEugene Shalygin 	int sensor_index = find_ec_sensor_index(state, type, channel);
913d0ddfd24SEugene Shalygin 	*str = get_sensor_info(state, sensor_index)->label;
914d0ddfd24SEugene Shalygin 
915d0ddfd24SEugene Shalygin 	return 0;
916d0ddfd24SEugene Shalygin }
917d0ddfd24SEugene Shalygin 
asus_ec_hwmon_is_visible(const void * drvdata,enum hwmon_sensor_types type,u32 attr,int channel)918d0ddfd24SEugene Shalygin static umode_t asus_ec_hwmon_is_visible(const void *drvdata,
919d0ddfd24SEugene Shalygin 					enum hwmon_sensor_types type, u32 attr,
920d0ddfd24SEugene Shalygin 					int channel)
921d0ddfd24SEugene Shalygin {
922d0ddfd24SEugene Shalygin 	const struct ec_sensors_data *state = drvdata;
923d0ddfd24SEugene Shalygin 
924d0ddfd24SEugene Shalygin 	return find_ec_sensor_index(state, type, channel) >= 0 ? S_IRUGO : 0;
925d0ddfd24SEugene Shalygin }
926d0ddfd24SEugene Shalygin 
92788700d13SEugene Shalygin static int
asus_ec_hwmon_add_chan_info(struct hwmon_channel_info * asus_ec_hwmon_chan,struct device * dev,int num,enum hwmon_sensor_types type,u32 config)928d0ddfd24SEugene Shalygin asus_ec_hwmon_add_chan_info(struct hwmon_channel_info *asus_ec_hwmon_chan,
929d0ddfd24SEugene Shalygin 			     struct device *dev, int num,
930d0ddfd24SEugene Shalygin 			     enum hwmon_sensor_types type, u32 config)
931d0ddfd24SEugene Shalygin {
932d0ddfd24SEugene Shalygin 	int i;
933d0ddfd24SEugene Shalygin 	u32 *cfg = devm_kcalloc(dev, num + 1, sizeof(*cfg), GFP_KERNEL);
934d0ddfd24SEugene Shalygin 
935d0ddfd24SEugene Shalygin 	if (!cfg)
936d0ddfd24SEugene Shalygin 		return -ENOMEM;
937d0ddfd24SEugene Shalygin 
938d0ddfd24SEugene Shalygin 	asus_ec_hwmon_chan->type = type;
939d0ddfd24SEugene Shalygin 	asus_ec_hwmon_chan->config = cfg;
940d0ddfd24SEugene Shalygin 	for (i = 0; i < num; i++, cfg++)
941d0ddfd24SEugene Shalygin 		*cfg = config;
942d0ddfd24SEugene Shalygin 
943d0ddfd24SEugene Shalygin 	return 0;
944d0ddfd24SEugene Shalygin }
945d0ddfd24SEugene Shalygin 
946d0ddfd24SEugene Shalygin static const struct hwmon_ops asus_ec_hwmon_ops = {
947d0ddfd24SEugene Shalygin 	.is_visible = asus_ec_hwmon_is_visible,
948d0ddfd24SEugene Shalygin 	.read = asus_ec_hwmon_read,
949d0ddfd24SEugene Shalygin 	.read_string = asus_ec_hwmon_read_string,
950d0ddfd24SEugene Shalygin };
951d0ddfd24SEugene Shalygin 
952d0ddfd24SEugene Shalygin static struct hwmon_chip_info asus_ec_chip_info = {
953d0ddfd24SEugene Shalygin 	.ops = &asus_ec_hwmon_ops,
954d0ddfd24SEugene Shalygin };
955d0ddfd24SEugene Shalygin 
get_board_info(void)95688700d13SEugene Shalygin static const struct ec_board_info *get_board_info(void)
957d0ddfd24SEugene Shalygin {
95888700d13SEugene Shalygin 	const struct dmi_system_id *dmi_entry;
959d0ddfd24SEugene Shalygin 
96088700d13SEugene Shalygin 	dmi_entry = dmi_first_match(dmi_table);
96188700d13SEugene Shalygin 	return dmi_entry ? dmi_entry->driver_data : NULL;
9625cd29012SEugene Shalygin }
9635cd29012SEugene Shalygin 
asus_ec_probe(struct platform_device * pdev)96488700d13SEugene Shalygin static int asus_ec_probe(struct platform_device *pdev)
965d0ddfd24SEugene Shalygin {
966d0ddfd24SEugene Shalygin 	const struct hwmon_channel_info **ptr_asus_ec_ci;
9671298184bSEugene Shalygin 	int nr_count[hwmon_max] = { 0 }, nr_types = 0;
9681298184bSEugene Shalygin 	struct hwmon_channel_info *asus_ec_hwmon_chan;
9695cd29012SEugene Shalygin 	const struct ec_board_info *pboard_info;
970d0ddfd24SEugene Shalygin 	const struct hwmon_chip_info *chip_info;
9711298184bSEugene Shalygin 	struct device *dev = &pdev->dev;
9721298184bSEugene Shalygin 	struct ec_sensors_data *ec_data;
973d0ddfd24SEugene Shalygin 	const struct ec_sensor_info *si;
974d0ddfd24SEugene Shalygin 	enum hwmon_sensor_types type;
9751298184bSEugene Shalygin 	struct device *hwdev;
976d0ddfd24SEugene Shalygin 	unsigned int i;
977de8fbac5SEugene Shalygin 	int status;
978d0ddfd24SEugene Shalygin 
9795cd29012SEugene Shalygin 	pboard_info = get_board_info();
9805cd29012SEugene Shalygin 	if (!pboard_info)
981d0ddfd24SEugene Shalygin 		return -ENODEV;
982d0ddfd24SEugene Shalygin 
9831298184bSEugene Shalygin 	ec_data = devm_kzalloc(dev, sizeof(struct ec_sensors_data),
9841298184bSEugene Shalygin 			       GFP_KERNEL);
9851298184bSEugene Shalygin 	if (!ec_data)
9861298184bSEugene Shalygin 		return -ENOMEM;
9871298184bSEugene Shalygin 
9881298184bSEugene Shalygin 	dev_set_drvdata(dev, ec_data);
9895cd29012SEugene Shalygin 	ec_data->board_info = pboard_info;
99045934e4aSEugene Shalygin 
99145934e4aSEugene Shalygin 	switch (ec_data->board_info->family) {
9927cc44e5aSEugene Shalygin 	case family_amd_400_series:
9937cc44e5aSEugene Shalygin 		ec_data->sensors_info = sensors_family_amd_400;
9947cc44e5aSEugene Shalygin 		break;
99545934e4aSEugene Shalygin 	case family_amd_500_series:
99645934e4aSEugene Shalygin 		ec_data->sensors_info = sensors_family_amd_500;
99745934e4aSEugene Shalygin 		break;
998790dec13SMichael Carns 	case family_amd_600_series:
999790dec13SMichael Carns 		ec_data->sensors_info = sensors_family_amd_600;
1000790dec13SMichael Carns 		break;
10018f9eb10fSMichael Carns 	case family_intel_300_series:
10028f9eb10fSMichael Carns 		ec_data->sensors_info = sensors_family_intel_300;
10038f9eb10fSMichael Carns 		break;
1004bae26b80SShady Nawara 	case family_intel_600_series:
1005bae26b80SShady Nawara 		ec_data->sensors_info = sensors_family_intel_600;
1006bae26b80SShady Nawara 		break;
100745934e4aSEugene Shalygin 	default:
100845934e4aSEugene Shalygin 		dev_err(dev, "Unknown board family: %d",
100945934e4aSEugene Shalygin 			ec_data->board_info->family);
101045934e4aSEugene Shalygin 		return -EINVAL;
101145934e4aSEugene Shalygin 	}
101245934e4aSEugene Shalygin 
10135cd29012SEugene Shalygin 	ec_data->nr_sensors = hweight_long(ec_data->board_info->sensors);
1014d0ddfd24SEugene Shalygin 	ec_data->sensors = devm_kcalloc(dev, ec_data->nr_sensors,
1015d0ddfd24SEugene Shalygin 					sizeof(struct ec_sensor), GFP_KERNEL);
10169bdc112bSYuan Can 	if (!ec_data->sensors)
10179bdc112bSYuan Can 		return -ENOMEM;
1018d0ddfd24SEugene Shalygin 
1019de8fbac5SEugene Shalygin 	status = setup_lock_data(dev);
1020de8fbac5SEugene Shalygin 	if (status) {
1021de8fbac5SEugene Shalygin 		dev_err(dev, "Failed to setup state/EC locking: %d", status);
1022de8fbac5SEugene Shalygin 		return status;
1023de8fbac5SEugene Shalygin 	}
102445934e4aSEugene Shalygin 
1025d0ddfd24SEugene Shalygin 	setup_sensor_data(ec_data);
1026d0ddfd24SEugene Shalygin 	ec_data->registers = devm_kcalloc(dev, ec_data->nr_registers,
1027d0ddfd24SEugene Shalygin 					  sizeof(u16), GFP_KERNEL);
1028d0ddfd24SEugene Shalygin 	ec_data->read_buffer = devm_kcalloc(dev, ec_data->nr_registers,
1029d0ddfd24SEugene Shalygin 					    sizeof(u8), GFP_KERNEL);
1030d0ddfd24SEugene Shalygin 
10311298184bSEugene Shalygin 	if (!ec_data->registers || !ec_data->read_buffer)
1032d0ddfd24SEugene Shalygin 		return -ENOMEM;
1033d0ddfd24SEugene Shalygin 
1034d0ddfd24SEugene Shalygin 	fill_ec_registers(ec_data);
1035d0ddfd24SEugene Shalygin 
1036d0ddfd24SEugene Shalygin 	for (i = 0; i < ec_data->nr_sensors; ++i) {
1037d0ddfd24SEugene Shalygin 		si = get_sensor_info(ec_data, i);
1038d0ddfd24SEugene Shalygin 		if (!nr_count[si->type])
1039d0ddfd24SEugene Shalygin 			++nr_types;
1040d0ddfd24SEugene Shalygin 		++nr_count[si->type];
1041d0ddfd24SEugene Shalygin 	}
1042d0ddfd24SEugene Shalygin 
1043d0ddfd24SEugene Shalygin 	if (nr_count[hwmon_temp])
1044d0ddfd24SEugene Shalygin 		nr_count[hwmon_chip]++, nr_types++;
1045d0ddfd24SEugene Shalygin 
1046d0ddfd24SEugene Shalygin 	asus_ec_hwmon_chan = devm_kcalloc(
1047d0ddfd24SEugene Shalygin 		dev, nr_types, sizeof(*asus_ec_hwmon_chan), GFP_KERNEL);
1048d0ddfd24SEugene Shalygin 	if (!asus_ec_hwmon_chan)
1049d0ddfd24SEugene Shalygin 		return -ENOMEM;
1050d0ddfd24SEugene Shalygin 
1051d0ddfd24SEugene Shalygin 	ptr_asus_ec_ci = devm_kcalloc(dev, nr_types + 1,
1052d0ddfd24SEugene Shalygin 				       sizeof(*ptr_asus_ec_ci), GFP_KERNEL);
1053d0ddfd24SEugene Shalygin 	if (!ptr_asus_ec_ci)
1054d0ddfd24SEugene Shalygin 		return -ENOMEM;
1055d0ddfd24SEugene Shalygin 
1056d0ddfd24SEugene Shalygin 	asus_ec_chip_info.info = ptr_asus_ec_ci;
1057d0ddfd24SEugene Shalygin 	chip_info = &asus_ec_chip_info;
1058d0ddfd24SEugene Shalygin 
1059d0ddfd24SEugene Shalygin 	for (type = 0; type < hwmon_max; ++type) {
1060d0ddfd24SEugene Shalygin 		if (!nr_count[type])
1061d0ddfd24SEugene Shalygin 			continue;
1062d0ddfd24SEugene Shalygin 
1063d0ddfd24SEugene Shalygin 		asus_ec_hwmon_add_chan_info(asus_ec_hwmon_chan, dev,
1064d0ddfd24SEugene Shalygin 					     nr_count[type], type,
1065d0ddfd24SEugene Shalygin 					     hwmon_attributes[type]);
1066d0ddfd24SEugene Shalygin 		*ptr_asus_ec_ci++ = asus_ec_hwmon_chan++;
1067d0ddfd24SEugene Shalygin 	}
1068d0ddfd24SEugene Shalygin 
1069d0ddfd24SEugene Shalygin 	dev_info(dev, "board has %d EC sensors that span %d registers",
1070d0ddfd24SEugene Shalygin 		 ec_data->nr_sensors, ec_data->nr_registers);
1071d0ddfd24SEugene Shalygin 
1072d0ddfd24SEugene Shalygin 	hwdev = devm_hwmon_device_register_with_info(dev, "asusec",
1073d0ddfd24SEugene Shalygin 						     ec_data, chip_info, NULL);
1074d0ddfd24SEugene Shalygin 
1075d0ddfd24SEugene Shalygin 	return PTR_ERR_OR_ZERO(hwdev);
1076d0ddfd24SEugene Shalygin }
1077d0ddfd24SEugene Shalygin 
107888700d13SEugene Shalygin MODULE_DEVICE_TABLE(dmi, dmi_table);
1079d0ddfd24SEugene Shalygin 
1080d0ddfd24SEugene Shalygin static struct platform_driver asus_ec_sensors_platform_driver = {
1081d0ddfd24SEugene Shalygin 	.driver = {
1082d0ddfd24SEugene Shalygin 		.name	= "asus-ec-sensors",
1083d0ddfd24SEugene Shalygin 	},
108488700d13SEugene Shalygin 	.probe = asus_ec_probe,
1085d0ddfd24SEugene Shalygin };
1086d0ddfd24SEugene Shalygin 
108788700d13SEugene Shalygin static struct platform_device *asus_ec_sensors_platform_device;
108888700d13SEugene Shalygin 
asus_ec_init(void)108988700d13SEugene Shalygin static int __init asus_ec_init(void)
109088700d13SEugene Shalygin {
109188700d13SEugene Shalygin 	asus_ec_sensors_platform_device =
109288700d13SEugene Shalygin 		platform_create_bundle(&asus_ec_sensors_platform_driver,
109388700d13SEugene Shalygin 				       asus_ec_probe, NULL, 0, NULL, 0);
109488700d13SEugene Shalygin 
109588700d13SEugene Shalygin 	if (IS_ERR(asus_ec_sensors_platform_device))
109688700d13SEugene Shalygin 		return PTR_ERR(asus_ec_sensors_platform_device);
109788700d13SEugene Shalygin 
109888700d13SEugene Shalygin 	return 0;
109988700d13SEugene Shalygin }
110088700d13SEugene Shalygin 
asus_ec_exit(void)110188700d13SEugene Shalygin static void __exit asus_ec_exit(void)
110288700d13SEugene Shalygin {
110388700d13SEugene Shalygin 	platform_device_unregister(asus_ec_sensors_platform_device);
110488700d13SEugene Shalygin 	platform_driver_unregister(&asus_ec_sensors_platform_driver);
110588700d13SEugene Shalygin }
110688700d13SEugene Shalygin 
110788700d13SEugene Shalygin module_init(asus_ec_init);
110888700d13SEugene Shalygin module_exit(asus_ec_exit);
1109d0ddfd24SEugene Shalygin 
1110d0ddfd24SEugene Shalygin module_param_named(mutex_path, mutex_path_override, charp, 0);
1111d0ddfd24SEugene Shalygin MODULE_PARM_DESC(mutex_path,
1112d0ddfd24SEugene Shalygin 		 "Override ACPI mutex path used to guard access to hardware");
1113d0ddfd24SEugene Shalygin 
1114d0ddfd24SEugene Shalygin MODULE_AUTHOR("Eugene Shalygin <eugene.shalygin@gmail.com>");
1115d0ddfd24SEugene Shalygin MODULE_DESCRIPTION(
1116d0ddfd24SEugene Shalygin 	"HWMON driver for sensors accessible via ACPI EC in ASUS motherboards");
1117d0ddfd24SEugene Shalygin MODULE_LICENSE("GPL");
1118