1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "xe_wa.h" 7 8 #include <drm/drm_managed.h> 9 #include <kunit/visibility.h> 10 #include <linux/compiler_types.h> 11 #include <linux/fault-inject.h> 12 13 #include <generated/xe_wa_oob.h> 14 15 #include "regs/xe_engine_regs.h" 16 #include "regs/xe_gt_regs.h" 17 #include "regs/xe_regs.h" 18 #include "xe_device_types.h" 19 #include "xe_force_wake.h" 20 #include "xe_gt.h" 21 #include "xe_hw_engine_types.h" 22 #include "xe_mmio.h" 23 #include "xe_platform_types.h" 24 #include "xe_rtp.h" 25 #include "xe_sriov.h" 26 #include "xe_step.h" 27 28 /** 29 * DOC: Hardware workarounds 30 * 31 * Hardware workarounds are register programming documented to be executed in 32 * the driver that fall outside of the normal programming sequences for a 33 * platform. There are some basic categories of workarounds, depending on 34 * how/when they are applied: 35 * 36 * - LRC workarounds: workarounds that touch registers that are 37 * saved/restored to/from the HW context image. The list is emitted (via Load 38 * Register Immediate commands) once when initializing the device and saved in 39 * the default context. That default context is then used on every context 40 * creation to have a "primed golden context", i.e. a context image that 41 * already contains the changes needed to all the registers. 42 * 43 * - Engine workarounds: the list of these WAs is applied whenever the specific 44 * engine is reset. It's also possible that a set of engine classes share a 45 * common power domain and they are reset together. This happens on some 46 * platforms with render and compute engines. In this case (at least) one of 47 * them need to keeep the workaround programming: the approach taken in the 48 * driver is to tie those workarounds to the first compute/render engine that 49 * is registered. When executing with GuC submission, engine resets are 50 * outside of kernel driver control, hence the list of registers involved in 51 * written once, on engine initialization, and then passed to GuC, that 52 * saves/restores their values before/after the reset takes place. See 53 * ``drivers/gpu/drm/xe/xe_guc_ads.c`` for reference. 54 * 55 * - GT workarounds: the list of these WAs is applied whenever these registers 56 * revert to their default values: on GPU reset, suspend/resume [1]_, etc. 57 * 58 * - Register whitelist: some workarounds need to be implemented in userspace, 59 * but need to touch privileged registers. The whitelist in the kernel 60 * instructs the hardware to allow the access to happen. From the kernel side, 61 * this is just a special case of a MMIO workaround (as we write the list of 62 * these to/be-whitelisted registers to some special HW registers). 63 * 64 * - Workaround batchbuffers: buffers that get executed automatically by the 65 * hardware on every HW context restore. These buffers are created and 66 * programmed in the default context so the hardware always go through those 67 * programming sequences when switching contexts. The support for workaround 68 * batchbuffers is enabled these hardware mechanisms: 69 * 70 * #. INDIRECT_CTX: A batchbuffer and an offset are provided in the default 71 * context, pointing the hardware to jump to that location when that offset 72 * is reached in the context restore. Workaround batchbuffer in the driver 73 * currently uses this mechanism for all platforms. 74 * 75 * #. BB_PER_CTX_PTR: A batchbuffer is provided in the default context, 76 * pointing the hardware to a buffer to continue executing after the 77 * engine registers are restored in a context restore sequence. This is 78 * currently not used in the driver. 79 * 80 * - Other/OOB: There are WAs that, due to their nature, cannot be applied from 81 * a central place. Those are peppered around the rest of the code, as needed. 82 * Workarounds related to the display IP are the main example. 83 * 84 * .. [1] Technically, some registers are powercontext saved & restored, so they 85 * survive a suspend/resume. In practice, writing them again is not too 86 * costly and simplifies things, so it's the approach taken in the driver. 87 * 88 * .. note:: 89 * Hardware workarounds in xe work the same way as in i915, with the 90 * difference of how they are maintained in the code. In xe it uses the 91 * xe_rtp infrastructure so the workarounds can be kept in tables, following 92 * a more declarative approach rather than procedural. 93 */ 94 95 #undef XE_REG_MCR 96 #define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1) 97 98 __diag_push(); 99 __diag_ignore_all("-Woverride-init", "Allow field overrides in table"); 100 101 static const struct xe_rtp_entry_sr gt_was[] = { 102 { XE_RTP_NAME("14011060649"), 103 XE_RTP_RULES(MEDIA_VERSION_RANGE(1200, 1255), 104 ENGINE_CLASS(VIDEO_DECODE), 105 FUNC(xe_rtp_match_even_instance)), 106 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)), 107 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 108 }, 109 { XE_RTP_NAME("14011059788"), 110 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)), 111 XE_RTP_ACTIONS(SET(DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE)) 112 }, 113 { XE_RTP_NAME("14015795083"), 114 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1260)), 115 XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE)) 116 }, 117 118 /* DG1 */ 119 120 { XE_RTP_NAME("1409420604"), 121 XE_RTP_RULES(PLATFORM(DG1)), 122 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE2, CPSSUNIT_CLKGATE_DIS)) 123 }, 124 { XE_RTP_NAME("1408615072"), 125 XE_RTP_RULES(PLATFORM(DG1)), 126 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE2_DIS)) 127 }, 128 129 /* DG2 */ 130 131 { XE_RTP_NAME("22010523718"), 132 XE_RTP_RULES(SUBPLATFORM(DG2, G10)), 133 XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE, CG3DDISCFEG_CLKGATE_DIS)) 134 }, 135 { XE_RTP_NAME("14011006942"), 136 XE_RTP_RULES(SUBPLATFORM(DG2, G10)), 137 XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE, DSS_ROUTER_CLKGATE_DIS)) 138 }, 139 { XE_RTP_NAME("14014830051"), 140 XE_RTP_RULES(PLATFORM(DG2)), 141 XE_RTP_ACTIONS(CLR(SARB_CHICKEN1, COMP_CKN_IN)) 142 }, 143 { XE_RTP_NAME("18018781329"), 144 XE_RTP_RULES(PLATFORM(DG2)), 145 XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB), 146 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB), 147 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB), 148 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB)) 149 }, 150 { XE_RTP_NAME("1509235366"), 151 XE_RTP_RULES(PLATFORM(DG2)), 152 XE_RTP_ACTIONS(SET(XEHP_GAMCNTRL_CTRL, 153 INVALIDATION_BROADCAST_MODE_DIS | 154 GLOBAL_INVALIDATION_MODE)) 155 }, 156 157 /* PVC */ 158 159 { XE_RTP_NAME("18018781329"), 160 XE_RTP_RULES(PLATFORM(PVC)), 161 XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB), 162 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB), 163 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB), 164 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB)) 165 }, 166 { XE_RTP_NAME("16016694945"), 167 XE_RTP_RULES(PLATFORM(PVC)), 168 XE_RTP_ACTIONS(SET(XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC)) 169 }, 170 171 /* Xe_LPG */ 172 173 { XE_RTP_NAME("14015795083"), 174 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271), GRAPHICS_STEP(A0, B0)), 175 XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE)) 176 }, 177 { XE_RTP_NAME("14018575942"), 178 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)), 179 XE_RTP_ACTIONS(SET(COMP_MOD_CTRL, FORCE_MISS_FTLB)) 180 }, 181 { XE_RTP_NAME("22016670082"), 182 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)), 183 XE_RTP_ACTIONS(SET(SQCNT1, ENFORCE_RAR)) 184 }, 185 186 /* Xe_LPM+ */ 187 188 { XE_RTP_NAME("16021867713"), 189 XE_RTP_RULES(MEDIA_VERSION(1300), 190 ENGINE_CLASS(VIDEO_DECODE)), 191 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)), 192 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 193 }, 194 { XE_RTP_NAME("22016670082"), 195 XE_RTP_RULES(MEDIA_VERSION(1300)), 196 XE_RTP_ACTIONS(SET(XELPMP_SQCNT1, ENFORCE_RAR)) 197 }, 198 199 /* Xe2_LPG */ 200 201 { XE_RTP_NAME("16020975621"), 202 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)), 203 XE_RTP_ACTIONS(SET(XEHP_SLICE_UNIT_LEVEL_CLKGATE, SBEUNIT_CLKGATE_DIS)) 204 }, 205 { XE_RTP_NAME("14018157293"), 206 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)), 207 XE_RTP_ACTIONS(SET(XEHPC_L3CLOS_MASK(0), ~0), 208 SET(XEHPC_L3CLOS_MASK(1), ~0), 209 SET(XEHPC_L3CLOS_MASK(2), ~0), 210 SET(XEHPC_L3CLOS_MASK(3), ~0)) 211 }, 212 213 /* Xe2_LPM */ 214 215 { XE_RTP_NAME("14017421178"), 216 XE_RTP_RULES(MEDIA_VERSION(2000), 217 ENGINE_CLASS(VIDEO_DECODE)), 218 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)), 219 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 220 }, 221 { XE_RTP_NAME("16021867713"), 222 XE_RTP_RULES(MEDIA_VERSION(2000), 223 ENGINE_CLASS(VIDEO_DECODE)), 224 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)), 225 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 226 }, 227 { XE_RTP_NAME("14019449301"), 228 XE_RTP_RULES(MEDIA_VERSION(2000), ENGINE_CLASS(VIDEO_DECODE)), 229 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)), 230 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 231 }, 232 233 /* Xe2_HPM */ 234 235 { XE_RTP_NAME("16021867713"), 236 XE_RTP_RULES(MEDIA_VERSION(1301), 237 ENGINE_CLASS(VIDEO_DECODE)), 238 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)), 239 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 240 }, 241 { XE_RTP_NAME("14020316580"), 242 XE_RTP_RULES(MEDIA_VERSION(1301)), 243 XE_RTP_ACTIONS(CLR(POWERGATE_ENABLE, 244 VDN_HCP_POWERGATE_ENABLE(0) | 245 VDN_MFXVDENC_POWERGATE_ENABLE(0) | 246 VDN_HCP_POWERGATE_ENABLE(2) | 247 VDN_MFXVDENC_POWERGATE_ENABLE(2))), 248 }, 249 { XE_RTP_NAME("14019449301"), 250 XE_RTP_RULES(MEDIA_VERSION(1301), ENGINE_CLASS(VIDEO_DECODE)), 251 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)), 252 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 253 }, 254 255 /* Xe3_LPG */ 256 257 { XE_RTP_NAME("14021871409"), 258 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0)), 259 XE_RTP_ACTIONS(SET(UNSLCGCTL9454, LSCFE_CLKGATE_DIS)) 260 }, 261 262 /* Xe3_LPM */ 263 264 { XE_RTP_NAME("16021867713"), 265 XE_RTP_RULES(MEDIA_VERSION(3000), 266 ENGINE_CLASS(VIDEO_DECODE)), 267 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)), 268 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 269 }, 270 { XE_RTP_NAME("16021865536"), 271 XE_RTP_RULES(MEDIA_VERSION(3000), 272 ENGINE_CLASS(VIDEO_DECODE)), 273 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)), 274 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 275 }, 276 { XE_RTP_NAME("14021486841"), 277 XE_RTP_RULES(MEDIA_VERSION(3000), MEDIA_STEP(A0, B0), 278 ENGINE_CLASS(VIDEO_DECODE)), 279 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), RAMDFTUNIT_CLKGATE_DIS)), 280 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 281 }, 282 }; 283 284 static const struct xe_rtp_entry_sr engine_was[] = { 285 { XE_RTP_NAME("22010931296, 18011464164, 14010919138"), 286 XE_RTP_RULES(GRAPHICS_VERSION(1200), ENGINE_CLASS(RENDER)), 287 XE_RTP_ACTIONS(SET(FF_THREAD_MODE(RENDER_RING_BASE), 288 FF_TESSELATION_DOP_GATE_DISABLE)) 289 }, 290 { XE_RTP_NAME("1409804808"), 291 XE_RTP_RULES(GRAPHICS_VERSION(1200), 292 ENGINE_CLASS(RENDER), 293 IS_INTEGRATED), 294 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, PUSH_CONST_DEREF_HOLD_DIS)) 295 }, 296 { XE_RTP_NAME("14010229206, 1409085225"), 297 XE_RTP_RULES(GRAPHICS_VERSION(1200), 298 ENGINE_CLASS(RENDER), 299 IS_INTEGRATED), 300 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH)) 301 }, 302 { XE_RTP_NAME("1606931601"), 303 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 304 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_EARLY_READ)) 305 }, 306 { XE_RTP_NAME("14010826681, 1606700617, 22010271021, 18019627453"), 307 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1255), ENGINE_CLASS(RENDER)), 308 XE_RTP_ACTIONS(SET(CS_DEBUG_MODE1(RENDER_RING_BASE), 309 FF_DOP_CLOCK_GATE_DISABLE)) 310 }, 311 { XE_RTP_NAME("1406941453"), 312 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 313 XE_RTP_ACTIONS(SET(SAMPLER_MODE, ENABLE_SMALLPL)) 314 }, 315 { XE_RTP_NAME("FtrPerCtxtPreemptionGranularityControl"), 316 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1250), ENGINE_CLASS(RENDER)), 317 XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN1(RENDER_RING_BASE), 318 FFSC_PERCTX_PREEMPT_CTRL)) 319 }, 320 321 /* TGL */ 322 323 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"), 324 XE_RTP_RULES(PLATFORM(TIGERLAKE), ENGINE_CLASS(RENDER)), 325 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE), 326 WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 327 RC_SEMA_IDLE_MSG_DISABLE)) 328 }, 329 330 /* RKL */ 331 332 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"), 333 XE_RTP_RULES(PLATFORM(ROCKETLAKE), ENGINE_CLASS(RENDER)), 334 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE), 335 WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 336 RC_SEMA_IDLE_MSG_DISABLE)) 337 }, 338 339 /* ADL-P */ 340 341 { XE_RTP_NAME("1607297627, 1607030317, 1607186500"), 342 XE_RTP_RULES(PLATFORM(ALDERLAKE_P), ENGINE_CLASS(RENDER)), 343 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE), 344 WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 345 RC_SEMA_IDLE_MSG_DISABLE)) 346 }, 347 348 /* DG2 */ 349 350 { XE_RTP_NAME("22013037850"), 351 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 352 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, 353 DISABLE_128B_EVICTION_COMMAND_UDW)) 354 }, 355 { XE_RTP_NAME("22014226127"), 356 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 357 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE)) 358 }, 359 { XE_RTP_NAME("18017747507"), 360 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 361 XE_RTP_ACTIONS(SET(VFG_PREEMPTION_CHICKEN, 362 POLYGON_TRIFAN_LINELOOP_DISABLE)) 363 }, 364 { XE_RTP_NAME("22012826095, 22013059131"), 365 XE_RTP_RULES(SUBPLATFORM(DG2, G11), 366 FUNC(xe_rtp_match_first_render_or_compute)), 367 XE_RTP_ACTIONS(FIELD_SET(LSC_CHICKEN_BIT_0_UDW, 368 MAXREQS_PER_BANK, 369 REG_FIELD_PREP(MAXREQS_PER_BANK, 2))) 370 }, 371 { XE_RTP_NAME("22013059131"), 372 XE_RTP_RULES(SUBPLATFORM(DG2, G11), 373 FUNC(xe_rtp_match_first_render_or_compute)), 374 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, FORCE_1_SUB_MESSAGE_PER_FRAGMENT)) 375 }, 376 { XE_RTP_NAME("14015227452"), 377 XE_RTP_RULES(PLATFORM(DG2), 378 FUNC(xe_rtp_match_first_render_or_compute)), 379 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE)) 380 }, 381 { XE_RTP_NAME("18028616096"), 382 XE_RTP_RULES(PLATFORM(DG2), 383 FUNC(xe_rtp_match_first_render_or_compute)), 384 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3)) 385 }, 386 { XE_RTP_NAME("22015475538"), 387 XE_RTP_RULES(PLATFORM(DG2), 388 FUNC(xe_rtp_match_first_render_or_compute)), 389 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8)) 390 }, 391 { XE_RTP_NAME("22012654132"), 392 XE_RTP_RULES(SUBPLATFORM(DG2, G11), 393 FUNC(xe_rtp_match_first_render_or_compute)), 394 XE_RTP_ACTIONS(SET(CACHE_MODE_SS, ENABLE_PREFETCH_INTO_IC, 395 /* 396 * Register can't be read back for verification on 397 * DG2 due to Wa_14012342262 398 */ 399 .read_mask = 0)) 400 }, 401 { XE_RTP_NAME("1509727124"), 402 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), 403 XE_RTP_ACTIONS(SET(SAMPLER_MODE, SC_DISABLE_POWER_OPTIMIZATION_EBB)) 404 }, 405 { XE_RTP_NAME("22012856258"), 406 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), 407 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_READ_SUPPRESSION)) 408 }, 409 { XE_RTP_NAME("22010960976, 14013347512"), 410 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)), 411 XE_RTP_ACTIONS(CLR(XEHP_HDC_CHICKEN0, 412 LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK)) 413 }, 414 { XE_RTP_NAME("14015150844"), 415 XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), 416 XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES, 417 XE_RTP_NOCHECK)) 418 }, 419 420 /* PVC */ 421 422 { XE_RTP_NAME("22014226127"), 423 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)), 424 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE)) 425 }, 426 { XE_RTP_NAME("14015227452"), 427 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)), 428 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE)) 429 }, 430 { XE_RTP_NAME("18020744125"), 431 XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute), 432 ENGINE_CLASS(COMPUTE)), 433 XE_RTP_ACTIONS(SET(RING_HWSTAM(RENDER_RING_BASE), ~0)) 434 }, 435 { XE_RTP_NAME("14014999345"), 436 XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COMPUTE), 437 GRAPHICS_STEP(B0, C0)), 438 XE_RTP_ACTIONS(SET(CACHE_MODE_SS, DISABLE_ECC)) 439 }, 440 441 /* Xe_LPG */ 442 443 { XE_RTP_NAME("14017856879"), 444 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274), 445 FUNC(xe_rtp_match_first_render_or_compute)), 446 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, DIS_FIX_EOT1_FLUSH)) 447 }, 448 { XE_RTP_NAME("14015150844"), 449 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271), 450 FUNC(xe_rtp_match_first_render_or_compute)), 451 XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES, 452 XE_RTP_NOCHECK)) 453 }, 454 { XE_RTP_NAME("14020495402"), 455 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274), 456 FUNC(xe_rtp_match_first_render_or_compute)), 457 XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_TDL_SVHS_GATING)) 458 }, 459 460 /* Xe2_LPG */ 461 462 { XE_RTP_NAME("18032247524"), 463 XE_RTP_RULES(GRAPHICS_VERSION(2004), 464 FUNC(xe_rtp_match_first_render_or_compute)), 465 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE)) 466 }, 467 { XE_RTP_NAME("16018712365"), 468 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)), 469 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS)) 470 }, 471 { XE_RTP_NAME("14018957109"), 472 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0), 473 FUNC(xe_rtp_match_first_render_or_compute)), 474 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN5, DISABLE_SAMPLE_G_PERFORMANCE)) 475 }, 476 { XE_RTP_NAME("14020338487"), 477 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)), 478 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS)) 479 }, 480 { XE_RTP_NAME("18034896535, 16021540221"), /* 16021540221: GRAPHICS_STEP(A0, B0) */ 481 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), 482 FUNC(xe_rtp_match_first_render_or_compute)), 483 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH)) 484 }, 485 { XE_RTP_NAME("14019322943"), 486 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0), 487 FUNC(xe_rtp_match_first_render_or_compute)), 488 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, TGM_WRITE_EOM_FORCE)) 489 }, 490 { XE_RTP_NAME("14018471104"), 491 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)), 492 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL)) 493 }, 494 { XE_RTP_NAME("16018737384"), 495 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)), 496 XE_RTP_ACTIONS(SET(ROW_CHICKEN, EARLY_EOT_DIS)) 497 }, 498 /* 499 * These two workarounds are the same, just applying to different 500 * engines. Although Wa_18032095049 (for the RCS) isn't required on 501 * all steppings, disabling these reports has no impact for our 502 * driver or the GuC, so we go ahead and treat it the same as 503 * Wa_16021639441 which does apply to all steppings. 504 */ 505 { XE_RTP_NAME("18032095049, 16021639441"), 506 XE_RTP_RULES(GRAPHICS_VERSION(2004)), 507 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), 508 GHWSP_CSB_REPORT_DIS | 509 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS, 510 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 511 }, 512 { XE_RTP_NAME("16018610683"), 513 XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)), 514 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, SLM_WMTP_RESTORE)) 515 }, 516 { XE_RTP_NAME("14021402888"), 517 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 518 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE)) 519 }, 520 521 /* Xe2_HPG */ 522 523 { XE_RTP_NAME("16018712365"), 524 XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)), 525 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS)) 526 }, 527 { XE_RTP_NAME("16018737384"), 528 XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)), 529 XE_RTP_ACTIONS(SET(ROW_CHICKEN, EARLY_EOT_DIS)) 530 }, 531 { XE_RTP_NAME("14019988906"), 532 XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)), 533 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD)) 534 }, 535 { XE_RTP_NAME("14019877138"), 536 XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)), 537 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT)) 538 }, 539 { XE_RTP_NAME("14020338487"), 540 XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)), 541 XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS)) 542 }, 543 { XE_RTP_NAME("18032247524"), 544 XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)), 545 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE)) 546 }, 547 { XE_RTP_NAME("14018471104"), 548 XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)), 549 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL)) 550 }, 551 /* 552 * Although this workaround isn't required for the RCS, disabling these 553 * reports has no impact for our driver or the GuC, so we go ahead and 554 * apply this to all engines for simplicity. 555 */ 556 { XE_RTP_NAME("16021639441"), 557 XE_RTP_RULES(GRAPHICS_VERSION(2001)), 558 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), 559 GHWSP_CSB_REPORT_DIS | 560 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS, 561 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 562 }, 563 { XE_RTP_NAME("14019811474"), 564 XE_RTP_RULES(GRAPHICS_VERSION(2001), 565 FUNC(xe_rtp_match_first_render_or_compute)), 566 XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, WR_REQ_CHAINING_DIS)) 567 }, 568 { XE_RTP_NAME("14021402888"), 569 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), 570 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE)) 571 }, 572 { XE_RTP_NAME("14021821874"), 573 XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)), 574 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, STK_ID_RESTRICT)) 575 }, 576 577 /* Xe2_LPM */ 578 579 { XE_RTP_NAME("16021639441"), 580 XE_RTP_RULES(MEDIA_VERSION(2000)), 581 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), 582 GHWSP_CSB_REPORT_DIS | 583 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS, 584 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 585 }, 586 587 /* Xe2_HPM */ 588 589 { XE_RTP_NAME("16021639441"), 590 XE_RTP_RULES(MEDIA_VERSION(1301)), 591 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), 592 GHWSP_CSB_REPORT_DIS | 593 PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS, 594 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 595 }, 596 597 /* Xe3_LPG */ 598 599 { XE_RTP_NAME("14021402888"), 600 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001), 601 FUNC(xe_rtp_match_first_render_or_compute)), 602 XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE)) 603 }, 604 { XE_RTP_NAME("18034896535"), 605 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0), 606 FUNC(xe_rtp_match_first_render_or_compute)), 607 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH)) 608 }, 609 { XE_RTP_NAME("16024792527"), 610 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0), 611 FUNC(xe_rtp_match_first_render_or_compute)), 612 XE_RTP_ACTIONS(FIELD_SET(SAMPLER_MODE, SMP_WAIT_FETCH_MERGING_COUNTER, 613 SMP_FORCE_128B_OVERFETCH)) 614 }, 615 { XE_RTP_NAME("14023061436"), 616 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001), 617 FUNC(xe_rtp_match_first_render_or_compute)), 618 XE_RTP_ACTIONS(SET(TDL_CHICKEN, QID_WAIT_FOR_THREAD_NOT_RUN_DISABLE)) 619 }, 620 { XE_RTP_NAME("13012615864"), 621 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001), 622 FUNC(xe_rtp_match_first_render_or_compute)), 623 XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS)) 624 }, 625 }; 626 627 static const struct xe_rtp_entry_sr lrc_was[] = { 628 { XE_RTP_NAME("16011163337"), 629 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 630 /* read verification is ignored due to 1608008084. */ 631 XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(FF_MODE2, 632 FF_MODE2_GS_TIMER_MASK, 633 FF_MODE2_GS_TIMER_224)) 634 }, 635 { XE_RTP_NAME("1604555607"), 636 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)), 637 /* read verification is ignored due to 1608008084. */ 638 XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(FF_MODE2, 639 FF_MODE2_TDS_TIMER_MASK, 640 FF_MODE2_TDS_TIMER_128)) 641 }, 642 { XE_RTP_NAME("1409342910, 14010698770, 14010443199, 1408979724, 1409178076, 1409207793, 1409217633, 1409252684, 1409347922, 1409142259"), 643 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)), 644 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN3, 645 DISABLE_CPS_AWARE_COLOR_PIPE)) 646 }, 647 { XE_RTP_NAME("WaDisableGPGPUMidThreadPreemption"), 648 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)), 649 XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1(RENDER_RING_BASE), 650 PREEMPT_GPGPU_LEVEL_MASK, 651 PREEMPT_GPGPU_THREAD_GROUP_LEVEL)) 652 }, 653 { XE_RTP_NAME("1806527549"), 654 XE_RTP_RULES(GRAPHICS_VERSION(1200)), 655 XE_RTP_ACTIONS(SET(HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE)) 656 }, 657 { XE_RTP_NAME("1606376872"), 658 XE_RTP_RULES(GRAPHICS_VERSION(1200)), 659 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC)) 660 }, 661 662 /* DG1 */ 663 664 { XE_RTP_NAME("1409044764"), 665 XE_RTP_RULES(PLATFORM(DG1)), 666 XE_RTP_ACTIONS(CLR(COMMON_SLICE_CHICKEN3, 667 DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN)) 668 }, 669 { XE_RTP_NAME("22010493298"), 670 XE_RTP_RULES(PLATFORM(DG1)), 671 XE_RTP_ACTIONS(SET(HIZ_CHICKEN, 672 DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE)) 673 }, 674 675 /* DG2 */ 676 677 { XE_RTP_NAME("16013271637"), 678 XE_RTP_RULES(PLATFORM(DG2)), 679 XE_RTP_ACTIONS(SET(XEHP_SLICE_COMMON_ECO_CHICKEN1, 680 MSC_MSAA_REODER_BUF_BYPASS_DISABLE)) 681 }, 682 { XE_RTP_NAME("14014947963"), 683 XE_RTP_RULES(PLATFORM(DG2)), 684 XE_RTP_ACTIONS(FIELD_SET(VF_PREEMPTION, 685 PREEMPTION_VERTEX_COUNT, 686 0x4000)) 687 }, 688 { XE_RTP_NAME("18018764978"), 689 XE_RTP_RULES(PLATFORM(DG2)), 690 XE_RTP_ACTIONS(SET(XEHP_PSS_MODE2, 691 SCOREBOARD_STALL_FLUSH_CONTROL)) 692 }, 693 { XE_RTP_NAME("18019271663"), 694 XE_RTP_RULES(PLATFORM(DG2)), 695 XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE)) 696 }, 697 { XE_RTP_NAME("14019877138"), 698 XE_RTP_RULES(PLATFORM(DG2)), 699 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT)) 700 }, 701 702 /* PVC */ 703 704 { XE_RTP_NAME("16017236439"), 705 XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COPY), 706 FUNC(xe_rtp_match_even_instance)), 707 XE_RTP_ACTIONS(SET(BCS_SWCTRL(0), 708 BCS_SWCTRL_DISABLE_256B, 709 XE_RTP_ACTION_FLAG(ENGINE_BASE))), 710 }, 711 712 /* Xe_LPG */ 713 714 { XE_RTP_NAME("18019271663"), 715 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)), 716 XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE)) 717 }, 718 { XE_RTP_NAME("14019877138"), 719 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274), ENGINE_CLASS(RENDER)), 720 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT)) 721 }, 722 723 /* Xe2_LPG */ 724 725 { XE_RTP_NAME("16020518922"), 726 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0), 727 ENGINE_CLASS(RENDER)), 728 XE_RTP_ACTIONS(SET(FF_MODE, 729 DIS_TE_AUTOSTRIP | 730 DIS_MESH_PARTIAL_AUTOSTRIP | 731 DIS_MESH_AUTOSTRIP), 732 SET(VFLSKPD, 733 DIS_PARTIAL_AUTOSTRIP | 734 DIS_AUTOSTRIP)) 735 }, 736 { XE_RTP_NAME("14019386621"), 737 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 738 XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE)) 739 }, 740 { XE_RTP_NAME("14019877138"), 741 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 742 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT)) 743 }, 744 { XE_RTP_NAME("14020013138"), 745 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0), 746 ENGINE_CLASS(RENDER)), 747 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS)) 748 }, 749 { XE_RTP_NAME("14019988906"), 750 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 751 XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD)) 752 }, 753 { XE_RTP_NAME("16020183090"), 754 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0), 755 ENGINE_CLASS(RENDER)), 756 XE_RTP_ACTIONS(SET(INSTPM(RENDER_RING_BASE), ENABLE_SEMAPHORE_POLL_BIT)) 757 }, 758 { XE_RTP_NAME("18033852989"), 759 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2004), ENGINE_CLASS(RENDER)), 760 XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1, DISABLE_BOTTOM_CLIP_RECTANGLE_TEST)) 761 }, 762 { XE_RTP_NAME("14021567978"), 763 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED), 764 ENGINE_CLASS(RENDER)), 765 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_2, TBIMR_FAST_CLIP)) 766 }, 767 { XE_RTP_NAME("14020756599"), 768 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER), OR, 769 MEDIA_VERSION_ANY_GT(2000), ENGINE_CLASS(RENDER)), 770 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS)) 771 }, 772 { XE_RTP_NAME("14021490052"), 773 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 774 XE_RTP_ACTIONS(SET(FF_MODE, 775 DIS_MESH_PARTIAL_AUTOSTRIP | 776 DIS_MESH_AUTOSTRIP), 777 SET(VFLSKPD, 778 DIS_PARTIAL_AUTOSTRIP | 779 DIS_AUTOSTRIP)) 780 }, 781 { XE_RTP_NAME("15016589081"), 782 XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), 783 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX)) 784 }, 785 786 /* Xe2_HPG */ 787 { XE_RTP_NAME("15010599737"), 788 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), 789 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN)) 790 }, 791 { XE_RTP_NAME("14019386621"), 792 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), 793 XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE)) 794 }, 795 { XE_RTP_NAME("14020756599"), 796 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), 797 XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS)) 798 }, 799 { XE_RTP_NAME("14021490052"), 800 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), 801 XE_RTP_ACTIONS(SET(FF_MODE, 802 DIS_MESH_PARTIAL_AUTOSTRIP | 803 DIS_MESH_AUTOSTRIP), 804 SET(VFLSKPD, 805 DIS_PARTIAL_AUTOSTRIP | 806 DIS_AUTOSTRIP)) 807 }, 808 { XE_RTP_NAME("15016589081"), 809 XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), 810 XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX)) 811 }, 812 813 /* Xe3_LPG */ 814 { XE_RTP_NAME("14021490052"), 815 XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0), 816 ENGINE_CLASS(RENDER)), 817 XE_RTP_ACTIONS(SET(FF_MODE, 818 DIS_MESH_PARTIAL_AUTOSTRIP | 819 DIS_MESH_AUTOSTRIP), 820 SET(VFLSKPD, 821 DIS_PARTIAL_AUTOSTRIP | 822 DIS_AUTOSTRIP)) 823 }, 824 }; 825 826 static __maybe_unused const struct xe_rtp_entry oob_was[] = { 827 #include <generated/xe_wa_oob.c> 828 {} 829 }; 830 831 static_assert(ARRAY_SIZE(oob_was) - 1 == _XE_WA_OOB_COUNT); 832 833 __diag_pop(); 834 835 /** 836 * xe_wa_process_oob - process OOB workaround table 837 * @gt: GT instance to process workarounds for 838 * 839 * Process OOB workaround table for this platform, marking in @gt the 840 * workarounds that are active. 841 */ 842 void xe_wa_process_oob(struct xe_gt *gt) 843 { 844 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt); 845 846 xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.oob, 847 ARRAY_SIZE(oob_was)); 848 gt->wa_active.oob_initialized = true; 849 xe_rtp_process(&ctx, oob_was); 850 } 851 852 /** 853 * xe_wa_process_gt - process GT workaround table 854 * @gt: GT instance to process workarounds for 855 * 856 * Process GT workaround table for this platform, saving in @gt all the 857 * workarounds that need to be applied at the GT level. 858 */ 859 void xe_wa_process_gt(struct xe_gt *gt) 860 { 861 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt); 862 863 xe_rtp_process_ctx_enable_active_tracking(&ctx, gt->wa_active.gt, 864 ARRAY_SIZE(gt_was)); 865 xe_rtp_process_to_sr(&ctx, gt_was, ARRAY_SIZE(gt_was), >->reg_sr); 866 } 867 EXPORT_SYMBOL_IF_KUNIT(xe_wa_process_gt); 868 869 /** 870 * xe_wa_process_engine - process engine workaround table 871 * @hwe: engine instance to process workarounds for 872 * 873 * Process engine workaround table for this platform, saving in @hwe all the 874 * workarounds that need to be applied at the engine level that match this 875 * engine. 876 */ 877 void xe_wa_process_engine(struct xe_hw_engine *hwe) 878 { 879 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe); 880 881 xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.engine, 882 ARRAY_SIZE(engine_was)); 883 xe_rtp_process_to_sr(&ctx, engine_was, ARRAY_SIZE(engine_was), &hwe->reg_sr); 884 } 885 886 /** 887 * xe_wa_process_lrc - process context workaround table 888 * @hwe: engine instance to process workarounds for 889 * 890 * Process context workaround table for this platform, saving in @hwe all the 891 * workarounds that need to be applied on context restore. These are workarounds 892 * touching registers that are part of the HW context image. 893 */ 894 void xe_wa_process_lrc(struct xe_hw_engine *hwe) 895 { 896 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe); 897 898 xe_rtp_process_ctx_enable_active_tracking(&ctx, hwe->gt->wa_active.lrc, 899 ARRAY_SIZE(lrc_was)); 900 xe_rtp_process_to_sr(&ctx, lrc_was, ARRAY_SIZE(lrc_was), &hwe->reg_lrc); 901 } 902 903 /** 904 * xe_wa_init - initialize gt with workaround bookkeeping 905 * @gt: GT instance to initialize 906 * 907 * Returns 0 for success, negative error code otherwise. 908 */ 909 int xe_wa_init(struct xe_gt *gt) 910 { 911 struct xe_device *xe = gt_to_xe(gt); 912 size_t n_oob, n_lrc, n_engine, n_gt, total; 913 unsigned long *p; 914 915 n_gt = BITS_TO_LONGS(ARRAY_SIZE(gt_was)); 916 n_engine = BITS_TO_LONGS(ARRAY_SIZE(engine_was)); 917 n_lrc = BITS_TO_LONGS(ARRAY_SIZE(lrc_was)); 918 n_oob = BITS_TO_LONGS(ARRAY_SIZE(oob_was)); 919 total = n_gt + n_engine + n_lrc + n_oob; 920 921 p = drmm_kzalloc(&xe->drm, sizeof(*p) * total, GFP_KERNEL); 922 if (!p) 923 return -ENOMEM; 924 925 gt->wa_active.gt = p; 926 p += n_gt; 927 gt->wa_active.engine = p; 928 p += n_engine; 929 gt->wa_active.lrc = p; 930 p += n_lrc; 931 gt->wa_active.oob = p; 932 933 return 0; 934 } 935 ALLOW_ERROR_INJECTION(xe_wa_init, ERRNO); /* See xe_pci_probe() */ 936 937 void xe_wa_dump(struct xe_gt *gt, struct drm_printer *p) 938 { 939 size_t idx; 940 941 drm_printf(p, "GT Workarounds\n"); 942 for_each_set_bit(idx, gt->wa_active.gt, ARRAY_SIZE(gt_was)) 943 drm_printf_indent(p, 1, "%s\n", gt_was[idx].name); 944 945 drm_printf(p, "\nEngine Workarounds\n"); 946 for_each_set_bit(idx, gt->wa_active.engine, ARRAY_SIZE(engine_was)) 947 drm_printf_indent(p, 1, "%s\n", engine_was[idx].name); 948 949 drm_printf(p, "\nLRC Workarounds\n"); 950 for_each_set_bit(idx, gt->wa_active.lrc, ARRAY_SIZE(lrc_was)) 951 drm_printf_indent(p, 1, "%s\n", lrc_was[idx].name); 952 953 drm_printf(p, "\nOOB Workarounds\n"); 954 for_each_set_bit(idx, gt->wa_active.oob, ARRAY_SIZE(oob_was)) 955 if (oob_was[idx].name) 956 drm_printf_indent(p, 1, "%s\n", oob_was[idx].name); 957 } 958 959 /* 960 * Apply tile (non-GT, non-display) workarounds. Think very carefully before 961 * adding anything to this function; most workarounds should be implemented 962 * elsewhere. The programming here is primarily for sgunit/soc workarounds, 963 * which are relatively rare. Since the registers these workarounds target are 964 * outside the GT, they should only need to be applied once at device 965 * probe/resume; they will not lose their values on any kind of GT or engine 966 * reset. 967 * 968 * TODO: We may want to move this over to xe_rtp in the future once we have 969 * enough workarounds to justify the work. 970 */ 971 void xe_wa_apply_tile_workarounds(struct xe_tile *tile) 972 { 973 struct xe_mmio *mmio = &tile->mmio; 974 975 if (IS_SRIOV_VF(tile->xe)) 976 return; 977 978 if (XE_WA(tile->primary_gt, 22010954014)) 979 xe_mmio_rmw32(mmio, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS); 980 } 981