1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021 Intel Corporation 4 */ 5 6 #include "xe_vm.h" 7 8 #include <linux/dma-fence-array.h> 9 #include <linux/nospec.h> 10 11 #include <drm/drm_exec.h> 12 #include <drm/drm_print.h> 13 #include <drm/ttm/ttm_execbuf_util.h> 14 #include <drm/ttm/ttm_tt.h> 15 #include <drm/xe_drm.h> 16 #include <linux/ascii85.h> 17 #include <linux/delay.h> 18 #include <linux/kthread.h> 19 #include <linux/mm.h> 20 #include <linux/swap.h> 21 22 #include <generated/xe_wa_oob.h> 23 24 #include "regs/xe_gtt_defs.h" 25 #include "xe_assert.h" 26 #include "xe_bo.h" 27 #include "xe_device.h" 28 #include "xe_drm_client.h" 29 #include "xe_exec_queue.h" 30 #include "xe_gt_pagefault.h" 31 #include "xe_gt_tlb_invalidation.h" 32 #include "xe_migrate.h" 33 #include "xe_pat.h" 34 #include "xe_pm.h" 35 #include "xe_preempt_fence.h" 36 #include "xe_pt.h" 37 #include "xe_res_cursor.h" 38 #include "xe_sync.h" 39 #include "xe_trace.h" 40 #include "xe_wa.h" 41 #include "xe_hmm.h" 42 43 static struct drm_gem_object *xe_vm_obj(struct xe_vm *vm) 44 { 45 return vm->gpuvm.r_obj; 46 } 47 48 /** 49 * xe_vma_userptr_check_repin() - Advisory check for repin needed 50 * @uvma: The userptr vma 51 * 52 * Check if the userptr vma has been invalidated since last successful 53 * repin. The check is advisory only and can the function can be called 54 * without the vm->userptr.notifier_lock held. There is no guarantee that the 55 * vma userptr will remain valid after a lockless check, so typically 56 * the call needs to be followed by a proper check under the notifier_lock. 57 * 58 * Return: 0 if userptr vma is valid, -EAGAIN otherwise; repin recommended. 59 */ 60 int xe_vma_userptr_check_repin(struct xe_userptr_vma *uvma) 61 { 62 return mmu_interval_check_retry(&uvma->userptr.notifier, 63 uvma->userptr.notifier_seq) ? 64 -EAGAIN : 0; 65 } 66 67 int xe_vma_userptr_pin_pages(struct xe_userptr_vma *uvma) 68 { 69 struct xe_vma *vma = &uvma->vma; 70 struct xe_vm *vm = xe_vma_vm(vma); 71 struct xe_device *xe = vm->xe; 72 73 lockdep_assert_held(&vm->lock); 74 xe_assert(xe, xe_vma_is_userptr(vma)); 75 76 return xe_hmm_userptr_populate_range(uvma, false); 77 } 78 79 static bool preempt_fences_waiting(struct xe_vm *vm) 80 { 81 struct xe_exec_queue *q; 82 83 lockdep_assert_held(&vm->lock); 84 xe_vm_assert_held(vm); 85 86 list_for_each_entry(q, &vm->preempt.exec_queues, compute.link) { 87 if (!q->compute.pfence || 88 (q->compute.pfence && test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, 89 &q->compute.pfence->flags))) { 90 return true; 91 } 92 } 93 94 return false; 95 } 96 97 static void free_preempt_fences(struct list_head *list) 98 { 99 struct list_head *link, *next; 100 101 list_for_each_safe(link, next, list) 102 xe_preempt_fence_free(to_preempt_fence_from_link(link)); 103 } 104 105 static int alloc_preempt_fences(struct xe_vm *vm, struct list_head *list, 106 unsigned int *count) 107 { 108 lockdep_assert_held(&vm->lock); 109 xe_vm_assert_held(vm); 110 111 if (*count >= vm->preempt.num_exec_queues) 112 return 0; 113 114 for (; *count < vm->preempt.num_exec_queues; ++(*count)) { 115 struct xe_preempt_fence *pfence = xe_preempt_fence_alloc(); 116 117 if (IS_ERR(pfence)) 118 return PTR_ERR(pfence); 119 120 list_move_tail(xe_preempt_fence_link(pfence), list); 121 } 122 123 return 0; 124 } 125 126 static int wait_for_existing_preempt_fences(struct xe_vm *vm) 127 { 128 struct xe_exec_queue *q; 129 130 xe_vm_assert_held(vm); 131 132 list_for_each_entry(q, &vm->preempt.exec_queues, compute.link) { 133 if (q->compute.pfence) { 134 long timeout = dma_fence_wait(q->compute.pfence, false); 135 136 if (timeout < 0) 137 return -ETIME; 138 dma_fence_put(q->compute.pfence); 139 q->compute.pfence = NULL; 140 } 141 } 142 143 return 0; 144 } 145 146 static bool xe_vm_is_idle(struct xe_vm *vm) 147 { 148 struct xe_exec_queue *q; 149 150 xe_vm_assert_held(vm); 151 list_for_each_entry(q, &vm->preempt.exec_queues, compute.link) { 152 if (!xe_exec_queue_is_idle(q)) 153 return false; 154 } 155 156 return true; 157 } 158 159 static void arm_preempt_fences(struct xe_vm *vm, struct list_head *list) 160 { 161 struct list_head *link; 162 struct xe_exec_queue *q; 163 164 list_for_each_entry(q, &vm->preempt.exec_queues, compute.link) { 165 struct dma_fence *fence; 166 167 link = list->next; 168 xe_assert(vm->xe, link != list); 169 170 fence = xe_preempt_fence_arm(to_preempt_fence_from_link(link), 171 q, q->compute.context, 172 ++q->compute.seqno); 173 dma_fence_put(q->compute.pfence); 174 q->compute.pfence = fence; 175 } 176 } 177 178 static int add_preempt_fences(struct xe_vm *vm, struct xe_bo *bo) 179 { 180 struct xe_exec_queue *q; 181 int err; 182 183 if (!vm->preempt.num_exec_queues) 184 return 0; 185 186 err = xe_bo_lock(bo, true); 187 if (err) 188 return err; 189 190 err = dma_resv_reserve_fences(bo->ttm.base.resv, vm->preempt.num_exec_queues); 191 if (err) 192 goto out_unlock; 193 194 list_for_each_entry(q, &vm->preempt.exec_queues, compute.link) 195 if (q->compute.pfence) { 196 dma_resv_add_fence(bo->ttm.base.resv, 197 q->compute.pfence, 198 DMA_RESV_USAGE_BOOKKEEP); 199 } 200 201 out_unlock: 202 xe_bo_unlock(bo); 203 return err; 204 } 205 206 static void resume_and_reinstall_preempt_fences(struct xe_vm *vm, 207 struct drm_exec *exec) 208 { 209 struct xe_exec_queue *q; 210 211 lockdep_assert_held(&vm->lock); 212 xe_vm_assert_held(vm); 213 214 list_for_each_entry(q, &vm->preempt.exec_queues, compute.link) { 215 q->ops->resume(q); 216 217 drm_gpuvm_resv_add_fence(&vm->gpuvm, exec, q->compute.pfence, 218 DMA_RESV_USAGE_BOOKKEEP, DMA_RESV_USAGE_BOOKKEEP); 219 } 220 } 221 222 int xe_vm_add_compute_exec_queue(struct xe_vm *vm, struct xe_exec_queue *q) 223 { 224 struct drm_gpuvm_exec vm_exec = { 225 .vm = &vm->gpuvm, 226 .flags = DRM_EXEC_INTERRUPTIBLE_WAIT, 227 .num_fences = 1, 228 }; 229 struct drm_exec *exec = &vm_exec.exec; 230 struct dma_fence *pfence; 231 int err; 232 bool wait; 233 234 xe_assert(vm->xe, xe_vm_in_preempt_fence_mode(vm)); 235 236 down_write(&vm->lock); 237 err = drm_gpuvm_exec_lock(&vm_exec); 238 if (err) 239 goto out_up_write; 240 241 pfence = xe_preempt_fence_create(q, q->compute.context, 242 ++q->compute.seqno); 243 if (!pfence) { 244 err = -ENOMEM; 245 goto out_fini; 246 } 247 248 list_add(&q->compute.link, &vm->preempt.exec_queues); 249 ++vm->preempt.num_exec_queues; 250 q->compute.pfence = pfence; 251 252 down_read(&vm->userptr.notifier_lock); 253 254 drm_gpuvm_resv_add_fence(&vm->gpuvm, exec, pfence, 255 DMA_RESV_USAGE_BOOKKEEP, DMA_RESV_USAGE_BOOKKEEP); 256 257 /* 258 * Check to see if a preemption on VM is in flight or userptr 259 * invalidation, if so trigger this preempt fence to sync state with 260 * other preempt fences on the VM. 261 */ 262 wait = __xe_vm_userptr_needs_repin(vm) || preempt_fences_waiting(vm); 263 if (wait) 264 dma_fence_enable_sw_signaling(pfence); 265 266 up_read(&vm->userptr.notifier_lock); 267 268 out_fini: 269 drm_exec_fini(exec); 270 out_up_write: 271 up_write(&vm->lock); 272 273 return err; 274 } 275 276 /** 277 * xe_vm_remove_compute_exec_queue() - Remove compute exec queue from VM 278 * @vm: The VM. 279 * @q: The exec_queue 280 */ 281 void xe_vm_remove_compute_exec_queue(struct xe_vm *vm, struct xe_exec_queue *q) 282 { 283 if (!xe_vm_in_preempt_fence_mode(vm)) 284 return; 285 286 down_write(&vm->lock); 287 list_del(&q->compute.link); 288 --vm->preempt.num_exec_queues; 289 if (q->compute.pfence) { 290 dma_fence_enable_sw_signaling(q->compute.pfence); 291 dma_fence_put(q->compute.pfence); 292 q->compute.pfence = NULL; 293 } 294 up_write(&vm->lock); 295 } 296 297 /** 298 * __xe_vm_userptr_needs_repin() - Check whether the VM does have userptrs 299 * that need repinning. 300 * @vm: The VM. 301 * 302 * This function checks for whether the VM has userptrs that need repinning, 303 * and provides a release-type barrier on the userptr.notifier_lock after 304 * checking. 305 * 306 * Return: 0 if there are no userptrs needing repinning, -EAGAIN if there are. 307 */ 308 int __xe_vm_userptr_needs_repin(struct xe_vm *vm) 309 { 310 lockdep_assert_held_read(&vm->userptr.notifier_lock); 311 312 return (list_empty(&vm->userptr.repin_list) && 313 list_empty(&vm->userptr.invalidated)) ? 0 : -EAGAIN; 314 } 315 316 #define XE_VM_REBIND_RETRY_TIMEOUT_MS 1000 317 318 static void xe_vm_kill(struct xe_vm *vm) 319 { 320 struct xe_exec_queue *q; 321 322 lockdep_assert_held(&vm->lock); 323 324 xe_vm_lock(vm, false); 325 vm->flags |= XE_VM_FLAG_BANNED; 326 trace_xe_vm_kill(vm); 327 328 list_for_each_entry(q, &vm->preempt.exec_queues, compute.link) 329 q->ops->kill(q); 330 xe_vm_unlock(vm); 331 332 /* TODO: Inform user the VM is banned */ 333 } 334 335 /** 336 * xe_vm_validate_should_retry() - Whether to retry after a validate error. 337 * @exec: The drm_exec object used for locking before validation. 338 * @err: The error returned from ttm_bo_validate(). 339 * @end: A ktime_t cookie that should be set to 0 before first use and 340 * that should be reused on subsequent calls. 341 * 342 * With multiple active VMs, under memory pressure, it is possible that 343 * ttm_bo_validate() run into -EDEADLK and in such case returns -ENOMEM. 344 * Until ttm properly handles locking in such scenarios, best thing the 345 * driver can do is retry with a timeout. Check if that is necessary, and 346 * if so unlock the drm_exec's objects while keeping the ticket to prepare 347 * for a rerun. 348 * 349 * Return: true if a retry after drm_exec_init() is recommended; 350 * false otherwise. 351 */ 352 bool xe_vm_validate_should_retry(struct drm_exec *exec, int err, ktime_t *end) 353 { 354 ktime_t cur; 355 356 if (err != -ENOMEM) 357 return false; 358 359 cur = ktime_get(); 360 *end = *end ? : ktime_add_ms(cur, XE_VM_REBIND_RETRY_TIMEOUT_MS); 361 if (!ktime_before(cur, *end)) 362 return false; 363 364 msleep(20); 365 return true; 366 } 367 368 static int xe_gpuvm_validate(struct drm_gpuvm_bo *vm_bo, struct drm_exec *exec) 369 { 370 struct xe_vm *vm = gpuvm_to_vm(vm_bo->vm); 371 struct drm_gpuva *gpuva; 372 int ret; 373 374 lockdep_assert_held(&vm->lock); 375 drm_gpuvm_bo_for_each_va(gpuva, vm_bo) 376 list_move_tail(&gpuva_to_vma(gpuva)->combined_links.rebind, 377 &vm->rebind_list); 378 379 ret = xe_bo_validate(gem_to_xe_bo(vm_bo->obj), vm, false); 380 if (ret) 381 return ret; 382 383 vm_bo->evicted = false; 384 return 0; 385 } 386 387 /** 388 * xe_vm_validate_rebind() - Validate buffer objects and rebind vmas 389 * @vm: The vm for which we are rebinding. 390 * @exec: The struct drm_exec with the locked GEM objects. 391 * @num_fences: The number of fences to reserve for the operation, not 392 * including rebinds and validations. 393 * 394 * Validates all evicted gem objects and rebinds their vmas. Note that 395 * rebindings may cause evictions and hence the validation-rebind 396 * sequence is rerun until there are no more objects to validate. 397 * 398 * Return: 0 on success, negative error code on error. In particular, 399 * may return -EINTR or -ERESTARTSYS if interrupted, and -EDEADLK if 400 * the drm_exec transaction needs to be restarted. 401 */ 402 int xe_vm_validate_rebind(struct xe_vm *vm, struct drm_exec *exec, 403 unsigned int num_fences) 404 { 405 struct drm_gem_object *obj; 406 unsigned long index; 407 int ret; 408 409 do { 410 ret = drm_gpuvm_validate(&vm->gpuvm, exec); 411 if (ret) 412 return ret; 413 414 ret = xe_vm_rebind(vm, false); 415 if (ret) 416 return ret; 417 } while (!list_empty(&vm->gpuvm.evict.list)); 418 419 drm_exec_for_each_locked_object(exec, index, obj) { 420 ret = dma_resv_reserve_fences(obj->resv, num_fences); 421 if (ret) 422 return ret; 423 } 424 425 return 0; 426 } 427 428 static int xe_preempt_work_begin(struct drm_exec *exec, struct xe_vm *vm, 429 bool *done) 430 { 431 int err; 432 433 err = drm_gpuvm_prepare_vm(&vm->gpuvm, exec, 0); 434 if (err) 435 return err; 436 437 if (xe_vm_is_idle(vm)) { 438 vm->preempt.rebind_deactivated = true; 439 *done = true; 440 return 0; 441 } 442 443 if (!preempt_fences_waiting(vm)) { 444 *done = true; 445 return 0; 446 } 447 448 err = drm_gpuvm_prepare_objects(&vm->gpuvm, exec, 0); 449 if (err) 450 return err; 451 452 err = wait_for_existing_preempt_fences(vm); 453 if (err) 454 return err; 455 456 /* 457 * Add validation and rebinding to the locking loop since both can 458 * cause evictions which may require blocing dma_resv locks. 459 * The fence reservation here is intended for the new preempt fences 460 * we attach at the end of the rebind work. 461 */ 462 return xe_vm_validate_rebind(vm, exec, vm->preempt.num_exec_queues); 463 } 464 465 static void preempt_rebind_work_func(struct work_struct *w) 466 { 467 struct xe_vm *vm = container_of(w, struct xe_vm, preempt.rebind_work); 468 struct drm_exec exec; 469 unsigned int fence_count = 0; 470 LIST_HEAD(preempt_fences); 471 ktime_t end = 0; 472 int err = 0; 473 long wait; 474 int __maybe_unused tries = 0; 475 476 xe_assert(vm->xe, xe_vm_in_preempt_fence_mode(vm)); 477 trace_xe_vm_rebind_worker_enter(vm); 478 479 down_write(&vm->lock); 480 481 if (xe_vm_is_closed_or_banned(vm)) { 482 up_write(&vm->lock); 483 trace_xe_vm_rebind_worker_exit(vm); 484 return; 485 } 486 487 retry: 488 if (xe_vm_userptr_check_repin(vm)) { 489 err = xe_vm_userptr_pin(vm); 490 if (err) 491 goto out_unlock_outer; 492 } 493 494 drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0); 495 496 drm_exec_until_all_locked(&exec) { 497 bool done = false; 498 499 err = xe_preempt_work_begin(&exec, vm, &done); 500 drm_exec_retry_on_contention(&exec); 501 if (err || done) { 502 drm_exec_fini(&exec); 503 if (err && xe_vm_validate_should_retry(&exec, err, &end)) 504 err = -EAGAIN; 505 506 goto out_unlock_outer; 507 } 508 } 509 510 err = alloc_preempt_fences(vm, &preempt_fences, &fence_count); 511 if (err) 512 goto out_unlock; 513 514 err = xe_vm_rebind(vm, true); 515 if (err) 516 goto out_unlock; 517 518 /* Wait on rebinds and munmap style VM unbinds */ 519 wait = dma_resv_wait_timeout(xe_vm_resv(vm), 520 DMA_RESV_USAGE_KERNEL, 521 false, MAX_SCHEDULE_TIMEOUT); 522 if (wait <= 0) { 523 err = -ETIME; 524 goto out_unlock; 525 } 526 527 #define retry_required(__tries, __vm) \ 528 (IS_ENABLED(CONFIG_DRM_XE_USERPTR_INVAL_INJECT) ? \ 529 (!(__tries)++ || __xe_vm_userptr_needs_repin(__vm)) : \ 530 __xe_vm_userptr_needs_repin(__vm)) 531 532 down_read(&vm->userptr.notifier_lock); 533 if (retry_required(tries, vm)) { 534 up_read(&vm->userptr.notifier_lock); 535 err = -EAGAIN; 536 goto out_unlock; 537 } 538 539 #undef retry_required 540 541 spin_lock(&vm->xe->ttm.lru_lock); 542 ttm_lru_bulk_move_tail(&vm->lru_bulk_move); 543 spin_unlock(&vm->xe->ttm.lru_lock); 544 545 /* Point of no return. */ 546 arm_preempt_fences(vm, &preempt_fences); 547 resume_and_reinstall_preempt_fences(vm, &exec); 548 up_read(&vm->userptr.notifier_lock); 549 550 out_unlock: 551 drm_exec_fini(&exec); 552 out_unlock_outer: 553 if (err == -EAGAIN) { 554 trace_xe_vm_rebind_worker_retry(vm); 555 goto retry; 556 } 557 558 if (err) { 559 drm_warn(&vm->xe->drm, "VM worker error: %d\n", err); 560 xe_vm_kill(vm); 561 } 562 up_write(&vm->lock); 563 564 free_preempt_fences(&preempt_fences); 565 566 trace_xe_vm_rebind_worker_exit(vm); 567 } 568 569 static bool vma_userptr_invalidate(struct mmu_interval_notifier *mni, 570 const struct mmu_notifier_range *range, 571 unsigned long cur_seq) 572 { 573 struct xe_userptr *userptr = container_of(mni, typeof(*userptr), notifier); 574 struct xe_userptr_vma *uvma = container_of(userptr, typeof(*uvma), userptr); 575 struct xe_vma *vma = &uvma->vma; 576 struct xe_vm *vm = xe_vma_vm(vma); 577 struct dma_resv_iter cursor; 578 struct dma_fence *fence; 579 long err; 580 581 xe_assert(vm->xe, xe_vma_is_userptr(vma)); 582 trace_xe_vma_userptr_invalidate(vma); 583 584 if (!mmu_notifier_range_blockable(range)) 585 return false; 586 587 vm_dbg(&xe_vma_vm(vma)->xe->drm, 588 "NOTIFIER: addr=0x%016llx, range=0x%016llx", 589 xe_vma_start(vma), xe_vma_size(vma)); 590 591 down_write(&vm->userptr.notifier_lock); 592 mmu_interval_set_seq(mni, cur_seq); 593 594 /* No need to stop gpu access if the userptr is not yet bound. */ 595 if (!userptr->initial_bind) { 596 up_write(&vm->userptr.notifier_lock); 597 return true; 598 } 599 600 /* 601 * Tell exec and rebind worker they need to repin and rebind this 602 * userptr. 603 */ 604 if (!xe_vm_in_fault_mode(vm) && 605 !(vma->gpuva.flags & XE_VMA_DESTROYED) && vma->tile_present) { 606 spin_lock(&vm->userptr.invalidated_lock); 607 list_move_tail(&userptr->invalidate_link, 608 &vm->userptr.invalidated); 609 spin_unlock(&vm->userptr.invalidated_lock); 610 } 611 612 up_write(&vm->userptr.notifier_lock); 613 614 /* 615 * Preempt fences turn into schedule disables, pipeline these. 616 * Note that even in fault mode, we need to wait for binds and 617 * unbinds to complete, and those are attached as BOOKMARK fences 618 * to the vm. 619 */ 620 dma_resv_iter_begin(&cursor, xe_vm_resv(vm), 621 DMA_RESV_USAGE_BOOKKEEP); 622 dma_resv_for_each_fence_unlocked(&cursor, fence) 623 dma_fence_enable_sw_signaling(fence); 624 dma_resv_iter_end(&cursor); 625 626 err = dma_resv_wait_timeout(xe_vm_resv(vm), 627 DMA_RESV_USAGE_BOOKKEEP, 628 false, MAX_SCHEDULE_TIMEOUT); 629 XE_WARN_ON(err <= 0); 630 631 if (xe_vm_in_fault_mode(vm)) { 632 err = xe_vm_invalidate_vma(vma); 633 XE_WARN_ON(err); 634 } 635 636 trace_xe_vma_userptr_invalidate_complete(vma); 637 638 return true; 639 } 640 641 static const struct mmu_interval_notifier_ops vma_userptr_notifier_ops = { 642 .invalidate = vma_userptr_invalidate, 643 }; 644 645 int xe_vm_userptr_pin(struct xe_vm *vm) 646 { 647 struct xe_userptr_vma *uvma, *next; 648 int err = 0; 649 LIST_HEAD(tmp_evict); 650 651 xe_assert(vm->xe, !xe_vm_in_fault_mode(vm)); 652 lockdep_assert_held_write(&vm->lock); 653 654 /* Collect invalidated userptrs */ 655 spin_lock(&vm->userptr.invalidated_lock); 656 list_for_each_entry_safe(uvma, next, &vm->userptr.invalidated, 657 userptr.invalidate_link) { 658 list_del_init(&uvma->userptr.invalidate_link); 659 list_move_tail(&uvma->userptr.repin_link, 660 &vm->userptr.repin_list); 661 } 662 spin_unlock(&vm->userptr.invalidated_lock); 663 664 /* Pin and move to temporary list */ 665 list_for_each_entry_safe(uvma, next, &vm->userptr.repin_list, 666 userptr.repin_link) { 667 err = xe_vma_userptr_pin_pages(uvma); 668 if (err == -EFAULT) { 669 list_del_init(&uvma->userptr.repin_link); 670 671 /* Wait for pending binds */ 672 xe_vm_lock(vm, false); 673 dma_resv_wait_timeout(xe_vm_resv(vm), 674 DMA_RESV_USAGE_BOOKKEEP, 675 false, MAX_SCHEDULE_TIMEOUT); 676 677 err = xe_vm_invalidate_vma(&uvma->vma); 678 xe_vm_unlock(vm); 679 if (err) 680 return err; 681 } else { 682 if (err < 0) 683 return err; 684 685 list_del_init(&uvma->userptr.repin_link); 686 list_move_tail(&uvma->vma.combined_links.rebind, 687 &vm->rebind_list); 688 } 689 } 690 691 return 0; 692 } 693 694 /** 695 * xe_vm_userptr_check_repin() - Check whether the VM might have userptrs 696 * that need repinning. 697 * @vm: The VM. 698 * 699 * This function does an advisory check for whether the VM has userptrs that 700 * need repinning. 701 * 702 * Return: 0 if there are no indications of userptrs needing repinning, 703 * -EAGAIN if there are. 704 */ 705 int xe_vm_userptr_check_repin(struct xe_vm *vm) 706 { 707 return (list_empty_careful(&vm->userptr.repin_list) && 708 list_empty_careful(&vm->userptr.invalidated)) ? 0 : -EAGAIN; 709 } 710 711 static struct dma_fence * 712 xe_vm_bind_vma(struct xe_vma *vma, struct xe_exec_queue *q, 713 struct xe_sync_entry *syncs, u32 num_syncs, 714 bool first_op, bool last_op); 715 716 int xe_vm_rebind(struct xe_vm *vm, bool rebind_worker) 717 { 718 struct dma_fence *fence; 719 struct xe_vma *vma, *next; 720 721 lockdep_assert_held(&vm->lock); 722 if (xe_vm_in_lr_mode(vm) && !rebind_worker) 723 return 0; 724 725 xe_vm_assert_held(vm); 726 list_for_each_entry_safe(vma, next, &vm->rebind_list, 727 combined_links.rebind) { 728 xe_assert(vm->xe, vma->tile_present); 729 730 list_del_init(&vma->combined_links.rebind); 731 if (rebind_worker) 732 trace_xe_vma_rebind_worker(vma); 733 else 734 trace_xe_vma_rebind_exec(vma); 735 fence = xe_vm_bind_vma(vma, NULL, NULL, 0, false, false); 736 if (IS_ERR(fence)) 737 return PTR_ERR(fence); 738 dma_fence_put(fence); 739 } 740 741 return 0; 742 } 743 744 static void xe_vma_free(struct xe_vma *vma) 745 { 746 if (xe_vma_is_userptr(vma)) 747 kfree(to_userptr_vma(vma)); 748 else 749 kfree(vma); 750 } 751 752 #define VMA_CREATE_FLAG_READ_ONLY BIT(0) 753 #define VMA_CREATE_FLAG_IS_NULL BIT(1) 754 #define VMA_CREATE_FLAG_DUMPABLE BIT(2) 755 756 static struct xe_vma *xe_vma_create(struct xe_vm *vm, 757 struct xe_bo *bo, 758 u64 bo_offset_or_userptr, 759 u64 start, u64 end, 760 u16 pat_index, unsigned int flags) 761 { 762 struct xe_vma *vma; 763 struct xe_tile *tile; 764 u8 id; 765 bool read_only = (flags & VMA_CREATE_FLAG_READ_ONLY); 766 bool is_null = (flags & VMA_CREATE_FLAG_IS_NULL); 767 bool dumpable = (flags & VMA_CREATE_FLAG_DUMPABLE); 768 769 xe_assert(vm->xe, start < end); 770 xe_assert(vm->xe, end < vm->size); 771 772 /* 773 * Allocate and ensure that the xe_vma_is_userptr() return 774 * matches what was allocated. 775 */ 776 if (!bo && !is_null) { 777 struct xe_userptr_vma *uvma = kzalloc(sizeof(*uvma), GFP_KERNEL); 778 779 if (!uvma) 780 return ERR_PTR(-ENOMEM); 781 782 vma = &uvma->vma; 783 } else { 784 vma = kzalloc(sizeof(*vma), GFP_KERNEL); 785 if (!vma) 786 return ERR_PTR(-ENOMEM); 787 788 if (is_null) 789 vma->gpuva.flags |= DRM_GPUVA_SPARSE; 790 if (bo) 791 vma->gpuva.gem.obj = &bo->ttm.base; 792 } 793 794 INIT_LIST_HEAD(&vma->combined_links.rebind); 795 796 INIT_LIST_HEAD(&vma->gpuva.gem.entry); 797 vma->gpuva.vm = &vm->gpuvm; 798 vma->gpuva.va.addr = start; 799 vma->gpuva.va.range = end - start + 1; 800 if (read_only) 801 vma->gpuva.flags |= XE_VMA_READ_ONLY; 802 if (dumpable) 803 vma->gpuva.flags |= XE_VMA_DUMPABLE; 804 805 for_each_tile(tile, vm->xe, id) 806 vma->tile_mask |= 0x1 << id; 807 808 if (GRAPHICS_VER(vm->xe) >= 20 || vm->xe->info.platform == XE_PVC) 809 vma->gpuva.flags |= XE_VMA_ATOMIC_PTE_BIT; 810 811 vma->pat_index = pat_index; 812 813 if (bo) { 814 struct drm_gpuvm_bo *vm_bo; 815 816 xe_bo_assert_held(bo); 817 818 vm_bo = drm_gpuvm_bo_obtain(vma->gpuva.vm, &bo->ttm.base); 819 if (IS_ERR(vm_bo)) { 820 xe_vma_free(vma); 821 return ERR_CAST(vm_bo); 822 } 823 824 drm_gpuvm_bo_extobj_add(vm_bo); 825 drm_gem_object_get(&bo->ttm.base); 826 vma->gpuva.gem.offset = bo_offset_or_userptr; 827 drm_gpuva_link(&vma->gpuva, vm_bo); 828 drm_gpuvm_bo_put(vm_bo); 829 } else /* userptr or null */ { 830 if (!is_null) { 831 struct xe_userptr *userptr = &to_userptr_vma(vma)->userptr; 832 u64 size = end - start + 1; 833 int err; 834 835 INIT_LIST_HEAD(&userptr->invalidate_link); 836 INIT_LIST_HEAD(&userptr->repin_link); 837 vma->gpuva.gem.offset = bo_offset_or_userptr; 838 839 err = mmu_interval_notifier_insert(&userptr->notifier, 840 current->mm, 841 xe_vma_userptr(vma), size, 842 &vma_userptr_notifier_ops); 843 if (err) { 844 xe_vma_free(vma); 845 return ERR_PTR(err); 846 } 847 848 userptr->notifier_seq = LONG_MAX; 849 } 850 851 xe_vm_get(vm); 852 } 853 854 return vma; 855 } 856 857 static void xe_vma_destroy_late(struct xe_vma *vma) 858 { 859 struct xe_vm *vm = xe_vma_vm(vma); 860 861 if (vma->ufence) { 862 xe_sync_ufence_put(vma->ufence); 863 vma->ufence = NULL; 864 } 865 866 if (vma->ufence) { 867 xe_sync_ufence_put(vma->ufence); 868 vma->ufence = NULL; 869 } 870 871 if (xe_vma_is_userptr(vma)) { 872 struct xe_userptr_vma *uvma = to_userptr_vma(vma); 873 struct xe_userptr *userptr = &uvma->userptr; 874 875 if (userptr->sg) 876 xe_hmm_userptr_free_sg(uvma); 877 878 /* 879 * Since userptr pages are not pinned, we can't remove 880 * the notifer until we're sure the GPU is not accessing 881 * them anymore 882 */ 883 mmu_interval_notifier_remove(&userptr->notifier); 884 xe_vm_put(vm); 885 } else if (xe_vma_is_null(vma)) { 886 xe_vm_put(vm); 887 } else { 888 xe_bo_put(xe_vma_bo(vma)); 889 } 890 891 xe_vma_free(vma); 892 } 893 894 static void vma_destroy_work_func(struct work_struct *w) 895 { 896 struct xe_vma *vma = 897 container_of(w, struct xe_vma, destroy_work); 898 899 xe_vma_destroy_late(vma); 900 } 901 902 static void vma_destroy_cb(struct dma_fence *fence, 903 struct dma_fence_cb *cb) 904 { 905 struct xe_vma *vma = container_of(cb, struct xe_vma, destroy_cb); 906 907 INIT_WORK(&vma->destroy_work, vma_destroy_work_func); 908 queue_work(system_unbound_wq, &vma->destroy_work); 909 } 910 911 static void xe_vma_destroy(struct xe_vma *vma, struct dma_fence *fence) 912 { 913 struct xe_vm *vm = xe_vma_vm(vma); 914 915 lockdep_assert_held_write(&vm->lock); 916 xe_assert(vm->xe, list_empty(&vma->combined_links.destroy)); 917 918 if (xe_vma_is_userptr(vma)) { 919 xe_assert(vm->xe, vma->gpuva.flags & XE_VMA_DESTROYED); 920 921 spin_lock(&vm->userptr.invalidated_lock); 922 list_del(&to_userptr_vma(vma)->userptr.invalidate_link); 923 spin_unlock(&vm->userptr.invalidated_lock); 924 } else if (!xe_vma_is_null(vma)) { 925 xe_bo_assert_held(xe_vma_bo(vma)); 926 927 drm_gpuva_unlink(&vma->gpuva); 928 } 929 930 xe_vm_assert_held(vm); 931 if (fence) { 932 int ret = dma_fence_add_callback(fence, &vma->destroy_cb, 933 vma_destroy_cb); 934 935 if (ret) { 936 XE_WARN_ON(ret != -ENOENT); 937 xe_vma_destroy_late(vma); 938 } 939 } else { 940 xe_vma_destroy_late(vma); 941 } 942 } 943 944 /** 945 * xe_vm_lock_vma() - drm_exec utility to lock a vma 946 * @exec: The drm_exec object we're currently locking for. 947 * @vma: The vma for witch we want to lock the vm resv and any attached 948 * object's resv. 949 * 950 * Return: 0 on success, negative error code on error. In particular 951 * may return -EDEADLK on WW transaction contention and -EINTR if 952 * an interruptible wait is terminated by a signal. 953 */ 954 int xe_vm_lock_vma(struct drm_exec *exec, struct xe_vma *vma) 955 { 956 struct xe_vm *vm = xe_vma_vm(vma); 957 struct xe_bo *bo = xe_vma_bo(vma); 958 int err; 959 960 XE_WARN_ON(!vm); 961 962 err = drm_exec_lock_obj(exec, xe_vm_obj(vm)); 963 if (!err && bo && !bo->vm) 964 err = drm_exec_lock_obj(exec, &bo->ttm.base); 965 966 return err; 967 } 968 969 static void xe_vma_destroy_unlocked(struct xe_vma *vma) 970 { 971 struct drm_exec exec; 972 int err; 973 974 drm_exec_init(&exec, 0, 0); 975 drm_exec_until_all_locked(&exec) { 976 err = xe_vm_lock_vma(&exec, vma); 977 drm_exec_retry_on_contention(&exec); 978 if (XE_WARN_ON(err)) 979 break; 980 } 981 982 xe_vma_destroy(vma, NULL); 983 984 drm_exec_fini(&exec); 985 } 986 987 struct xe_vma * 988 xe_vm_find_overlapping_vma(struct xe_vm *vm, u64 start, u64 range) 989 { 990 struct drm_gpuva *gpuva; 991 992 lockdep_assert_held(&vm->lock); 993 994 if (xe_vm_is_closed_or_banned(vm)) 995 return NULL; 996 997 xe_assert(vm->xe, start + range <= vm->size); 998 999 gpuva = drm_gpuva_find_first(&vm->gpuvm, start, range); 1000 1001 return gpuva ? gpuva_to_vma(gpuva) : NULL; 1002 } 1003 1004 static int xe_vm_insert_vma(struct xe_vm *vm, struct xe_vma *vma) 1005 { 1006 int err; 1007 1008 xe_assert(vm->xe, xe_vma_vm(vma) == vm); 1009 lockdep_assert_held(&vm->lock); 1010 1011 mutex_lock(&vm->snap_mutex); 1012 err = drm_gpuva_insert(&vm->gpuvm, &vma->gpuva); 1013 mutex_unlock(&vm->snap_mutex); 1014 XE_WARN_ON(err); /* Shouldn't be possible */ 1015 1016 return err; 1017 } 1018 1019 static void xe_vm_remove_vma(struct xe_vm *vm, struct xe_vma *vma) 1020 { 1021 xe_assert(vm->xe, xe_vma_vm(vma) == vm); 1022 lockdep_assert_held(&vm->lock); 1023 1024 mutex_lock(&vm->snap_mutex); 1025 drm_gpuva_remove(&vma->gpuva); 1026 mutex_unlock(&vm->snap_mutex); 1027 if (vm->usm.last_fault_vma == vma) 1028 vm->usm.last_fault_vma = NULL; 1029 } 1030 1031 static struct drm_gpuva_op *xe_vm_op_alloc(void) 1032 { 1033 struct xe_vma_op *op; 1034 1035 op = kzalloc(sizeof(*op), GFP_KERNEL); 1036 1037 if (unlikely(!op)) 1038 return NULL; 1039 1040 return &op->base; 1041 } 1042 1043 static void xe_vm_free(struct drm_gpuvm *gpuvm); 1044 1045 static const struct drm_gpuvm_ops gpuvm_ops = { 1046 .op_alloc = xe_vm_op_alloc, 1047 .vm_bo_validate = xe_gpuvm_validate, 1048 .vm_free = xe_vm_free, 1049 }; 1050 1051 static u64 pde_encode_pat_index(struct xe_device *xe, u16 pat_index) 1052 { 1053 u64 pte = 0; 1054 1055 if (pat_index & BIT(0)) 1056 pte |= XE_PPGTT_PTE_PAT0; 1057 1058 if (pat_index & BIT(1)) 1059 pte |= XE_PPGTT_PTE_PAT1; 1060 1061 return pte; 1062 } 1063 1064 static u64 pte_encode_pat_index(struct xe_device *xe, u16 pat_index, 1065 u32 pt_level) 1066 { 1067 u64 pte = 0; 1068 1069 if (pat_index & BIT(0)) 1070 pte |= XE_PPGTT_PTE_PAT0; 1071 1072 if (pat_index & BIT(1)) 1073 pte |= XE_PPGTT_PTE_PAT1; 1074 1075 if (pat_index & BIT(2)) { 1076 if (pt_level) 1077 pte |= XE_PPGTT_PDE_PDPE_PAT2; 1078 else 1079 pte |= XE_PPGTT_PTE_PAT2; 1080 } 1081 1082 if (pat_index & BIT(3)) 1083 pte |= XELPG_PPGTT_PTE_PAT3; 1084 1085 if (pat_index & (BIT(4))) 1086 pte |= XE2_PPGTT_PTE_PAT4; 1087 1088 return pte; 1089 } 1090 1091 static u64 pte_encode_ps(u32 pt_level) 1092 { 1093 XE_WARN_ON(pt_level > MAX_HUGEPTE_LEVEL); 1094 1095 if (pt_level == 1) 1096 return XE_PDE_PS_2M; 1097 else if (pt_level == 2) 1098 return XE_PDPE_PS_1G; 1099 1100 return 0; 1101 } 1102 1103 static u64 xelp_pde_encode_bo(struct xe_bo *bo, u64 bo_offset, 1104 const u16 pat_index) 1105 { 1106 struct xe_device *xe = xe_bo_device(bo); 1107 u64 pde; 1108 1109 pde = xe_bo_addr(bo, bo_offset, XE_PAGE_SIZE); 1110 pde |= XE_PAGE_PRESENT | XE_PAGE_RW; 1111 pde |= pde_encode_pat_index(xe, pat_index); 1112 1113 return pde; 1114 } 1115 1116 static u64 xelp_pte_encode_bo(struct xe_bo *bo, u64 bo_offset, 1117 u16 pat_index, u32 pt_level) 1118 { 1119 struct xe_device *xe = xe_bo_device(bo); 1120 u64 pte; 1121 1122 pte = xe_bo_addr(bo, bo_offset, XE_PAGE_SIZE); 1123 pte |= XE_PAGE_PRESENT | XE_PAGE_RW; 1124 pte |= pte_encode_pat_index(xe, pat_index, pt_level); 1125 pte |= pte_encode_ps(pt_level); 1126 1127 if (xe_bo_is_vram(bo) || xe_bo_is_stolen_devmem(bo)) 1128 pte |= XE_PPGTT_PTE_DM; 1129 1130 return pte; 1131 } 1132 1133 static u64 xelp_pte_encode_vma(u64 pte, struct xe_vma *vma, 1134 u16 pat_index, u32 pt_level) 1135 { 1136 struct xe_device *xe = xe_vma_vm(vma)->xe; 1137 1138 pte |= XE_PAGE_PRESENT; 1139 1140 if (likely(!xe_vma_read_only(vma))) 1141 pte |= XE_PAGE_RW; 1142 1143 pte |= pte_encode_pat_index(xe, pat_index, pt_level); 1144 pte |= pte_encode_ps(pt_level); 1145 1146 if (unlikely(xe_vma_is_null(vma))) 1147 pte |= XE_PTE_NULL; 1148 1149 return pte; 1150 } 1151 1152 static u64 xelp_pte_encode_addr(struct xe_device *xe, u64 addr, 1153 u16 pat_index, 1154 u32 pt_level, bool devmem, u64 flags) 1155 { 1156 u64 pte; 1157 1158 /* Avoid passing random bits directly as flags */ 1159 xe_assert(xe, !(flags & ~XE_PTE_PS64)); 1160 1161 pte = addr; 1162 pte |= XE_PAGE_PRESENT | XE_PAGE_RW; 1163 pte |= pte_encode_pat_index(xe, pat_index, pt_level); 1164 pte |= pte_encode_ps(pt_level); 1165 1166 if (devmem) 1167 pte |= XE_PPGTT_PTE_DM; 1168 1169 pte |= flags; 1170 1171 return pte; 1172 } 1173 1174 static const struct xe_pt_ops xelp_pt_ops = { 1175 .pte_encode_bo = xelp_pte_encode_bo, 1176 .pte_encode_vma = xelp_pte_encode_vma, 1177 .pte_encode_addr = xelp_pte_encode_addr, 1178 .pde_encode_bo = xelp_pde_encode_bo, 1179 }; 1180 1181 /** 1182 * xe_vm_create_scratch() - Setup a scratch memory pagetable tree for the 1183 * given tile and vm. 1184 * @xe: xe device. 1185 * @tile: tile to set up for. 1186 * @vm: vm to set up for. 1187 * 1188 * Sets up a pagetable tree with one page-table per level and a single 1189 * leaf PTE. All pagetable entries point to the single page-table or, 1190 * for MAX_HUGEPTE_LEVEL, a NULL huge PTE returning 0 on read and 1191 * writes become NOPs. 1192 * 1193 * Return: 0 on success, negative error code on error. 1194 */ 1195 static int xe_vm_create_scratch(struct xe_device *xe, struct xe_tile *tile, 1196 struct xe_vm *vm) 1197 { 1198 u8 id = tile->id; 1199 int i; 1200 1201 for (i = MAX_HUGEPTE_LEVEL; i < vm->pt_root[id]->level; i++) { 1202 vm->scratch_pt[id][i] = xe_pt_create(vm, tile, i); 1203 if (IS_ERR(vm->scratch_pt[id][i])) 1204 return PTR_ERR(vm->scratch_pt[id][i]); 1205 1206 xe_pt_populate_empty(tile, vm, vm->scratch_pt[id][i]); 1207 } 1208 1209 return 0; 1210 } 1211 1212 static void xe_vm_free_scratch(struct xe_vm *vm) 1213 { 1214 struct xe_tile *tile; 1215 u8 id; 1216 1217 if (!xe_vm_has_scratch(vm)) 1218 return; 1219 1220 for_each_tile(tile, vm->xe, id) { 1221 u32 i; 1222 1223 if (!vm->pt_root[id]) 1224 continue; 1225 1226 for (i = MAX_HUGEPTE_LEVEL; i < vm->pt_root[id]->level; ++i) 1227 if (vm->scratch_pt[id][i]) 1228 xe_pt_destroy(vm->scratch_pt[id][i], vm->flags, NULL); 1229 } 1230 } 1231 1232 struct xe_vm *xe_vm_create(struct xe_device *xe, u32 flags) 1233 { 1234 struct drm_gem_object *vm_resv_obj; 1235 struct xe_vm *vm; 1236 int err, number_tiles = 0; 1237 struct xe_tile *tile; 1238 u8 id; 1239 1240 vm = kzalloc(sizeof(*vm), GFP_KERNEL); 1241 if (!vm) 1242 return ERR_PTR(-ENOMEM); 1243 1244 vm->xe = xe; 1245 1246 vm->size = 1ull << xe->info.va_bits; 1247 1248 vm->flags = flags; 1249 1250 init_rwsem(&vm->lock); 1251 mutex_init(&vm->snap_mutex); 1252 1253 INIT_LIST_HEAD(&vm->rebind_list); 1254 1255 INIT_LIST_HEAD(&vm->userptr.repin_list); 1256 INIT_LIST_HEAD(&vm->userptr.invalidated); 1257 init_rwsem(&vm->userptr.notifier_lock); 1258 spin_lock_init(&vm->userptr.invalidated_lock); 1259 1260 INIT_LIST_HEAD(&vm->preempt.exec_queues); 1261 vm->preempt.min_run_period_ms = 10; /* FIXME: Wire up to uAPI */ 1262 1263 for_each_tile(tile, xe, id) 1264 xe_range_fence_tree_init(&vm->rftree[id]); 1265 1266 vm->pt_ops = &xelp_pt_ops; 1267 1268 if (!(flags & XE_VM_FLAG_MIGRATION)) 1269 xe_pm_runtime_get_noresume(xe); 1270 1271 vm_resv_obj = drm_gpuvm_resv_object_alloc(&xe->drm); 1272 if (!vm_resv_obj) { 1273 err = -ENOMEM; 1274 goto err_no_resv; 1275 } 1276 1277 drm_gpuvm_init(&vm->gpuvm, "Xe VM", DRM_GPUVM_RESV_PROTECTED, &xe->drm, 1278 vm_resv_obj, 0, vm->size, 0, 0, &gpuvm_ops); 1279 1280 drm_gem_object_put(vm_resv_obj); 1281 1282 err = dma_resv_lock_interruptible(xe_vm_resv(vm), NULL); 1283 if (err) 1284 goto err_close; 1285 1286 if (IS_DGFX(xe) && xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K) 1287 vm->flags |= XE_VM_FLAG_64K; 1288 1289 for_each_tile(tile, xe, id) { 1290 if (flags & XE_VM_FLAG_MIGRATION && 1291 tile->id != XE_VM_FLAG_TILE_ID(flags)) 1292 continue; 1293 1294 vm->pt_root[id] = xe_pt_create(vm, tile, xe->info.vm_max_level); 1295 if (IS_ERR(vm->pt_root[id])) { 1296 err = PTR_ERR(vm->pt_root[id]); 1297 vm->pt_root[id] = NULL; 1298 goto err_unlock_close; 1299 } 1300 } 1301 1302 if (xe_vm_has_scratch(vm)) { 1303 for_each_tile(tile, xe, id) { 1304 if (!vm->pt_root[id]) 1305 continue; 1306 1307 err = xe_vm_create_scratch(xe, tile, vm); 1308 if (err) 1309 goto err_unlock_close; 1310 } 1311 vm->batch_invalidate_tlb = true; 1312 } 1313 1314 if (vm->flags & XE_VM_FLAG_LR_MODE) { 1315 INIT_WORK(&vm->preempt.rebind_work, preempt_rebind_work_func); 1316 vm->batch_invalidate_tlb = false; 1317 } 1318 1319 /* Fill pt_root after allocating scratch tables */ 1320 for_each_tile(tile, xe, id) { 1321 if (!vm->pt_root[id]) 1322 continue; 1323 1324 xe_pt_populate_empty(tile, vm, vm->pt_root[id]); 1325 } 1326 dma_resv_unlock(xe_vm_resv(vm)); 1327 1328 /* Kernel migration VM shouldn't have a circular loop.. */ 1329 if (!(flags & XE_VM_FLAG_MIGRATION)) { 1330 for_each_tile(tile, xe, id) { 1331 struct xe_gt *gt = tile->primary_gt; 1332 struct xe_vm *migrate_vm; 1333 struct xe_exec_queue *q; 1334 u32 create_flags = EXEC_QUEUE_FLAG_VM; 1335 1336 if (!vm->pt_root[id]) 1337 continue; 1338 1339 migrate_vm = xe_migrate_get_vm(tile->migrate); 1340 q = xe_exec_queue_create_class(xe, gt, migrate_vm, 1341 XE_ENGINE_CLASS_COPY, 1342 create_flags); 1343 xe_vm_put(migrate_vm); 1344 if (IS_ERR(q)) { 1345 err = PTR_ERR(q); 1346 goto err_close; 1347 } 1348 vm->q[id] = q; 1349 number_tiles++; 1350 } 1351 } 1352 1353 if (number_tiles > 1) 1354 vm->composite_fence_ctx = dma_fence_context_alloc(1); 1355 1356 mutex_lock(&xe->usm.lock); 1357 if (flags & XE_VM_FLAG_FAULT_MODE) 1358 xe->usm.num_vm_in_fault_mode++; 1359 else if (!(flags & XE_VM_FLAG_MIGRATION)) 1360 xe->usm.num_vm_in_non_fault_mode++; 1361 mutex_unlock(&xe->usm.lock); 1362 1363 trace_xe_vm_create(vm); 1364 1365 return vm; 1366 1367 err_unlock_close: 1368 dma_resv_unlock(xe_vm_resv(vm)); 1369 err_close: 1370 xe_vm_close_and_put(vm); 1371 return ERR_PTR(err); 1372 1373 err_no_resv: 1374 mutex_destroy(&vm->snap_mutex); 1375 for_each_tile(tile, xe, id) 1376 xe_range_fence_tree_fini(&vm->rftree[id]); 1377 kfree(vm); 1378 if (!(flags & XE_VM_FLAG_MIGRATION)) 1379 xe_pm_runtime_put(xe); 1380 return ERR_PTR(err); 1381 } 1382 1383 static void xe_vm_close(struct xe_vm *vm) 1384 { 1385 down_write(&vm->lock); 1386 vm->size = 0; 1387 up_write(&vm->lock); 1388 } 1389 1390 void xe_vm_close_and_put(struct xe_vm *vm) 1391 { 1392 LIST_HEAD(contested); 1393 struct xe_device *xe = vm->xe; 1394 struct xe_tile *tile; 1395 struct xe_vma *vma, *next_vma; 1396 struct drm_gpuva *gpuva, *next; 1397 u8 id; 1398 1399 xe_assert(xe, !vm->preempt.num_exec_queues); 1400 1401 xe_vm_close(vm); 1402 if (xe_vm_in_preempt_fence_mode(vm)) 1403 flush_work(&vm->preempt.rebind_work); 1404 1405 down_write(&vm->lock); 1406 for_each_tile(tile, xe, id) { 1407 if (vm->q[id]) 1408 xe_exec_queue_last_fence_put(vm->q[id], vm); 1409 } 1410 up_write(&vm->lock); 1411 1412 for_each_tile(tile, xe, id) { 1413 if (vm->q[id]) { 1414 xe_exec_queue_kill(vm->q[id]); 1415 xe_exec_queue_put(vm->q[id]); 1416 vm->q[id] = NULL; 1417 } 1418 } 1419 1420 down_write(&vm->lock); 1421 xe_vm_lock(vm, false); 1422 drm_gpuvm_for_each_va_safe(gpuva, next, &vm->gpuvm) { 1423 vma = gpuva_to_vma(gpuva); 1424 1425 if (xe_vma_has_no_bo(vma)) { 1426 down_read(&vm->userptr.notifier_lock); 1427 vma->gpuva.flags |= XE_VMA_DESTROYED; 1428 up_read(&vm->userptr.notifier_lock); 1429 } 1430 1431 xe_vm_remove_vma(vm, vma); 1432 1433 /* easy case, remove from VMA? */ 1434 if (xe_vma_has_no_bo(vma) || xe_vma_bo(vma)->vm) { 1435 list_del_init(&vma->combined_links.rebind); 1436 xe_vma_destroy(vma, NULL); 1437 continue; 1438 } 1439 1440 list_move_tail(&vma->combined_links.destroy, &contested); 1441 vma->gpuva.flags |= XE_VMA_DESTROYED; 1442 } 1443 1444 /* 1445 * All vm operations will add shared fences to resv. 1446 * The only exception is eviction for a shared object, 1447 * but even so, the unbind when evicted would still 1448 * install a fence to resv. Hence it's safe to 1449 * destroy the pagetables immediately. 1450 */ 1451 xe_vm_free_scratch(vm); 1452 1453 for_each_tile(tile, xe, id) { 1454 if (vm->pt_root[id]) { 1455 xe_pt_destroy(vm->pt_root[id], vm->flags, NULL); 1456 vm->pt_root[id] = NULL; 1457 } 1458 } 1459 xe_vm_unlock(vm); 1460 1461 /* 1462 * VM is now dead, cannot re-add nodes to vm->vmas if it's NULL 1463 * Since we hold a refcount to the bo, we can remove and free 1464 * the members safely without locking. 1465 */ 1466 list_for_each_entry_safe(vma, next_vma, &contested, 1467 combined_links.destroy) { 1468 list_del_init(&vma->combined_links.destroy); 1469 xe_vma_destroy_unlocked(vma); 1470 } 1471 1472 up_write(&vm->lock); 1473 1474 mutex_lock(&xe->usm.lock); 1475 if (vm->flags & XE_VM_FLAG_FAULT_MODE) 1476 xe->usm.num_vm_in_fault_mode--; 1477 else if (!(vm->flags & XE_VM_FLAG_MIGRATION)) 1478 xe->usm.num_vm_in_non_fault_mode--; 1479 1480 if (vm->usm.asid) { 1481 void *lookup; 1482 1483 xe_assert(xe, xe->info.has_asid); 1484 xe_assert(xe, !(vm->flags & XE_VM_FLAG_MIGRATION)); 1485 1486 lookup = xa_erase(&xe->usm.asid_to_vm, vm->usm.asid); 1487 xe_assert(xe, lookup == vm); 1488 } 1489 mutex_unlock(&xe->usm.lock); 1490 1491 for_each_tile(tile, xe, id) 1492 xe_range_fence_tree_fini(&vm->rftree[id]); 1493 1494 xe_vm_put(vm); 1495 } 1496 1497 static void xe_vm_free(struct drm_gpuvm *gpuvm) 1498 { 1499 struct xe_vm *vm = container_of(gpuvm, struct xe_vm, gpuvm); 1500 struct xe_device *xe = vm->xe; 1501 struct xe_tile *tile; 1502 u8 id; 1503 1504 /* xe_vm_close_and_put was not called? */ 1505 xe_assert(xe, !vm->size); 1506 1507 mutex_destroy(&vm->snap_mutex); 1508 1509 if (!(vm->flags & XE_VM_FLAG_MIGRATION)) 1510 xe_pm_runtime_put(xe); 1511 1512 for_each_tile(tile, xe, id) 1513 XE_WARN_ON(vm->pt_root[id]); 1514 1515 trace_xe_vm_free(vm); 1516 kfree(vm); 1517 } 1518 1519 struct xe_vm *xe_vm_lookup(struct xe_file *xef, u32 id) 1520 { 1521 struct xe_vm *vm; 1522 1523 mutex_lock(&xef->vm.lock); 1524 vm = xa_load(&xef->vm.xa, id); 1525 if (vm) 1526 xe_vm_get(vm); 1527 mutex_unlock(&xef->vm.lock); 1528 1529 return vm; 1530 } 1531 1532 u64 xe_vm_pdp4_descriptor(struct xe_vm *vm, struct xe_tile *tile) 1533 { 1534 return vm->pt_ops->pde_encode_bo(vm->pt_root[tile->id]->bo, 0, 1535 tile_to_xe(tile)->pat.idx[XE_CACHE_WB]); 1536 } 1537 1538 static struct xe_exec_queue * 1539 to_wait_exec_queue(struct xe_vm *vm, struct xe_exec_queue *q) 1540 { 1541 return q ? q : vm->q[0]; 1542 } 1543 1544 static struct dma_fence * 1545 xe_vm_unbind_vma(struct xe_vma *vma, struct xe_exec_queue *q, 1546 struct xe_sync_entry *syncs, u32 num_syncs, 1547 bool first_op, bool last_op) 1548 { 1549 struct xe_vm *vm = xe_vma_vm(vma); 1550 struct xe_exec_queue *wait_exec_queue = to_wait_exec_queue(vm, q); 1551 struct xe_tile *tile; 1552 struct dma_fence *fence = NULL; 1553 struct dma_fence **fences = NULL; 1554 struct dma_fence_array *cf = NULL; 1555 int cur_fence = 0, i; 1556 int number_tiles = hweight8(vma->tile_present); 1557 int err; 1558 u8 id; 1559 1560 trace_xe_vma_unbind(vma); 1561 1562 if (vma->ufence) { 1563 struct xe_user_fence * const f = vma->ufence; 1564 1565 if (!xe_sync_ufence_get_status(f)) 1566 return ERR_PTR(-EBUSY); 1567 1568 vma->ufence = NULL; 1569 xe_sync_ufence_put(f); 1570 } 1571 1572 if (number_tiles > 1) { 1573 fences = kmalloc_array(number_tiles, sizeof(*fences), 1574 GFP_KERNEL); 1575 if (!fences) 1576 return ERR_PTR(-ENOMEM); 1577 } 1578 1579 for_each_tile(tile, vm->xe, id) { 1580 if (!(vma->tile_present & BIT(id))) 1581 goto next; 1582 1583 fence = __xe_pt_unbind_vma(tile, vma, q ? q : vm->q[id], 1584 first_op ? syncs : NULL, 1585 first_op ? num_syncs : 0); 1586 if (IS_ERR(fence)) { 1587 err = PTR_ERR(fence); 1588 goto err_fences; 1589 } 1590 1591 if (fences) 1592 fences[cur_fence++] = fence; 1593 1594 next: 1595 if (q && vm->pt_root[id] && !list_empty(&q->multi_gt_list)) 1596 q = list_next_entry(q, multi_gt_list); 1597 } 1598 1599 if (fences) { 1600 cf = dma_fence_array_create(number_tiles, fences, 1601 vm->composite_fence_ctx, 1602 vm->composite_fence_seqno++, 1603 false); 1604 if (!cf) { 1605 --vm->composite_fence_seqno; 1606 err = -ENOMEM; 1607 goto err_fences; 1608 } 1609 } 1610 1611 fence = cf ? &cf->base : !fence ? 1612 xe_exec_queue_last_fence_get(wait_exec_queue, vm) : fence; 1613 if (last_op) { 1614 for (i = 0; i < num_syncs; i++) 1615 xe_sync_entry_signal(&syncs[i], fence); 1616 } 1617 1618 return fence; 1619 1620 err_fences: 1621 if (fences) { 1622 while (cur_fence) 1623 dma_fence_put(fences[--cur_fence]); 1624 kfree(fences); 1625 } 1626 1627 return ERR_PTR(err); 1628 } 1629 1630 static struct dma_fence * 1631 xe_vm_bind_vma(struct xe_vma *vma, struct xe_exec_queue *q, 1632 struct xe_sync_entry *syncs, u32 num_syncs, 1633 bool first_op, bool last_op) 1634 { 1635 struct xe_tile *tile; 1636 struct dma_fence *fence; 1637 struct dma_fence **fences = NULL; 1638 struct dma_fence_array *cf = NULL; 1639 struct xe_vm *vm = xe_vma_vm(vma); 1640 int cur_fence = 0, i; 1641 int number_tiles = hweight8(vma->tile_mask); 1642 int err; 1643 u8 id; 1644 1645 trace_xe_vma_bind(vma); 1646 1647 if (number_tiles > 1) { 1648 fences = kmalloc_array(number_tiles, sizeof(*fences), 1649 GFP_KERNEL); 1650 if (!fences) 1651 return ERR_PTR(-ENOMEM); 1652 } 1653 1654 for_each_tile(tile, vm->xe, id) { 1655 if (!(vma->tile_mask & BIT(id))) 1656 goto next; 1657 1658 fence = __xe_pt_bind_vma(tile, vma, q ? q : vm->q[id], 1659 first_op ? syncs : NULL, 1660 first_op ? num_syncs : 0, 1661 vma->tile_present & BIT(id)); 1662 if (IS_ERR(fence)) { 1663 err = PTR_ERR(fence); 1664 goto err_fences; 1665 } 1666 1667 if (fences) 1668 fences[cur_fence++] = fence; 1669 1670 next: 1671 if (q && vm->pt_root[id] && !list_empty(&q->multi_gt_list)) 1672 q = list_next_entry(q, multi_gt_list); 1673 } 1674 1675 if (fences) { 1676 cf = dma_fence_array_create(number_tiles, fences, 1677 vm->composite_fence_ctx, 1678 vm->composite_fence_seqno++, 1679 false); 1680 if (!cf) { 1681 --vm->composite_fence_seqno; 1682 err = -ENOMEM; 1683 goto err_fences; 1684 } 1685 } 1686 1687 if (last_op) { 1688 for (i = 0; i < num_syncs; i++) 1689 xe_sync_entry_signal(&syncs[i], 1690 cf ? &cf->base : fence); 1691 } 1692 1693 return cf ? &cf->base : fence; 1694 1695 err_fences: 1696 if (fences) { 1697 while (cur_fence) 1698 dma_fence_put(fences[--cur_fence]); 1699 kfree(fences); 1700 } 1701 1702 return ERR_PTR(err); 1703 } 1704 1705 static struct xe_user_fence * 1706 find_ufence_get(struct xe_sync_entry *syncs, u32 num_syncs) 1707 { 1708 unsigned int i; 1709 1710 for (i = 0; i < num_syncs; i++) { 1711 struct xe_sync_entry *e = &syncs[i]; 1712 1713 if (xe_sync_is_ufence(e)) 1714 return xe_sync_ufence_get(e); 1715 } 1716 1717 return NULL; 1718 } 1719 1720 static int __xe_vm_bind(struct xe_vm *vm, struct xe_vma *vma, 1721 struct xe_exec_queue *q, struct xe_sync_entry *syncs, 1722 u32 num_syncs, bool immediate, bool first_op, 1723 bool last_op) 1724 { 1725 struct dma_fence *fence; 1726 struct xe_exec_queue *wait_exec_queue = to_wait_exec_queue(vm, q); 1727 struct xe_user_fence *ufence; 1728 1729 xe_vm_assert_held(vm); 1730 1731 ufence = find_ufence_get(syncs, num_syncs); 1732 if (vma->ufence && ufence) 1733 xe_sync_ufence_put(vma->ufence); 1734 1735 vma->ufence = ufence ?: vma->ufence; 1736 1737 if (immediate) { 1738 fence = xe_vm_bind_vma(vma, q, syncs, num_syncs, first_op, 1739 last_op); 1740 if (IS_ERR(fence)) 1741 return PTR_ERR(fence); 1742 } else { 1743 int i; 1744 1745 xe_assert(vm->xe, xe_vm_in_fault_mode(vm)); 1746 1747 fence = xe_exec_queue_last_fence_get(wait_exec_queue, vm); 1748 if (last_op) { 1749 for (i = 0; i < num_syncs; i++) 1750 xe_sync_entry_signal(&syncs[i], fence); 1751 } 1752 } 1753 1754 if (last_op) 1755 xe_exec_queue_last_fence_set(wait_exec_queue, vm, fence); 1756 dma_fence_put(fence); 1757 1758 return 0; 1759 } 1760 1761 static int xe_vm_bind(struct xe_vm *vm, struct xe_vma *vma, struct xe_exec_queue *q, 1762 struct xe_bo *bo, struct xe_sync_entry *syncs, 1763 u32 num_syncs, bool immediate, bool first_op, 1764 bool last_op) 1765 { 1766 int err; 1767 1768 xe_vm_assert_held(vm); 1769 xe_bo_assert_held(bo); 1770 1771 if (bo && immediate) { 1772 err = xe_bo_validate(bo, vm, true); 1773 if (err) 1774 return err; 1775 } 1776 1777 return __xe_vm_bind(vm, vma, q, syncs, num_syncs, immediate, first_op, 1778 last_op); 1779 } 1780 1781 static int xe_vm_unbind(struct xe_vm *vm, struct xe_vma *vma, 1782 struct xe_exec_queue *q, struct xe_sync_entry *syncs, 1783 u32 num_syncs, bool first_op, bool last_op) 1784 { 1785 struct dma_fence *fence; 1786 struct xe_exec_queue *wait_exec_queue = to_wait_exec_queue(vm, q); 1787 1788 xe_vm_assert_held(vm); 1789 xe_bo_assert_held(xe_vma_bo(vma)); 1790 1791 fence = xe_vm_unbind_vma(vma, q, syncs, num_syncs, first_op, last_op); 1792 if (IS_ERR(fence)) 1793 return PTR_ERR(fence); 1794 1795 xe_vma_destroy(vma, fence); 1796 if (last_op) 1797 xe_exec_queue_last_fence_set(wait_exec_queue, vm, fence); 1798 dma_fence_put(fence); 1799 1800 return 0; 1801 } 1802 1803 #define ALL_DRM_XE_VM_CREATE_FLAGS (DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE | \ 1804 DRM_XE_VM_CREATE_FLAG_LR_MODE | \ 1805 DRM_XE_VM_CREATE_FLAG_FAULT_MODE) 1806 1807 int xe_vm_create_ioctl(struct drm_device *dev, void *data, 1808 struct drm_file *file) 1809 { 1810 struct xe_device *xe = to_xe_device(dev); 1811 struct xe_file *xef = to_xe_file(file); 1812 struct drm_xe_vm_create *args = data; 1813 struct xe_tile *tile; 1814 struct xe_vm *vm; 1815 u32 id, asid; 1816 int err; 1817 u32 flags = 0; 1818 1819 if (XE_IOCTL_DBG(xe, args->extensions)) 1820 return -EINVAL; 1821 1822 if (XE_WA(xe_root_mmio_gt(xe), 14016763929)) 1823 args->flags |= DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE; 1824 1825 if (XE_IOCTL_DBG(xe, args->flags & DRM_XE_VM_CREATE_FLAG_FAULT_MODE && 1826 !xe->info.has_usm)) 1827 return -EINVAL; 1828 1829 if (XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1])) 1830 return -EINVAL; 1831 1832 if (XE_IOCTL_DBG(xe, args->flags & ~ALL_DRM_XE_VM_CREATE_FLAGS)) 1833 return -EINVAL; 1834 1835 if (XE_IOCTL_DBG(xe, args->flags & DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE && 1836 args->flags & DRM_XE_VM_CREATE_FLAG_FAULT_MODE)) 1837 return -EINVAL; 1838 1839 if (XE_IOCTL_DBG(xe, !(args->flags & DRM_XE_VM_CREATE_FLAG_LR_MODE) && 1840 args->flags & DRM_XE_VM_CREATE_FLAG_FAULT_MODE)) 1841 return -EINVAL; 1842 1843 if (XE_IOCTL_DBG(xe, args->flags & DRM_XE_VM_CREATE_FLAG_FAULT_MODE && 1844 xe_device_in_non_fault_mode(xe))) 1845 return -EINVAL; 1846 1847 if (XE_IOCTL_DBG(xe, !(args->flags & DRM_XE_VM_CREATE_FLAG_FAULT_MODE) && 1848 xe_device_in_fault_mode(xe))) 1849 return -EINVAL; 1850 1851 if (XE_IOCTL_DBG(xe, args->extensions)) 1852 return -EINVAL; 1853 1854 if (args->flags & DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE) 1855 flags |= XE_VM_FLAG_SCRATCH_PAGE; 1856 if (args->flags & DRM_XE_VM_CREATE_FLAG_LR_MODE) 1857 flags |= XE_VM_FLAG_LR_MODE; 1858 if (args->flags & DRM_XE_VM_CREATE_FLAG_FAULT_MODE) 1859 flags |= XE_VM_FLAG_FAULT_MODE; 1860 1861 vm = xe_vm_create(xe, flags); 1862 if (IS_ERR(vm)) 1863 return PTR_ERR(vm); 1864 1865 mutex_lock(&xef->vm.lock); 1866 err = xa_alloc(&xef->vm.xa, &id, vm, xa_limit_32b, GFP_KERNEL); 1867 mutex_unlock(&xef->vm.lock); 1868 if (err) 1869 goto err_close_and_put; 1870 1871 if (xe->info.has_asid) { 1872 mutex_lock(&xe->usm.lock); 1873 err = xa_alloc_cyclic(&xe->usm.asid_to_vm, &asid, vm, 1874 XA_LIMIT(1, XE_MAX_ASID - 1), 1875 &xe->usm.next_asid, GFP_KERNEL); 1876 mutex_unlock(&xe->usm.lock); 1877 if (err < 0) 1878 goto err_free_id; 1879 1880 vm->usm.asid = asid; 1881 } 1882 1883 args->vm_id = id; 1884 vm->xef = xef; 1885 1886 /* Record BO memory for VM pagetable created against client */ 1887 for_each_tile(tile, xe, id) 1888 if (vm->pt_root[id]) 1889 xe_drm_client_add_bo(vm->xef->client, vm->pt_root[id]->bo); 1890 1891 #if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM) 1892 /* Warning: Security issue - never enable by default */ 1893 args->reserved[0] = xe_bo_main_addr(vm->pt_root[0]->bo, XE_PAGE_SIZE); 1894 #endif 1895 1896 return 0; 1897 1898 err_free_id: 1899 mutex_lock(&xef->vm.lock); 1900 xa_erase(&xef->vm.xa, id); 1901 mutex_unlock(&xef->vm.lock); 1902 err_close_and_put: 1903 xe_vm_close_and_put(vm); 1904 1905 return err; 1906 } 1907 1908 int xe_vm_destroy_ioctl(struct drm_device *dev, void *data, 1909 struct drm_file *file) 1910 { 1911 struct xe_device *xe = to_xe_device(dev); 1912 struct xe_file *xef = to_xe_file(file); 1913 struct drm_xe_vm_destroy *args = data; 1914 struct xe_vm *vm; 1915 int err = 0; 1916 1917 if (XE_IOCTL_DBG(xe, args->pad) || 1918 XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1])) 1919 return -EINVAL; 1920 1921 mutex_lock(&xef->vm.lock); 1922 vm = xa_load(&xef->vm.xa, args->vm_id); 1923 if (XE_IOCTL_DBG(xe, !vm)) 1924 err = -ENOENT; 1925 else if (XE_IOCTL_DBG(xe, vm->preempt.num_exec_queues)) 1926 err = -EBUSY; 1927 else 1928 xa_erase(&xef->vm.xa, args->vm_id); 1929 mutex_unlock(&xef->vm.lock); 1930 1931 if (!err) 1932 xe_vm_close_and_put(vm); 1933 1934 return err; 1935 } 1936 1937 static const u32 region_to_mem_type[] = { 1938 XE_PL_TT, 1939 XE_PL_VRAM0, 1940 XE_PL_VRAM1, 1941 }; 1942 1943 static int xe_vm_prefetch(struct xe_vm *vm, struct xe_vma *vma, 1944 struct xe_exec_queue *q, u32 region, 1945 struct xe_sync_entry *syncs, u32 num_syncs, 1946 bool first_op, bool last_op) 1947 { 1948 struct xe_exec_queue *wait_exec_queue = to_wait_exec_queue(vm, q); 1949 int err; 1950 1951 xe_assert(vm->xe, region < ARRAY_SIZE(region_to_mem_type)); 1952 1953 if (!xe_vma_has_no_bo(vma)) { 1954 err = xe_bo_migrate(xe_vma_bo(vma), region_to_mem_type[region]); 1955 if (err) 1956 return err; 1957 } 1958 1959 if (vma->tile_mask != (vma->tile_present & ~vma->tile_invalidated)) { 1960 return xe_vm_bind(vm, vma, q, xe_vma_bo(vma), syncs, num_syncs, 1961 true, first_op, last_op); 1962 } else { 1963 int i; 1964 1965 /* Nothing to do, signal fences now */ 1966 if (last_op) { 1967 for (i = 0; i < num_syncs; i++) { 1968 struct dma_fence *fence = 1969 xe_exec_queue_last_fence_get(wait_exec_queue, vm); 1970 1971 xe_sync_entry_signal(&syncs[i], fence); 1972 dma_fence_put(fence); 1973 } 1974 } 1975 1976 return 0; 1977 } 1978 } 1979 1980 static void prep_vma_destroy(struct xe_vm *vm, struct xe_vma *vma, 1981 bool post_commit) 1982 { 1983 down_read(&vm->userptr.notifier_lock); 1984 vma->gpuva.flags |= XE_VMA_DESTROYED; 1985 up_read(&vm->userptr.notifier_lock); 1986 if (post_commit) 1987 xe_vm_remove_vma(vm, vma); 1988 } 1989 1990 #undef ULL 1991 #define ULL unsigned long long 1992 1993 #if IS_ENABLED(CONFIG_DRM_XE_DEBUG_VM) 1994 static void print_op(struct xe_device *xe, struct drm_gpuva_op *op) 1995 { 1996 struct xe_vma *vma; 1997 1998 switch (op->op) { 1999 case DRM_GPUVA_OP_MAP: 2000 vm_dbg(&xe->drm, "MAP: addr=0x%016llx, range=0x%016llx", 2001 (ULL)op->map.va.addr, (ULL)op->map.va.range); 2002 break; 2003 case DRM_GPUVA_OP_REMAP: 2004 vma = gpuva_to_vma(op->remap.unmap->va); 2005 vm_dbg(&xe->drm, "REMAP:UNMAP: addr=0x%016llx, range=0x%016llx, keep=%d", 2006 (ULL)xe_vma_start(vma), (ULL)xe_vma_size(vma), 2007 op->remap.unmap->keep ? 1 : 0); 2008 if (op->remap.prev) 2009 vm_dbg(&xe->drm, 2010 "REMAP:PREV: addr=0x%016llx, range=0x%016llx", 2011 (ULL)op->remap.prev->va.addr, 2012 (ULL)op->remap.prev->va.range); 2013 if (op->remap.next) 2014 vm_dbg(&xe->drm, 2015 "REMAP:NEXT: addr=0x%016llx, range=0x%016llx", 2016 (ULL)op->remap.next->va.addr, 2017 (ULL)op->remap.next->va.range); 2018 break; 2019 case DRM_GPUVA_OP_UNMAP: 2020 vma = gpuva_to_vma(op->unmap.va); 2021 vm_dbg(&xe->drm, "UNMAP: addr=0x%016llx, range=0x%016llx, keep=%d", 2022 (ULL)xe_vma_start(vma), (ULL)xe_vma_size(vma), 2023 op->unmap.keep ? 1 : 0); 2024 break; 2025 case DRM_GPUVA_OP_PREFETCH: 2026 vma = gpuva_to_vma(op->prefetch.va); 2027 vm_dbg(&xe->drm, "PREFETCH: addr=0x%016llx, range=0x%016llx", 2028 (ULL)xe_vma_start(vma), (ULL)xe_vma_size(vma)); 2029 break; 2030 default: 2031 drm_warn(&xe->drm, "NOT POSSIBLE"); 2032 } 2033 } 2034 #else 2035 static void print_op(struct xe_device *xe, struct drm_gpuva_op *op) 2036 { 2037 } 2038 #endif 2039 2040 /* 2041 * Create operations list from IOCTL arguments, setup operations fields so parse 2042 * and commit steps are decoupled from IOCTL arguments. This step can fail. 2043 */ 2044 static struct drm_gpuva_ops * 2045 vm_bind_ioctl_ops_create(struct xe_vm *vm, struct xe_bo *bo, 2046 u64 bo_offset_or_userptr, u64 addr, u64 range, 2047 u32 operation, u32 flags, 2048 u32 prefetch_region, u16 pat_index) 2049 { 2050 struct drm_gem_object *obj = bo ? &bo->ttm.base : NULL; 2051 struct drm_gpuva_ops *ops; 2052 struct drm_gpuva_op *__op; 2053 struct drm_gpuvm_bo *vm_bo; 2054 int err; 2055 2056 lockdep_assert_held_write(&vm->lock); 2057 2058 vm_dbg(&vm->xe->drm, 2059 "op=%d, addr=0x%016llx, range=0x%016llx, bo_offset_or_userptr=0x%016llx", 2060 operation, (ULL)addr, (ULL)range, 2061 (ULL)bo_offset_or_userptr); 2062 2063 switch (operation) { 2064 case DRM_XE_VM_BIND_OP_MAP: 2065 case DRM_XE_VM_BIND_OP_MAP_USERPTR: 2066 ops = drm_gpuvm_sm_map_ops_create(&vm->gpuvm, addr, range, 2067 obj, bo_offset_or_userptr); 2068 break; 2069 case DRM_XE_VM_BIND_OP_UNMAP: 2070 ops = drm_gpuvm_sm_unmap_ops_create(&vm->gpuvm, addr, range); 2071 break; 2072 case DRM_XE_VM_BIND_OP_PREFETCH: 2073 ops = drm_gpuvm_prefetch_ops_create(&vm->gpuvm, addr, range); 2074 break; 2075 case DRM_XE_VM_BIND_OP_UNMAP_ALL: 2076 xe_assert(vm->xe, bo); 2077 2078 err = xe_bo_lock(bo, true); 2079 if (err) 2080 return ERR_PTR(err); 2081 2082 vm_bo = drm_gpuvm_bo_obtain(&vm->gpuvm, obj); 2083 if (IS_ERR(vm_bo)) { 2084 xe_bo_unlock(bo); 2085 return ERR_CAST(vm_bo); 2086 } 2087 2088 ops = drm_gpuvm_bo_unmap_ops_create(vm_bo); 2089 drm_gpuvm_bo_put(vm_bo); 2090 xe_bo_unlock(bo); 2091 break; 2092 default: 2093 drm_warn(&vm->xe->drm, "NOT POSSIBLE"); 2094 ops = ERR_PTR(-EINVAL); 2095 } 2096 if (IS_ERR(ops)) 2097 return ops; 2098 2099 drm_gpuva_for_each_op(__op, ops) { 2100 struct xe_vma_op *op = gpuva_op_to_vma_op(__op); 2101 2102 if (__op->op == DRM_GPUVA_OP_MAP) { 2103 op->map.is_null = flags & DRM_XE_VM_BIND_FLAG_NULL; 2104 op->map.dumpable = flags & DRM_XE_VM_BIND_FLAG_DUMPABLE; 2105 op->map.pat_index = pat_index; 2106 } else if (__op->op == DRM_GPUVA_OP_PREFETCH) { 2107 op->prefetch.region = prefetch_region; 2108 } 2109 2110 print_op(vm->xe, __op); 2111 } 2112 2113 return ops; 2114 } 2115 2116 static struct xe_vma *new_vma(struct xe_vm *vm, struct drm_gpuva_op_map *op, 2117 u16 pat_index, unsigned int flags) 2118 { 2119 struct xe_bo *bo = op->gem.obj ? gem_to_xe_bo(op->gem.obj) : NULL; 2120 struct drm_exec exec; 2121 struct xe_vma *vma; 2122 int err; 2123 2124 lockdep_assert_held_write(&vm->lock); 2125 2126 if (bo) { 2127 drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0); 2128 drm_exec_until_all_locked(&exec) { 2129 err = 0; 2130 if (!bo->vm) { 2131 err = drm_exec_lock_obj(&exec, xe_vm_obj(vm)); 2132 drm_exec_retry_on_contention(&exec); 2133 } 2134 if (!err) { 2135 err = drm_exec_lock_obj(&exec, &bo->ttm.base); 2136 drm_exec_retry_on_contention(&exec); 2137 } 2138 if (err) { 2139 drm_exec_fini(&exec); 2140 return ERR_PTR(err); 2141 } 2142 } 2143 } 2144 vma = xe_vma_create(vm, bo, op->gem.offset, 2145 op->va.addr, op->va.addr + 2146 op->va.range - 1, pat_index, flags); 2147 if (bo) 2148 drm_exec_fini(&exec); 2149 2150 if (xe_vma_is_userptr(vma)) { 2151 err = xe_vma_userptr_pin_pages(to_userptr_vma(vma)); 2152 if (err) { 2153 prep_vma_destroy(vm, vma, false); 2154 xe_vma_destroy_unlocked(vma); 2155 return ERR_PTR(err); 2156 } 2157 } else if (!xe_vma_has_no_bo(vma) && !bo->vm) { 2158 err = add_preempt_fences(vm, bo); 2159 if (err) { 2160 prep_vma_destroy(vm, vma, false); 2161 xe_vma_destroy_unlocked(vma); 2162 return ERR_PTR(err); 2163 } 2164 } 2165 2166 return vma; 2167 } 2168 2169 static u64 xe_vma_max_pte_size(struct xe_vma *vma) 2170 { 2171 if (vma->gpuva.flags & XE_VMA_PTE_1G) 2172 return SZ_1G; 2173 else if (vma->gpuva.flags & (XE_VMA_PTE_2M | XE_VMA_PTE_COMPACT)) 2174 return SZ_2M; 2175 else if (vma->gpuva.flags & XE_VMA_PTE_64K) 2176 return SZ_64K; 2177 else if (vma->gpuva.flags & XE_VMA_PTE_4K) 2178 return SZ_4K; 2179 2180 return SZ_1G; /* Uninitialized, used max size */ 2181 } 2182 2183 static void xe_vma_set_pte_size(struct xe_vma *vma, u64 size) 2184 { 2185 switch (size) { 2186 case SZ_1G: 2187 vma->gpuva.flags |= XE_VMA_PTE_1G; 2188 break; 2189 case SZ_2M: 2190 vma->gpuva.flags |= XE_VMA_PTE_2M; 2191 break; 2192 case SZ_64K: 2193 vma->gpuva.flags |= XE_VMA_PTE_64K; 2194 break; 2195 case SZ_4K: 2196 vma->gpuva.flags |= XE_VMA_PTE_4K; 2197 break; 2198 } 2199 } 2200 2201 static int xe_vma_op_commit(struct xe_vm *vm, struct xe_vma_op *op) 2202 { 2203 int err = 0; 2204 2205 lockdep_assert_held_write(&vm->lock); 2206 2207 switch (op->base.op) { 2208 case DRM_GPUVA_OP_MAP: 2209 err |= xe_vm_insert_vma(vm, op->map.vma); 2210 if (!err) 2211 op->flags |= XE_VMA_OP_COMMITTED; 2212 break; 2213 case DRM_GPUVA_OP_REMAP: 2214 { 2215 u8 tile_present = 2216 gpuva_to_vma(op->base.remap.unmap->va)->tile_present; 2217 2218 prep_vma_destroy(vm, gpuva_to_vma(op->base.remap.unmap->va), 2219 true); 2220 op->flags |= XE_VMA_OP_COMMITTED; 2221 2222 if (op->remap.prev) { 2223 err |= xe_vm_insert_vma(vm, op->remap.prev); 2224 if (!err) 2225 op->flags |= XE_VMA_OP_PREV_COMMITTED; 2226 if (!err && op->remap.skip_prev) { 2227 op->remap.prev->tile_present = 2228 tile_present; 2229 op->remap.prev = NULL; 2230 } 2231 } 2232 if (op->remap.next) { 2233 err |= xe_vm_insert_vma(vm, op->remap.next); 2234 if (!err) 2235 op->flags |= XE_VMA_OP_NEXT_COMMITTED; 2236 if (!err && op->remap.skip_next) { 2237 op->remap.next->tile_present = 2238 tile_present; 2239 op->remap.next = NULL; 2240 } 2241 } 2242 2243 /* Adjust for partial unbind after removin VMA from VM */ 2244 if (!err) { 2245 op->base.remap.unmap->va->va.addr = op->remap.start; 2246 op->base.remap.unmap->va->va.range = op->remap.range; 2247 } 2248 break; 2249 } 2250 case DRM_GPUVA_OP_UNMAP: 2251 prep_vma_destroy(vm, gpuva_to_vma(op->base.unmap.va), true); 2252 op->flags |= XE_VMA_OP_COMMITTED; 2253 break; 2254 case DRM_GPUVA_OP_PREFETCH: 2255 op->flags |= XE_VMA_OP_COMMITTED; 2256 break; 2257 default: 2258 drm_warn(&vm->xe->drm, "NOT POSSIBLE"); 2259 } 2260 2261 return err; 2262 } 2263 2264 2265 static int vm_bind_ioctl_ops_parse(struct xe_vm *vm, struct xe_exec_queue *q, 2266 struct drm_gpuva_ops *ops, 2267 struct xe_sync_entry *syncs, u32 num_syncs, 2268 struct list_head *ops_list, bool last) 2269 { 2270 struct xe_device *xe = vm->xe; 2271 struct xe_vma_op *last_op = NULL; 2272 struct drm_gpuva_op *__op; 2273 int err = 0; 2274 2275 lockdep_assert_held_write(&vm->lock); 2276 2277 drm_gpuva_for_each_op(__op, ops) { 2278 struct xe_vma_op *op = gpuva_op_to_vma_op(__op); 2279 struct xe_vma *vma; 2280 bool first = list_empty(ops_list); 2281 unsigned int flags = 0; 2282 2283 INIT_LIST_HEAD(&op->link); 2284 list_add_tail(&op->link, ops_list); 2285 2286 if (first) { 2287 op->flags |= XE_VMA_OP_FIRST; 2288 op->num_syncs = num_syncs; 2289 op->syncs = syncs; 2290 } 2291 2292 op->q = q; 2293 2294 switch (op->base.op) { 2295 case DRM_GPUVA_OP_MAP: 2296 { 2297 flags |= op->map.is_null ? 2298 VMA_CREATE_FLAG_IS_NULL : 0; 2299 flags |= op->map.dumpable ? 2300 VMA_CREATE_FLAG_DUMPABLE : 0; 2301 2302 vma = new_vma(vm, &op->base.map, op->map.pat_index, 2303 flags); 2304 if (IS_ERR(vma)) 2305 return PTR_ERR(vma); 2306 2307 op->map.vma = vma; 2308 break; 2309 } 2310 case DRM_GPUVA_OP_REMAP: 2311 { 2312 struct xe_vma *old = 2313 gpuva_to_vma(op->base.remap.unmap->va); 2314 2315 op->remap.start = xe_vma_start(old); 2316 op->remap.range = xe_vma_size(old); 2317 2318 if (op->base.remap.prev) { 2319 flags |= op->base.remap.unmap->va->flags & 2320 XE_VMA_READ_ONLY ? 2321 VMA_CREATE_FLAG_READ_ONLY : 0; 2322 flags |= op->base.remap.unmap->va->flags & 2323 DRM_GPUVA_SPARSE ? 2324 VMA_CREATE_FLAG_IS_NULL : 0; 2325 flags |= op->base.remap.unmap->va->flags & 2326 XE_VMA_DUMPABLE ? 2327 VMA_CREATE_FLAG_DUMPABLE : 0; 2328 2329 vma = new_vma(vm, op->base.remap.prev, 2330 old->pat_index, flags); 2331 if (IS_ERR(vma)) 2332 return PTR_ERR(vma); 2333 2334 op->remap.prev = vma; 2335 2336 /* 2337 * Userptr creates a new SG mapping so 2338 * we must also rebind. 2339 */ 2340 op->remap.skip_prev = !xe_vma_is_userptr(old) && 2341 IS_ALIGNED(xe_vma_end(vma), 2342 xe_vma_max_pte_size(old)); 2343 if (op->remap.skip_prev) { 2344 xe_vma_set_pte_size(vma, xe_vma_max_pte_size(old)); 2345 op->remap.range -= 2346 xe_vma_end(vma) - 2347 xe_vma_start(old); 2348 op->remap.start = xe_vma_end(vma); 2349 vm_dbg(&xe->drm, "REMAP:SKIP_PREV: addr=0x%016llx, range=0x%016llx", 2350 (ULL)op->remap.start, 2351 (ULL)op->remap.range); 2352 } 2353 } 2354 2355 if (op->base.remap.next) { 2356 flags |= op->base.remap.unmap->va->flags & 2357 XE_VMA_READ_ONLY ? 2358 VMA_CREATE_FLAG_READ_ONLY : 0; 2359 flags |= op->base.remap.unmap->va->flags & 2360 DRM_GPUVA_SPARSE ? 2361 VMA_CREATE_FLAG_IS_NULL : 0; 2362 flags |= op->base.remap.unmap->va->flags & 2363 XE_VMA_DUMPABLE ? 2364 VMA_CREATE_FLAG_DUMPABLE : 0; 2365 2366 vma = new_vma(vm, op->base.remap.next, 2367 old->pat_index, flags); 2368 if (IS_ERR(vma)) 2369 return PTR_ERR(vma); 2370 2371 op->remap.next = vma; 2372 2373 /* 2374 * Userptr creates a new SG mapping so 2375 * we must also rebind. 2376 */ 2377 op->remap.skip_next = !xe_vma_is_userptr(old) && 2378 IS_ALIGNED(xe_vma_start(vma), 2379 xe_vma_max_pte_size(old)); 2380 if (op->remap.skip_next) { 2381 xe_vma_set_pte_size(vma, xe_vma_max_pte_size(old)); 2382 op->remap.range -= 2383 xe_vma_end(old) - 2384 xe_vma_start(vma); 2385 vm_dbg(&xe->drm, "REMAP:SKIP_NEXT: addr=0x%016llx, range=0x%016llx", 2386 (ULL)op->remap.start, 2387 (ULL)op->remap.range); 2388 } 2389 } 2390 break; 2391 } 2392 case DRM_GPUVA_OP_UNMAP: 2393 case DRM_GPUVA_OP_PREFETCH: 2394 /* Nothing to do */ 2395 break; 2396 default: 2397 drm_warn(&vm->xe->drm, "NOT POSSIBLE"); 2398 } 2399 2400 last_op = op; 2401 2402 err = xe_vma_op_commit(vm, op); 2403 if (err) 2404 return err; 2405 } 2406 2407 /* FIXME: Unhandled corner case */ 2408 XE_WARN_ON(!last_op && last && !list_empty(ops_list)); 2409 2410 if (!last_op) 2411 return 0; 2412 2413 last_op->ops = ops; 2414 if (last) { 2415 last_op->flags |= XE_VMA_OP_LAST; 2416 last_op->num_syncs = num_syncs; 2417 last_op->syncs = syncs; 2418 } 2419 2420 return 0; 2421 } 2422 2423 static int op_execute(struct drm_exec *exec, struct xe_vm *vm, 2424 struct xe_vma *vma, struct xe_vma_op *op) 2425 { 2426 int err; 2427 2428 lockdep_assert_held_write(&vm->lock); 2429 2430 err = xe_vm_lock_vma(exec, vma); 2431 if (err) 2432 return err; 2433 2434 xe_vm_assert_held(vm); 2435 xe_bo_assert_held(xe_vma_bo(vma)); 2436 2437 switch (op->base.op) { 2438 case DRM_GPUVA_OP_MAP: 2439 err = xe_vm_bind(vm, vma, op->q, xe_vma_bo(vma), 2440 op->syncs, op->num_syncs, 2441 !xe_vm_in_fault_mode(vm), 2442 op->flags & XE_VMA_OP_FIRST, 2443 op->flags & XE_VMA_OP_LAST); 2444 break; 2445 case DRM_GPUVA_OP_REMAP: 2446 { 2447 bool prev = !!op->remap.prev; 2448 bool next = !!op->remap.next; 2449 2450 if (!op->remap.unmap_done) { 2451 if (prev || next) 2452 vma->gpuva.flags |= XE_VMA_FIRST_REBIND; 2453 err = xe_vm_unbind(vm, vma, op->q, op->syncs, 2454 op->num_syncs, 2455 op->flags & XE_VMA_OP_FIRST, 2456 op->flags & XE_VMA_OP_LAST && 2457 !prev && !next); 2458 if (err) 2459 break; 2460 op->remap.unmap_done = true; 2461 } 2462 2463 if (prev) { 2464 op->remap.prev->gpuva.flags |= XE_VMA_LAST_REBIND; 2465 err = xe_vm_bind(vm, op->remap.prev, op->q, 2466 xe_vma_bo(op->remap.prev), op->syncs, 2467 op->num_syncs, true, false, 2468 op->flags & XE_VMA_OP_LAST && !next); 2469 op->remap.prev->gpuva.flags &= ~XE_VMA_LAST_REBIND; 2470 if (err) 2471 break; 2472 op->remap.prev = NULL; 2473 } 2474 2475 if (next) { 2476 op->remap.next->gpuva.flags |= XE_VMA_LAST_REBIND; 2477 err = xe_vm_bind(vm, op->remap.next, op->q, 2478 xe_vma_bo(op->remap.next), 2479 op->syncs, op->num_syncs, 2480 true, false, 2481 op->flags & XE_VMA_OP_LAST); 2482 op->remap.next->gpuva.flags &= ~XE_VMA_LAST_REBIND; 2483 if (err) 2484 break; 2485 op->remap.next = NULL; 2486 } 2487 2488 break; 2489 } 2490 case DRM_GPUVA_OP_UNMAP: 2491 err = xe_vm_unbind(vm, vma, op->q, op->syncs, 2492 op->num_syncs, op->flags & XE_VMA_OP_FIRST, 2493 op->flags & XE_VMA_OP_LAST); 2494 break; 2495 case DRM_GPUVA_OP_PREFETCH: 2496 err = xe_vm_prefetch(vm, vma, op->q, op->prefetch.region, 2497 op->syncs, op->num_syncs, 2498 op->flags & XE_VMA_OP_FIRST, 2499 op->flags & XE_VMA_OP_LAST); 2500 break; 2501 default: 2502 drm_warn(&vm->xe->drm, "NOT POSSIBLE"); 2503 } 2504 2505 if (err) 2506 trace_xe_vma_fail(vma); 2507 2508 return err; 2509 } 2510 2511 static int __xe_vma_op_execute(struct xe_vm *vm, struct xe_vma *vma, 2512 struct xe_vma_op *op) 2513 { 2514 struct drm_exec exec; 2515 int err; 2516 2517 retry_userptr: 2518 drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0); 2519 drm_exec_until_all_locked(&exec) { 2520 err = op_execute(&exec, vm, vma, op); 2521 drm_exec_retry_on_contention(&exec); 2522 if (err) 2523 break; 2524 } 2525 drm_exec_fini(&exec); 2526 2527 if (err == -EAGAIN) { 2528 lockdep_assert_held_write(&vm->lock); 2529 2530 if (op->base.op == DRM_GPUVA_OP_REMAP) { 2531 if (!op->remap.unmap_done) 2532 vma = gpuva_to_vma(op->base.remap.unmap->va); 2533 else if (op->remap.prev) 2534 vma = op->remap.prev; 2535 else 2536 vma = op->remap.next; 2537 } 2538 2539 if (xe_vma_is_userptr(vma)) { 2540 err = xe_vma_userptr_pin_pages(to_userptr_vma(vma)); 2541 if (!err) 2542 goto retry_userptr; 2543 2544 trace_xe_vma_fail(vma); 2545 } 2546 } 2547 2548 return err; 2549 } 2550 2551 static int xe_vma_op_execute(struct xe_vm *vm, struct xe_vma_op *op) 2552 { 2553 int ret = 0; 2554 2555 lockdep_assert_held_write(&vm->lock); 2556 2557 switch (op->base.op) { 2558 case DRM_GPUVA_OP_MAP: 2559 ret = __xe_vma_op_execute(vm, op->map.vma, op); 2560 break; 2561 case DRM_GPUVA_OP_REMAP: 2562 { 2563 struct xe_vma *vma; 2564 2565 if (!op->remap.unmap_done) 2566 vma = gpuva_to_vma(op->base.remap.unmap->va); 2567 else if (op->remap.prev) 2568 vma = op->remap.prev; 2569 else 2570 vma = op->remap.next; 2571 2572 ret = __xe_vma_op_execute(vm, vma, op); 2573 break; 2574 } 2575 case DRM_GPUVA_OP_UNMAP: 2576 ret = __xe_vma_op_execute(vm, gpuva_to_vma(op->base.unmap.va), 2577 op); 2578 break; 2579 case DRM_GPUVA_OP_PREFETCH: 2580 ret = __xe_vma_op_execute(vm, 2581 gpuva_to_vma(op->base.prefetch.va), 2582 op); 2583 break; 2584 default: 2585 drm_warn(&vm->xe->drm, "NOT POSSIBLE"); 2586 } 2587 2588 return ret; 2589 } 2590 2591 static void xe_vma_op_cleanup(struct xe_vm *vm, struct xe_vma_op *op) 2592 { 2593 bool last = op->flags & XE_VMA_OP_LAST; 2594 2595 if (last) { 2596 while (op->num_syncs--) 2597 xe_sync_entry_cleanup(&op->syncs[op->num_syncs]); 2598 kfree(op->syncs); 2599 if (op->q) 2600 xe_exec_queue_put(op->q); 2601 } 2602 if (!list_empty(&op->link)) 2603 list_del(&op->link); 2604 if (op->ops) 2605 drm_gpuva_ops_free(&vm->gpuvm, op->ops); 2606 if (last) 2607 xe_vm_put(vm); 2608 } 2609 2610 static void xe_vma_op_unwind(struct xe_vm *vm, struct xe_vma_op *op, 2611 bool post_commit, bool prev_post_commit, 2612 bool next_post_commit) 2613 { 2614 lockdep_assert_held_write(&vm->lock); 2615 2616 switch (op->base.op) { 2617 case DRM_GPUVA_OP_MAP: 2618 if (op->map.vma) { 2619 prep_vma_destroy(vm, op->map.vma, post_commit); 2620 xe_vma_destroy_unlocked(op->map.vma); 2621 } 2622 break; 2623 case DRM_GPUVA_OP_UNMAP: 2624 { 2625 struct xe_vma *vma = gpuva_to_vma(op->base.unmap.va); 2626 2627 if (vma) { 2628 down_read(&vm->userptr.notifier_lock); 2629 vma->gpuva.flags &= ~XE_VMA_DESTROYED; 2630 up_read(&vm->userptr.notifier_lock); 2631 if (post_commit) 2632 xe_vm_insert_vma(vm, vma); 2633 } 2634 break; 2635 } 2636 case DRM_GPUVA_OP_REMAP: 2637 { 2638 struct xe_vma *vma = gpuva_to_vma(op->base.remap.unmap->va); 2639 2640 if (op->remap.prev) { 2641 prep_vma_destroy(vm, op->remap.prev, prev_post_commit); 2642 xe_vma_destroy_unlocked(op->remap.prev); 2643 } 2644 if (op->remap.next) { 2645 prep_vma_destroy(vm, op->remap.next, next_post_commit); 2646 xe_vma_destroy_unlocked(op->remap.next); 2647 } 2648 if (vma) { 2649 down_read(&vm->userptr.notifier_lock); 2650 vma->gpuva.flags &= ~XE_VMA_DESTROYED; 2651 up_read(&vm->userptr.notifier_lock); 2652 if (post_commit) 2653 xe_vm_insert_vma(vm, vma); 2654 } 2655 break; 2656 } 2657 case DRM_GPUVA_OP_PREFETCH: 2658 /* Nothing to do */ 2659 break; 2660 default: 2661 drm_warn(&vm->xe->drm, "NOT POSSIBLE"); 2662 } 2663 } 2664 2665 static void vm_bind_ioctl_ops_unwind(struct xe_vm *vm, 2666 struct drm_gpuva_ops **ops, 2667 int num_ops_list) 2668 { 2669 int i; 2670 2671 for (i = num_ops_list - 1; i >= 0; --i) { 2672 struct drm_gpuva_ops *__ops = ops[i]; 2673 struct drm_gpuva_op *__op; 2674 2675 if (!__ops) 2676 continue; 2677 2678 drm_gpuva_for_each_op_reverse(__op, __ops) { 2679 struct xe_vma_op *op = gpuva_op_to_vma_op(__op); 2680 2681 xe_vma_op_unwind(vm, op, 2682 op->flags & XE_VMA_OP_COMMITTED, 2683 op->flags & XE_VMA_OP_PREV_COMMITTED, 2684 op->flags & XE_VMA_OP_NEXT_COMMITTED); 2685 } 2686 2687 drm_gpuva_ops_free(&vm->gpuvm, __ops); 2688 } 2689 } 2690 2691 static int vm_bind_ioctl_ops_execute(struct xe_vm *vm, 2692 struct list_head *ops_list) 2693 { 2694 struct xe_vma_op *op, *next; 2695 int err; 2696 2697 lockdep_assert_held_write(&vm->lock); 2698 2699 list_for_each_entry_safe(op, next, ops_list, link) { 2700 err = xe_vma_op_execute(vm, op); 2701 if (err) { 2702 drm_warn(&vm->xe->drm, "VM op(%d) failed with %d", 2703 op->base.op, err); 2704 /* 2705 * FIXME: Killing VM rather than proper error handling 2706 */ 2707 xe_vm_kill(vm); 2708 return -ENOSPC; 2709 } 2710 xe_vma_op_cleanup(vm, op); 2711 } 2712 2713 return 0; 2714 } 2715 2716 #define SUPPORTED_FLAGS \ 2717 (DRM_XE_VM_BIND_FLAG_READONLY | \ 2718 DRM_XE_VM_BIND_FLAG_IMMEDIATE | \ 2719 DRM_XE_VM_BIND_FLAG_NULL | \ 2720 DRM_XE_VM_BIND_FLAG_DUMPABLE) 2721 #define XE_64K_PAGE_MASK 0xffffull 2722 #define ALL_DRM_XE_SYNCS_FLAGS (DRM_XE_SYNCS_FLAG_WAIT_FOR_OP) 2723 2724 static int vm_bind_ioctl_check_args(struct xe_device *xe, 2725 struct drm_xe_vm_bind *args, 2726 struct drm_xe_vm_bind_op **bind_ops) 2727 { 2728 int err; 2729 int i; 2730 2731 if (XE_IOCTL_DBG(xe, args->pad || args->pad2) || 2732 XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1])) 2733 return -EINVAL; 2734 2735 if (XE_IOCTL_DBG(xe, args->extensions)) 2736 return -EINVAL; 2737 2738 if (args->num_binds > 1) { 2739 u64 __user *bind_user = 2740 u64_to_user_ptr(args->vector_of_binds); 2741 2742 *bind_ops = kvmalloc_array(args->num_binds, 2743 sizeof(struct drm_xe_vm_bind_op), 2744 GFP_KERNEL | __GFP_ACCOUNT); 2745 if (!*bind_ops) 2746 return -ENOMEM; 2747 2748 err = __copy_from_user(*bind_ops, bind_user, 2749 sizeof(struct drm_xe_vm_bind_op) * 2750 args->num_binds); 2751 if (XE_IOCTL_DBG(xe, err)) { 2752 err = -EFAULT; 2753 goto free_bind_ops; 2754 } 2755 } else { 2756 *bind_ops = &args->bind; 2757 } 2758 2759 for (i = 0; i < args->num_binds; ++i) { 2760 u64 range = (*bind_ops)[i].range; 2761 u64 addr = (*bind_ops)[i].addr; 2762 u32 op = (*bind_ops)[i].op; 2763 u32 flags = (*bind_ops)[i].flags; 2764 u32 obj = (*bind_ops)[i].obj; 2765 u64 obj_offset = (*bind_ops)[i].obj_offset; 2766 u32 prefetch_region = (*bind_ops)[i].prefetch_mem_region_instance; 2767 bool is_null = flags & DRM_XE_VM_BIND_FLAG_NULL; 2768 u16 pat_index = (*bind_ops)[i].pat_index; 2769 u16 coh_mode; 2770 2771 if (XE_IOCTL_DBG(xe, pat_index >= xe->pat.n_entries)) { 2772 err = -EINVAL; 2773 goto free_bind_ops; 2774 } 2775 2776 pat_index = array_index_nospec(pat_index, xe->pat.n_entries); 2777 (*bind_ops)[i].pat_index = pat_index; 2778 coh_mode = xe_pat_index_get_coh_mode(xe, pat_index); 2779 if (XE_IOCTL_DBG(xe, !coh_mode)) { /* hw reserved */ 2780 err = -EINVAL; 2781 goto free_bind_ops; 2782 } 2783 2784 if (XE_WARN_ON(coh_mode > XE_COH_AT_LEAST_1WAY)) { 2785 err = -EINVAL; 2786 goto free_bind_ops; 2787 } 2788 2789 if (XE_IOCTL_DBG(xe, op > DRM_XE_VM_BIND_OP_PREFETCH) || 2790 XE_IOCTL_DBG(xe, flags & ~SUPPORTED_FLAGS) || 2791 XE_IOCTL_DBG(xe, obj && is_null) || 2792 XE_IOCTL_DBG(xe, obj_offset && is_null) || 2793 XE_IOCTL_DBG(xe, op != DRM_XE_VM_BIND_OP_MAP && 2794 is_null) || 2795 XE_IOCTL_DBG(xe, !obj && 2796 op == DRM_XE_VM_BIND_OP_MAP && 2797 !is_null) || 2798 XE_IOCTL_DBG(xe, !obj && 2799 op == DRM_XE_VM_BIND_OP_UNMAP_ALL) || 2800 XE_IOCTL_DBG(xe, addr && 2801 op == DRM_XE_VM_BIND_OP_UNMAP_ALL) || 2802 XE_IOCTL_DBG(xe, range && 2803 op == DRM_XE_VM_BIND_OP_UNMAP_ALL) || 2804 XE_IOCTL_DBG(xe, obj && 2805 op == DRM_XE_VM_BIND_OP_MAP_USERPTR) || 2806 XE_IOCTL_DBG(xe, coh_mode == XE_COH_NONE && 2807 op == DRM_XE_VM_BIND_OP_MAP_USERPTR) || 2808 XE_IOCTL_DBG(xe, obj && 2809 op == DRM_XE_VM_BIND_OP_PREFETCH) || 2810 XE_IOCTL_DBG(xe, prefetch_region && 2811 op != DRM_XE_VM_BIND_OP_PREFETCH) || 2812 XE_IOCTL_DBG(xe, !(BIT(prefetch_region) & 2813 xe->info.mem_region_mask)) || 2814 XE_IOCTL_DBG(xe, obj && 2815 op == DRM_XE_VM_BIND_OP_UNMAP)) { 2816 err = -EINVAL; 2817 goto free_bind_ops; 2818 } 2819 2820 if (XE_IOCTL_DBG(xe, obj_offset & ~PAGE_MASK) || 2821 XE_IOCTL_DBG(xe, addr & ~PAGE_MASK) || 2822 XE_IOCTL_DBG(xe, range & ~PAGE_MASK) || 2823 XE_IOCTL_DBG(xe, !range && 2824 op != DRM_XE_VM_BIND_OP_UNMAP_ALL)) { 2825 err = -EINVAL; 2826 goto free_bind_ops; 2827 } 2828 } 2829 2830 return 0; 2831 2832 free_bind_ops: 2833 if (args->num_binds > 1) 2834 kvfree(*bind_ops); 2835 return err; 2836 } 2837 2838 static int vm_bind_ioctl_signal_fences(struct xe_vm *vm, 2839 struct xe_exec_queue *q, 2840 struct xe_sync_entry *syncs, 2841 int num_syncs) 2842 { 2843 struct dma_fence *fence; 2844 int i, err = 0; 2845 2846 fence = xe_sync_in_fence_get(syncs, num_syncs, 2847 to_wait_exec_queue(vm, q), vm); 2848 if (IS_ERR(fence)) 2849 return PTR_ERR(fence); 2850 2851 for (i = 0; i < num_syncs; i++) 2852 xe_sync_entry_signal(&syncs[i], fence); 2853 2854 xe_exec_queue_last_fence_set(to_wait_exec_queue(vm, q), vm, 2855 fence); 2856 dma_fence_put(fence); 2857 2858 return err; 2859 } 2860 2861 int xe_vm_bind_ioctl(struct drm_device *dev, void *data, struct drm_file *file) 2862 { 2863 struct xe_device *xe = to_xe_device(dev); 2864 struct xe_file *xef = to_xe_file(file); 2865 struct drm_xe_vm_bind *args = data; 2866 struct drm_xe_sync __user *syncs_user; 2867 struct xe_bo **bos = NULL; 2868 struct drm_gpuva_ops **ops = NULL; 2869 struct xe_vm *vm; 2870 struct xe_exec_queue *q = NULL; 2871 u32 num_syncs, num_ufence = 0; 2872 struct xe_sync_entry *syncs = NULL; 2873 struct drm_xe_vm_bind_op *bind_ops; 2874 LIST_HEAD(ops_list); 2875 int err; 2876 int i; 2877 2878 err = vm_bind_ioctl_check_args(xe, args, &bind_ops); 2879 if (err) 2880 return err; 2881 2882 if (args->exec_queue_id) { 2883 q = xe_exec_queue_lookup(xef, args->exec_queue_id); 2884 if (XE_IOCTL_DBG(xe, !q)) { 2885 err = -ENOENT; 2886 goto free_objs; 2887 } 2888 2889 if (XE_IOCTL_DBG(xe, !(q->flags & EXEC_QUEUE_FLAG_VM))) { 2890 err = -EINVAL; 2891 goto put_exec_queue; 2892 } 2893 } 2894 2895 vm = xe_vm_lookup(xef, args->vm_id); 2896 if (XE_IOCTL_DBG(xe, !vm)) { 2897 err = -EINVAL; 2898 goto put_exec_queue; 2899 } 2900 2901 err = down_write_killable(&vm->lock); 2902 if (err) 2903 goto put_vm; 2904 2905 if (XE_IOCTL_DBG(xe, xe_vm_is_closed_or_banned(vm))) { 2906 err = -ENOENT; 2907 goto release_vm_lock; 2908 } 2909 2910 for (i = 0; i < args->num_binds; ++i) { 2911 u64 range = bind_ops[i].range; 2912 u64 addr = bind_ops[i].addr; 2913 2914 if (XE_IOCTL_DBG(xe, range > vm->size) || 2915 XE_IOCTL_DBG(xe, addr > vm->size - range)) { 2916 err = -EINVAL; 2917 goto release_vm_lock; 2918 } 2919 } 2920 2921 if (args->num_binds) { 2922 bos = kvcalloc(args->num_binds, sizeof(*bos), 2923 GFP_KERNEL | __GFP_ACCOUNT); 2924 if (!bos) { 2925 err = -ENOMEM; 2926 goto release_vm_lock; 2927 } 2928 2929 ops = kvcalloc(args->num_binds, sizeof(*ops), 2930 GFP_KERNEL | __GFP_ACCOUNT); 2931 if (!ops) { 2932 err = -ENOMEM; 2933 goto release_vm_lock; 2934 } 2935 } 2936 2937 for (i = 0; i < args->num_binds; ++i) { 2938 struct drm_gem_object *gem_obj; 2939 u64 range = bind_ops[i].range; 2940 u64 addr = bind_ops[i].addr; 2941 u32 obj = bind_ops[i].obj; 2942 u64 obj_offset = bind_ops[i].obj_offset; 2943 u16 pat_index = bind_ops[i].pat_index; 2944 u16 coh_mode; 2945 2946 if (!obj) 2947 continue; 2948 2949 gem_obj = drm_gem_object_lookup(file, obj); 2950 if (XE_IOCTL_DBG(xe, !gem_obj)) { 2951 err = -ENOENT; 2952 goto put_obj; 2953 } 2954 bos[i] = gem_to_xe_bo(gem_obj); 2955 2956 if (XE_IOCTL_DBG(xe, range > bos[i]->size) || 2957 XE_IOCTL_DBG(xe, obj_offset > 2958 bos[i]->size - range)) { 2959 err = -EINVAL; 2960 goto put_obj; 2961 } 2962 2963 if (bos[i]->flags & XE_BO_FLAG_INTERNAL_64K) { 2964 if (XE_IOCTL_DBG(xe, obj_offset & 2965 XE_64K_PAGE_MASK) || 2966 XE_IOCTL_DBG(xe, addr & XE_64K_PAGE_MASK) || 2967 XE_IOCTL_DBG(xe, range & XE_64K_PAGE_MASK)) { 2968 err = -EINVAL; 2969 goto put_obj; 2970 } 2971 } 2972 2973 coh_mode = xe_pat_index_get_coh_mode(xe, pat_index); 2974 if (bos[i]->cpu_caching) { 2975 if (XE_IOCTL_DBG(xe, coh_mode == XE_COH_NONE && 2976 bos[i]->cpu_caching == DRM_XE_GEM_CPU_CACHING_WB)) { 2977 err = -EINVAL; 2978 goto put_obj; 2979 } 2980 } else if (XE_IOCTL_DBG(xe, coh_mode == XE_COH_NONE)) { 2981 /* 2982 * Imported dma-buf from a different device should 2983 * require 1way or 2way coherency since we don't know 2984 * how it was mapped on the CPU. Just assume is it 2985 * potentially cached on CPU side. 2986 */ 2987 err = -EINVAL; 2988 goto put_obj; 2989 } 2990 } 2991 2992 if (args->num_syncs) { 2993 syncs = kcalloc(args->num_syncs, sizeof(*syncs), GFP_KERNEL); 2994 if (!syncs) { 2995 err = -ENOMEM; 2996 goto put_obj; 2997 } 2998 } 2999 3000 syncs_user = u64_to_user_ptr(args->syncs); 3001 for (num_syncs = 0; num_syncs < args->num_syncs; num_syncs++) { 3002 err = xe_sync_entry_parse(xe, xef, &syncs[num_syncs], 3003 &syncs_user[num_syncs], 3004 (xe_vm_in_lr_mode(vm) ? 3005 SYNC_PARSE_FLAG_LR_MODE : 0) | 3006 (!args->num_binds ? 3007 SYNC_PARSE_FLAG_DISALLOW_USER_FENCE : 0)); 3008 if (err) 3009 goto free_syncs; 3010 3011 if (xe_sync_is_ufence(&syncs[num_syncs])) 3012 num_ufence++; 3013 } 3014 3015 if (XE_IOCTL_DBG(xe, num_ufence > 1)) { 3016 err = -EINVAL; 3017 goto free_syncs; 3018 } 3019 3020 if (!args->num_binds) { 3021 err = -ENODATA; 3022 goto free_syncs; 3023 } 3024 3025 for (i = 0; i < args->num_binds; ++i) { 3026 u64 range = bind_ops[i].range; 3027 u64 addr = bind_ops[i].addr; 3028 u32 op = bind_ops[i].op; 3029 u32 flags = bind_ops[i].flags; 3030 u64 obj_offset = bind_ops[i].obj_offset; 3031 u32 prefetch_region = bind_ops[i].prefetch_mem_region_instance; 3032 u16 pat_index = bind_ops[i].pat_index; 3033 3034 ops[i] = vm_bind_ioctl_ops_create(vm, bos[i], obj_offset, 3035 addr, range, op, flags, 3036 prefetch_region, pat_index); 3037 if (IS_ERR(ops[i])) { 3038 err = PTR_ERR(ops[i]); 3039 ops[i] = NULL; 3040 goto unwind_ops; 3041 } 3042 3043 err = vm_bind_ioctl_ops_parse(vm, q, ops[i], syncs, num_syncs, 3044 &ops_list, 3045 i == args->num_binds - 1); 3046 if (err) 3047 goto unwind_ops; 3048 } 3049 3050 /* Nothing to do */ 3051 if (list_empty(&ops_list)) { 3052 err = -ENODATA; 3053 goto unwind_ops; 3054 } 3055 3056 xe_vm_get(vm); 3057 if (q) 3058 xe_exec_queue_get(q); 3059 3060 err = vm_bind_ioctl_ops_execute(vm, &ops_list); 3061 3062 up_write(&vm->lock); 3063 3064 if (q) 3065 xe_exec_queue_put(q); 3066 xe_vm_put(vm); 3067 3068 for (i = 0; bos && i < args->num_binds; ++i) 3069 xe_bo_put(bos[i]); 3070 3071 kvfree(bos); 3072 kvfree(ops); 3073 if (args->num_binds > 1) 3074 kvfree(bind_ops); 3075 3076 return err; 3077 3078 unwind_ops: 3079 vm_bind_ioctl_ops_unwind(vm, ops, args->num_binds); 3080 free_syncs: 3081 if (err == -ENODATA) 3082 err = vm_bind_ioctl_signal_fences(vm, q, syncs, num_syncs); 3083 while (num_syncs--) 3084 xe_sync_entry_cleanup(&syncs[num_syncs]); 3085 3086 kfree(syncs); 3087 put_obj: 3088 for (i = 0; i < args->num_binds; ++i) 3089 xe_bo_put(bos[i]); 3090 release_vm_lock: 3091 up_write(&vm->lock); 3092 put_vm: 3093 xe_vm_put(vm); 3094 put_exec_queue: 3095 if (q) 3096 xe_exec_queue_put(q); 3097 free_objs: 3098 kvfree(bos); 3099 kvfree(ops); 3100 if (args->num_binds > 1) 3101 kvfree(bind_ops); 3102 return err; 3103 } 3104 3105 /** 3106 * xe_vm_lock() - Lock the vm's dma_resv object 3107 * @vm: The struct xe_vm whose lock is to be locked 3108 * @intr: Whether to perform any wait interruptible 3109 * 3110 * Return: 0 on success, -EINTR if @intr is true and the wait for a 3111 * contended lock was interrupted. If @intr is false, the function 3112 * always returns 0. 3113 */ 3114 int xe_vm_lock(struct xe_vm *vm, bool intr) 3115 { 3116 if (intr) 3117 return dma_resv_lock_interruptible(xe_vm_resv(vm), NULL); 3118 3119 return dma_resv_lock(xe_vm_resv(vm), NULL); 3120 } 3121 3122 /** 3123 * xe_vm_unlock() - Unlock the vm's dma_resv object 3124 * @vm: The struct xe_vm whose lock is to be released. 3125 * 3126 * Unlock a buffer object lock that was locked by xe_vm_lock(). 3127 */ 3128 void xe_vm_unlock(struct xe_vm *vm) 3129 { 3130 dma_resv_unlock(xe_vm_resv(vm)); 3131 } 3132 3133 /** 3134 * xe_vm_invalidate_vma - invalidate GPU mappings for VMA without a lock 3135 * @vma: VMA to invalidate 3136 * 3137 * Walks a list of page tables leaves which it memset the entries owned by this 3138 * VMA to zero, invalidates the TLBs, and block until TLBs invalidation is 3139 * complete. 3140 * 3141 * Returns 0 for success, negative error code otherwise. 3142 */ 3143 int xe_vm_invalidate_vma(struct xe_vma *vma) 3144 { 3145 struct xe_device *xe = xe_vma_vm(vma)->xe; 3146 struct xe_tile *tile; 3147 u32 tile_needs_invalidate = 0; 3148 int seqno[XE_MAX_TILES_PER_DEVICE]; 3149 u8 id; 3150 int ret; 3151 3152 xe_assert(xe, !xe_vma_is_null(vma)); 3153 trace_xe_vma_invalidate(vma); 3154 3155 vm_dbg(&xe_vma_vm(vma)->xe->drm, 3156 "INVALIDATE: addr=0x%016llx, range=0x%016llx", 3157 xe_vma_start(vma), xe_vma_size(vma)); 3158 3159 /* Check that we don't race with page-table updates */ 3160 if (IS_ENABLED(CONFIG_PROVE_LOCKING)) { 3161 if (xe_vma_is_userptr(vma)) { 3162 WARN_ON_ONCE(!mmu_interval_check_retry 3163 (&to_userptr_vma(vma)->userptr.notifier, 3164 to_userptr_vma(vma)->userptr.notifier_seq)); 3165 WARN_ON_ONCE(!dma_resv_test_signaled(xe_vm_resv(xe_vma_vm(vma)), 3166 DMA_RESV_USAGE_BOOKKEEP)); 3167 3168 } else { 3169 xe_bo_assert_held(xe_vma_bo(vma)); 3170 } 3171 } 3172 3173 for_each_tile(tile, xe, id) { 3174 if (xe_pt_zap_ptes(tile, vma)) { 3175 tile_needs_invalidate |= BIT(id); 3176 xe_device_wmb(xe); 3177 /* 3178 * FIXME: We potentially need to invalidate multiple 3179 * GTs within the tile 3180 */ 3181 seqno[id] = xe_gt_tlb_invalidation_vma(tile->primary_gt, NULL, vma); 3182 if (seqno[id] < 0) 3183 return seqno[id]; 3184 } 3185 } 3186 3187 for_each_tile(tile, xe, id) { 3188 if (tile_needs_invalidate & BIT(id)) { 3189 ret = xe_gt_tlb_invalidation_wait(tile->primary_gt, seqno[id]); 3190 if (ret < 0) 3191 return ret; 3192 } 3193 } 3194 3195 vma->tile_invalidated = vma->tile_mask; 3196 3197 return 0; 3198 } 3199 3200 int xe_analyze_vm(struct drm_printer *p, struct xe_vm *vm, int gt_id) 3201 { 3202 struct drm_gpuva *gpuva; 3203 bool is_vram; 3204 uint64_t addr; 3205 3206 if (!down_read_trylock(&vm->lock)) { 3207 drm_printf(p, " Failed to acquire VM lock to dump capture"); 3208 return 0; 3209 } 3210 if (vm->pt_root[gt_id]) { 3211 addr = xe_bo_addr(vm->pt_root[gt_id]->bo, 0, XE_PAGE_SIZE); 3212 is_vram = xe_bo_is_vram(vm->pt_root[gt_id]->bo); 3213 drm_printf(p, " VM root: A:0x%llx %s\n", addr, 3214 is_vram ? "VRAM" : "SYS"); 3215 } 3216 3217 drm_gpuvm_for_each_va(gpuva, &vm->gpuvm) { 3218 struct xe_vma *vma = gpuva_to_vma(gpuva); 3219 bool is_userptr = xe_vma_is_userptr(vma); 3220 bool is_null = xe_vma_is_null(vma); 3221 3222 if (is_null) { 3223 addr = 0; 3224 } else if (is_userptr) { 3225 struct sg_table *sg = to_userptr_vma(vma)->userptr.sg; 3226 struct xe_res_cursor cur; 3227 3228 if (sg) { 3229 xe_res_first_sg(sg, 0, XE_PAGE_SIZE, &cur); 3230 addr = xe_res_dma(&cur); 3231 } else { 3232 addr = 0; 3233 } 3234 } else { 3235 addr = __xe_bo_addr(xe_vma_bo(vma), 0, XE_PAGE_SIZE); 3236 is_vram = xe_bo_is_vram(xe_vma_bo(vma)); 3237 } 3238 drm_printf(p, " [%016llx-%016llx] S:0x%016llx A:%016llx %s\n", 3239 xe_vma_start(vma), xe_vma_end(vma) - 1, 3240 xe_vma_size(vma), 3241 addr, is_null ? "NULL" : is_userptr ? "USR" : 3242 is_vram ? "VRAM" : "SYS"); 3243 } 3244 up_read(&vm->lock); 3245 3246 return 0; 3247 } 3248 3249 struct xe_vm_snapshot { 3250 unsigned long num_snaps; 3251 struct { 3252 u64 ofs, bo_ofs; 3253 unsigned long len; 3254 struct xe_bo *bo; 3255 void *data; 3256 struct mm_struct *mm; 3257 } snap[]; 3258 }; 3259 3260 struct xe_vm_snapshot *xe_vm_snapshot_capture(struct xe_vm *vm) 3261 { 3262 unsigned long num_snaps = 0, i; 3263 struct xe_vm_snapshot *snap = NULL; 3264 struct drm_gpuva *gpuva; 3265 3266 if (!vm) 3267 return NULL; 3268 3269 mutex_lock(&vm->snap_mutex); 3270 drm_gpuvm_for_each_va(gpuva, &vm->gpuvm) { 3271 if (gpuva->flags & XE_VMA_DUMPABLE) 3272 num_snaps++; 3273 } 3274 3275 if (num_snaps) 3276 snap = kvzalloc(offsetof(struct xe_vm_snapshot, snap[num_snaps]), GFP_NOWAIT); 3277 if (!snap) { 3278 snap = num_snaps ? ERR_PTR(-ENOMEM) : ERR_PTR(-ENODEV); 3279 goto out_unlock; 3280 } 3281 3282 snap->num_snaps = num_snaps; 3283 i = 0; 3284 drm_gpuvm_for_each_va(gpuva, &vm->gpuvm) { 3285 struct xe_vma *vma = gpuva_to_vma(gpuva); 3286 struct xe_bo *bo = vma->gpuva.gem.obj ? 3287 gem_to_xe_bo(vma->gpuva.gem.obj) : NULL; 3288 3289 if (!(gpuva->flags & XE_VMA_DUMPABLE)) 3290 continue; 3291 3292 snap->snap[i].ofs = xe_vma_start(vma); 3293 snap->snap[i].len = xe_vma_size(vma); 3294 if (bo) { 3295 snap->snap[i].bo = xe_bo_get(bo); 3296 snap->snap[i].bo_ofs = xe_vma_bo_offset(vma); 3297 } else if (xe_vma_is_userptr(vma)) { 3298 struct mm_struct *mm = 3299 to_userptr_vma(vma)->userptr.notifier.mm; 3300 3301 if (mmget_not_zero(mm)) 3302 snap->snap[i].mm = mm; 3303 else 3304 snap->snap[i].data = ERR_PTR(-EFAULT); 3305 3306 snap->snap[i].bo_ofs = xe_vma_userptr(vma); 3307 } else { 3308 snap->snap[i].data = ERR_PTR(-ENOENT); 3309 } 3310 i++; 3311 } 3312 3313 out_unlock: 3314 mutex_unlock(&vm->snap_mutex); 3315 return snap; 3316 } 3317 3318 void xe_vm_snapshot_capture_delayed(struct xe_vm_snapshot *snap) 3319 { 3320 if (IS_ERR_OR_NULL(snap)) 3321 return; 3322 3323 for (int i = 0; i < snap->num_snaps; i++) { 3324 struct xe_bo *bo = snap->snap[i].bo; 3325 struct iosys_map src; 3326 int err; 3327 3328 if (IS_ERR(snap->snap[i].data)) 3329 continue; 3330 3331 snap->snap[i].data = kvmalloc(snap->snap[i].len, GFP_USER); 3332 if (!snap->snap[i].data) { 3333 snap->snap[i].data = ERR_PTR(-ENOMEM); 3334 goto cleanup_bo; 3335 } 3336 3337 if (bo) { 3338 dma_resv_lock(bo->ttm.base.resv, NULL); 3339 err = ttm_bo_vmap(&bo->ttm, &src); 3340 if (!err) { 3341 xe_map_memcpy_from(xe_bo_device(bo), 3342 snap->snap[i].data, 3343 &src, snap->snap[i].bo_ofs, 3344 snap->snap[i].len); 3345 ttm_bo_vunmap(&bo->ttm, &src); 3346 } 3347 dma_resv_unlock(bo->ttm.base.resv); 3348 } else { 3349 void __user *userptr = (void __user *)(size_t)snap->snap[i].bo_ofs; 3350 3351 kthread_use_mm(snap->snap[i].mm); 3352 if (!copy_from_user(snap->snap[i].data, userptr, snap->snap[i].len)) 3353 err = 0; 3354 else 3355 err = -EFAULT; 3356 kthread_unuse_mm(snap->snap[i].mm); 3357 3358 mmput(snap->snap[i].mm); 3359 snap->snap[i].mm = NULL; 3360 } 3361 3362 if (err) { 3363 kvfree(snap->snap[i].data); 3364 snap->snap[i].data = ERR_PTR(err); 3365 } 3366 3367 cleanup_bo: 3368 xe_bo_put(bo); 3369 snap->snap[i].bo = NULL; 3370 } 3371 } 3372 3373 void xe_vm_snapshot_print(struct xe_vm_snapshot *snap, struct drm_printer *p) 3374 { 3375 unsigned long i, j; 3376 3377 if (IS_ERR_OR_NULL(snap)) { 3378 drm_printf(p, "[0].error: %li\n", PTR_ERR(snap)); 3379 return; 3380 } 3381 3382 for (i = 0; i < snap->num_snaps; i++) { 3383 drm_printf(p, "[%llx].length: 0x%lx\n", snap->snap[i].ofs, snap->snap[i].len); 3384 3385 if (IS_ERR(snap->snap[i].data)) { 3386 drm_printf(p, "[%llx].error: %li\n", snap->snap[i].ofs, 3387 PTR_ERR(snap->snap[i].data)); 3388 continue; 3389 } 3390 3391 drm_printf(p, "[%llx].data: ", snap->snap[i].ofs); 3392 3393 for (j = 0; j < snap->snap[i].len; j += sizeof(u32)) { 3394 u32 *val = snap->snap[i].data + j; 3395 char dumped[ASCII85_BUFSZ]; 3396 3397 drm_puts(p, ascii85_encode(*val, dumped)); 3398 } 3399 3400 drm_puts(p, "\n"); 3401 } 3402 } 3403 3404 void xe_vm_snapshot_free(struct xe_vm_snapshot *snap) 3405 { 3406 unsigned long i; 3407 3408 if (IS_ERR_OR_NULL(snap)) 3409 return; 3410 3411 for (i = 0; i < snap->num_snaps; i++) { 3412 if (!IS_ERR(snap->snap[i].data)) 3413 kvfree(snap->snap[i].data); 3414 xe_bo_put(snap->snap[i].bo); 3415 if (snap->snap[i].mm) 3416 mmput(snap->snap[i].mm); 3417 } 3418 kvfree(snap); 3419 } 3420