1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021 Intel Corporation 4 */ 5 6 #include "xe_pci.h" 7 8 #include <kunit/static_stub.h> 9 #include <linux/device/driver.h> 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/pm_runtime.h> 13 14 #include <drm/drm_color_mgmt.h> 15 #include <drm/drm_drv.h> 16 #include <drm/intel/pciids.h> 17 18 #include "display/xe_display.h" 19 #include "regs/xe_gt_regs.h" 20 #include "xe_device.h" 21 #include "xe_drv.h" 22 #include "xe_gt.h" 23 #include "xe_gt_sriov_vf.h" 24 #include "xe_guc.h" 25 #include "xe_macros.h" 26 #include "xe_mmio.h" 27 #include "xe_module.h" 28 #include "xe_pci_sriov.h" 29 #include "xe_pci_types.h" 30 #include "xe_pm.h" 31 #include "xe_sriov.h" 32 #include "xe_step.h" 33 #include "xe_survivability_mode.h" 34 #include "xe_tile.h" 35 36 enum toggle_d3cold { 37 D3COLD_DISABLE, 38 D3COLD_ENABLE, 39 }; 40 41 __diag_push(); 42 __diag_ignore_all("-Woverride-init", "Allow field overrides in table"); 43 44 #define PLATFORM(x) \ 45 .platform = XE_##x, \ 46 .platform_name = #x 47 48 #define NOP(x) x 49 50 static const struct xe_graphics_desc graphics_xelp = { 51 .hw_engine_mask = BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0), 52 53 .va_bits = 48, 54 .vm_max_level = 3, 55 }; 56 57 #define XE_HP_FEATURES \ 58 .has_range_tlb_invalidation = true, \ 59 .va_bits = 48, \ 60 .vm_max_level = 3 61 62 static const struct xe_graphics_desc graphics_xehpg = { 63 .hw_engine_mask = 64 BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) | 65 BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) | 66 BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3), 67 68 XE_HP_FEATURES, 69 .vram_flags = XE_VRAM_FLAGS_NEED64K, 70 71 .has_flat_ccs = 1, 72 }; 73 74 static const struct xe_graphics_desc graphics_xehpc = { 75 .hw_engine_mask = 76 BIT(XE_HW_ENGINE_BCS0) | BIT(XE_HW_ENGINE_BCS1) | 77 BIT(XE_HW_ENGINE_BCS2) | BIT(XE_HW_ENGINE_BCS3) | 78 BIT(XE_HW_ENGINE_BCS4) | BIT(XE_HW_ENGINE_BCS5) | 79 BIT(XE_HW_ENGINE_BCS6) | BIT(XE_HW_ENGINE_BCS7) | 80 BIT(XE_HW_ENGINE_BCS8) | 81 BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) | 82 BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3), 83 84 XE_HP_FEATURES, 85 .va_bits = 57, 86 .vm_max_level = 4, 87 .vram_flags = XE_VRAM_FLAGS_NEED64K, 88 89 .has_asid = 1, 90 .has_atomic_enable_pte_bit = 1, 91 .has_usm = 1, 92 }; 93 94 static const struct xe_graphics_desc graphics_xelpg = { 95 .hw_engine_mask = 96 BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) | 97 BIT(XE_HW_ENGINE_CCS0), 98 99 XE_HP_FEATURES, 100 }; 101 102 #define XE2_GFX_FEATURES \ 103 .has_asid = 1, \ 104 .has_atomic_enable_pte_bit = 1, \ 105 .has_flat_ccs = 1, \ 106 .has_range_tlb_invalidation = 1, \ 107 .has_usm = 1, \ 108 .has_64bit_timestamp = 1, \ 109 .va_bits = 48, \ 110 .vm_max_level = 4, \ 111 .hw_engine_mask = \ 112 BIT(XE_HW_ENGINE_RCS0) | \ 113 BIT(XE_HW_ENGINE_BCS8) | BIT(XE_HW_ENGINE_BCS0) | \ 114 GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0) 115 116 static const struct xe_graphics_desc graphics_xe2 = { 117 XE2_GFX_FEATURES, 118 }; 119 120 static const struct xe_media_desc media_xem = { 121 .hw_engine_mask = 122 GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) | 123 GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0), 124 }; 125 126 static const struct xe_media_desc media_xelpmp = { 127 .hw_engine_mask = 128 GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) | 129 GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0) | 130 BIT(XE_HW_ENGINE_GSCCS0) 131 }; 132 133 /* Pre-GMDID Graphics IPs */ 134 static const struct xe_ip graphics_ip_xelp = { 1200, "Xe_LP", &graphics_xelp }; 135 static const struct xe_ip graphics_ip_xelpp = { 1210, "Xe_LP+", &graphics_xelp }; 136 static const struct xe_ip graphics_ip_xehpg = { 1255, "Xe_HPG", &graphics_xehpg }; 137 static const struct xe_ip graphics_ip_xehpc = { 1260, "Xe_HPC", &graphics_xehpc }; 138 139 /* GMDID-based Graphics IPs */ 140 static const struct xe_ip graphics_ips[] = { 141 { 1270, "Xe_LPG", &graphics_xelpg }, 142 { 1271, "Xe_LPG", &graphics_xelpg }, 143 { 1274, "Xe_LPG+", &graphics_xelpg }, 144 { 2001, "Xe2_HPG", &graphics_xe2 }, 145 { 2002, "Xe2_HPG", &graphics_xe2 }, 146 { 2004, "Xe2_LPG", &graphics_xe2 }, 147 { 3000, "Xe3_LPG", &graphics_xe2 }, 148 { 3001, "Xe3_LPG", &graphics_xe2 }, 149 { 3003, "Xe3_LPG", &graphics_xe2 }, 150 }; 151 152 /* Pre-GMDID Media IPs */ 153 static const struct xe_ip media_ip_xem = { 1200, "Xe_M", &media_xem }; 154 static const struct xe_ip media_ip_xehpm = { 1255, "Xe_HPM", &media_xem }; 155 156 /* GMDID-based Media IPs */ 157 static const struct xe_ip media_ips[] = { 158 { 1300, "Xe_LPM+", &media_xelpmp }, 159 { 1301, "Xe2_HPM", &media_xelpmp }, 160 { 2000, "Xe2_LPM", &media_xelpmp }, 161 { 3000, "Xe3_LPM", &media_xelpmp }, 162 { 3002, "Xe3_LPM", &media_xelpmp }, 163 }; 164 165 static const struct xe_device_desc tgl_desc = { 166 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 167 .pre_gmdid_media_ip = &media_ip_xem, 168 PLATFORM(TIGERLAKE), 169 .dma_mask_size = 39, 170 .has_display = true, 171 .has_llc = true, 172 .max_gt_per_tile = 1, 173 .require_force_probe = true, 174 }; 175 176 static const struct xe_device_desc rkl_desc = { 177 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 178 .pre_gmdid_media_ip = &media_ip_xem, 179 PLATFORM(ROCKETLAKE), 180 .dma_mask_size = 39, 181 .has_display = true, 182 .has_llc = true, 183 .max_gt_per_tile = 1, 184 .require_force_probe = true, 185 }; 186 187 static const u16 adls_rpls_ids[] = { INTEL_RPLS_IDS(NOP), 0 }; 188 189 static const struct xe_device_desc adl_s_desc = { 190 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 191 .pre_gmdid_media_ip = &media_ip_xem, 192 PLATFORM(ALDERLAKE_S), 193 .dma_mask_size = 39, 194 .has_display = true, 195 .has_llc = true, 196 .max_gt_per_tile = 1, 197 .require_force_probe = true, 198 .subplatforms = (const struct xe_subplatform_desc[]) { 199 { XE_SUBPLATFORM_ALDERLAKE_S_RPLS, "RPLS", adls_rpls_ids }, 200 {}, 201 }, 202 }; 203 204 static const u16 adlp_rplu_ids[] = { INTEL_RPLU_IDS(NOP), 0 }; 205 206 static const struct xe_device_desc adl_p_desc = { 207 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 208 .pre_gmdid_media_ip = &media_ip_xem, 209 PLATFORM(ALDERLAKE_P), 210 .dma_mask_size = 39, 211 .has_display = true, 212 .has_llc = true, 213 .max_gt_per_tile = 1, 214 .require_force_probe = true, 215 .subplatforms = (const struct xe_subplatform_desc[]) { 216 { XE_SUBPLATFORM_ALDERLAKE_P_RPLU, "RPLU", adlp_rplu_ids }, 217 {}, 218 }, 219 }; 220 221 static const struct xe_device_desc adl_n_desc = { 222 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 223 .pre_gmdid_media_ip = &media_ip_xem, 224 PLATFORM(ALDERLAKE_N), 225 .dma_mask_size = 39, 226 .has_display = true, 227 .has_llc = true, 228 .max_gt_per_tile = 1, 229 .require_force_probe = true, 230 }; 231 232 #define DGFX_FEATURES \ 233 .is_dgfx = 1 234 235 static const struct xe_device_desc dg1_desc = { 236 .pre_gmdid_graphics_ip = &graphics_ip_xelpp, 237 .pre_gmdid_media_ip = &media_ip_xem, 238 DGFX_FEATURES, 239 PLATFORM(DG1), 240 .dma_mask_size = 39, 241 .has_display = true, 242 .has_gsc_nvm = 1, 243 .has_heci_gscfi = 1, 244 .max_gt_per_tile = 1, 245 .require_force_probe = true, 246 }; 247 248 static const u16 dg2_g10_ids[] = { INTEL_DG2_G10_IDS(NOP), INTEL_ATS_M150_IDS(NOP), 0 }; 249 static const u16 dg2_g11_ids[] = { INTEL_DG2_G11_IDS(NOP), INTEL_ATS_M75_IDS(NOP), 0 }; 250 static const u16 dg2_g12_ids[] = { INTEL_DG2_G12_IDS(NOP), 0 }; 251 252 #define DG2_FEATURES \ 253 DGFX_FEATURES, \ 254 PLATFORM(DG2), \ 255 .has_gsc_nvm = 1, \ 256 .has_heci_gscfi = 1, \ 257 .subplatforms = (const struct xe_subplatform_desc[]) { \ 258 { XE_SUBPLATFORM_DG2_G10, "G10", dg2_g10_ids }, \ 259 { XE_SUBPLATFORM_DG2_G11, "G11", dg2_g11_ids }, \ 260 { XE_SUBPLATFORM_DG2_G12, "G12", dg2_g12_ids }, \ 261 { } \ 262 } 263 264 static const struct xe_device_desc ats_m_desc = { 265 .pre_gmdid_graphics_ip = &graphics_ip_xehpg, 266 .pre_gmdid_media_ip = &media_ip_xehpm, 267 .dma_mask_size = 46, 268 .max_gt_per_tile = 1, 269 .require_force_probe = true, 270 271 DG2_FEATURES, 272 .has_display = false, 273 }; 274 275 static const struct xe_device_desc dg2_desc = { 276 .pre_gmdid_graphics_ip = &graphics_ip_xehpg, 277 .pre_gmdid_media_ip = &media_ip_xehpm, 278 .dma_mask_size = 46, 279 .max_gt_per_tile = 1, 280 .require_force_probe = true, 281 282 DG2_FEATURES, 283 .has_display = true, 284 .has_fan_control = true, 285 .has_mbx_power_limits = false, 286 }; 287 288 static const __maybe_unused struct xe_device_desc pvc_desc = { 289 .pre_gmdid_graphics_ip = &graphics_ip_xehpc, 290 DGFX_FEATURES, 291 PLATFORM(PVC), 292 .dma_mask_size = 52, 293 .has_display = false, 294 .has_gsc_nvm = 1, 295 .has_heci_gscfi = 1, 296 .max_gt_per_tile = 1, 297 .max_remote_tiles = 1, 298 .require_force_probe = true, 299 .has_mbx_power_limits = false, 300 }; 301 302 static const struct xe_device_desc mtl_desc = { 303 /* .graphics and .media determined via GMD_ID */ 304 .require_force_probe = true, 305 PLATFORM(METEORLAKE), 306 .dma_mask_size = 46, 307 .has_display = true, 308 .has_pxp = true, 309 .max_gt_per_tile = 2, 310 }; 311 312 static const struct xe_device_desc lnl_desc = { 313 PLATFORM(LUNARLAKE), 314 .dma_mask_size = 46, 315 .has_display = true, 316 .has_pxp = true, 317 .max_gt_per_tile = 2, 318 .needs_scratch = true, 319 }; 320 321 static const struct xe_device_desc bmg_desc = { 322 DGFX_FEATURES, 323 PLATFORM(BATTLEMAGE), 324 .dma_mask_size = 46, 325 .has_display = true, 326 .has_fan_control = true, 327 .has_mbx_power_limits = true, 328 .has_gsc_nvm = 1, 329 .has_heci_cscfi = 1, 330 .max_gt_per_tile = 2, 331 .needs_scratch = true, 332 }; 333 334 static const struct xe_device_desc ptl_desc = { 335 PLATFORM(PANTHERLAKE), 336 .dma_mask_size = 46, 337 .has_display = true, 338 .has_sriov = true, 339 .max_gt_per_tile = 2, 340 .needs_scratch = true, 341 }; 342 343 #undef PLATFORM 344 __diag_pop(); 345 346 /* 347 * Make sure any device matches here are from most specific to most 348 * general. For example, since the Quanta match is based on the subsystem 349 * and subvendor IDs, we need it to come before the more general IVB 350 * PCI ID matches, otherwise we'll use the wrong info struct above. 351 */ 352 static const struct pci_device_id pciidlist[] = { 353 INTEL_TGL_IDS(INTEL_VGA_DEVICE, &tgl_desc), 354 INTEL_RKL_IDS(INTEL_VGA_DEVICE, &rkl_desc), 355 INTEL_ADLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc), 356 INTEL_ADLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc), 357 INTEL_ADLN_IDS(INTEL_VGA_DEVICE, &adl_n_desc), 358 INTEL_RPLU_IDS(INTEL_VGA_DEVICE, &adl_p_desc), 359 INTEL_RPLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc), 360 INTEL_RPLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc), 361 INTEL_DG1_IDS(INTEL_VGA_DEVICE, &dg1_desc), 362 INTEL_ATS_M_IDS(INTEL_VGA_DEVICE, &ats_m_desc), 363 INTEL_ARL_IDS(INTEL_VGA_DEVICE, &mtl_desc), 364 INTEL_DG2_IDS(INTEL_VGA_DEVICE, &dg2_desc), 365 INTEL_MTL_IDS(INTEL_VGA_DEVICE, &mtl_desc), 366 INTEL_LNL_IDS(INTEL_VGA_DEVICE, &lnl_desc), 367 INTEL_BMG_IDS(INTEL_VGA_DEVICE, &bmg_desc), 368 INTEL_PTL_IDS(INTEL_VGA_DEVICE, &ptl_desc), 369 { } 370 }; 371 MODULE_DEVICE_TABLE(pci, pciidlist); 372 373 /* is device_id present in comma separated list of ids */ 374 static bool device_id_in_list(u16 device_id, const char *devices, bool negative) 375 { 376 char *s, *p, *tok; 377 bool ret; 378 379 if (!devices || !*devices) 380 return false; 381 382 /* match everything */ 383 if (negative && strcmp(devices, "!*") == 0) 384 return true; 385 if (!negative && strcmp(devices, "*") == 0) 386 return true; 387 388 s = kstrdup(devices, GFP_KERNEL); 389 if (!s) 390 return false; 391 392 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) { 393 u16 val; 394 395 if (negative && tok[0] == '!') 396 tok++; 397 else if ((negative && tok[0] != '!') || 398 (!negative && tok[0] == '!')) 399 continue; 400 401 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) { 402 ret = true; 403 break; 404 } 405 } 406 407 kfree(s); 408 409 return ret; 410 } 411 412 static bool id_forced(u16 device_id) 413 { 414 return device_id_in_list(device_id, xe_modparam.force_probe, false); 415 } 416 417 static bool id_blocked(u16 device_id) 418 { 419 return device_id_in_list(device_id, xe_modparam.force_probe, true); 420 } 421 422 static const struct xe_subplatform_desc * 423 find_subplatform(const struct xe_device *xe, const struct xe_device_desc *desc) 424 { 425 const struct xe_subplatform_desc *sp; 426 const u16 *id; 427 428 for (sp = desc->subplatforms; sp && sp->subplatform; sp++) 429 for (id = sp->pciidlist; *id; id++) 430 if (*id == xe->info.devid) 431 return sp; 432 433 return NULL; 434 } 435 436 enum xe_gmdid_type { 437 GMDID_GRAPHICS, 438 GMDID_MEDIA 439 }; 440 441 static void read_gmdid(struct xe_device *xe, enum xe_gmdid_type type, u32 *ver, u32 *revid) 442 { 443 struct xe_mmio *mmio = xe_root_tile_mmio(xe); 444 struct xe_reg gmdid_reg = GMD_ID; 445 u32 val; 446 447 KUNIT_STATIC_STUB_REDIRECT(read_gmdid, xe, type, ver, revid); 448 449 if (IS_SRIOV_VF(xe)) { 450 struct xe_gt *gt = xe_root_mmio_gt(xe); 451 452 /* 453 * To get the value of the GMDID register, VFs must obtain it 454 * from the GuC using MMIO communication. 455 * 456 * Note that at this point the xe_gt is not fully uninitialized 457 * and only basic access to MMIO registers is possible. To use 458 * our existing GuC communication functions we must perform at 459 * least basic xe_gt and xe_guc initialization. 460 * 461 * Since to obtain the value of GMDID_MEDIA we need to use the 462 * media GuC, temporarily tweak the gt type. 463 */ 464 xe_gt_assert(gt, gt->info.type == XE_GT_TYPE_UNINITIALIZED); 465 466 if (type == GMDID_MEDIA) { 467 gt->info.id = 1; 468 gt->info.type = XE_GT_TYPE_MEDIA; 469 } else { 470 gt->info.id = 0; 471 gt->info.type = XE_GT_TYPE_MAIN; 472 } 473 474 xe_gt_mmio_init(gt); 475 xe_guc_comm_init_early(>->uc.guc); 476 477 /* Don't bother with GMDID if failed to negotiate the GuC ABI */ 478 val = xe_gt_sriov_vf_bootstrap(gt) ? 0 : xe_gt_sriov_vf_gmdid(gt); 479 480 /* 481 * Only undo xe_gt.info here, the remaining changes made above 482 * will be overwritten as part of the regular initialization. 483 */ 484 gt->info.id = 0; 485 gt->info.type = XE_GT_TYPE_UNINITIALIZED; 486 } else { 487 /* 488 * GMD_ID is a GT register, but at this point in the driver 489 * init we haven't fully initialized the GT yet so we need to 490 * read the register with the tile's MMIO accessor. That means 491 * we need to apply the GSI offset manually since it won't get 492 * automatically added as it would if we were using a GT mmio 493 * accessor. 494 */ 495 if (type == GMDID_MEDIA) 496 gmdid_reg.addr += MEDIA_GT_GSI_OFFSET; 497 498 val = xe_mmio_read32(mmio, gmdid_reg); 499 } 500 501 *ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val) * 100 + REG_FIELD_GET(GMD_ID_RELEASE_MASK, val); 502 *revid = REG_FIELD_GET(GMD_ID_REVID, val); 503 } 504 505 /* 506 * Read IP version from hardware and select graphics/media IP descriptors 507 * based on the result. 508 */ 509 static void handle_gmdid(struct xe_device *xe, 510 const struct xe_ip **graphics_ip, 511 const struct xe_ip **media_ip, 512 u32 *graphics_revid, 513 u32 *media_revid) 514 { 515 u32 ver; 516 517 *graphics_ip = NULL; 518 *media_ip = NULL; 519 520 read_gmdid(xe, GMDID_GRAPHICS, &ver, graphics_revid); 521 522 for (int i = 0; i < ARRAY_SIZE(graphics_ips); i++) { 523 if (ver == graphics_ips[i].verx100) { 524 *graphics_ip = &graphics_ips[i]; 525 526 break; 527 } 528 } 529 530 if (!*graphics_ip) { 531 drm_err(&xe->drm, "Hardware reports unknown graphics version %u.%02u\n", 532 ver / 100, ver % 100); 533 } 534 535 read_gmdid(xe, GMDID_MEDIA, &ver, media_revid); 536 /* Media may legitimately be fused off / not present */ 537 if (ver == 0) 538 return; 539 540 for (int i = 0; i < ARRAY_SIZE(media_ips); i++) { 541 if (ver == media_ips[i].verx100) { 542 *media_ip = &media_ips[i]; 543 544 break; 545 } 546 } 547 548 if (!*media_ip) { 549 drm_err(&xe->drm, "Hardware reports unknown media version %u.%02u\n", 550 ver / 100, ver % 100); 551 } 552 } 553 554 /* 555 * Initialize device info content that only depends on static driver_data 556 * passed to the driver at probe time from PCI ID table. 557 */ 558 static int xe_info_init_early(struct xe_device *xe, 559 const struct xe_device_desc *desc, 560 const struct xe_subplatform_desc *subplatform_desc) 561 { 562 int err; 563 564 xe->info.platform_name = desc->platform_name; 565 xe->info.platform = desc->platform; 566 xe->info.subplatform = subplatform_desc ? 567 subplatform_desc->subplatform : XE_SUBPLATFORM_NONE; 568 569 xe->info.dma_mask_size = desc->dma_mask_size; 570 xe->info.is_dgfx = desc->is_dgfx; 571 xe->info.has_fan_control = desc->has_fan_control; 572 xe->info.has_mbx_power_limits = desc->has_mbx_power_limits; 573 xe->info.has_gsc_nvm = desc->has_gsc_nvm; 574 xe->info.has_heci_gscfi = desc->has_heci_gscfi; 575 xe->info.has_heci_cscfi = desc->has_heci_cscfi; 576 xe->info.has_llc = desc->has_llc; 577 xe->info.has_pxp = desc->has_pxp; 578 xe->info.has_sriov = desc->has_sriov; 579 xe->info.skip_guc_pc = desc->skip_guc_pc; 580 xe->info.skip_mtcfg = desc->skip_mtcfg; 581 xe->info.skip_pcode = desc->skip_pcode; 582 xe->info.needs_scratch = desc->needs_scratch; 583 584 xe->info.probe_display = IS_ENABLED(CONFIG_DRM_XE_DISPLAY) && 585 xe_modparam.probe_display && 586 desc->has_display; 587 588 xe_assert(xe, desc->max_gt_per_tile > 0); 589 xe_assert(xe, desc->max_gt_per_tile <= XE_MAX_GT_PER_TILE); 590 xe->info.max_gt_per_tile = desc->max_gt_per_tile; 591 xe->info.tile_count = 1 + desc->max_remote_tiles; 592 593 err = xe_tile_init_early(xe_device_get_root_tile(xe), xe, 0); 594 if (err) 595 return err; 596 597 return 0; 598 } 599 600 /* 601 * Initialize device info content that does require knowledge about 602 * graphics / media IP version. 603 * Make sure that GT / tile structures allocated by the driver match the data 604 * present in device info. 605 */ 606 static int xe_info_init(struct xe_device *xe, 607 const struct xe_device_desc *desc) 608 { 609 u32 graphics_gmdid_revid = 0, media_gmdid_revid = 0; 610 const struct xe_ip *graphics_ip; 611 const struct xe_ip *media_ip; 612 const struct xe_graphics_desc *graphics_desc; 613 const struct xe_media_desc *media_desc; 614 struct xe_tile *tile; 615 struct xe_gt *gt; 616 u8 id; 617 618 /* 619 * If this platform supports GMD_ID, we'll detect the proper IP 620 * descriptor to use from hardware registers. 621 * desc->pre_gmdid_graphics_ip will only ever be set at this point for 622 * platforms before GMD_ID. In that case the IP descriptions and 623 * versions are simply derived from that. 624 */ 625 if (desc->pre_gmdid_graphics_ip) { 626 graphics_ip = desc->pre_gmdid_graphics_ip; 627 media_ip = desc->pre_gmdid_media_ip; 628 xe->info.step = xe_step_pre_gmdid_get(xe); 629 } else { 630 xe_assert(xe, !desc->pre_gmdid_media_ip); 631 handle_gmdid(xe, &graphics_ip, &media_ip, 632 &graphics_gmdid_revid, &media_gmdid_revid); 633 xe->info.step = xe_step_gmdid_get(xe, 634 graphics_gmdid_revid, 635 media_gmdid_revid); 636 } 637 638 /* 639 * If we couldn't detect the graphics IP, that's considered a fatal 640 * error and we should abort driver load. Failing to detect media 641 * IP is non-fatal; we'll just proceed without enabling media support. 642 */ 643 if (!graphics_ip) 644 return -ENODEV; 645 646 xe->info.graphics_verx100 = graphics_ip->verx100; 647 xe->info.graphics_name = graphics_ip->name; 648 graphics_desc = graphics_ip->desc; 649 650 if (media_ip) { 651 xe->info.media_verx100 = media_ip->verx100; 652 xe->info.media_name = media_ip->name; 653 media_desc = media_ip->desc; 654 } else { 655 xe->info.media_name = "none"; 656 media_desc = NULL; 657 } 658 659 xe->info.vram_flags = graphics_desc->vram_flags; 660 xe->info.va_bits = graphics_desc->va_bits; 661 xe->info.vm_max_level = graphics_desc->vm_max_level; 662 xe->info.has_asid = graphics_desc->has_asid; 663 xe->info.has_atomic_enable_pte_bit = graphics_desc->has_atomic_enable_pte_bit; 664 if (xe->info.platform != XE_PVC) 665 xe->info.has_device_atomics_on_smem = 1; 666 667 /* Runtime detection may change this later */ 668 xe->info.has_flat_ccs = graphics_desc->has_flat_ccs; 669 670 xe->info.has_range_tlb_invalidation = graphics_desc->has_range_tlb_invalidation; 671 xe->info.has_usm = graphics_desc->has_usm; 672 xe->info.has_64bit_timestamp = graphics_desc->has_64bit_timestamp; 673 674 for_each_remote_tile(tile, xe, id) { 675 int err; 676 677 err = xe_tile_init_early(tile, xe, id); 678 if (err) 679 return err; 680 } 681 682 /* 683 * All platforms have at least one primary GT. Any platform with media 684 * version 13 or higher has an additional dedicated media GT. And 685 * depending on the graphics IP there may be additional "remote tiles." 686 * All of these together determine the overall GT count. 687 */ 688 for_each_tile(tile, xe, id) { 689 gt = tile->primary_gt; 690 gt->info.type = XE_GT_TYPE_MAIN; 691 gt->info.id = tile->id * xe->info.max_gt_per_tile; 692 gt->info.has_indirect_ring_state = graphics_desc->has_indirect_ring_state; 693 gt->info.engine_mask = graphics_desc->hw_engine_mask; 694 xe->info.gt_count++; 695 696 if (MEDIA_VER(xe) < 13 && media_desc) 697 gt->info.engine_mask |= media_desc->hw_engine_mask; 698 699 if (MEDIA_VER(xe) < 13 || !media_desc) 700 continue; 701 702 /* 703 * Allocate and setup media GT for platforms with standalone 704 * media. 705 */ 706 tile->media_gt = xe_gt_alloc(tile); 707 if (IS_ERR(tile->media_gt)) 708 return PTR_ERR(tile->media_gt); 709 710 gt = tile->media_gt; 711 gt->info.type = XE_GT_TYPE_MEDIA; 712 gt->info.id = tile->id * xe->info.max_gt_per_tile + 1; 713 gt->info.has_indirect_ring_state = media_desc->has_indirect_ring_state; 714 gt->info.engine_mask = media_desc->hw_engine_mask; 715 xe->info.gt_count++; 716 } 717 718 return 0; 719 } 720 721 static void xe_pci_remove(struct pci_dev *pdev) 722 { 723 struct xe_device *xe = pdev_to_xe_device(pdev); 724 725 if (IS_SRIOV_PF(xe)) 726 xe_pci_sriov_configure(pdev, 0); 727 728 if (xe_survivability_mode_is_enabled(xe)) 729 return; 730 731 xe_device_remove(xe); 732 xe_pm_fini(xe); 733 } 734 735 /* 736 * Probe the PCI device, initialize various parts of the driver. 737 * 738 * Fault injection is used to test the error paths of some initialization 739 * functions called either directly from xe_pci_probe() or indirectly for 740 * example through xe_device_probe(). Those functions use the kernel fault 741 * injection capabilities infrastructure, see 742 * Documentation/fault-injection/fault-injection.rst for details. The macro 743 * ALLOW_ERROR_INJECTION() is used to conditionally skip function execution 744 * at runtime and use a provided return value. The first requirement for 745 * error injectable functions is proper handling of the error code by the 746 * caller for recovery, which is always the case here. The second 747 * requirement is that no state is changed before the first error return. 748 * It is not strictly fulfilled for all initialization functions using the 749 * ALLOW_ERROR_INJECTION() macro but this is acceptable because for those 750 * error cases at probe time, the error code is simply propagated up by the 751 * caller. Therefore there is no consequence on those specific callers when 752 * function error injection skips the whole function. 753 */ 754 static int xe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 755 { 756 const struct xe_device_desc *desc = (const void *)ent->driver_data; 757 const struct xe_subplatform_desc *subplatform_desc; 758 struct xe_device *xe; 759 int err; 760 761 if (desc->require_force_probe && !id_forced(pdev->device)) { 762 dev_info(&pdev->dev, 763 "Your graphics device %04x is not officially supported\n" 764 "by xe driver in this kernel version. To force Xe probe,\n" 765 "use xe.force_probe='%04x' and i915.force_probe='!%04x'\n" 766 "module parameters or CONFIG_DRM_XE_FORCE_PROBE='%04x' and\n" 767 "CONFIG_DRM_I915_FORCE_PROBE='!%04x' configuration options.\n", 768 pdev->device, pdev->device, pdev->device, 769 pdev->device, pdev->device); 770 return -ENODEV; 771 } 772 773 if (id_blocked(pdev->device)) { 774 dev_info(&pdev->dev, "Probe blocked for device [%04x:%04x].\n", 775 pdev->vendor, pdev->device); 776 return -ENODEV; 777 } 778 779 if (xe_display_driver_probe_defer(pdev)) 780 return -EPROBE_DEFER; 781 782 err = pcim_enable_device(pdev); 783 if (err) 784 return err; 785 786 xe = xe_device_create(pdev, ent); 787 if (IS_ERR(xe)) 788 return PTR_ERR(xe); 789 790 pci_set_drvdata(pdev, &xe->drm); 791 792 xe_pm_assert_unbounded_bridge(xe); 793 subplatform_desc = find_subplatform(xe, desc); 794 795 pci_set_master(pdev); 796 797 err = xe_info_init_early(xe, desc, subplatform_desc); 798 if (err) 799 return err; 800 801 err = xe_device_probe_early(xe); 802 /* 803 * In Boot Survivability mode, no drm card is exposed and driver 804 * is loaded with bare minimum to allow for firmware to be 805 * flashed through mei. Return success, if survivability mode 806 * is enabled due to pcode failure or configfs being set 807 */ 808 if (xe_survivability_mode_is_enabled(xe)) 809 return 0; 810 811 if (err) 812 return err; 813 814 err = xe_info_init(xe, desc); 815 if (err) 816 return err; 817 818 err = xe_display_probe(xe); 819 if (err) 820 return err; 821 822 drm_dbg(&xe->drm, "%s %s %04x:%04x dgfx:%d gfx:%s (%d.%02d) media:%s (%d.%02d) display:%s dma_m_s:%d tc:%d gscfi:%d cscfi:%d", 823 desc->platform_name, 824 subplatform_desc ? subplatform_desc->name : "", 825 xe->info.devid, xe->info.revid, 826 xe->info.is_dgfx, 827 xe->info.graphics_name, 828 xe->info.graphics_verx100 / 100, 829 xe->info.graphics_verx100 % 100, 830 xe->info.media_name, 831 xe->info.media_verx100 / 100, 832 xe->info.media_verx100 % 100, 833 str_yes_no(xe->info.probe_display), 834 xe->info.dma_mask_size, xe->info.tile_count, 835 xe->info.has_heci_gscfi, xe->info.has_heci_cscfi); 836 837 drm_dbg(&xe->drm, "Stepping = (G:%s, M:%s, B:%s)\n", 838 xe_step_name(xe->info.step.graphics), 839 xe_step_name(xe->info.step.media), 840 xe_step_name(xe->info.step.basedie)); 841 842 drm_dbg(&xe->drm, "SR-IOV support: %s (mode: %s)\n", 843 str_yes_no(xe_device_has_sriov(xe)), 844 xe_sriov_mode_to_string(xe_device_sriov_mode(xe))); 845 846 err = xe_pm_init_early(xe); 847 if (err) 848 return err; 849 850 err = xe_device_probe(xe); 851 if (err) 852 return err; 853 854 err = xe_pm_init(xe); 855 if (err) 856 goto err_driver_cleanup; 857 858 drm_dbg(&xe->drm, "d3cold: capable=%s\n", 859 str_yes_no(xe->d3cold.capable)); 860 861 return 0; 862 863 err_driver_cleanup: 864 xe_pci_remove(pdev); 865 return err; 866 } 867 868 static void xe_pci_shutdown(struct pci_dev *pdev) 869 { 870 xe_device_shutdown(pdev_to_xe_device(pdev)); 871 } 872 873 #ifdef CONFIG_PM_SLEEP 874 static void d3cold_toggle(struct pci_dev *pdev, enum toggle_d3cold toggle) 875 { 876 struct xe_device *xe = pdev_to_xe_device(pdev); 877 struct pci_dev *root_pdev; 878 879 if (!xe->d3cold.capable) 880 return; 881 882 root_pdev = pcie_find_root_port(pdev); 883 if (!root_pdev) 884 return; 885 886 switch (toggle) { 887 case D3COLD_DISABLE: 888 pci_d3cold_disable(root_pdev); 889 break; 890 case D3COLD_ENABLE: 891 pci_d3cold_enable(root_pdev); 892 break; 893 } 894 } 895 896 static int xe_pci_suspend(struct device *dev) 897 { 898 struct pci_dev *pdev = to_pci_dev(dev); 899 struct xe_device *xe = pdev_to_xe_device(pdev); 900 int err; 901 902 if (xe_survivability_mode_is_enabled(xe)) 903 return -EBUSY; 904 905 err = xe_pm_suspend(xe); 906 if (err) 907 return err; 908 909 /* 910 * Enabling D3Cold is needed for S2Idle/S0ix. 911 * It is save to allow here since xe_pm_suspend has evicted 912 * the local memory and the direct complete optimization is disabled. 913 */ 914 d3cold_toggle(pdev, D3COLD_ENABLE); 915 916 pci_save_state(pdev); 917 pci_disable_device(pdev); 918 pci_set_power_state(pdev, PCI_D3cold); 919 920 return 0; 921 } 922 923 static int xe_pci_resume(struct device *dev) 924 { 925 struct pci_dev *pdev = to_pci_dev(dev); 926 int err; 927 928 /* Give back the D3Cold decision to the runtime P M*/ 929 d3cold_toggle(pdev, D3COLD_DISABLE); 930 931 err = pci_set_power_state(pdev, PCI_D0); 932 if (err) 933 return err; 934 935 pci_restore_state(pdev); 936 937 err = pci_enable_device(pdev); 938 if (err) 939 return err; 940 941 pci_set_master(pdev); 942 943 err = xe_pm_resume(pdev_to_xe_device(pdev)); 944 if (err) 945 return err; 946 947 return 0; 948 } 949 950 static int xe_pci_runtime_suspend(struct device *dev) 951 { 952 struct pci_dev *pdev = to_pci_dev(dev); 953 struct xe_device *xe = pdev_to_xe_device(pdev); 954 int err; 955 956 err = xe_pm_runtime_suspend(xe); 957 if (err) 958 return err; 959 960 pci_save_state(pdev); 961 962 if (xe->d3cold.allowed) { 963 d3cold_toggle(pdev, D3COLD_ENABLE); 964 pci_disable_device(pdev); 965 pci_ignore_hotplug(pdev); 966 pci_set_power_state(pdev, PCI_D3cold); 967 } else { 968 d3cold_toggle(pdev, D3COLD_DISABLE); 969 pci_set_power_state(pdev, PCI_D3hot); 970 } 971 972 return 0; 973 } 974 975 static int xe_pci_runtime_resume(struct device *dev) 976 { 977 struct pci_dev *pdev = to_pci_dev(dev); 978 struct xe_device *xe = pdev_to_xe_device(pdev); 979 int err; 980 981 err = pci_set_power_state(pdev, PCI_D0); 982 if (err) 983 return err; 984 985 pci_restore_state(pdev); 986 987 if (xe->d3cold.allowed) { 988 err = pci_enable_device(pdev); 989 if (err) 990 return err; 991 992 pci_set_master(pdev); 993 } 994 995 return xe_pm_runtime_resume(xe); 996 } 997 998 static int xe_pci_runtime_idle(struct device *dev) 999 { 1000 struct pci_dev *pdev = to_pci_dev(dev); 1001 struct xe_device *xe = pdev_to_xe_device(pdev); 1002 1003 xe_pm_d3cold_allowed_toggle(xe); 1004 1005 return 0; 1006 } 1007 1008 static const struct dev_pm_ops xe_pm_ops = { 1009 SET_SYSTEM_SLEEP_PM_OPS(xe_pci_suspend, xe_pci_resume) 1010 SET_RUNTIME_PM_OPS(xe_pci_runtime_suspend, xe_pci_runtime_resume, xe_pci_runtime_idle) 1011 }; 1012 #endif 1013 1014 static struct pci_driver xe_pci_driver = { 1015 .name = DRIVER_NAME, 1016 .id_table = pciidlist, 1017 .probe = xe_pci_probe, 1018 .remove = xe_pci_remove, 1019 .shutdown = xe_pci_shutdown, 1020 .sriov_configure = xe_pci_sriov_configure, 1021 #ifdef CONFIG_PM_SLEEP 1022 .driver.pm = &xe_pm_ops, 1023 #endif 1024 }; 1025 1026 int xe_register_pci_driver(void) 1027 { 1028 return pci_register_driver(&xe_pci_driver); 1029 } 1030 1031 void xe_unregister_pci_driver(void) 1032 { 1033 pci_unregister_driver(&xe_pci_driver); 1034 } 1035 1036 #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST) 1037 #include "tests/xe_pci.c" 1038 #endif 1039