1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021 Intel Corporation 4 */ 5 6 #include "xe_pci.h" 7 8 #include <kunit/static_stub.h> 9 #include <linux/device/driver.h> 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/pm_runtime.h> 13 14 #include <drm/drm_color_mgmt.h> 15 #include <drm/drm_drv.h> 16 #include <drm/intel/pciids.h> 17 18 #include "display/xe_display.h" 19 #include "regs/xe_gt_regs.h" 20 #include "regs/xe_regs.h" 21 #include "xe_configfs.h" 22 #include "xe_device.h" 23 #include "xe_drv.h" 24 #include "xe_gt.h" 25 #include "xe_gt_sriov_vf.h" 26 #include "xe_guc.h" 27 #include "xe_macros.h" 28 #include "xe_mmio.h" 29 #include "xe_module.h" 30 #include "xe_pci_sriov.h" 31 #include "xe_pci_types.h" 32 #include "xe_pm.h" 33 #include "xe_printk.h" 34 #include "xe_sriov.h" 35 #include "xe_step.h" 36 #include "xe_survivability_mode.h" 37 #include "xe_tile.h" 38 39 enum toggle_d3cold { 40 D3COLD_DISABLE, 41 D3COLD_ENABLE, 42 }; 43 44 __diag_push(); 45 __diag_ignore_all("-Woverride-init", "Allow field overrides in table"); 46 47 #define PLATFORM(x) \ 48 .platform = XE_##x, \ 49 .platform_name = #x 50 51 #define NOP(x) x 52 53 static const struct xe_graphics_desc graphics_xelp = { 54 .hw_engine_mask = BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0), 55 }; 56 57 #define XE_HP_FEATURES \ 58 .has_range_tlb_inval = true 59 60 static const struct xe_graphics_desc graphics_xehpg = { 61 .hw_engine_mask = 62 BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) | 63 BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) | 64 BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3), 65 66 XE_HP_FEATURES, 67 }; 68 69 static const struct xe_graphics_desc graphics_xehpc = { 70 .hw_engine_mask = 71 BIT(XE_HW_ENGINE_BCS0) | BIT(XE_HW_ENGINE_BCS1) | 72 BIT(XE_HW_ENGINE_BCS2) | BIT(XE_HW_ENGINE_BCS3) | 73 BIT(XE_HW_ENGINE_BCS4) | BIT(XE_HW_ENGINE_BCS5) | 74 BIT(XE_HW_ENGINE_BCS6) | BIT(XE_HW_ENGINE_BCS7) | 75 BIT(XE_HW_ENGINE_BCS8) | 76 BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) | 77 BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3), 78 79 XE_HP_FEATURES, 80 81 .has_asid = 1, 82 .has_atomic_enable_pte_bit = 1, 83 .has_usm = 1, 84 }; 85 86 static const struct xe_graphics_desc graphics_xelpg = { 87 .hw_engine_mask = 88 BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) | 89 BIT(XE_HW_ENGINE_CCS0), 90 91 XE_HP_FEATURES, 92 }; 93 94 #define XE2_GFX_FEATURES \ 95 .has_asid = 1, \ 96 .has_atomic_enable_pte_bit = 1, \ 97 .has_range_tlb_inval = 1, \ 98 .has_usm = 1, \ 99 .has_64bit_timestamp = 1, \ 100 .hw_engine_mask = \ 101 BIT(XE_HW_ENGINE_RCS0) | \ 102 BIT(XE_HW_ENGINE_BCS8) | BIT(XE_HW_ENGINE_BCS0) | \ 103 GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0) 104 105 static const struct xe_graphics_desc graphics_xe2 = { 106 XE2_GFX_FEATURES, 107 }; 108 109 static const struct xe_graphics_desc graphics_xe3p_xpc = { 110 XE2_GFX_FEATURES, 111 .hw_engine_mask = 112 GENMASK(XE_HW_ENGINE_BCS8, XE_HW_ENGINE_BCS1) | 113 GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0), 114 }; 115 116 static const struct xe_media_desc media_xem = { 117 .hw_engine_mask = 118 GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) | 119 GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0), 120 }; 121 122 static const struct xe_media_desc media_xelpmp = { 123 .hw_engine_mask = 124 GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) | 125 GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0) | 126 BIT(XE_HW_ENGINE_GSCCS0) 127 }; 128 129 /* Pre-GMDID Graphics IPs */ 130 static const struct xe_ip graphics_ip_xelp = { 1200, "Xe_LP", &graphics_xelp }; 131 static const struct xe_ip graphics_ip_xelpp = { 1210, "Xe_LP+", &graphics_xelp }; 132 static const struct xe_ip graphics_ip_xehpg = { 1255, "Xe_HPG", &graphics_xehpg }; 133 static const struct xe_ip graphics_ip_xehpc = { 1260, "Xe_HPC", &graphics_xehpc }; 134 135 /* GMDID-based Graphics IPs */ 136 static const struct xe_ip graphics_ips[] = { 137 { 1270, "Xe_LPG", &graphics_xelpg }, 138 { 1271, "Xe_LPG", &graphics_xelpg }, 139 { 1274, "Xe_LPG+", &graphics_xelpg }, 140 { 2001, "Xe2_HPG", &graphics_xe2 }, 141 { 2002, "Xe2_HPG", &graphics_xe2 }, 142 { 2004, "Xe2_LPG", &graphics_xe2 }, 143 { 3000, "Xe3_LPG", &graphics_xe2 }, 144 { 3001, "Xe3_LPG", &graphics_xe2 }, 145 { 3003, "Xe3_LPG", &graphics_xe2 }, 146 { 3004, "Xe3_LPG", &graphics_xe2 }, 147 { 3005, "Xe3_LPG", &graphics_xe2 }, 148 { 3511, "Xe3p_XPC", &graphics_xe3p_xpc }, 149 }; 150 151 /* Pre-GMDID Media IPs */ 152 static const struct xe_ip media_ip_xem = { 1200, "Xe_M", &media_xem }; 153 static const struct xe_ip media_ip_xehpm = { 1255, "Xe_HPM", &media_xem }; 154 155 /* GMDID-based Media IPs */ 156 static const struct xe_ip media_ips[] = { 157 { 1300, "Xe_LPM+", &media_xelpmp }, 158 { 1301, "Xe2_HPM", &media_xelpmp }, 159 { 2000, "Xe2_LPM", &media_xelpmp }, 160 { 3000, "Xe3_LPM", &media_xelpmp }, 161 { 3002, "Xe3_LPM", &media_xelpmp }, 162 { 3500, "Xe3p_LPM", &media_xelpmp }, 163 { 3503, "Xe3p_HPM", &media_xelpmp }, 164 }; 165 166 static const struct xe_device_desc tgl_desc = { 167 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 168 .pre_gmdid_media_ip = &media_ip_xem, 169 PLATFORM(TIGERLAKE), 170 .dma_mask_size = 39, 171 .has_display = true, 172 .has_llc = true, 173 .has_sriov = true, 174 .max_gt_per_tile = 1, 175 .require_force_probe = true, 176 .va_bits = 48, 177 .vm_max_level = 3, 178 }; 179 180 static const struct xe_device_desc rkl_desc = { 181 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 182 .pre_gmdid_media_ip = &media_ip_xem, 183 PLATFORM(ROCKETLAKE), 184 .dma_mask_size = 39, 185 .has_display = true, 186 .has_llc = true, 187 .max_gt_per_tile = 1, 188 .require_force_probe = true, 189 .va_bits = 48, 190 .vm_max_level = 3, 191 }; 192 193 static const u16 adls_rpls_ids[] = { INTEL_RPLS_IDS(NOP), 0 }; 194 195 static const struct xe_device_desc adl_s_desc = { 196 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 197 .pre_gmdid_media_ip = &media_ip_xem, 198 PLATFORM(ALDERLAKE_S), 199 .dma_mask_size = 39, 200 .has_display = true, 201 .has_llc = true, 202 .has_sriov = true, 203 .max_gt_per_tile = 1, 204 .require_force_probe = true, 205 .subplatforms = (const struct xe_subplatform_desc[]) { 206 { XE_SUBPLATFORM_ALDERLAKE_S_RPLS, "RPLS", adls_rpls_ids }, 207 {}, 208 }, 209 .va_bits = 48, 210 .vm_max_level = 3, 211 }; 212 213 static const u16 adlp_rplu_ids[] = { INTEL_RPLU_IDS(NOP), 0 }; 214 215 static const struct xe_device_desc adl_p_desc = { 216 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 217 .pre_gmdid_media_ip = &media_ip_xem, 218 PLATFORM(ALDERLAKE_P), 219 .dma_mask_size = 39, 220 .has_display = true, 221 .has_llc = true, 222 .has_sriov = true, 223 .max_gt_per_tile = 1, 224 .require_force_probe = true, 225 .subplatforms = (const struct xe_subplatform_desc[]) { 226 { XE_SUBPLATFORM_ALDERLAKE_P_RPLU, "RPLU", adlp_rplu_ids }, 227 {}, 228 }, 229 .va_bits = 48, 230 .vm_max_level = 3, 231 }; 232 233 static const struct xe_device_desc adl_n_desc = { 234 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 235 .pre_gmdid_media_ip = &media_ip_xem, 236 PLATFORM(ALDERLAKE_N), 237 .dma_mask_size = 39, 238 .has_display = true, 239 .has_llc = true, 240 .has_sriov = true, 241 .max_gt_per_tile = 1, 242 .require_force_probe = true, 243 .va_bits = 48, 244 .vm_max_level = 3, 245 }; 246 247 #define DGFX_FEATURES \ 248 .is_dgfx = 1 249 250 static const struct xe_device_desc dg1_desc = { 251 .pre_gmdid_graphics_ip = &graphics_ip_xelpp, 252 .pre_gmdid_media_ip = &media_ip_xem, 253 DGFX_FEATURES, 254 PLATFORM(DG1), 255 .dma_mask_size = 39, 256 .has_display = true, 257 .has_gsc_nvm = 1, 258 .has_heci_gscfi = 1, 259 .max_gt_per_tile = 1, 260 .require_force_probe = true, 261 .va_bits = 48, 262 .vm_max_level = 3, 263 }; 264 265 static const u16 dg2_g10_ids[] = { INTEL_DG2_G10_IDS(NOP), INTEL_ATS_M150_IDS(NOP), 0 }; 266 static const u16 dg2_g11_ids[] = { INTEL_DG2_G11_IDS(NOP), INTEL_ATS_M75_IDS(NOP), 0 }; 267 static const u16 dg2_g12_ids[] = { INTEL_DG2_G12_IDS(NOP), 0 }; 268 269 #define DG2_FEATURES \ 270 DGFX_FEATURES, \ 271 PLATFORM(DG2), \ 272 .has_flat_ccs = 1, \ 273 .has_gsc_nvm = 1, \ 274 .has_heci_gscfi = 1, \ 275 .subplatforms = (const struct xe_subplatform_desc[]) { \ 276 { XE_SUBPLATFORM_DG2_G10, "G10", dg2_g10_ids }, \ 277 { XE_SUBPLATFORM_DG2_G11, "G11", dg2_g11_ids }, \ 278 { XE_SUBPLATFORM_DG2_G12, "G12", dg2_g12_ids }, \ 279 { } \ 280 }, \ 281 .va_bits = 48, \ 282 .vm_max_level = 3, \ 283 .vram_flags = XE_VRAM_FLAGS_NEED64K 284 285 static const struct xe_device_desc ats_m_desc = { 286 .pre_gmdid_graphics_ip = &graphics_ip_xehpg, 287 .pre_gmdid_media_ip = &media_ip_xehpm, 288 .dma_mask_size = 46, 289 .max_gt_per_tile = 1, 290 .require_force_probe = true, 291 292 DG2_FEATURES, 293 .has_display = false, 294 .has_sriov = true, 295 }; 296 297 static const struct xe_device_desc dg2_desc = { 298 .pre_gmdid_graphics_ip = &graphics_ip_xehpg, 299 .pre_gmdid_media_ip = &media_ip_xehpm, 300 .dma_mask_size = 46, 301 .max_gt_per_tile = 1, 302 .require_force_probe = true, 303 304 DG2_FEATURES, 305 .has_display = true, 306 .has_fan_control = true, 307 .has_mbx_power_limits = false, 308 }; 309 310 static const __maybe_unused struct xe_device_desc pvc_desc = { 311 .pre_gmdid_graphics_ip = &graphics_ip_xehpc, 312 DGFX_FEATURES, 313 PLATFORM(PVC), 314 .dma_mask_size = 52, 315 .has_display = false, 316 .has_gsc_nvm = 1, 317 .has_heci_gscfi = 1, 318 .max_gt_per_tile = 1, 319 .max_remote_tiles = 1, 320 .require_force_probe = true, 321 .va_bits = 57, 322 .vm_max_level = 4, 323 .vram_flags = XE_VRAM_FLAGS_NEED64K, 324 .has_mbx_power_limits = false, 325 }; 326 327 static const struct xe_device_desc mtl_desc = { 328 /* .graphics and .media determined via GMD_ID */ 329 .require_force_probe = true, 330 PLATFORM(METEORLAKE), 331 .dma_mask_size = 46, 332 .has_display = true, 333 .has_pxp = true, 334 .max_gt_per_tile = 2, 335 .va_bits = 48, 336 .vm_max_level = 4, 337 }; 338 339 static const struct xe_device_desc lnl_desc = { 340 PLATFORM(LUNARLAKE), 341 .dma_mask_size = 46, 342 .has_display = true, 343 .has_flat_ccs = 1, 344 .has_pxp = true, 345 .has_mem_copy_instr = true, 346 .max_gt_per_tile = 2, 347 .needs_scratch = true, 348 .va_bits = 48, 349 .vm_max_level = 4, 350 }; 351 352 static const u16 bmg_g21_ids[] = { INTEL_BMG_G21_IDS(NOP), 0 }; 353 354 static const struct xe_device_desc bmg_desc = { 355 DGFX_FEATURES, 356 PLATFORM(BATTLEMAGE), 357 .dma_mask_size = 46, 358 .has_display = true, 359 .has_fan_control = true, 360 .has_flat_ccs = 1, 361 .has_mbx_power_limits = true, 362 .has_gsc_nvm = 1, 363 .has_heci_cscfi = 1, 364 .has_late_bind = true, 365 .has_sriov = true, 366 .has_mem_copy_instr = true, 367 .max_gt_per_tile = 2, 368 .needs_scratch = true, 369 .subplatforms = (const struct xe_subplatform_desc[]) { 370 { XE_SUBPLATFORM_BATTLEMAGE_G21, "G21", bmg_g21_ids }, 371 { } 372 }, 373 .va_bits = 48, 374 .vm_max_level = 4, 375 }; 376 377 static const struct xe_device_desc ptl_desc = { 378 PLATFORM(PANTHERLAKE), 379 .dma_mask_size = 46, 380 .has_display = true, 381 .has_flat_ccs = 1, 382 .has_sriov = true, 383 .has_mem_copy_instr = true, 384 .max_gt_per_tile = 2, 385 .needs_scratch = true, 386 .needs_shared_vf_gt_wq = true, 387 .va_bits = 48, 388 .vm_max_level = 4, 389 }; 390 391 static const struct xe_device_desc nvls_desc = { 392 PLATFORM(NOVALAKE_S), 393 .dma_mask_size = 46, 394 .has_display = true, 395 .has_flat_ccs = 1, 396 .has_mem_copy_instr = true, 397 .max_gt_per_tile = 2, 398 .require_force_probe = true, 399 .va_bits = 48, 400 .vm_max_level = 4, 401 }; 402 403 static const struct xe_device_desc cri_desc = { 404 DGFX_FEATURES, 405 PLATFORM(CRESCENTISLAND), 406 .dma_mask_size = 52, 407 .has_display = false, 408 .has_flat_ccs = false, 409 .has_mbx_power_limits = true, 410 .has_sriov = true, 411 .max_gt_per_tile = 2, 412 .require_force_probe = true, 413 .va_bits = 57, 414 .vm_max_level = 4, 415 }; 416 417 #undef PLATFORM 418 __diag_pop(); 419 420 /* 421 * Make sure any device matches here are from most specific to most 422 * general. For example, since the Quanta match is based on the subsystem 423 * and subvendor IDs, we need it to come before the more general IVB 424 * PCI ID matches, otherwise we'll use the wrong info struct above. 425 */ 426 static const struct pci_device_id pciidlist[] = { 427 INTEL_TGL_IDS(INTEL_VGA_DEVICE, &tgl_desc), 428 INTEL_RKL_IDS(INTEL_VGA_DEVICE, &rkl_desc), 429 INTEL_ADLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc), 430 INTEL_ADLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc), 431 INTEL_ADLN_IDS(INTEL_VGA_DEVICE, &adl_n_desc), 432 INTEL_RPLU_IDS(INTEL_VGA_DEVICE, &adl_p_desc), 433 INTEL_RPLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc), 434 INTEL_RPLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc), 435 INTEL_DG1_IDS(INTEL_VGA_DEVICE, &dg1_desc), 436 INTEL_ATS_M_IDS(INTEL_VGA_DEVICE, &ats_m_desc), 437 INTEL_ARL_IDS(INTEL_VGA_DEVICE, &mtl_desc), 438 INTEL_DG2_IDS(INTEL_VGA_DEVICE, &dg2_desc), 439 INTEL_MTL_IDS(INTEL_VGA_DEVICE, &mtl_desc), 440 INTEL_LNL_IDS(INTEL_VGA_DEVICE, &lnl_desc), 441 INTEL_BMG_IDS(INTEL_VGA_DEVICE, &bmg_desc), 442 INTEL_PTL_IDS(INTEL_VGA_DEVICE, &ptl_desc), 443 INTEL_NVLS_IDS(INTEL_VGA_DEVICE, &nvls_desc), 444 INTEL_CRI_IDS(INTEL_PCI_DEVICE, &cri_desc), 445 INTEL_WCL_IDS(INTEL_VGA_DEVICE, &ptl_desc), 446 { } 447 }; 448 MODULE_DEVICE_TABLE(pci, pciidlist); 449 450 /* is device_id present in comma separated list of ids */ 451 static bool device_id_in_list(u16 device_id, const char *devices, bool negative) 452 { 453 char *s, *p, *tok; 454 bool ret; 455 456 if (!devices || !*devices) 457 return false; 458 459 /* match everything */ 460 if (negative && strcmp(devices, "!*") == 0) 461 return true; 462 if (!negative && strcmp(devices, "*") == 0) 463 return true; 464 465 s = kstrdup(devices, GFP_KERNEL); 466 if (!s) 467 return false; 468 469 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) { 470 u16 val; 471 472 if (negative && tok[0] == '!') 473 tok++; 474 else if ((negative && tok[0] != '!') || 475 (!negative && tok[0] == '!')) 476 continue; 477 478 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) { 479 ret = true; 480 break; 481 } 482 } 483 484 kfree(s); 485 486 return ret; 487 } 488 489 static bool id_forced(u16 device_id) 490 { 491 return device_id_in_list(device_id, xe_modparam.force_probe, false); 492 } 493 494 static bool id_blocked(u16 device_id) 495 { 496 return device_id_in_list(device_id, xe_modparam.force_probe, true); 497 } 498 499 static const struct xe_subplatform_desc * 500 find_subplatform(const struct xe_device *xe, const struct xe_device_desc *desc) 501 { 502 const struct xe_subplatform_desc *sp; 503 const u16 *id; 504 505 for (sp = desc->subplatforms; sp && sp->subplatform; sp++) 506 for (id = sp->pciidlist; *id; id++) 507 if (*id == xe->info.devid) 508 return sp; 509 510 return NULL; 511 } 512 513 enum xe_gmdid_type { 514 GMDID_GRAPHICS, 515 GMDID_MEDIA 516 }; 517 518 static int read_gmdid(struct xe_device *xe, enum xe_gmdid_type type, u32 *ver, u32 *revid) 519 { 520 struct xe_mmio *mmio = xe_root_tile_mmio(xe); 521 struct xe_reg gmdid_reg = GMD_ID; 522 u32 val; 523 524 KUNIT_STATIC_STUB_REDIRECT(read_gmdid, xe, type, ver, revid); 525 526 if (IS_SRIOV_VF(xe)) { 527 /* 528 * To get the value of the GMDID register, VFs must obtain it 529 * from the GuC using MMIO communication. 530 * 531 * Note that at this point the GTs are not initialized and only 532 * tile-level access to MMIO registers is possible. To use our 533 * existing GuC communication functions we must create a dummy 534 * GT structure and perform at least basic xe_gt and xe_guc 535 * initialization. 536 */ 537 struct xe_gt *gt __free(kfree) = NULL; 538 int err; 539 540 gt = kzalloc(sizeof(*gt), GFP_KERNEL); 541 if (!gt) 542 return -ENOMEM; 543 544 gt->tile = &xe->tiles[0]; 545 if (type == GMDID_MEDIA) { 546 gt->info.id = 1; 547 gt->info.type = XE_GT_TYPE_MEDIA; 548 } else { 549 gt->info.id = 0; 550 gt->info.type = XE_GT_TYPE_MAIN; 551 } 552 553 xe_gt_mmio_init(gt); 554 xe_guc_comm_init_early(>->uc.guc); 555 556 err = xe_gt_sriov_vf_bootstrap(gt); 557 if (err) 558 return err; 559 560 val = xe_gt_sriov_vf_gmdid(gt); 561 } else { 562 /* 563 * GMD_ID is a GT register, but at this point in the driver 564 * init we haven't fully initialized the GT yet so we need to 565 * read the register with the tile's MMIO accessor. That means 566 * we need to apply the GSI offset manually since it won't get 567 * automatically added as it would if we were using a GT mmio 568 * accessor. 569 */ 570 if (type == GMDID_MEDIA) 571 gmdid_reg.addr += MEDIA_GT_GSI_OFFSET; 572 573 val = xe_mmio_read32(mmio, gmdid_reg); 574 } 575 576 *ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val) * 100 + REG_FIELD_GET(GMD_ID_RELEASE_MASK, val); 577 *revid = REG_FIELD_GET(GMD_ID_REVID, val); 578 579 return 0; 580 } 581 582 static const struct xe_ip *find_graphics_ip(unsigned int verx100) 583 { 584 KUNIT_STATIC_STUB_REDIRECT(find_graphics_ip, verx100); 585 586 for (int i = 0; i < ARRAY_SIZE(graphics_ips); i++) 587 if (graphics_ips[i].verx100 == verx100) 588 return &graphics_ips[i]; 589 return NULL; 590 } 591 592 static const struct xe_ip *find_media_ip(unsigned int verx100) 593 { 594 KUNIT_STATIC_STUB_REDIRECT(find_media_ip, verx100); 595 596 for (int i = 0; i < ARRAY_SIZE(media_ips); i++) 597 if (media_ips[i].verx100 == verx100) 598 return &media_ips[i]; 599 return NULL; 600 } 601 602 /* 603 * Read IP version from hardware and select graphics/media IP descriptors 604 * based on the result. 605 */ 606 static int handle_gmdid(struct xe_device *xe, 607 const struct xe_ip **graphics_ip, 608 const struct xe_ip **media_ip, 609 u32 *graphics_revid, 610 u32 *media_revid) 611 { 612 u32 ver; 613 int ret; 614 615 *graphics_ip = NULL; 616 *media_ip = NULL; 617 618 ret = read_gmdid(xe, GMDID_GRAPHICS, &ver, graphics_revid); 619 if (ret) 620 return ret; 621 622 *graphics_ip = find_graphics_ip(ver); 623 if (!*graphics_ip) { 624 drm_err(&xe->drm, "Hardware reports unknown graphics version %u.%02u\n", 625 ver / 100, ver % 100); 626 } 627 628 ret = read_gmdid(xe, GMDID_MEDIA, &ver, media_revid); 629 if (ret) 630 return ret; 631 632 /* Media may legitimately be fused off / not present */ 633 if (ver == 0) 634 return 0; 635 636 *media_ip = find_media_ip(ver); 637 if (!*media_ip) { 638 drm_err(&xe->drm, "Hardware reports unknown media version %u.%02u\n", 639 ver / 100, ver % 100); 640 } 641 642 return 0; 643 } 644 645 /* 646 * Initialize device info content that only depends on static driver_data 647 * passed to the driver at probe time from PCI ID table. 648 */ 649 static int xe_info_init_early(struct xe_device *xe, 650 const struct xe_device_desc *desc, 651 const struct xe_subplatform_desc *subplatform_desc) 652 { 653 int err; 654 655 xe->info.platform_name = desc->platform_name; 656 xe->info.platform = desc->platform; 657 xe->info.subplatform = subplatform_desc ? 658 subplatform_desc->subplatform : XE_SUBPLATFORM_NONE; 659 660 xe->info.dma_mask_size = desc->dma_mask_size; 661 xe->info.va_bits = desc->va_bits; 662 xe->info.vm_max_level = desc->vm_max_level; 663 xe->info.vram_flags = desc->vram_flags; 664 665 xe->info.is_dgfx = desc->is_dgfx; 666 xe->info.has_fan_control = desc->has_fan_control; 667 /* runtime fusing may force flat_ccs to disabled later */ 668 xe->info.has_flat_ccs = desc->has_flat_ccs; 669 xe->info.has_mbx_power_limits = desc->has_mbx_power_limits; 670 xe->info.has_gsc_nvm = desc->has_gsc_nvm; 671 xe->info.has_heci_gscfi = desc->has_heci_gscfi; 672 xe->info.has_heci_cscfi = desc->has_heci_cscfi; 673 xe->info.has_late_bind = desc->has_late_bind; 674 xe->info.has_llc = desc->has_llc; 675 xe->info.has_pxp = desc->has_pxp; 676 xe->info.has_sriov = xe_configfs_primary_gt_allowed(to_pci_dev(xe->drm.dev)) && 677 desc->has_sriov; 678 xe->info.has_mem_copy_instr = desc->has_mem_copy_instr; 679 xe->info.skip_guc_pc = desc->skip_guc_pc; 680 xe->info.skip_mtcfg = desc->skip_mtcfg; 681 xe->info.skip_pcode = desc->skip_pcode; 682 xe->info.needs_scratch = desc->needs_scratch; 683 xe->info.needs_shared_vf_gt_wq = desc->needs_shared_vf_gt_wq; 684 685 xe->info.probe_display = IS_ENABLED(CONFIG_DRM_XE_DISPLAY) && 686 xe_modparam.probe_display && 687 desc->has_display; 688 689 xe_assert(xe, desc->max_gt_per_tile > 0); 690 xe_assert(xe, desc->max_gt_per_tile <= XE_MAX_GT_PER_TILE); 691 xe->info.max_gt_per_tile = desc->max_gt_per_tile; 692 xe->info.tile_count = 1 + desc->max_remote_tiles; 693 694 err = xe_tile_init_early(xe_device_get_root_tile(xe), xe, 0); 695 if (err) 696 return err; 697 698 return 0; 699 } 700 701 /* 702 * Possibly override number of tile based on configuration register. 703 */ 704 static void xe_info_probe_tile_count(struct xe_device *xe) 705 { 706 struct xe_mmio *mmio; 707 u8 tile_count; 708 u32 mtcfg; 709 710 KUNIT_STATIC_STUB_REDIRECT(xe_info_probe_tile_count, xe); 711 712 /* 713 * Probe for tile count only for platforms that support multiple 714 * tiles. 715 */ 716 if (xe->info.tile_count == 1) 717 return; 718 719 if (xe->info.skip_mtcfg) 720 return; 721 722 mmio = xe_root_tile_mmio(xe); 723 724 /* 725 * Although the per-tile mmio regs are not yet initialized, this 726 * is fine as it's going to the root tile's mmio, that's 727 * guaranteed to be initialized earlier in xe_mmio_probe_early() 728 */ 729 mtcfg = xe_mmio_read32(mmio, XEHP_MTCFG_ADDR); 730 tile_count = REG_FIELD_GET(TILE_COUNT, mtcfg) + 1; 731 732 if (tile_count < xe->info.tile_count) { 733 drm_info(&xe->drm, "tile_count: %d, reduced_tile_count %d\n", 734 xe->info.tile_count, tile_count); 735 xe->info.tile_count = tile_count; 736 } 737 } 738 739 static struct xe_gt *alloc_primary_gt(struct xe_tile *tile, 740 const struct xe_graphics_desc *graphics_desc, 741 const struct xe_media_desc *media_desc) 742 { 743 struct xe_device *xe = tile_to_xe(tile); 744 struct xe_gt *gt; 745 746 if (!xe_configfs_primary_gt_allowed(to_pci_dev(xe->drm.dev))) { 747 xe_info(xe, "Primary GT disabled via configfs\n"); 748 return NULL; 749 } 750 751 gt = xe_gt_alloc(tile); 752 if (IS_ERR(gt)) 753 return gt; 754 755 gt->info.type = XE_GT_TYPE_MAIN; 756 gt->info.id = tile->id * xe->info.max_gt_per_tile; 757 gt->info.has_indirect_ring_state = graphics_desc->has_indirect_ring_state; 758 gt->info.engine_mask = graphics_desc->hw_engine_mask; 759 760 /* 761 * Before media version 13, the media IP was part of the primary GT 762 * so we need to add the media engines to the primary GT's engine list. 763 */ 764 if (MEDIA_VER(xe) < 13 && media_desc) 765 gt->info.engine_mask |= media_desc->hw_engine_mask; 766 767 return gt; 768 } 769 770 static struct xe_gt *alloc_media_gt(struct xe_tile *tile, 771 const struct xe_media_desc *media_desc) 772 { 773 struct xe_device *xe = tile_to_xe(tile); 774 struct xe_gt *gt; 775 776 if (!xe_configfs_media_gt_allowed(to_pci_dev(xe->drm.dev))) { 777 xe_info(xe, "Media GT disabled via configfs\n"); 778 return NULL; 779 } 780 781 if (MEDIA_VER(xe) < 13 || !media_desc) 782 return NULL; 783 784 gt = xe_gt_alloc(tile); 785 if (IS_ERR(gt)) 786 return gt; 787 788 gt->info.type = XE_GT_TYPE_MEDIA; 789 gt->info.id = tile->id * xe->info.max_gt_per_tile + 1; 790 gt->info.has_indirect_ring_state = media_desc->has_indirect_ring_state; 791 gt->info.engine_mask = media_desc->hw_engine_mask; 792 793 return gt; 794 } 795 796 /* 797 * Initialize device info content that does require knowledge about 798 * graphics / media IP version. 799 * Make sure that GT / tile structures allocated by the driver match the data 800 * present in device info. 801 */ 802 static int xe_info_init(struct xe_device *xe, 803 const struct xe_device_desc *desc) 804 { 805 u32 graphics_gmdid_revid = 0, media_gmdid_revid = 0; 806 const struct xe_ip *graphics_ip; 807 const struct xe_ip *media_ip; 808 const struct xe_graphics_desc *graphics_desc; 809 const struct xe_media_desc *media_desc; 810 struct xe_tile *tile; 811 struct xe_gt *gt; 812 int ret; 813 u8 id; 814 815 /* 816 * If this platform supports GMD_ID, we'll detect the proper IP 817 * descriptor to use from hardware registers. 818 * desc->pre_gmdid_graphics_ip will only ever be set at this point for 819 * platforms before GMD_ID. In that case the IP descriptions and 820 * versions are simply derived from that. 821 */ 822 if (desc->pre_gmdid_graphics_ip) { 823 graphics_ip = desc->pre_gmdid_graphics_ip; 824 media_ip = desc->pre_gmdid_media_ip; 825 xe->info.step = xe_step_pre_gmdid_get(xe); 826 } else { 827 xe_assert(xe, !desc->pre_gmdid_media_ip); 828 ret = handle_gmdid(xe, &graphics_ip, &media_ip, 829 &graphics_gmdid_revid, &media_gmdid_revid); 830 if (ret) 831 return ret; 832 833 xe->info.step = xe_step_gmdid_get(xe, 834 graphics_gmdid_revid, 835 media_gmdid_revid); 836 } 837 838 /* 839 * If we couldn't detect the graphics IP, that's considered a fatal 840 * error and we should abort driver load. Failing to detect media 841 * IP is non-fatal; we'll just proceed without enabling media support. 842 */ 843 if (!graphics_ip) 844 return -ENODEV; 845 846 xe->info.graphics_verx100 = graphics_ip->verx100; 847 xe->info.graphics_name = graphics_ip->name; 848 graphics_desc = graphics_ip->desc; 849 850 if (media_ip) { 851 xe->info.media_verx100 = media_ip->verx100; 852 xe->info.media_name = media_ip->name; 853 media_desc = media_ip->desc; 854 } else { 855 xe->info.media_name = "none"; 856 media_desc = NULL; 857 } 858 859 xe->info.has_asid = graphics_desc->has_asid; 860 xe->info.has_atomic_enable_pte_bit = graphics_desc->has_atomic_enable_pte_bit; 861 if (xe->info.platform != XE_PVC) 862 xe->info.has_device_atomics_on_smem = 1; 863 864 xe->info.has_range_tlb_inval = graphics_desc->has_range_tlb_inval; 865 xe->info.has_usm = graphics_desc->has_usm; 866 xe->info.has_64bit_timestamp = graphics_desc->has_64bit_timestamp; 867 868 xe_info_probe_tile_count(xe); 869 870 for_each_remote_tile(tile, xe, id) { 871 int err; 872 873 err = xe_tile_init_early(tile, xe, id); 874 if (err) 875 return err; 876 } 877 878 /* Allocate any GT and VRAM structures necessary for the platform. */ 879 for_each_tile(tile, xe, id) { 880 int err; 881 882 err = xe_tile_alloc_vram(tile); 883 if (err) 884 return err; 885 886 tile->primary_gt = alloc_primary_gt(tile, graphics_desc, media_desc); 887 if (IS_ERR(tile->primary_gt)) 888 return PTR_ERR(tile->primary_gt); 889 890 /* 891 * It's not currently possible to probe a device with the 892 * primary GT disabled. With some work, this may be future in 893 * the possible for igpu platforms (although probably not for 894 * dgpu's since access to the primary GT's BCS engines is 895 * required for VRAM management). 896 */ 897 if (!tile->primary_gt) { 898 drm_err(&xe->drm, "Cannot probe device with without a primary GT\n"); 899 return -ENODEV; 900 } 901 902 tile->media_gt = alloc_media_gt(tile, media_desc); 903 if (IS_ERR(tile->media_gt)) 904 return PTR_ERR(tile->media_gt); 905 } 906 907 /* 908 * Now that we have tiles and GTs defined, let's loop over valid GTs 909 * in order to define gt_count. 910 */ 911 for_each_gt(gt, xe, id) 912 xe->info.gt_count++; 913 914 return 0; 915 } 916 917 static void xe_pci_remove(struct pci_dev *pdev) 918 { 919 struct xe_device *xe = pdev_to_xe_device(pdev); 920 921 if (IS_SRIOV_PF(xe)) 922 xe_pci_sriov_configure(pdev, 0); 923 924 if (xe_survivability_mode_is_boot_enabled(xe)) 925 return; 926 927 xe_device_remove(xe); 928 xe_pm_fini(xe); 929 } 930 931 /* 932 * Probe the PCI device, initialize various parts of the driver. 933 * 934 * Fault injection is used to test the error paths of some initialization 935 * functions called either directly from xe_pci_probe() or indirectly for 936 * example through xe_device_probe(). Those functions use the kernel fault 937 * injection capabilities infrastructure, see 938 * Documentation/fault-injection/fault-injection.rst for details. The macro 939 * ALLOW_ERROR_INJECTION() is used to conditionally skip function execution 940 * at runtime and use a provided return value. The first requirement for 941 * error injectable functions is proper handling of the error code by the 942 * caller for recovery, which is always the case here. The second 943 * requirement is that no state is changed before the first error return. 944 * It is not strictly fulfilled for all initialization functions using the 945 * ALLOW_ERROR_INJECTION() macro but this is acceptable because for those 946 * error cases at probe time, the error code is simply propagated up by the 947 * caller. Therefore there is no consequence on those specific callers when 948 * function error injection skips the whole function. 949 */ 950 static int xe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 951 { 952 const struct xe_device_desc *desc = (const void *)ent->driver_data; 953 const struct xe_subplatform_desc *subplatform_desc; 954 struct xe_device *xe; 955 int err; 956 957 xe_configfs_check_device(pdev); 958 959 if (desc->require_force_probe && !id_forced(pdev->device)) { 960 dev_info(&pdev->dev, 961 "Your graphics device %04x is not officially supported\n" 962 "by xe driver in this kernel version. To force Xe probe,\n" 963 "use xe.force_probe='%04x' and i915.force_probe='!%04x'\n" 964 "module parameters or CONFIG_DRM_XE_FORCE_PROBE='%04x' and\n" 965 "CONFIG_DRM_I915_FORCE_PROBE='!%04x' configuration options.\n", 966 pdev->device, pdev->device, pdev->device, 967 pdev->device, pdev->device); 968 return -ENODEV; 969 } 970 971 if (id_blocked(pdev->device)) { 972 dev_info(&pdev->dev, "Probe blocked for device [%04x:%04x].\n", 973 pdev->vendor, pdev->device); 974 return -ENODEV; 975 } 976 977 if (xe_display_driver_probe_defer(pdev)) 978 return -EPROBE_DEFER; 979 980 err = pcim_enable_device(pdev); 981 if (err) 982 return err; 983 984 xe = xe_device_create(pdev, ent); 985 if (IS_ERR(xe)) 986 return PTR_ERR(xe); 987 988 pci_set_drvdata(pdev, &xe->drm); 989 990 xe_pm_assert_unbounded_bridge(xe); 991 subplatform_desc = find_subplatform(xe, desc); 992 993 pci_set_master(pdev); 994 995 err = xe_info_init_early(xe, desc, subplatform_desc); 996 if (err) 997 return err; 998 999 xe_vram_resize_bar(xe); 1000 1001 err = xe_device_probe_early(xe); 1002 /* 1003 * In Boot Survivability mode, no drm card is exposed and driver 1004 * is loaded with bare minimum to allow for firmware to be 1005 * flashed through mei. Return success, if survivability mode 1006 * is enabled due to pcode failure or configfs being set 1007 */ 1008 if (xe_survivability_mode_is_boot_enabled(xe)) 1009 return 0; 1010 1011 if (err) 1012 return err; 1013 1014 err = xe_info_init(xe, desc); 1015 if (err) 1016 return err; 1017 1018 err = xe_display_probe(xe); 1019 if (err) 1020 return err; 1021 1022 drm_dbg(&xe->drm, "%s %s %04x:%04x dgfx:%d gfx:%s (%d.%02d) media:%s (%d.%02d) display:%s dma_m_s:%d tc:%d gscfi:%d cscfi:%d", 1023 desc->platform_name, 1024 subplatform_desc ? subplatform_desc->name : "", 1025 xe->info.devid, xe->info.revid, 1026 xe->info.is_dgfx, 1027 xe->info.graphics_name, 1028 xe->info.graphics_verx100 / 100, 1029 xe->info.graphics_verx100 % 100, 1030 xe->info.media_name, 1031 xe->info.media_verx100 / 100, 1032 xe->info.media_verx100 % 100, 1033 str_yes_no(xe->info.probe_display), 1034 xe->info.dma_mask_size, xe->info.tile_count, 1035 xe->info.has_heci_gscfi, xe->info.has_heci_cscfi); 1036 1037 drm_dbg(&xe->drm, "Stepping = (G:%s, M:%s, B:%s)\n", 1038 xe_step_name(xe->info.step.graphics), 1039 xe_step_name(xe->info.step.media), 1040 xe_step_name(xe->info.step.basedie)); 1041 1042 drm_dbg(&xe->drm, "SR-IOV support: %s (mode: %s)\n", 1043 str_yes_no(xe_device_has_sriov(xe)), 1044 xe_sriov_mode_to_string(xe_device_sriov_mode(xe))); 1045 1046 err = xe_pm_init_early(xe); 1047 if (err) 1048 return err; 1049 1050 err = xe_device_probe(xe); 1051 if (err) 1052 return err; 1053 1054 err = xe_pm_init(xe); 1055 if (err) 1056 goto err_driver_cleanup; 1057 1058 drm_dbg(&xe->drm, "d3cold: capable=%s\n", 1059 str_yes_no(xe->d3cold.capable)); 1060 1061 return 0; 1062 1063 err_driver_cleanup: 1064 xe_pci_remove(pdev); 1065 return err; 1066 } 1067 1068 static void xe_pci_shutdown(struct pci_dev *pdev) 1069 { 1070 xe_device_shutdown(pdev_to_xe_device(pdev)); 1071 } 1072 1073 #ifdef CONFIG_PM_SLEEP 1074 static void d3cold_toggle(struct pci_dev *pdev, enum toggle_d3cold toggle) 1075 { 1076 struct xe_device *xe = pdev_to_xe_device(pdev); 1077 struct pci_dev *root_pdev; 1078 1079 if (!xe->d3cold.capable) 1080 return; 1081 1082 root_pdev = pcie_find_root_port(pdev); 1083 if (!root_pdev) 1084 return; 1085 1086 switch (toggle) { 1087 case D3COLD_DISABLE: 1088 pci_d3cold_disable(root_pdev); 1089 break; 1090 case D3COLD_ENABLE: 1091 pci_d3cold_enable(root_pdev); 1092 break; 1093 } 1094 } 1095 1096 static int xe_pci_suspend(struct device *dev) 1097 { 1098 struct pci_dev *pdev = to_pci_dev(dev); 1099 struct xe_device *xe = pdev_to_xe_device(pdev); 1100 int err; 1101 1102 if (xe_survivability_mode_is_boot_enabled(xe)) 1103 return -EBUSY; 1104 1105 err = xe_pm_suspend(xe); 1106 if (err) 1107 return err; 1108 1109 /* 1110 * Enabling D3Cold is needed for S2Idle/S0ix. 1111 * It is save to allow here since xe_pm_suspend has evicted 1112 * the local memory and the direct complete optimization is disabled. 1113 */ 1114 d3cold_toggle(pdev, D3COLD_ENABLE); 1115 1116 pci_save_state(pdev); 1117 pci_disable_device(pdev); 1118 pci_set_power_state(pdev, PCI_D3cold); 1119 1120 return 0; 1121 } 1122 1123 static int xe_pci_resume(struct device *dev) 1124 { 1125 struct pci_dev *pdev = to_pci_dev(dev); 1126 int err; 1127 1128 /* Give back the D3Cold decision to the runtime P M*/ 1129 d3cold_toggle(pdev, D3COLD_DISABLE); 1130 1131 err = pci_set_power_state(pdev, PCI_D0); 1132 if (err) 1133 return err; 1134 1135 pci_restore_state(pdev); 1136 1137 err = pci_enable_device(pdev); 1138 if (err) 1139 return err; 1140 1141 pci_set_master(pdev); 1142 1143 err = xe_pm_resume(pdev_to_xe_device(pdev)); 1144 if (err) 1145 return err; 1146 1147 return 0; 1148 } 1149 1150 static int xe_pci_runtime_suspend(struct device *dev) 1151 { 1152 struct pci_dev *pdev = to_pci_dev(dev); 1153 struct xe_device *xe = pdev_to_xe_device(pdev); 1154 int err; 1155 1156 err = xe_pm_runtime_suspend(xe); 1157 if (err) 1158 return err; 1159 1160 pci_save_state(pdev); 1161 1162 if (xe->d3cold.allowed) { 1163 d3cold_toggle(pdev, D3COLD_ENABLE); 1164 pci_disable_device(pdev); 1165 pci_ignore_hotplug(pdev); 1166 pci_set_power_state(pdev, PCI_D3cold); 1167 } else { 1168 d3cold_toggle(pdev, D3COLD_DISABLE); 1169 pci_set_power_state(pdev, PCI_D3hot); 1170 } 1171 1172 return 0; 1173 } 1174 1175 static int xe_pci_runtime_resume(struct device *dev) 1176 { 1177 struct pci_dev *pdev = to_pci_dev(dev); 1178 struct xe_device *xe = pdev_to_xe_device(pdev); 1179 int err; 1180 1181 err = pci_set_power_state(pdev, PCI_D0); 1182 if (err) 1183 return err; 1184 1185 pci_restore_state(pdev); 1186 1187 if (xe->d3cold.allowed) { 1188 err = pci_enable_device(pdev); 1189 if (err) 1190 return err; 1191 1192 pci_set_master(pdev); 1193 } 1194 1195 return xe_pm_runtime_resume(xe); 1196 } 1197 1198 static int xe_pci_runtime_idle(struct device *dev) 1199 { 1200 struct pci_dev *pdev = to_pci_dev(dev); 1201 struct xe_device *xe = pdev_to_xe_device(pdev); 1202 1203 xe_pm_d3cold_allowed_toggle(xe); 1204 1205 return 0; 1206 } 1207 1208 static const struct dev_pm_ops xe_pm_ops = { 1209 SET_SYSTEM_SLEEP_PM_OPS(xe_pci_suspend, xe_pci_resume) 1210 SET_RUNTIME_PM_OPS(xe_pci_runtime_suspend, xe_pci_runtime_resume, xe_pci_runtime_idle) 1211 }; 1212 #endif 1213 1214 static struct pci_driver xe_pci_driver = { 1215 .name = DRIVER_NAME, 1216 .id_table = pciidlist, 1217 .probe = xe_pci_probe, 1218 .remove = xe_pci_remove, 1219 .shutdown = xe_pci_shutdown, 1220 .sriov_configure = xe_pci_sriov_configure, 1221 #ifdef CONFIG_PM_SLEEP 1222 .driver.pm = &xe_pm_ops, 1223 #endif 1224 }; 1225 1226 int xe_register_pci_driver(void) 1227 { 1228 return pci_register_driver(&xe_pci_driver); 1229 } 1230 1231 void xe_unregister_pci_driver(void) 1232 { 1233 pci_unregister_driver(&xe_pci_driver); 1234 } 1235 1236 #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST) 1237 #include "tests/xe_pci.c" 1238 #endif 1239