1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "xe_guc.h" 7 8 #include <linux/iopoll.h> 9 #include <drm/drm_managed.h> 10 11 #include <generated/xe_wa_oob.h> 12 13 #include "abi/guc_actions_abi.h" 14 #include "abi/guc_errors_abi.h" 15 #include "regs/xe_gt_regs.h" 16 #include "regs/xe_gtt_defs.h" 17 #include "regs/xe_guc_regs.h" 18 #include "regs/xe_irq_regs.h" 19 #include "xe_bo.h" 20 #include "xe_configfs.h" 21 #include "xe_device.h" 22 #include "xe_force_wake.h" 23 #include "xe_gt.h" 24 #include "xe_gt_printk.h" 25 #include "xe_gt_sriov_vf.h" 26 #include "xe_gt_throttle.h" 27 #include "xe_guc_ads.h" 28 #include "xe_guc_buf.h" 29 #include "xe_guc_capture.h" 30 #include "xe_guc_ct.h" 31 #include "xe_guc_db_mgr.h" 32 #include "xe_guc_engine_activity.h" 33 #include "xe_guc_hwconfig.h" 34 #include "xe_guc_klv_helpers.h" 35 #include "xe_guc_log.h" 36 #include "xe_guc_pc.h" 37 #include "xe_guc_relay.h" 38 #include "xe_guc_submit.h" 39 #include "xe_memirq.h" 40 #include "xe_mmio.h" 41 #include "xe_platform_types.h" 42 #include "xe_sriov.h" 43 #include "xe_uc.h" 44 #include "xe_uc_fw.h" 45 #include "xe_wa.h" 46 #include "xe_wopcm.h" 47 48 static u32 guc_bo_ggtt_addr(struct xe_guc *guc, 49 struct xe_bo *bo) 50 { 51 struct xe_device *xe = guc_to_xe(guc); 52 u32 addr; 53 54 /* 55 * For most BOs, the address on the allocating tile is fine. However for 56 * some, e.g. G2G CTB, the address on a specific tile is required as it 57 * might be different for each tile. So, just always ask for the address 58 * on the target GuC. 59 */ 60 addr = __xe_bo_ggtt_addr(bo, gt_to_tile(guc_to_gt(guc))->id); 61 62 /* GuC addresses above GUC_GGTT_TOP don't map through the GTT */ 63 xe_assert(xe, addr >= xe_wopcm_size(guc_to_xe(guc))); 64 xe_assert(xe, addr < GUC_GGTT_TOP); 65 xe_assert(xe, xe_bo_size(bo) <= GUC_GGTT_TOP - addr); 66 67 return addr; 68 } 69 70 static u32 guc_ctl_debug_flags(struct xe_guc *guc) 71 { 72 u32 level = xe_guc_log_get_level(&guc->log); 73 u32 flags = 0; 74 75 if (!GUC_LOG_LEVEL_IS_VERBOSE(level)) 76 flags |= GUC_LOG_DISABLED; 77 else 78 flags |= FIELD_PREP(GUC_LOG_VERBOSITY, GUC_LOG_LEVEL_TO_VERBOSITY(level)); 79 80 return flags; 81 } 82 83 static u32 guc_ctl_feature_flags(struct xe_guc *guc) 84 { 85 struct xe_device *xe = guc_to_xe(guc); 86 u32 flags = GUC_CTL_ENABLE_LITE_RESTORE; 87 88 if (!xe->info.skip_guc_pc) 89 flags |= GUC_CTL_ENABLE_SLPC; 90 91 if (xe_configfs_get_psmi_enabled(to_pci_dev(xe->drm.dev))) 92 flags |= GUC_CTL_ENABLE_PSMI_LOGGING; 93 94 if (xe_guc_using_main_gamctrl_queues(guc)) 95 flags |= GUC_CTL_MAIN_GAMCTRL_QUEUES; 96 97 return flags; 98 } 99 100 static u32 guc_ctl_log_params_flags(struct xe_guc *guc) 101 { 102 u32 offset = guc_bo_ggtt_addr(guc, guc->log.bo) >> PAGE_SHIFT; 103 u32 flags; 104 105 #if (((CRASH_BUFFER_SIZE) % SZ_1M) == 0) 106 #define LOG_UNIT SZ_1M 107 #define LOG_FLAG GUC_LOG_LOG_ALLOC_UNITS 108 #else 109 #define LOG_UNIT SZ_4K 110 #define LOG_FLAG 0 111 #endif 112 113 #if (((CAPTURE_BUFFER_SIZE) % SZ_1M) == 0) 114 #define CAPTURE_UNIT SZ_1M 115 #define CAPTURE_FLAG GUC_LOG_CAPTURE_ALLOC_UNITS 116 #else 117 #define CAPTURE_UNIT SZ_4K 118 #define CAPTURE_FLAG 0 119 #endif 120 121 BUILD_BUG_ON(!CRASH_BUFFER_SIZE); 122 BUILD_BUG_ON(!IS_ALIGNED(CRASH_BUFFER_SIZE, LOG_UNIT)); 123 BUILD_BUG_ON(!DEBUG_BUFFER_SIZE); 124 BUILD_BUG_ON(!IS_ALIGNED(DEBUG_BUFFER_SIZE, LOG_UNIT)); 125 BUILD_BUG_ON(!CAPTURE_BUFFER_SIZE); 126 BUILD_BUG_ON(!IS_ALIGNED(CAPTURE_BUFFER_SIZE, CAPTURE_UNIT)); 127 128 flags = GUC_LOG_VALID | 129 GUC_LOG_NOTIFY_ON_HALF_FULL | 130 CAPTURE_FLAG | 131 LOG_FLAG | 132 FIELD_PREP(GUC_LOG_CRASH, CRASH_BUFFER_SIZE / LOG_UNIT - 1) | 133 FIELD_PREP(GUC_LOG_DEBUG, DEBUG_BUFFER_SIZE / LOG_UNIT - 1) | 134 FIELD_PREP(GUC_LOG_CAPTURE, CAPTURE_BUFFER_SIZE / CAPTURE_UNIT - 1) | 135 FIELD_PREP(GUC_LOG_BUF_ADDR, offset); 136 137 #undef LOG_UNIT 138 #undef LOG_FLAG 139 #undef CAPTURE_UNIT 140 #undef CAPTURE_FLAG 141 142 return flags; 143 } 144 145 static u32 guc_ctl_ads_flags(struct xe_guc *guc) 146 { 147 u32 ads = guc_bo_ggtt_addr(guc, guc->ads.bo) >> PAGE_SHIFT; 148 u32 flags = FIELD_PREP(GUC_ADS_ADDR, ads); 149 150 return flags; 151 } 152 153 static bool needs_wa_dual_queue(struct xe_gt *gt) 154 { 155 /* 156 * The DUAL_QUEUE_WA tells the GuC to not allow concurrent submissions 157 * on RCS and CCSes with different address spaces, which on DG2 is 158 * required as a WA for an HW bug. 159 */ 160 if (XE_GT_WA(gt, 22011391025)) 161 return true; 162 163 /* 164 * On newer platforms, the HW has been updated to not allow parallel 165 * execution of different address spaces, so the RCS/CCS will stall the 166 * context switch if one of the other RCS/CCSes is busy with a different 167 * address space. While functionally correct, having a submission 168 * stalled on the HW limits the GuC ability to shuffle things around and 169 * can cause complications if the non-stalled submission runs for a long 170 * time, because the GuC doesn't know that the stalled submission isn't 171 * actually running and might declare it as hung. Therefore, we enable 172 * the DUAL_QUEUE_WA on all newer platforms on GTs that have CCS engines 173 * to move management back to the GuC. 174 */ 175 if (CCS_MASK(gt) && GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270) 176 return true; 177 178 return false; 179 } 180 181 static u32 guc_ctl_wa_flags(struct xe_guc *guc) 182 { 183 struct xe_device *xe = guc_to_xe(guc); 184 struct xe_gt *gt = guc_to_gt(guc); 185 u32 flags = 0; 186 187 if (XE_GT_WA(gt, 22012773006)) 188 flags |= GUC_WA_POLLCS; 189 190 if (XE_GT_WA(gt, 14014475959)) 191 flags |= GUC_WA_HOLD_CCS_SWITCHOUT; 192 193 if (needs_wa_dual_queue(gt)) 194 flags |= GUC_WA_DUAL_QUEUE; 195 196 /* 197 * Wa_22011802037: FIXME - there's more to be done than simply setting 198 * this flag: make sure each CS is stopped when preparing for GT reset 199 * and wait for pending MI_FW. 200 */ 201 if (GRAPHICS_VERx100(xe) < 1270) 202 flags |= GUC_WA_PRE_PARSER; 203 204 if (XE_GT_WA(gt, 22012727170) || XE_GT_WA(gt, 22012727685)) 205 flags |= GUC_WA_CONTEXT_ISOLATION; 206 207 if (XE_GT_WA(gt, 18020744125) && 208 !xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_RENDER)) 209 flags |= GUC_WA_RCS_REGS_IN_CCS_REGS_LIST; 210 211 if (XE_GT_WA(gt, 1509372804)) 212 flags |= GUC_WA_RENDER_RST_RC6_EXIT; 213 214 if (XE_GT_WA(gt, 14018913170)) 215 flags |= GUC_WA_ENABLE_TSC_CHECK_ON_RC6; 216 217 if (XE_GT_WA(gt, 16023683509)) 218 flags |= GUC_WA_SAVE_RESTORE_MCFG_REG_AT_MC6; 219 220 return flags; 221 } 222 223 static u32 guc_ctl_devid(struct xe_guc *guc) 224 { 225 struct xe_device *xe = guc_to_xe(guc); 226 227 return (((u32)xe->info.devid) << 16) | xe->info.revid; 228 } 229 230 static void guc_print_params(struct xe_guc *guc) 231 { 232 struct xe_gt *gt = guc_to_gt(guc); 233 u32 *params = guc->params; 234 int i; 235 236 BUILD_BUG_ON(sizeof(guc->params) != GUC_CTL_MAX_DWORDS * sizeof(u32)); 237 BUILD_BUG_ON(GUC_CTL_MAX_DWORDS + 2 != SOFT_SCRATCH_COUNT); 238 239 for (i = 0; i < GUC_CTL_MAX_DWORDS; i++) 240 xe_gt_dbg(gt, "GuC param[%2d] = 0x%08x\n", i, params[i]); 241 } 242 243 static void guc_init_params(struct xe_guc *guc) 244 { 245 u32 *params = guc->params; 246 247 params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc); 248 params[GUC_CTL_FEATURE] = 0; 249 params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc); 250 params[GUC_CTL_ADS] = guc_ctl_ads_flags(guc); 251 params[GUC_CTL_WA] = 0; 252 params[GUC_CTL_DEVID] = guc_ctl_devid(guc); 253 254 guc_print_params(guc); 255 } 256 257 static void guc_init_params_post_hwconfig(struct xe_guc *guc) 258 { 259 u32 *params = guc->params; 260 261 params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc); 262 params[GUC_CTL_FEATURE] = guc_ctl_feature_flags(guc); 263 params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc); 264 params[GUC_CTL_ADS] = guc_ctl_ads_flags(guc); 265 params[GUC_CTL_WA] = guc_ctl_wa_flags(guc); 266 params[GUC_CTL_DEVID] = guc_ctl_devid(guc); 267 268 guc_print_params(guc); 269 } 270 271 /* 272 * Initialize the GuC parameter block before starting the firmware 273 * transfer. These parameters are read by the firmware on startup 274 * and cannot be changed thereafter. 275 */ 276 static void guc_write_params(struct xe_guc *guc) 277 { 278 struct xe_gt *gt = guc_to_gt(guc); 279 int i; 280 281 xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT); 282 283 xe_mmio_write32(>->mmio, SOFT_SCRATCH(0), 0); 284 285 for (i = 0; i < GUC_CTL_MAX_DWORDS; i++) 286 xe_mmio_write32(>->mmio, SOFT_SCRATCH(1 + i), guc->params[i]); 287 } 288 289 static int guc_action_register_g2g_buffer(struct xe_guc *guc, u32 type, u32 dst_tile, u32 dst_dev, 290 u32 desc_addr, u32 buff_addr, u32 size) 291 { 292 struct xe_gt *gt = guc_to_gt(guc); 293 struct xe_device *xe = gt_to_xe(gt); 294 u32 action[] = { 295 XE_GUC_ACTION_REGISTER_G2G, 296 FIELD_PREP(XE_G2G_REGISTER_SIZE, size / SZ_4K - 1) | 297 FIELD_PREP(XE_G2G_REGISTER_TYPE, type) | 298 FIELD_PREP(XE_G2G_REGISTER_TILE, dst_tile) | 299 FIELD_PREP(XE_G2G_REGISTER_DEVICE, dst_dev), 300 desc_addr, 301 buff_addr, 302 }; 303 304 xe_assert(xe, (type == XE_G2G_TYPE_IN) || (type == XE_G2G_TYPE_OUT)); 305 xe_assert(xe, !(size % SZ_4K)); 306 307 return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action)); 308 } 309 310 static int guc_action_deregister_g2g_buffer(struct xe_guc *guc, u32 type, u32 dst_tile, u32 dst_dev) 311 { 312 struct xe_gt *gt = guc_to_gt(guc); 313 struct xe_device *xe = gt_to_xe(gt); 314 u32 action[] = { 315 XE_GUC_ACTION_DEREGISTER_G2G, 316 FIELD_PREP(XE_G2G_DEREGISTER_TYPE, type) | 317 FIELD_PREP(XE_G2G_DEREGISTER_TILE, dst_tile) | 318 FIELD_PREP(XE_G2G_DEREGISTER_DEVICE, dst_dev), 319 }; 320 321 xe_assert(xe, (type == XE_G2G_TYPE_IN) || (type == XE_G2G_TYPE_OUT)); 322 323 return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action)); 324 } 325 326 #define G2G_DEV(gt) (((gt)->info.type == XE_GT_TYPE_MAIN) ? 0 : 1) 327 328 #define G2G_BUFFER_SIZE (SZ_4K) 329 #define G2G_DESC_SIZE (64) 330 #define G2G_DESC_AREA_SIZE (SZ_4K) 331 332 /* 333 * Generate a unique id for each bi-directional CTB for each pair of 334 * near and far tiles/devices. The id can then be used as an index into 335 * a single allocation that is sub-divided into multiple CTBs. 336 * 337 * For example, with two devices per tile and two tiles, the table should 338 * look like: 339 * Far <tile>.<dev> 340 * 0.0 0.1 1.0 1.1 341 * N 0.0 --/-- 00/01 02/03 04/05 342 * e 0.1 01/00 --/-- 06/07 08/09 343 * a 1.0 03/02 07/06 --/-- 10/11 344 * r 1.1 05/04 09/08 11/10 --/-- 345 * 346 * Where each entry is Rx/Tx channel id. 347 * 348 * So GuC #3 (tile 1, dev 1) talking to GuC #2 (tile 1, dev 0) would 349 * be reading from channel #11 and writing to channel #10. Whereas, 350 * GuC #2 talking to GuC #3 would be read on #10 and write to #11. 351 */ 352 static unsigned int g2g_slot(u32 near_tile, u32 near_dev, u32 far_tile, u32 far_dev, 353 u32 type, u32 max_inst, bool have_dev) 354 { 355 u32 near = near_tile, far = far_tile; 356 u32 idx = 0, x, y, direction; 357 int i; 358 359 if (have_dev) { 360 near = (near << 1) | near_dev; 361 far = (far << 1) | far_dev; 362 } 363 364 /* No need to send to one's self */ 365 if (far == near) 366 return -1; 367 368 if (far > near) { 369 /* Top right table half */ 370 x = far; 371 y = near; 372 373 /* T/R is 'forwards' direction */ 374 direction = type; 375 } else { 376 /* Bottom left table half */ 377 x = near; 378 y = far; 379 380 /* B/L is 'backwards' direction */ 381 direction = (1 - type); 382 } 383 384 /* Count the rows prior to the target */ 385 for (i = y; i > 0; i--) 386 idx += max_inst - i; 387 388 /* Count this row up to the target */ 389 idx += (x - 1 - y); 390 391 /* Slots are in Rx/Tx pairs */ 392 idx *= 2; 393 394 /* Pick Rx/Tx direction */ 395 idx += direction; 396 397 return idx; 398 } 399 400 static int guc_g2g_register(struct xe_guc *near_guc, struct xe_gt *far_gt, u32 type, bool have_dev) 401 { 402 struct xe_gt *near_gt = guc_to_gt(near_guc); 403 struct xe_device *xe = gt_to_xe(near_gt); 404 struct xe_bo *g2g_bo; 405 u32 near_tile = gt_to_tile(near_gt)->id; 406 u32 near_dev = G2G_DEV(near_gt); 407 u32 far_tile = gt_to_tile(far_gt)->id; 408 u32 far_dev = G2G_DEV(far_gt); 409 u32 max = xe->info.gt_count; 410 u32 base, desc, buf; 411 int slot; 412 413 /* G2G is not allowed between different cards */ 414 xe_assert(xe, xe == gt_to_xe(far_gt)); 415 416 g2g_bo = near_guc->g2g.bo; 417 xe_assert(xe, g2g_bo); 418 419 slot = g2g_slot(near_tile, near_dev, far_tile, far_dev, type, max, have_dev); 420 xe_assert(xe, slot >= 0); 421 422 base = guc_bo_ggtt_addr(near_guc, g2g_bo); 423 desc = base + slot * G2G_DESC_SIZE; 424 buf = base + G2G_DESC_AREA_SIZE + slot * G2G_BUFFER_SIZE; 425 426 xe_assert(xe, (desc - base + G2G_DESC_SIZE) <= G2G_DESC_AREA_SIZE); 427 xe_assert(xe, (buf - base + G2G_BUFFER_SIZE) <= xe_bo_size(g2g_bo)); 428 429 return guc_action_register_g2g_buffer(near_guc, type, far_tile, far_dev, 430 desc, buf, G2G_BUFFER_SIZE); 431 } 432 433 static void guc_g2g_deregister(struct xe_guc *guc, u32 far_tile, u32 far_dev, u32 type) 434 { 435 guc_action_deregister_g2g_buffer(guc, type, far_tile, far_dev); 436 } 437 438 static u32 guc_g2g_size(struct xe_guc *guc) 439 { 440 struct xe_gt *gt = guc_to_gt(guc); 441 struct xe_device *xe = gt_to_xe(gt); 442 unsigned int count = xe->info.gt_count; 443 u32 num_channels = (count * (count - 1)) / 2; 444 445 xe_assert(xe, num_channels * XE_G2G_TYPE_LIMIT * G2G_DESC_SIZE <= G2G_DESC_AREA_SIZE); 446 447 return num_channels * XE_G2G_TYPE_LIMIT * G2G_BUFFER_SIZE + G2G_DESC_AREA_SIZE; 448 } 449 450 static bool xe_guc_g2g_wanted(struct xe_device *xe) 451 { 452 /* Can't do GuC to GuC communication if there is only one GuC */ 453 if (xe->info.gt_count <= 1) 454 return false; 455 456 /* No current user */ 457 return false; 458 } 459 460 static int guc_g2g_alloc(struct xe_guc *guc) 461 { 462 struct xe_gt *gt = guc_to_gt(guc); 463 struct xe_device *xe = gt_to_xe(gt); 464 struct xe_tile *tile = gt_to_tile(gt); 465 struct xe_bo *bo; 466 u32 g2g_size; 467 468 if (guc->g2g.bo) 469 return 0; 470 471 if (gt->info.id != 0) { 472 struct xe_gt *root_gt = xe_device_get_gt(xe, 0); 473 struct xe_guc *root_guc = &root_gt->uc.guc; 474 struct xe_bo *bo; 475 476 bo = xe_bo_get(root_guc->g2g.bo); 477 if (!bo) 478 return -ENODEV; 479 480 guc->g2g.bo = bo; 481 guc->g2g.owned = false; 482 return 0; 483 } 484 485 g2g_size = guc_g2g_size(guc); 486 bo = xe_managed_bo_create_pin_map(xe, tile, g2g_size, 487 XE_BO_FLAG_VRAM_IF_DGFX(tile) | 488 XE_BO_FLAG_GGTT | 489 XE_BO_FLAG_GGTT_ALL | 490 XE_BO_FLAG_GGTT_INVALIDATE | 491 XE_BO_FLAG_PINNED_NORESTORE); 492 if (IS_ERR(bo)) 493 return PTR_ERR(bo); 494 495 xe_map_memset(xe, &bo->vmap, 0, 0, g2g_size); 496 guc->g2g.bo = bo; 497 guc->g2g.owned = true; 498 499 return 0; 500 } 501 502 static void guc_g2g_fini(struct xe_guc *guc) 503 { 504 if (!guc->g2g.bo) 505 return; 506 507 /* Unpinning the owned object is handled by generic shutdown */ 508 if (!guc->g2g.owned) 509 xe_bo_put(guc->g2g.bo); 510 511 guc->g2g.bo = NULL; 512 } 513 514 static int guc_g2g_start(struct xe_guc *guc) 515 { 516 struct xe_gt *far_gt, *gt = guc_to_gt(guc); 517 struct xe_device *xe = gt_to_xe(gt); 518 unsigned int i, j; 519 int t, err; 520 bool have_dev; 521 522 if (!guc->g2g.bo) { 523 int ret; 524 525 ret = guc_g2g_alloc(guc); 526 if (ret) 527 return ret; 528 } 529 530 /* GuC interface will need extending if more GT device types are ever created. */ 531 xe_gt_assert(gt, (gt->info.type == XE_GT_TYPE_MAIN) || (gt->info.type == XE_GT_TYPE_MEDIA)); 532 533 /* Channel numbering depends on whether there are multiple GTs per tile */ 534 have_dev = xe->info.gt_count > xe->info.tile_count; 535 536 for_each_gt(far_gt, xe, i) { 537 u32 far_tile, far_dev; 538 539 if (far_gt->info.id == gt->info.id) 540 continue; 541 542 far_tile = gt_to_tile(far_gt)->id; 543 far_dev = G2G_DEV(far_gt); 544 545 for (t = 0; t < XE_G2G_TYPE_LIMIT; t++) { 546 err = guc_g2g_register(guc, far_gt, t, have_dev); 547 if (err) { 548 while (--t >= 0) 549 guc_g2g_deregister(guc, far_tile, far_dev, t); 550 goto err_deregister; 551 } 552 } 553 } 554 555 return 0; 556 557 err_deregister: 558 for_each_gt(far_gt, xe, j) { 559 u32 tile, dev; 560 561 if (far_gt->info.id == gt->info.id) 562 continue; 563 564 if (j >= i) 565 break; 566 567 tile = gt_to_tile(far_gt)->id; 568 dev = G2G_DEV(far_gt); 569 570 for (t = 0; t < XE_G2G_TYPE_LIMIT; t++) 571 guc_g2g_deregister(guc, tile, dev, t); 572 } 573 574 return err; 575 } 576 577 static int __guc_opt_in_features_enable(struct xe_guc *guc, u64 addr, u32 num_dwords) 578 { 579 u32 action[] = { 580 XE_GUC_ACTION_OPT_IN_FEATURE_KLV, 581 lower_32_bits(addr), 582 upper_32_bits(addr), 583 num_dwords 584 }; 585 586 return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action)); 587 } 588 589 static bool supports_dynamic_ics(struct xe_guc *guc) 590 { 591 struct xe_device *xe = guc_to_xe(guc); 592 struct xe_gt *gt = guc_to_gt(guc); 593 594 /* Dynamic ICS is available for PVC and Xe2 and newer platforms. */ 595 if (xe->info.platform != XE_PVC && GRAPHICS_VER(xe) < 20) 596 return false; 597 598 /* 599 * The feature is currently not compatible with multi-lrc, so the GuC 600 * does not support it at all on the media engines (which are the main 601 * users of mlrc). On the primary GT side, to avoid it being used in 602 * conjunction with mlrc, we only enable it if we are in single CCS 603 * mode. 604 */ 605 if (xe_gt_is_media_type(gt) || gt->ccs_mode > 1) 606 return false; 607 608 /* 609 * Dynamic ICS requires GuC v70.40.1, which maps to compatibility 610 * version v1.18.4. 611 */ 612 return GUC_SUBMIT_VER(guc) >= MAKE_GUC_VER(1, 18, 4); 613 } 614 615 #define OPT_IN_MAX_DWORDS 16 616 int xe_guc_opt_in_features_enable(struct xe_guc *guc) 617 { 618 struct xe_device *xe = guc_to_xe(guc); 619 CLASS(xe_guc_buf, buf)(&guc->buf, OPT_IN_MAX_DWORDS); 620 u32 count = 0; 621 u32 *klvs; 622 int ret; 623 624 if (!xe_guc_buf_is_valid(buf)) 625 return -ENOBUFS; 626 627 klvs = xe_guc_buf_cpu_ptr(buf); 628 629 /* 630 * The extra CAT error type opt-in was added in GuC v70.17.0, which maps 631 * to compatibility version v1.7.0. 632 * Note that the GuC allows enabling this KLV even on platforms that do 633 * not support the extra type; in such case the returned type variable 634 * will be set to a known invalid value which we can check against. 635 */ 636 if (GUC_SUBMIT_VER(guc) >= MAKE_GUC_VER(1, 7, 0)) 637 klvs[count++] = PREP_GUC_KLV_TAG(OPT_IN_FEATURE_EXT_CAT_ERR_TYPE); 638 639 if (supports_dynamic_ics(guc)) 640 klvs[count++] = PREP_GUC_KLV_TAG(OPT_IN_FEATURE_DYNAMIC_INHIBIT_CONTEXT_SWITCH); 641 642 if (count) { 643 xe_assert(xe, count <= OPT_IN_MAX_DWORDS); 644 645 ret = __guc_opt_in_features_enable(guc, xe_guc_buf_flush(buf), count); 646 if (ret < 0) { 647 xe_gt_err(guc_to_gt(guc), 648 "failed to enable GuC opt-in features: %pe\n", 649 ERR_PTR(ret)); 650 return ret; 651 } 652 } 653 654 return 0; 655 } 656 657 static void guc_fini_hw(void *arg) 658 { 659 struct xe_guc *guc = arg; 660 struct xe_gt *gt = guc_to_gt(guc); 661 unsigned int fw_ref; 662 663 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); 664 xe_uc_sanitize_reset(&guc_to_gt(guc)->uc); 665 xe_force_wake_put(gt_to_fw(gt), fw_ref); 666 667 guc_g2g_fini(guc); 668 } 669 670 /** 671 * xe_guc_comm_init_early - early initialization of GuC communication 672 * @guc: the &xe_guc to initialize 673 * 674 * Must be called prior to first MMIO communication with GuC firmware. 675 */ 676 void xe_guc_comm_init_early(struct xe_guc *guc) 677 { 678 struct xe_gt *gt = guc_to_gt(guc); 679 680 if (xe_gt_is_media_type(gt)) 681 guc->notify_reg = MED_GUC_HOST_INTERRUPT; 682 else 683 guc->notify_reg = GUC_HOST_INTERRUPT; 684 } 685 686 static int xe_guc_realloc_post_hwconfig(struct xe_guc *guc) 687 { 688 struct xe_tile *tile = gt_to_tile(guc_to_gt(guc)); 689 struct xe_device *xe = guc_to_xe(guc); 690 int ret; 691 692 if (!IS_DGFX(guc_to_xe(guc))) 693 return 0; 694 695 ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->fw.bo); 696 if (ret) 697 return ret; 698 699 ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->log.bo); 700 if (ret) 701 return ret; 702 703 ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->ads.bo); 704 if (ret) 705 return ret; 706 707 return 0; 708 } 709 710 static int vf_guc_init_noalloc(struct xe_guc *guc) 711 { 712 struct xe_gt *gt = guc_to_gt(guc); 713 int err; 714 715 err = xe_gt_sriov_vf_bootstrap(gt); 716 if (err) 717 return err; 718 719 err = xe_gt_sriov_vf_query_config(gt); 720 if (err) 721 return err; 722 723 return 0; 724 } 725 726 int xe_guc_init_noalloc(struct xe_guc *guc) 727 { 728 struct xe_device *xe = guc_to_xe(guc); 729 struct xe_gt *gt = guc_to_gt(guc); 730 int ret; 731 732 xe_guc_comm_init_early(guc); 733 734 ret = xe_guc_ct_init_noalloc(&guc->ct); 735 if (ret) 736 goto out; 737 738 ret = xe_guc_relay_init(&guc->relay); 739 if (ret) 740 goto out; 741 742 if (IS_SRIOV_VF(xe)) { 743 ret = vf_guc_init_noalloc(guc); 744 if (ret) 745 goto out; 746 } 747 748 return 0; 749 750 out: 751 xe_gt_err(gt, "GuC init failed with %pe\n", ERR_PTR(ret)); 752 return ret; 753 } 754 755 int xe_guc_init(struct xe_guc *guc) 756 { 757 struct xe_device *xe = guc_to_xe(guc); 758 struct xe_gt *gt = guc_to_gt(guc); 759 int ret; 760 761 guc->fw.type = XE_UC_FW_TYPE_GUC; 762 ret = xe_uc_fw_init(&guc->fw); 763 if (ret) 764 return ret; 765 766 if (!xe_uc_fw_is_enabled(&guc->fw)) 767 return 0; 768 769 if (IS_SRIOV_VF(xe)) { 770 ret = xe_guc_ct_init(&guc->ct); 771 if (ret) 772 goto out; 773 return 0; 774 } 775 776 ret = xe_guc_log_init(&guc->log); 777 if (ret) 778 goto out; 779 780 ret = xe_guc_capture_init(guc); 781 if (ret) 782 goto out; 783 784 ret = xe_guc_ads_init(&guc->ads); 785 if (ret) 786 goto out; 787 788 ret = xe_guc_ct_init(&guc->ct); 789 if (ret) 790 goto out; 791 792 xe_uc_fw_change_status(&guc->fw, XE_UC_FIRMWARE_LOADABLE); 793 794 ret = devm_add_action_or_reset(xe->drm.dev, guc_fini_hw, guc); 795 if (ret) 796 goto out; 797 798 guc_init_params(guc); 799 800 return 0; 801 802 out: 803 xe_gt_err(gt, "GuC init failed with %pe\n", ERR_PTR(ret)); 804 return ret; 805 } 806 807 static int vf_guc_init_post_hwconfig(struct xe_guc *guc) 808 { 809 int err; 810 811 err = xe_guc_submit_init(guc, xe_gt_sriov_vf_guc_ids(guc_to_gt(guc))); 812 if (err) 813 return err; 814 815 err = xe_guc_buf_cache_init(&guc->buf); 816 if (err) 817 return err; 818 819 /* XXX xe_guc_db_mgr_init not needed for now */ 820 821 return 0; 822 } 823 824 /** 825 * xe_guc_init_post_hwconfig - initialize GuC post hwconfig load 826 * @guc: The GuC object 827 * 828 * Return: 0 on success, negative error code on error. 829 */ 830 int xe_guc_init_post_hwconfig(struct xe_guc *guc) 831 { 832 int ret; 833 834 if (IS_SRIOV_VF(guc_to_xe(guc))) 835 return vf_guc_init_post_hwconfig(guc); 836 837 ret = xe_guc_realloc_post_hwconfig(guc); 838 if (ret) 839 return ret; 840 841 ret = xe_guc_ct_init_post_hwconfig(&guc->ct); 842 if (ret) 843 return ret; 844 845 guc_init_params_post_hwconfig(guc); 846 847 ret = xe_guc_submit_init(guc, ~0); 848 if (ret) 849 return ret; 850 851 ret = xe_guc_db_mgr_init(&guc->dbm, ~0); 852 if (ret) 853 return ret; 854 855 ret = xe_guc_pc_init(&guc->pc); 856 if (ret) 857 return ret; 858 859 ret = xe_guc_engine_activity_init(guc); 860 if (ret) 861 return ret; 862 863 ret = xe_guc_buf_cache_init(&guc->buf); 864 if (ret) 865 return ret; 866 867 return xe_guc_ads_init_post_hwconfig(&guc->ads); 868 } 869 870 int xe_guc_post_load_init(struct xe_guc *guc) 871 { 872 int ret; 873 874 xe_guc_ads_populate_post_load(&guc->ads); 875 876 ret = xe_guc_opt_in_features_enable(guc); 877 if (ret) 878 return ret; 879 880 if (xe_guc_g2g_wanted(guc_to_xe(guc))) { 881 ret = guc_g2g_start(guc); 882 if (ret) 883 return ret; 884 } 885 886 return xe_guc_submit_enable(guc); 887 } 888 889 int xe_guc_reset(struct xe_guc *guc) 890 { 891 struct xe_gt *gt = guc_to_gt(guc); 892 struct xe_mmio *mmio = >->mmio; 893 u32 guc_status, gdrst; 894 int ret; 895 896 xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT); 897 898 if (IS_SRIOV_VF(gt_to_xe(gt))) 899 return xe_gt_sriov_vf_bootstrap(gt); 900 901 xe_mmio_write32(mmio, GDRST, GRDOM_GUC); 902 903 ret = xe_mmio_wait32(mmio, GDRST, GRDOM_GUC, 0, 5000, &gdrst, false); 904 if (ret) { 905 xe_gt_err(gt, "GuC reset timed out, GDRST=%#x\n", gdrst); 906 goto err_out; 907 } 908 909 guc_status = xe_mmio_read32(mmio, GUC_STATUS); 910 if (!(guc_status & GS_MIA_IN_RESET)) { 911 xe_gt_err(gt, "GuC status: %#x, MIA core expected to be in reset\n", 912 guc_status); 913 ret = -EIO; 914 goto err_out; 915 } 916 917 return 0; 918 919 err_out: 920 921 return ret; 922 } 923 924 static void guc_prepare_xfer(struct xe_guc *guc) 925 { 926 struct xe_gt *gt = guc_to_gt(guc); 927 struct xe_mmio *mmio = >->mmio; 928 struct xe_device *xe = guc_to_xe(guc); 929 u32 shim_flags = GUC_ENABLE_READ_CACHE_LOGIC | 930 GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA | 931 GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA | 932 GUC_ENABLE_MIA_CLOCK_GATING; 933 934 if (GRAPHICS_VERx100(xe) < 1250) 935 shim_flags |= GUC_DISABLE_SRAM_INIT_TO_ZEROES | 936 GUC_ENABLE_MIA_CACHING; 937 938 if (GRAPHICS_VER(xe) >= 20 || xe->info.platform == XE_PVC) 939 shim_flags |= REG_FIELD_PREP(GUC_MOCS_INDEX_MASK, gt->mocs.uc_index); 940 941 /* Must program this register before loading the ucode with DMA */ 942 xe_mmio_write32(mmio, GUC_SHIM_CONTROL, shim_flags); 943 944 xe_mmio_write32(mmio, GT_PM_CONFIG, GT_DOORBELL_ENABLE); 945 946 /* Make sure GuC receives ARAT interrupts */ 947 xe_mmio_rmw32(mmio, PMINTRMSK, ARAT_EXPIRED_INTRMSK, 0); 948 } 949 950 /* 951 * Supporting MMIO & in memory RSA 952 */ 953 static int guc_xfer_rsa(struct xe_guc *guc) 954 { 955 struct xe_gt *gt = guc_to_gt(guc); 956 u32 rsa[UOS_RSA_SCRATCH_COUNT]; 957 size_t copied; 958 int i; 959 960 if (guc->fw.rsa_size > 256) { 961 u32 rsa_ggtt_addr = xe_bo_ggtt_addr(guc->fw.bo) + 962 xe_uc_fw_rsa_offset(&guc->fw); 963 xe_mmio_write32(>->mmio, UOS_RSA_SCRATCH(0), rsa_ggtt_addr); 964 return 0; 965 } 966 967 copied = xe_uc_fw_copy_rsa(&guc->fw, rsa, sizeof(rsa)); 968 if (copied < sizeof(rsa)) 969 return -ENOMEM; 970 971 for (i = 0; i < UOS_RSA_SCRATCH_COUNT; i++) 972 xe_mmio_write32(>->mmio, UOS_RSA_SCRATCH(i), rsa[i]); 973 974 return 0; 975 } 976 977 /* 978 * Wait for the GuC to start up. 979 * 980 * Measurements indicate this should take no more than 20ms (assuming the GT 981 * clock is at maximum frequency). However, thermal throttling and other issues 982 * can prevent the clock hitting max and thus making the load take significantly 983 * longer. Allow up to 3s as a safety margin in normal builds. For 984 * CONFIG_DRM_XE_DEBUG allow up to 10s to account for slower execution, issues 985 * in PCODE, driver, fan, etc. 986 * 987 * Keep checking the GUC_STATUS every 10ms with a debug message every 100 988 * attempts as a "I'm slow, but alive" message. Regardless, if it takes more 989 * than 200ms, emit a warning. 990 */ 991 992 #if IS_ENABLED(CONFIG_DRM_XE_DEBUG) 993 #define GUC_LOAD_TIMEOUT_SEC 20 994 #else 995 #define GUC_LOAD_TIMEOUT_SEC 3 996 #endif 997 #define GUC_LOAD_TIME_WARN_MSEC 200 998 999 static void print_load_status_err(struct xe_gt *gt, u32 status) 1000 { 1001 struct xe_mmio *mmio = >->mmio; 1002 u32 ukernel = REG_FIELD_GET(GS_UKERNEL_MASK, status); 1003 u32 bootrom = REG_FIELD_GET(GS_BOOTROM_MASK, status); 1004 1005 xe_gt_err(gt, "load failed: status: Reset = %d, BootROM = 0x%02X, UKernel = 0x%02X, MIA = 0x%02X, Auth = 0x%02X\n", 1006 REG_FIELD_GET(GS_MIA_IN_RESET, status), 1007 bootrom, ukernel, 1008 REG_FIELD_GET(GS_MIA_MASK, status), 1009 REG_FIELD_GET(GS_AUTH_STATUS_MASK, status)); 1010 1011 switch (bootrom) { 1012 case XE_BOOTROM_STATUS_NO_KEY_FOUND: 1013 xe_gt_err(gt, "invalid key requested, header = 0x%08X\n", 1014 xe_mmio_read32(mmio, GUC_HEADER_INFO)); 1015 break; 1016 case XE_BOOTROM_STATUS_RSA_FAILED: 1017 xe_gt_err(gt, "firmware signature verification failed\n"); 1018 break; 1019 case XE_BOOTROM_STATUS_PROD_KEY_CHECK_FAILURE: 1020 xe_gt_err(gt, "firmware production part check failure\n"); 1021 break; 1022 } 1023 1024 switch (ukernel) { 1025 case XE_GUC_LOAD_STATUS_HWCONFIG_START: 1026 xe_gt_err(gt, "still extracting hwconfig table.\n"); 1027 break; 1028 case XE_GUC_LOAD_STATUS_EXCEPTION: 1029 xe_gt_err(gt, "firmware exception. EIP: %#x\n", 1030 xe_mmio_read32(mmio, SOFT_SCRATCH(13))); 1031 break; 1032 case XE_GUC_LOAD_STATUS_INIT_DATA_INVALID: 1033 xe_gt_err(gt, "illegal init/ADS data\n"); 1034 break; 1035 case XE_GUC_LOAD_STATUS_INIT_MMIO_SAVE_RESTORE_INVALID: 1036 xe_gt_err(gt, "illegal register in save/restore workaround list\n"); 1037 break; 1038 case XE_GUC_LOAD_STATUS_KLV_WORKAROUND_INIT_ERROR: 1039 xe_gt_err(gt, "illegal workaround KLV data\n"); 1040 break; 1041 case XE_GUC_LOAD_STATUS_INVALID_FTR_FLAG: 1042 xe_gt_err(gt, "illegal feature flag specified\n"); 1043 break; 1044 } 1045 } 1046 1047 /* 1048 * Check GUC_STATUS looking for known terminal states (either completion or 1049 * failure) of either the microkernel status field or the boot ROM status field. 1050 * 1051 * Returns 1 for successful completion, -1 for failure and 0 for any 1052 * intermediate state. 1053 */ 1054 static int guc_load_done(struct xe_gt *gt, u32 *status, u32 *tries) 1055 { 1056 u32 ukernel, bootrom; 1057 1058 *status = xe_mmio_read32(>->mmio, GUC_STATUS); 1059 ukernel = REG_FIELD_GET(GS_UKERNEL_MASK, *status); 1060 bootrom = REG_FIELD_GET(GS_BOOTROM_MASK, *status); 1061 1062 switch (ukernel) { 1063 case XE_GUC_LOAD_STATUS_READY: 1064 return 1; 1065 case XE_GUC_LOAD_STATUS_ERROR_DEVID_BUILD_MISMATCH: 1066 case XE_GUC_LOAD_STATUS_GUC_PREPROD_BUILD_MISMATCH: 1067 case XE_GUC_LOAD_STATUS_ERROR_DEVID_INVALID_GUCTYPE: 1068 case XE_GUC_LOAD_STATUS_HWCONFIG_ERROR: 1069 case XE_GUC_LOAD_STATUS_BOOTROM_VERSION_MISMATCH: 1070 case XE_GUC_LOAD_STATUS_DPC_ERROR: 1071 case XE_GUC_LOAD_STATUS_EXCEPTION: 1072 case XE_GUC_LOAD_STATUS_INIT_DATA_INVALID: 1073 case XE_GUC_LOAD_STATUS_MPU_DATA_INVALID: 1074 case XE_GUC_LOAD_STATUS_INIT_MMIO_SAVE_RESTORE_INVALID: 1075 case XE_GUC_LOAD_STATUS_KLV_WORKAROUND_INIT_ERROR: 1076 case XE_GUC_LOAD_STATUS_INVALID_FTR_FLAG: 1077 return -1; 1078 } 1079 1080 switch (bootrom) { 1081 case XE_BOOTROM_STATUS_NO_KEY_FOUND: 1082 case XE_BOOTROM_STATUS_RSA_FAILED: 1083 case XE_BOOTROM_STATUS_PAVPC_FAILED: 1084 case XE_BOOTROM_STATUS_WOPCM_FAILED: 1085 case XE_BOOTROM_STATUS_LOADLOC_FAILED: 1086 case XE_BOOTROM_STATUS_JUMP_FAILED: 1087 case XE_BOOTROM_STATUS_RC6CTXCONFIG_FAILED: 1088 case XE_BOOTROM_STATUS_MPUMAP_INCORRECT: 1089 case XE_BOOTROM_STATUS_EXCEPTION: 1090 case XE_BOOTROM_STATUS_PROD_KEY_CHECK_FAILURE: 1091 return -1; 1092 } 1093 1094 if (++*tries >= 100) { 1095 struct xe_guc_pc *guc_pc = >->uc.guc.pc; 1096 1097 *tries = 0; 1098 xe_gt_dbg(gt, "GuC load still in progress, freq = %dMHz (req %dMHz), status = 0x%08X [0x%02X/%02X]\n", 1099 xe_guc_pc_get_act_freq(guc_pc), 1100 xe_guc_pc_get_cur_freq_fw(guc_pc), 1101 *status, ukernel, bootrom); 1102 } 1103 1104 return 0; 1105 } 1106 1107 static int guc_wait_ucode(struct xe_guc *guc) 1108 { 1109 struct xe_gt *gt = guc_to_gt(guc); 1110 struct xe_guc_pc *guc_pc = >->uc.guc.pc; 1111 u32 before_freq, act_freq, cur_freq; 1112 u32 status = 0, tries = 0; 1113 ktime_t before; 1114 u64 delta_ms; 1115 int ret; 1116 1117 before_freq = xe_guc_pc_get_act_freq(guc_pc); 1118 before = ktime_get(); 1119 1120 ret = poll_timeout_us(ret = guc_load_done(gt, &status, &tries), ret, 1121 10 * USEC_PER_MSEC, 1122 GUC_LOAD_TIMEOUT_SEC * USEC_PER_SEC, false); 1123 1124 delta_ms = ktime_to_ms(ktime_sub(ktime_get(), before)); 1125 act_freq = xe_guc_pc_get_act_freq(guc_pc); 1126 cur_freq = xe_guc_pc_get_cur_freq_fw(guc_pc); 1127 1128 if (ret) { 1129 xe_gt_err(gt, "load failed: status = 0x%08X, time = %lldms, freq = %dMHz (req %dMHz)\n", 1130 status, delta_ms, xe_guc_pc_get_act_freq(guc_pc), 1131 xe_guc_pc_get_cur_freq_fw(guc_pc)); 1132 print_load_status_err(gt, status); 1133 1134 return -EPROTO; 1135 } 1136 1137 if (delta_ms > GUC_LOAD_TIME_WARN_MSEC) { 1138 xe_gt_warn(gt, "GuC load: excessive init time: %lldms! [status = 0x%08X]\n", 1139 delta_ms, status); 1140 xe_gt_warn(gt, "GuC load: excessive init time: [freq = %dMHz (req = %dMHz), before = %dMHz, perf_limit_reasons = 0x%08X]\n", 1141 act_freq, cur_freq, before_freq, 1142 xe_gt_throttle_get_limit_reasons(gt)); 1143 } else { 1144 xe_gt_dbg(gt, "GuC load: init took %lldms, freq = %dMHz (req = %dMHz), before = %dMHz, status = 0x%08X\n", 1145 delta_ms, act_freq, cur_freq, before_freq, status); 1146 } 1147 1148 return 0; 1149 } 1150 ALLOW_ERROR_INJECTION(guc_wait_ucode, ERRNO); 1151 1152 static int __xe_guc_upload(struct xe_guc *guc) 1153 { 1154 int ret; 1155 1156 /* Raise GT freq to speed up HuC/GuC load */ 1157 xe_guc_pc_raise_unslice(&guc->pc); 1158 1159 guc_write_params(guc); 1160 guc_prepare_xfer(guc); 1161 1162 /* 1163 * Note that GuC needs the CSS header plus uKernel code to be copied 1164 * by the DMA engine in one operation, whereas the RSA signature is 1165 * loaded separately, either by copying it to the UOS_RSA_SCRATCH 1166 * register (if key size <= 256) or through a ggtt-pinned vma (if key 1167 * size > 256). The RSA size and therefore the way we provide it to the 1168 * HW is fixed for each platform and hard-coded in the bootrom. 1169 */ 1170 ret = guc_xfer_rsa(guc); 1171 if (ret) 1172 goto out; 1173 /* 1174 * Current uCode expects the code to be loaded at 8k; locations below 1175 * this are used for the stack. 1176 */ 1177 ret = xe_uc_fw_upload(&guc->fw, 0x2000, UOS_MOVE); 1178 if (ret) 1179 goto out; 1180 1181 /* Wait for authentication */ 1182 ret = guc_wait_ucode(guc); 1183 if (ret) 1184 goto out; 1185 1186 xe_uc_fw_change_status(&guc->fw, XE_UC_FIRMWARE_RUNNING); 1187 return 0; 1188 1189 out: 1190 xe_uc_fw_change_status(&guc->fw, XE_UC_FIRMWARE_LOAD_FAIL); 1191 return ret; 1192 } 1193 1194 static int vf_guc_min_load_for_hwconfig(struct xe_guc *guc) 1195 { 1196 struct xe_gt *gt = guc_to_gt(guc); 1197 int ret; 1198 1199 ret = xe_guc_hwconfig_init(guc); 1200 if (ret) 1201 return ret; 1202 1203 ret = xe_guc_enable_communication(guc); 1204 if (ret) 1205 return ret; 1206 1207 ret = xe_gt_sriov_vf_connect(gt); 1208 if (ret) 1209 goto err_out; 1210 1211 ret = xe_gt_sriov_vf_query_runtime(gt); 1212 if (ret) 1213 goto err_out; 1214 1215 return 0; 1216 1217 err_out: 1218 xe_guc_sanitize(guc); 1219 return ret; 1220 } 1221 1222 /** 1223 * xe_guc_min_load_for_hwconfig - load minimal GuC and read hwconfig table 1224 * @guc: The GuC object 1225 * 1226 * This function uploads a minimal GuC that does not support submissions but 1227 * in a state where the hwconfig table can be read. Next, it reads and parses 1228 * the hwconfig table so it can be used for subsequent steps in the driver load. 1229 * Lastly, it enables CT communication (XXX: this is needed for PFs/VFs only). 1230 * 1231 * Return: 0 on success, negative error code on error. 1232 */ 1233 int xe_guc_min_load_for_hwconfig(struct xe_guc *guc) 1234 { 1235 int ret; 1236 1237 if (IS_SRIOV_VF(guc_to_xe(guc))) 1238 return vf_guc_min_load_for_hwconfig(guc); 1239 1240 xe_guc_ads_populate_minimal(&guc->ads); 1241 1242 xe_guc_pc_init_early(&guc->pc); 1243 1244 ret = __xe_guc_upload(guc); 1245 if (ret) 1246 return ret; 1247 1248 ret = xe_guc_hwconfig_init(guc); 1249 if (ret) 1250 return ret; 1251 1252 ret = xe_guc_enable_communication(guc); 1253 if (ret) 1254 return ret; 1255 1256 return 0; 1257 } 1258 1259 int xe_guc_upload(struct xe_guc *guc) 1260 { 1261 struct xe_gt *gt = guc_to_gt(guc); 1262 1263 xe_guc_ads_populate(&guc->ads); 1264 1265 if (xe_guc_using_main_gamctrl_queues(guc)) 1266 xe_mmio_write32(>->mmio, MAIN_GAMCTRL_MODE, MAIN_GAMCTRL_QUEUE_SELECT); 1267 1268 return __xe_guc_upload(guc); 1269 } 1270 1271 static void guc_handle_mmio_msg(struct xe_guc *guc) 1272 { 1273 struct xe_gt *gt = guc_to_gt(guc); 1274 u32 msg; 1275 1276 if (IS_SRIOV_VF(guc_to_xe(guc))) 1277 return; 1278 1279 xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT); 1280 1281 msg = xe_mmio_read32(>->mmio, SOFT_SCRATCH(15)); 1282 msg &= XE_GUC_RECV_MSG_EXCEPTION | 1283 XE_GUC_RECV_MSG_CRASH_DUMP_POSTED; 1284 xe_mmio_write32(>->mmio, SOFT_SCRATCH(15), 0); 1285 1286 if (msg & XE_GUC_RECV_MSG_CRASH_DUMP_POSTED) 1287 xe_gt_err(gt, "Received early GuC crash dump notification!\n"); 1288 1289 if (msg & XE_GUC_RECV_MSG_EXCEPTION) 1290 xe_gt_err(gt, "Received early GuC exception notification!\n"); 1291 } 1292 1293 static void guc_enable_irq(struct xe_guc *guc) 1294 { 1295 struct xe_gt *gt = guc_to_gt(guc); 1296 u32 events = xe_gt_is_media_type(gt) ? 1297 REG_FIELD_PREP(ENGINE0_MASK, GUC_INTR_GUC2HOST) : 1298 REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST); 1299 1300 /* Primary GuC and media GuC share a single enable bit */ 1301 xe_mmio_write32(>->mmio, GUC_SG_INTR_ENABLE, 1302 REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST)); 1303 1304 /* 1305 * There are separate mask bits for primary and media GuCs, so use 1306 * a RMW operation to avoid clobbering the other GuC's setting. 1307 */ 1308 xe_mmio_rmw32(>->mmio, GUC_SG_INTR_MASK, events, 0); 1309 } 1310 1311 int xe_guc_enable_communication(struct xe_guc *guc) 1312 { 1313 struct xe_device *xe = guc_to_xe(guc); 1314 int err; 1315 1316 if (IS_SRIOV_VF(xe) && xe_device_has_memirq(xe)) { 1317 struct xe_gt *gt = guc_to_gt(guc); 1318 struct xe_tile *tile = gt_to_tile(gt); 1319 1320 err = xe_memirq_init_guc(&tile->memirq, guc); 1321 if (err) 1322 return err; 1323 } else { 1324 guc_enable_irq(guc); 1325 } 1326 1327 err = xe_guc_ct_enable(&guc->ct); 1328 if (err) 1329 return err; 1330 1331 guc_handle_mmio_msg(guc); 1332 1333 return 0; 1334 } 1335 1336 int xe_guc_suspend(struct xe_guc *guc) 1337 { 1338 struct xe_gt *gt = guc_to_gt(guc); 1339 u32 action[] = { 1340 XE_GUC_ACTION_CLIENT_SOFT_RESET, 1341 }; 1342 int ret; 1343 1344 ret = xe_guc_mmio_send(guc, action, ARRAY_SIZE(action)); 1345 if (ret) { 1346 xe_gt_err(gt, "GuC suspend failed: %pe\n", ERR_PTR(ret)); 1347 return ret; 1348 } 1349 1350 xe_guc_sanitize(guc); 1351 return 0; 1352 } 1353 1354 void xe_guc_notify(struct xe_guc *guc) 1355 { 1356 struct xe_gt *gt = guc_to_gt(guc); 1357 const u32 default_notify_data = 0; 1358 1359 /* 1360 * Both GUC_HOST_INTERRUPT and MED_GUC_HOST_INTERRUPT can pass 1361 * additional payload data to the GuC but this capability is not 1362 * used by the firmware yet. Use default value in the meantime. 1363 */ 1364 xe_mmio_write32(>->mmio, guc->notify_reg, default_notify_data); 1365 } 1366 1367 int xe_guc_auth_huc(struct xe_guc *guc, u32 rsa_addr) 1368 { 1369 u32 action[] = { 1370 XE_GUC_ACTION_AUTHENTICATE_HUC, 1371 rsa_addr 1372 }; 1373 1374 return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action)); 1375 } 1376 1377 int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request, 1378 u32 len, u32 *response_buf) 1379 { 1380 struct xe_device *xe = guc_to_xe(guc); 1381 struct xe_gt *gt = guc_to_gt(guc); 1382 struct xe_mmio *mmio = >->mmio; 1383 u32 header, reply; 1384 struct xe_reg reply_reg = xe_gt_is_media_type(gt) ? 1385 MED_VF_SW_FLAG(0) : VF_SW_FLAG(0); 1386 const u32 LAST_INDEX = VF_SW_FLAG_COUNT - 1; 1387 bool lost = false; 1388 int ret; 1389 int i; 1390 1391 BUILD_BUG_ON(VF_SW_FLAG_COUNT != MED_VF_SW_FLAG_COUNT); 1392 1393 xe_assert(xe, len); 1394 xe_assert(xe, len <= VF_SW_FLAG_COUNT); 1395 xe_assert(xe, len <= MED_VF_SW_FLAG_COUNT); 1396 xe_assert(xe, FIELD_GET(GUC_HXG_MSG_0_ORIGIN, request[0]) == 1397 GUC_HXG_ORIGIN_HOST); 1398 xe_assert(xe, FIELD_GET(GUC_HXG_MSG_0_TYPE, request[0]) == 1399 GUC_HXG_TYPE_REQUEST); 1400 1401 retry: 1402 /* Not in critical data-path, just do if else for GT type */ 1403 if (xe_gt_is_media_type(gt)) { 1404 for (i = 0; i < len; ++i) 1405 xe_mmio_write32(mmio, MED_VF_SW_FLAG(i), 1406 request[i]); 1407 xe_mmio_read32(mmio, MED_VF_SW_FLAG(LAST_INDEX)); 1408 } else { 1409 for (i = 0; i < len; ++i) 1410 xe_mmio_write32(mmio, VF_SW_FLAG(i), 1411 request[i]); 1412 xe_mmio_read32(mmio, VF_SW_FLAG(LAST_INDEX)); 1413 } 1414 1415 xe_guc_notify(guc); 1416 1417 ret = xe_mmio_wait32(mmio, reply_reg, GUC_HXG_MSG_0_ORIGIN, 1418 FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_GUC), 1419 50000, &reply, false); 1420 if (ret) { 1421 /* scratch registers might be cleared during FLR, try once more */ 1422 if (!reply && !lost) { 1423 xe_gt_dbg(gt, "GuC mmio request %#x: lost, trying again\n", request[0]); 1424 lost = true; 1425 goto retry; 1426 } 1427 timeout: 1428 xe_gt_err(gt, "GuC mmio request %#x: no reply %#x\n", 1429 request[0], reply); 1430 return ret; 1431 } 1432 1433 header = xe_mmio_read32(mmio, reply_reg); 1434 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == 1435 GUC_HXG_TYPE_NO_RESPONSE_BUSY) { 1436 /* 1437 * Once we got a BUSY reply we must wait again for the final 1438 * response but this time we can't use ORIGIN mask anymore. 1439 * To spot a right change in the reply, we take advantage that 1440 * response SUCCESS and FAILURE differ only by the single bit 1441 * and all other bits are set and can be used as a new mask. 1442 */ 1443 u32 resp_bits = GUC_HXG_TYPE_RESPONSE_SUCCESS & GUC_HXG_TYPE_RESPONSE_FAILURE; 1444 u32 resp_mask = FIELD_PREP(GUC_HXG_MSG_0_TYPE, resp_bits); 1445 1446 BUILD_BUG_ON(FIELD_MAX(GUC_HXG_MSG_0_TYPE) != GUC_HXG_TYPE_RESPONSE_SUCCESS); 1447 BUILD_BUG_ON((GUC_HXG_TYPE_RESPONSE_SUCCESS ^ GUC_HXG_TYPE_RESPONSE_FAILURE) != 1); 1448 1449 ret = xe_mmio_wait32(mmio, reply_reg, resp_mask, resp_mask, 1450 2000000, &header, false); 1451 1452 if (unlikely(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, header) != 1453 GUC_HXG_ORIGIN_GUC)) 1454 goto proto; 1455 if (unlikely(ret)) { 1456 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) != 1457 GUC_HXG_TYPE_NO_RESPONSE_BUSY) 1458 goto proto; 1459 goto timeout; 1460 } 1461 } 1462 1463 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == 1464 GUC_HXG_TYPE_NO_RESPONSE_RETRY) { 1465 u32 reason = FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, header); 1466 1467 xe_gt_dbg(gt, "GuC mmio request %#x: retrying, reason %#x\n", 1468 request[0], reason); 1469 goto retry; 1470 } 1471 1472 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == 1473 GUC_HXG_TYPE_RESPONSE_FAILURE) { 1474 u32 hint = FIELD_GET(GUC_HXG_FAILURE_MSG_0_HINT, header); 1475 u32 error = FIELD_GET(GUC_HXG_FAILURE_MSG_0_ERROR, header); 1476 1477 xe_gt_err(gt, "GuC mmio request %#x: failure %#x hint %#x\n", 1478 request[0], error, hint); 1479 return -ENXIO; 1480 } 1481 1482 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) != 1483 GUC_HXG_TYPE_RESPONSE_SUCCESS) { 1484 proto: 1485 xe_gt_err(gt, "GuC mmio request %#x: unexpected reply %#x\n", 1486 request[0], header); 1487 return -EPROTO; 1488 } 1489 1490 /* Just copy entire possible message response */ 1491 if (response_buf) { 1492 response_buf[0] = header; 1493 1494 for (i = 1; i < VF_SW_FLAG_COUNT; i++) { 1495 reply_reg.addr += sizeof(u32); 1496 response_buf[i] = xe_mmio_read32(mmio, reply_reg); 1497 } 1498 } 1499 1500 /* Use data from the GuC response as our return value */ 1501 return FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0, header); 1502 } 1503 ALLOW_ERROR_INJECTION(xe_guc_mmio_send_recv, ERRNO); 1504 1505 int xe_guc_mmio_send(struct xe_guc *guc, const u32 *request, u32 len) 1506 { 1507 return xe_guc_mmio_send_recv(guc, request, len, NULL); 1508 } 1509 1510 static int guc_self_cfg(struct xe_guc *guc, u16 key, u16 len, u64 val) 1511 { 1512 struct xe_device *xe = guc_to_xe(guc); 1513 u32 request[HOST2GUC_SELF_CFG_REQUEST_MSG_LEN] = { 1514 FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_HOST) | 1515 FIELD_PREP(GUC_HXG_MSG_0_TYPE, GUC_HXG_TYPE_REQUEST) | 1516 FIELD_PREP(GUC_HXG_REQUEST_MSG_0_ACTION, 1517 GUC_ACTION_HOST2GUC_SELF_CFG), 1518 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_KEY, key) | 1519 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_LEN, len), 1520 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_2_VALUE32, 1521 lower_32_bits(val)), 1522 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_3_VALUE64, 1523 upper_32_bits(val)), 1524 }; 1525 int ret; 1526 1527 xe_assert(xe, len <= 2); 1528 xe_assert(xe, len != 1 || !upper_32_bits(val)); 1529 1530 /* Self config must go over MMIO */ 1531 ret = xe_guc_mmio_send(guc, request, ARRAY_SIZE(request)); 1532 1533 if (unlikely(ret < 0)) 1534 return ret; 1535 if (unlikely(ret > 1)) 1536 return -EPROTO; 1537 if (unlikely(!ret)) 1538 return -ENOKEY; 1539 1540 return 0; 1541 } 1542 1543 int xe_guc_self_cfg32(struct xe_guc *guc, u16 key, u32 val) 1544 { 1545 return guc_self_cfg(guc, key, 1, val); 1546 } 1547 1548 int xe_guc_self_cfg64(struct xe_guc *guc, u16 key, u64 val) 1549 { 1550 return guc_self_cfg(guc, key, 2, val); 1551 } 1552 1553 static void xe_guc_sw_0_irq_handler(struct xe_guc *guc) 1554 { 1555 struct xe_gt *gt = guc_to_gt(guc); 1556 1557 if (IS_SRIOV_VF(gt_to_xe(gt))) 1558 xe_gt_sriov_vf_migrated_event_handler(gt); 1559 } 1560 1561 void xe_guc_irq_handler(struct xe_guc *guc, const u16 iir) 1562 { 1563 if (iir & GUC_INTR_GUC2HOST) 1564 xe_guc_ct_irq_handler(&guc->ct); 1565 1566 if (iir & GUC_INTR_SW_INT_0) 1567 xe_guc_sw_0_irq_handler(guc); 1568 } 1569 1570 void xe_guc_sanitize(struct xe_guc *guc) 1571 { 1572 xe_uc_fw_sanitize(&guc->fw); 1573 xe_guc_ct_disable(&guc->ct); 1574 xe_guc_submit_disable(guc); 1575 } 1576 1577 int xe_guc_reset_prepare(struct xe_guc *guc) 1578 { 1579 return xe_guc_submit_reset_prepare(guc); 1580 } 1581 1582 void xe_guc_reset_wait(struct xe_guc *guc) 1583 { 1584 xe_guc_submit_reset_wait(guc); 1585 } 1586 1587 void xe_guc_stop_prepare(struct xe_guc *guc) 1588 { 1589 if (!IS_SRIOV_VF(guc_to_xe(guc))) { 1590 int err; 1591 1592 err = xe_guc_pc_stop(&guc->pc); 1593 xe_gt_WARN(guc_to_gt(guc), err, "Failed to stop GuC PC: %pe\n", 1594 ERR_PTR(err)); 1595 } 1596 } 1597 1598 void xe_guc_stop(struct xe_guc *guc) 1599 { 1600 xe_guc_ct_stop(&guc->ct); 1601 1602 xe_guc_submit_stop(guc); 1603 } 1604 1605 int xe_guc_start(struct xe_guc *guc) 1606 { 1607 return xe_guc_submit_start(guc); 1608 } 1609 1610 void xe_guc_print_info(struct xe_guc *guc, struct drm_printer *p) 1611 { 1612 struct xe_gt *gt = guc_to_gt(guc); 1613 unsigned int fw_ref; 1614 u32 status; 1615 int i; 1616 1617 xe_uc_fw_print(&guc->fw, p); 1618 1619 if (!IS_SRIOV_VF(gt_to_xe(gt))) { 1620 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 1621 if (!fw_ref) 1622 return; 1623 1624 status = xe_mmio_read32(>->mmio, GUC_STATUS); 1625 1626 drm_printf(p, "\nGuC status 0x%08x:\n", status); 1627 drm_printf(p, "\tBootrom status = 0x%x\n", 1628 REG_FIELD_GET(GS_BOOTROM_MASK, status)); 1629 drm_printf(p, "\tuKernel status = 0x%x\n", 1630 REG_FIELD_GET(GS_UKERNEL_MASK, status)); 1631 drm_printf(p, "\tMIA Core status = 0x%x\n", 1632 REG_FIELD_GET(GS_MIA_MASK, status)); 1633 drm_printf(p, "\tLog level = %d\n", 1634 xe_guc_log_get_level(&guc->log)); 1635 1636 drm_puts(p, "\nScratch registers:\n"); 1637 for (i = 0; i < SOFT_SCRATCH_COUNT; i++) { 1638 drm_printf(p, "\t%2d: \t0x%x\n", 1639 i, xe_mmio_read32(>->mmio, SOFT_SCRATCH(i))); 1640 } 1641 1642 xe_force_wake_put(gt_to_fw(gt), fw_ref); 1643 } 1644 1645 drm_puts(p, "\n"); 1646 xe_guc_ct_print(&guc->ct, p, false); 1647 1648 drm_puts(p, "\n"); 1649 xe_guc_submit_print(guc, p); 1650 } 1651 1652 /** 1653 * xe_guc_declare_wedged() - Declare GuC wedged 1654 * @guc: the GuC object 1655 * 1656 * Wedge the GuC which stops all submission, saves desired debug state, and 1657 * cleans up anything which could timeout. 1658 */ 1659 void xe_guc_declare_wedged(struct xe_guc *guc) 1660 { 1661 xe_gt_assert(guc_to_gt(guc), guc_to_xe(guc)->wedged.mode); 1662 1663 xe_guc_reset_prepare(guc); 1664 xe_guc_ct_stop(&guc->ct); 1665 xe_guc_submit_wedge(guc); 1666 } 1667 1668 /** 1669 * xe_guc_using_main_gamctrl_queues() - Detect which reporting queues to use. 1670 * @guc: The GuC object 1671 * 1672 * For Xe3p and beyond, we want to program the hardware to use the 1673 * "Main GAMCTRL queue" rather than the legacy queue before we upload 1674 * the GuC firmware. This will allow the GuC to use a new set of 1675 * registers for pagefault handling and avoid some unnecessary 1676 * complications with MCR register range handling. 1677 * 1678 * Return: true if can use new main gamctrl queues. 1679 */ 1680 bool xe_guc_using_main_gamctrl_queues(struct xe_guc *guc) 1681 { 1682 struct xe_gt *gt = guc_to_gt(guc); 1683 1684 /* 1685 * For Xe3p media gt (35), the GuC and the CS subunits may be still Xe3 1686 * that lacks the Main GAMCTRL support. Reserved bits from the GMD_ID 1687 * inform the IP version of the subunits. 1688 */ 1689 if (xe_gt_is_media_type(gt) && MEDIA_VER(gt_to_xe(gt)) == 35) { 1690 u32 val = xe_mmio_read32(>->mmio, GMD_ID); 1691 u32 subip = REG_FIELD_GET(GMD_ID_SUBIP_FLAG_MASK, val); 1692 1693 if (!subip) 1694 return true; 1695 1696 xe_gt_WARN(gt, subip != 1, 1697 "GMD_ID has unknown value in the SUBIP_FLAG field - 0x%x\n", 1698 subip); 1699 1700 return false; 1701 } 1702 1703 return GT_VER(gt) >= 35; 1704 } 1705 1706 #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST) 1707 #include "tests/xe_guc_g2g_test.c" 1708 #endif 1709