1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2014-2018 Broadcom */ 3 4 /** 5 * DOC: Broadcom V3D Graphics Driver 6 * 7 * This driver supports the Broadcom V3D 3.3 and 4.1 OpenGL ES GPUs. 8 * For V3D 2.x support, see the VC4 driver. 9 * 10 * The V3D GPU includes a tiled render (composed of a bin and render 11 * pipelines), the TFU (texture formatting unit), and the CSD (compute 12 * shader dispatch). 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/device.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/io.h> 19 #include <linux/module.h> 20 #include <linux/of.h> 21 #include <linux/of_platform.h> 22 #include <linux/platform_device.h> 23 #include <linux/sched/clock.h> 24 #include <linux/reset.h> 25 26 #include <drm/drm_drv.h> 27 #include <drm/drm_managed.h> 28 #include <drm/drm_print.h> 29 #include <uapi/drm/v3d_drm.h> 30 31 #include "v3d_drv.h" 32 #include "v3d_regs.h" 33 34 #define DRIVER_NAME "v3d" 35 #define DRIVER_DESC "Broadcom V3D graphics" 36 #define DRIVER_MAJOR 1 37 #define DRIVER_MINOR 0 38 #define DRIVER_PATCHLEVEL 0 39 40 /* Only expose the `super_pages` modparam if THP is enabled. */ 41 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 42 bool super_pages = true; 43 module_param_named(super_pages, super_pages, bool, 0400); 44 MODULE_PARM_DESC(super_pages, "Enable/Disable Super Pages support."); 45 #endif 46 47 static int v3d_get_param_ioctl(struct drm_device *dev, void *data, 48 struct drm_file *file_priv) 49 { 50 struct v3d_file_priv *v3d_priv = file_priv->driver_priv; 51 struct v3d_dev *v3d = to_v3d_dev(dev); 52 struct drm_v3d_get_param *args = data; 53 static const u32 reg_map[] = { 54 [DRM_V3D_PARAM_V3D_UIFCFG] = V3D_HUB_UIFCFG, 55 [DRM_V3D_PARAM_V3D_HUB_IDENT1] = V3D_HUB_IDENT1, 56 [DRM_V3D_PARAM_V3D_HUB_IDENT2] = V3D_HUB_IDENT2, 57 [DRM_V3D_PARAM_V3D_HUB_IDENT3] = V3D_HUB_IDENT3, 58 [DRM_V3D_PARAM_V3D_CORE0_IDENT0] = V3D_CTL_IDENT0, 59 [DRM_V3D_PARAM_V3D_CORE0_IDENT1] = V3D_CTL_IDENT1, 60 [DRM_V3D_PARAM_V3D_CORE0_IDENT2] = V3D_CTL_IDENT2, 61 }; 62 63 if (args->pad != 0) 64 return -EINVAL; 65 66 /* Note that DRM_V3D_PARAM_V3D_CORE0_IDENT0 is 0, so we need 67 * to explicitly allow it in the "the register in our 68 * parameter map" check. 69 */ 70 if (args->param < ARRAY_SIZE(reg_map) && 71 (reg_map[args->param] || 72 args->param == DRM_V3D_PARAM_V3D_CORE0_IDENT0)) { 73 u32 offset = reg_map[args->param]; 74 75 if (args->value != 0) 76 return -EINVAL; 77 78 if (args->param >= DRM_V3D_PARAM_V3D_CORE0_IDENT0 && 79 args->param <= DRM_V3D_PARAM_V3D_CORE0_IDENT2) { 80 args->value = V3D_CORE_READ(0, offset); 81 } else { 82 args->value = V3D_READ(offset); 83 } 84 return 0; 85 } 86 87 switch (args->param) { 88 case DRM_V3D_PARAM_SUPPORTS_TFU: 89 args->value = 1; 90 return 0; 91 case DRM_V3D_PARAM_SUPPORTS_CSD: 92 args->value = v3d_has_csd(v3d); 93 return 0; 94 case DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH: 95 args->value = 1; 96 return 0; 97 case DRM_V3D_PARAM_SUPPORTS_PERFMON: 98 args->value = (v3d->ver >= V3D_GEN_41); 99 return 0; 100 case DRM_V3D_PARAM_SUPPORTS_MULTISYNC_EXT: 101 args->value = 1; 102 return 0; 103 case DRM_V3D_PARAM_SUPPORTS_CPU_QUEUE: 104 args->value = 1; 105 return 0; 106 case DRM_V3D_PARAM_MAX_PERF_COUNTERS: 107 args->value = v3d->perfmon_info.max_counters; 108 return 0; 109 case DRM_V3D_PARAM_SUPPORTS_SUPER_PAGES: 110 args->value = !!v3d->gemfs; 111 return 0; 112 case DRM_V3D_PARAM_GLOBAL_RESET_COUNTER: 113 mutex_lock(&v3d->reset_lock); 114 args->value = v3d->reset_counter; 115 mutex_unlock(&v3d->reset_lock); 116 return 0; 117 case DRM_V3D_PARAM_CONTEXT_RESET_COUNTER: 118 mutex_lock(&v3d->reset_lock); 119 args->value = v3d_priv->reset_counter; 120 mutex_unlock(&v3d->reset_lock); 121 return 0; 122 default: 123 DRM_DEBUG("Unknown parameter %d\n", args->param); 124 return -EINVAL; 125 } 126 } 127 128 static int 129 v3d_open(struct drm_device *dev, struct drm_file *file) 130 { 131 struct v3d_dev *v3d = to_v3d_dev(dev); 132 struct v3d_file_priv *v3d_priv; 133 struct drm_gpu_scheduler *sched; 134 int i; 135 136 v3d_priv = kzalloc(sizeof(*v3d_priv), GFP_KERNEL); 137 if (!v3d_priv) 138 return -ENOMEM; 139 140 v3d_priv->v3d = v3d; 141 142 for (i = 0; i < V3D_MAX_QUEUES; i++) { 143 sched = &v3d->queue[i].sched; 144 drm_sched_entity_init(&v3d_priv->sched_entity[i], 145 DRM_SCHED_PRIORITY_NORMAL, &sched, 146 1, NULL); 147 148 memset(&v3d_priv->stats[i], 0, sizeof(v3d_priv->stats[i])); 149 seqcount_init(&v3d_priv->stats[i].lock); 150 } 151 152 v3d_perfmon_open_file(v3d_priv); 153 file->driver_priv = v3d_priv; 154 155 return 0; 156 } 157 158 static void 159 v3d_postclose(struct drm_device *dev, struct drm_file *file) 160 { 161 struct v3d_dev *v3d = to_v3d_dev(dev); 162 struct v3d_file_priv *v3d_priv = file->driver_priv; 163 unsigned long irqflags; 164 enum v3d_queue q; 165 166 for (q = 0; q < V3D_MAX_QUEUES; q++) { 167 struct v3d_queue_state *queue = &v3d->queue[q]; 168 struct v3d_job *job = queue->active_job; 169 170 drm_sched_entity_destroy(&v3d_priv->sched_entity[q]); 171 172 if (job && job->base.entity == &v3d_priv->sched_entity[q]) { 173 spin_lock_irqsave(&queue->queue_lock, irqflags); 174 job->file_priv = NULL; 175 spin_unlock_irqrestore(&queue->queue_lock, irqflags); 176 } 177 } 178 179 v3d_perfmon_close_file(v3d_priv); 180 kfree(v3d_priv); 181 } 182 183 void v3d_get_stats(const struct v3d_stats *stats, u64 timestamp, 184 u64 *active_runtime, u64 *jobs_completed) 185 { 186 unsigned int seq; 187 188 do { 189 seq = read_seqcount_begin(&stats->lock); 190 *active_runtime = stats->enabled_ns; 191 if (stats->start_ns) 192 *active_runtime += timestamp - stats->start_ns; 193 *jobs_completed = stats->jobs_completed; 194 } while (read_seqcount_retry(&stats->lock, seq)); 195 } 196 197 static void v3d_show_fdinfo(struct drm_printer *p, struct drm_file *file) 198 { 199 struct v3d_file_priv *file_priv = file->driver_priv; 200 u64 timestamp = local_clock(); 201 enum v3d_queue queue; 202 203 for (queue = 0; queue < V3D_MAX_QUEUES; queue++) { 204 struct v3d_stats *stats = &file_priv->stats[queue]; 205 u64 active_runtime, jobs_completed; 206 207 v3d_get_stats(stats, timestamp, &active_runtime, &jobs_completed); 208 209 /* Note that, in case of a GPU reset, the time spent during an 210 * attempt of executing the job is not computed in the runtime. 211 */ 212 drm_printf(p, "drm-engine-%s: \t%llu ns\n", 213 v3d_queue_to_string(queue), active_runtime); 214 215 /* Note that we only count jobs that completed. Therefore, jobs 216 * that were resubmitted due to a GPU reset are not computed. 217 */ 218 drm_printf(p, "v3d-jobs-%s: \t%llu jobs\n", 219 v3d_queue_to_string(queue), jobs_completed); 220 } 221 222 drm_show_memory_stats(p, file); 223 } 224 225 static const struct file_operations v3d_drm_fops = { 226 .owner = THIS_MODULE, 227 DRM_GEM_FOPS, 228 .show_fdinfo = drm_show_fdinfo, 229 }; 230 231 /* DRM_AUTH is required on SUBMIT_CL for now, while we don't have GMP 232 * protection between clients. Note that render nodes would be 233 * able to submit CLs that could access BOs from clients authenticated 234 * with the master node. The TFU doesn't use the GMP, so it would 235 * need to stay DRM_AUTH until we do buffer size/offset validation. 236 */ 237 static const struct drm_ioctl_desc v3d_drm_ioctls[] = { 238 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CL, v3d_submit_cl_ioctl, DRM_RENDER_ALLOW | DRM_AUTH), 239 DRM_IOCTL_DEF_DRV(V3D_WAIT_BO, v3d_wait_bo_ioctl, DRM_RENDER_ALLOW), 240 DRM_IOCTL_DEF_DRV(V3D_CREATE_BO, v3d_create_bo_ioctl, DRM_RENDER_ALLOW), 241 DRM_IOCTL_DEF_DRV(V3D_MMAP_BO, v3d_mmap_bo_ioctl, DRM_RENDER_ALLOW), 242 DRM_IOCTL_DEF_DRV(V3D_GET_PARAM, v3d_get_param_ioctl, DRM_RENDER_ALLOW), 243 DRM_IOCTL_DEF_DRV(V3D_GET_BO_OFFSET, v3d_get_bo_offset_ioctl, DRM_RENDER_ALLOW), 244 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_TFU, v3d_submit_tfu_ioctl, DRM_RENDER_ALLOW | DRM_AUTH), 245 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CSD, v3d_submit_csd_ioctl, DRM_RENDER_ALLOW | DRM_AUTH), 246 DRM_IOCTL_DEF_DRV(V3D_PERFMON_CREATE, v3d_perfmon_create_ioctl, DRM_RENDER_ALLOW), 247 DRM_IOCTL_DEF_DRV(V3D_PERFMON_DESTROY, v3d_perfmon_destroy_ioctl, DRM_RENDER_ALLOW), 248 DRM_IOCTL_DEF_DRV(V3D_PERFMON_GET_VALUES, v3d_perfmon_get_values_ioctl, DRM_RENDER_ALLOW), 249 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CPU, v3d_submit_cpu_ioctl, DRM_RENDER_ALLOW | DRM_AUTH), 250 DRM_IOCTL_DEF_DRV(V3D_PERFMON_GET_COUNTER, v3d_perfmon_get_counter_ioctl, DRM_RENDER_ALLOW), 251 DRM_IOCTL_DEF_DRV(V3D_PERFMON_SET_GLOBAL, v3d_perfmon_set_global_ioctl, DRM_RENDER_ALLOW), 252 }; 253 254 static const struct drm_driver v3d_drm_driver = { 255 .driver_features = (DRIVER_GEM | 256 DRIVER_RENDER | 257 DRIVER_SYNCOBJ), 258 259 .open = v3d_open, 260 .postclose = v3d_postclose, 261 262 #if defined(CONFIG_DEBUG_FS) 263 .debugfs_init = v3d_debugfs_init, 264 #endif 265 266 .gem_create_object = v3d_create_object, 267 .gem_prime_import_sg_table = v3d_prime_import_sg_table, 268 269 .ioctls = v3d_drm_ioctls, 270 .num_ioctls = ARRAY_SIZE(v3d_drm_ioctls), 271 .fops = &v3d_drm_fops, 272 .show_fdinfo = v3d_show_fdinfo, 273 274 .name = DRIVER_NAME, 275 .desc = DRIVER_DESC, 276 .major = DRIVER_MAJOR, 277 .minor = DRIVER_MINOR, 278 .patchlevel = DRIVER_PATCHLEVEL, 279 }; 280 281 static const struct of_device_id v3d_of_match[] = { 282 { .compatible = "brcm,2711-v3d", .data = (void *)V3D_GEN_42 }, 283 { .compatible = "brcm,2712-v3d", .data = (void *)V3D_GEN_71 }, 284 { .compatible = "brcm,7268-v3d", .data = (void *)V3D_GEN_33 }, 285 { .compatible = "brcm,7278-v3d", .data = (void *)V3D_GEN_41 }, 286 {}, 287 }; 288 MODULE_DEVICE_TABLE(of, v3d_of_match); 289 290 static void 291 v3d_idle_sms(struct v3d_dev *v3d) 292 { 293 if (v3d->ver < V3D_GEN_71) 294 return; 295 296 V3D_SMS_WRITE(V3D_SMS_TEE_CS, V3D_SMS_CLEAR_POWER_OFF); 297 298 if (wait_for((V3D_GET_FIELD(V3D_SMS_READ(V3D_SMS_TEE_CS), 299 V3D_SMS_STATE) == V3D_SMS_IDLE), 100)) { 300 DRM_ERROR("Failed to power up SMS\n"); 301 } 302 303 v3d_reset_sms(v3d); 304 } 305 306 static void 307 v3d_power_off_sms(struct v3d_dev *v3d) 308 { 309 if (v3d->ver < V3D_GEN_71) 310 return; 311 312 V3D_SMS_WRITE(V3D_SMS_TEE_CS, V3D_SMS_POWER_OFF); 313 314 if (wait_for((V3D_GET_FIELD(V3D_SMS_READ(V3D_SMS_TEE_CS), 315 V3D_SMS_STATE) == V3D_SMS_POWER_OFF_STATE), 100)) { 316 DRM_ERROR("Failed to power off SMS\n"); 317 } 318 } 319 320 static int 321 map_regs(struct v3d_dev *v3d, void __iomem **regs, const char *name) 322 { 323 *regs = devm_platform_ioremap_resource_byname(v3d_to_pdev(v3d), name); 324 return PTR_ERR_OR_ZERO(*regs); 325 } 326 327 static int v3d_platform_drm_probe(struct platform_device *pdev) 328 { 329 struct device *dev = &pdev->dev; 330 struct drm_device *drm; 331 struct v3d_dev *v3d; 332 enum v3d_gen gen; 333 int ret; 334 u32 mmu_debug; 335 u32 ident1, ident3; 336 u64 mask; 337 338 v3d = devm_drm_dev_alloc(dev, &v3d_drm_driver, struct v3d_dev, drm); 339 if (IS_ERR(v3d)) 340 return PTR_ERR(v3d); 341 342 drm = &v3d->drm; 343 344 platform_set_drvdata(pdev, drm); 345 346 gen = (uintptr_t)of_device_get_match_data(dev); 347 v3d->ver = gen; 348 349 ret = map_regs(v3d, &v3d->hub_regs, "hub"); 350 if (ret) 351 return ret; 352 353 ret = map_regs(v3d, &v3d->core_regs[0], "core0"); 354 if (ret) 355 return ret; 356 357 if (v3d->ver >= V3D_GEN_71) { 358 ret = map_regs(v3d, &v3d->sms_regs, "sms"); 359 if (ret) 360 return ret; 361 } 362 363 v3d->clk = devm_clk_get_optional(dev, NULL); 364 if (IS_ERR(v3d->clk)) 365 return dev_err_probe(dev, PTR_ERR(v3d->clk), "Failed to get V3D clock\n"); 366 367 ret = clk_prepare_enable(v3d->clk); 368 if (ret) { 369 dev_err(&pdev->dev, "Couldn't enable the V3D clock\n"); 370 return ret; 371 } 372 373 v3d_idle_sms(v3d); 374 375 mmu_debug = V3D_READ(V3D_MMU_DEBUG_INFO); 376 mask = DMA_BIT_MASK(30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_PA_WIDTH)); 377 ret = dma_set_mask_and_coherent(dev, mask); 378 if (ret) 379 goto clk_disable; 380 381 v3d->va_width = 30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_VA_WIDTH); 382 383 ident1 = V3D_READ(V3D_HUB_IDENT1); 384 v3d->ver = (V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER) * 10 + 385 V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_REV)); 386 /* Make sure that the V3D tech version retrieved from the HW is equal 387 * to the one advertised by the device tree. 388 */ 389 WARN_ON(v3d->ver != gen); 390 391 v3d->cores = V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_NCORES); 392 WARN_ON(v3d->cores > 1); /* multicore not yet implemented */ 393 394 ident3 = V3D_READ(V3D_HUB_IDENT3); 395 v3d->rev = V3D_GET_FIELD(ident3, V3D_HUB_IDENT3_IPREV); 396 397 v3d_perfmon_init(v3d); 398 399 v3d->reset = devm_reset_control_get_exclusive(dev, NULL); 400 if (IS_ERR(v3d->reset)) { 401 ret = PTR_ERR(v3d->reset); 402 403 if (ret == -EPROBE_DEFER) 404 goto clk_disable; 405 406 v3d->reset = NULL; 407 ret = map_regs(v3d, &v3d->bridge_regs, "bridge"); 408 if (ret) { 409 dev_err(dev, 410 "Failed to get reset control or bridge regs\n"); 411 goto clk_disable; 412 } 413 } 414 415 if (v3d->ver < V3D_GEN_41) { 416 ret = map_regs(v3d, &v3d->gca_regs, "gca"); 417 if (ret) 418 goto clk_disable; 419 } 420 421 v3d->mmu_scratch = dma_alloc_wc(dev, 4096, &v3d->mmu_scratch_paddr, 422 GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO); 423 if (!v3d->mmu_scratch) { 424 dev_err(dev, "Failed to allocate MMU scratch page\n"); 425 ret = -ENOMEM; 426 goto clk_disable; 427 } 428 429 ret = v3d_gem_init(drm); 430 if (ret) 431 goto dma_free; 432 433 ret = v3d_irq_init(v3d); 434 if (ret) 435 goto gem_destroy; 436 437 ret = drm_dev_register(drm, 0); 438 if (ret) 439 goto irq_disable; 440 441 ret = v3d_sysfs_init(dev); 442 if (ret) 443 goto drm_unregister; 444 445 return 0; 446 447 drm_unregister: 448 drm_dev_unregister(drm); 449 irq_disable: 450 v3d_irq_disable(v3d); 451 gem_destroy: 452 v3d_gem_destroy(drm); 453 dma_free: 454 dma_free_wc(dev, 4096, v3d->mmu_scratch, v3d->mmu_scratch_paddr); 455 clk_disable: 456 clk_disable_unprepare(v3d->clk); 457 return ret; 458 } 459 460 static void v3d_platform_drm_remove(struct platform_device *pdev) 461 { 462 struct drm_device *drm = platform_get_drvdata(pdev); 463 struct v3d_dev *v3d = to_v3d_dev(drm); 464 struct device *dev = &pdev->dev; 465 466 v3d_sysfs_destroy(dev); 467 468 drm_dev_unregister(drm); 469 470 v3d_gem_destroy(drm); 471 472 dma_free_wc(v3d->drm.dev, 4096, v3d->mmu_scratch, 473 v3d->mmu_scratch_paddr); 474 475 v3d_power_off_sms(v3d); 476 477 clk_disable_unprepare(v3d->clk); 478 } 479 480 static struct platform_driver v3d_platform_driver = { 481 .probe = v3d_platform_drm_probe, 482 .remove = v3d_platform_drm_remove, 483 .driver = { 484 .name = "v3d", 485 .of_match_table = v3d_of_match, 486 }, 487 }; 488 489 module_platform_driver(v3d_platform_driver); 490 491 MODULE_ALIAS("platform:v3d-drm"); 492 MODULE_DESCRIPTION("Broadcom V3D DRM Driver"); 493 MODULE_AUTHOR("Eric Anholt <eric@anholt.net>"); 494 MODULE_LICENSE("GPL v2"); 495