1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ 4 * Author: Jyri Sarha <jsarha@ti.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/delay.h> 9 #include <linux/dma-mapping.h> 10 #include <linux/err.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/kernel.h> 14 #include <linux/media-bus-format.h> 15 #include <linux/module.h> 16 #include <linux/mfd/syscon.h> 17 #include <linux/of.h> 18 #include <linux/of_graph.h> 19 #include <linux/of_device.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/regmap.h> 23 #include <linux/sys_soc.h> 24 25 #include <drm/drm_blend.h> 26 #include <drm/drm_fourcc.h> 27 #include <drm/drm_fb_dma_helper.h> 28 #include <drm/drm_framebuffer.h> 29 #include <drm/drm_gem_dma_helper.h> 30 #include <drm/drm_panel.h> 31 32 #include "tidss_crtc.h" 33 #include "tidss_dispc.h" 34 #include "tidss_drv.h" 35 #include "tidss_irq.h" 36 #include "tidss_plane.h" 37 38 #include "tidss_dispc_regs.h" 39 #include "tidss_scale_coefs.h" 40 41 static const u16 tidss_k2g_common_regs[DISPC_COMMON_REG_TABLE_LEN] = { 42 [DSS_REVISION_OFF] = 0x00, 43 [DSS_SYSCONFIG_OFF] = 0x04, 44 [DSS_SYSSTATUS_OFF] = 0x08, 45 [DISPC_IRQ_EOI_OFF] = 0x20, 46 [DISPC_IRQSTATUS_RAW_OFF] = 0x24, 47 [DISPC_IRQSTATUS_OFF] = 0x28, 48 [DISPC_IRQENABLE_SET_OFF] = 0x2c, 49 [DISPC_IRQENABLE_CLR_OFF] = 0x30, 50 51 [DISPC_GLOBAL_MFLAG_ATTRIBUTE_OFF] = 0x40, 52 [DISPC_GLOBAL_BUFFER_OFF] = 0x44, 53 54 [DISPC_DBG_CONTROL_OFF] = 0x4c, 55 [DISPC_DBG_STATUS_OFF] = 0x50, 56 57 [DISPC_CLKGATING_DISABLE_OFF] = 0x54, 58 }; 59 60 const struct dispc_features dispc_k2g_feats = { 61 .min_pclk_khz = 4375, 62 63 .max_pclk_khz = { 64 [DISPC_VP_DPI] = 150000, 65 }, 66 67 /* 68 * XXX According TRM the RGB input buffer width up to 2560 should 69 * work on 3 taps, but in practice it only works up to 1280. 70 */ 71 .scaling = { 72 .in_width_max_5tap_rgb = 1280, 73 .in_width_max_3tap_rgb = 1280, 74 .in_width_max_5tap_yuv = 2560, 75 .in_width_max_3tap_yuv = 2560, 76 .upscale_limit = 16, 77 .downscale_limit_5tap = 4, 78 .downscale_limit_3tap = 2, 79 /* 80 * The max supported pixel inc value is 255. The value 81 * of pixel inc is calculated like this: 1+(xinc-1)*bpp. 82 * The maximum bpp of all formats supported by the HW 83 * is 8. So the maximum supported xinc value is 32, 84 * because 1+(32-1)*8 < 255 < 1+(33-1)*4. 85 */ 86 .xinc_max = 32, 87 }, 88 89 .subrev = DISPC_K2G, 90 91 .common = "common", 92 93 .common_regs = tidss_k2g_common_regs, 94 95 .num_vps = 1, 96 .vp_name = { "vp1" }, 97 .ovr_name = { "ovr1" }, 98 .vpclk_name = { "vp1" }, 99 .vp_bus_type = { DISPC_VP_DPI }, 100 101 .vp_feat = { .color = { 102 .has_ctm = true, 103 .gamma_size = 256, 104 .gamma_type = TIDSS_GAMMA_8BIT, 105 }, 106 }, 107 108 .num_planes = 1, 109 .vid_name = { "vid1" }, 110 .vid_lite = { false }, 111 .vid_order = { 0 }, 112 }; 113 114 static const u16 tidss_am65x_common_regs[DISPC_COMMON_REG_TABLE_LEN] = { 115 [DSS_REVISION_OFF] = 0x4, 116 [DSS_SYSCONFIG_OFF] = 0x8, 117 [DSS_SYSSTATUS_OFF] = 0x20, 118 [DISPC_IRQ_EOI_OFF] = 0x24, 119 [DISPC_IRQSTATUS_RAW_OFF] = 0x28, 120 [DISPC_IRQSTATUS_OFF] = 0x2c, 121 [DISPC_IRQENABLE_SET_OFF] = 0x30, 122 [DISPC_IRQENABLE_CLR_OFF] = 0x40, 123 [DISPC_VID_IRQENABLE_OFF] = 0x44, 124 [DISPC_VID_IRQSTATUS_OFF] = 0x58, 125 [DISPC_VP_IRQENABLE_OFF] = 0x70, 126 [DISPC_VP_IRQSTATUS_OFF] = 0x7c, 127 128 [WB_IRQENABLE_OFF] = 0x88, 129 [WB_IRQSTATUS_OFF] = 0x8c, 130 131 [DISPC_GLOBAL_MFLAG_ATTRIBUTE_OFF] = 0x90, 132 [DISPC_GLOBAL_OUTPUT_ENABLE_OFF] = 0x94, 133 [DISPC_GLOBAL_BUFFER_OFF] = 0x98, 134 [DSS_CBA_CFG_OFF] = 0x9c, 135 [DISPC_DBG_CONTROL_OFF] = 0xa0, 136 [DISPC_DBG_STATUS_OFF] = 0xa4, 137 [DISPC_CLKGATING_DISABLE_OFF] = 0xa8, 138 [DISPC_SECURE_DISABLE_OFF] = 0xac, 139 }; 140 141 const struct dispc_features dispc_am65x_feats = { 142 .max_pclk_khz = { 143 [DISPC_VP_DPI] = 165000, 144 [DISPC_VP_OLDI] = 165000, 145 }, 146 147 .scaling = { 148 .in_width_max_5tap_rgb = 1280, 149 .in_width_max_3tap_rgb = 2560, 150 .in_width_max_5tap_yuv = 2560, 151 .in_width_max_3tap_yuv = 4096, 152 .upscale_limit = 16, 153 .downscale_limit_5tap = 4, 154 .downscale_limit_3tap = 2, 155 /* 156 * The max supported pixel inc value is 255. The value 157 * of pixel inc is calculated like this: 1+(xinc-1)*bpp. 158 * The maximum bpp of all formats supported by the HW 159 * is 8. So the maximum supported xinc value is 32, 160 * because 1+(32-1)*8 < 255 < 1+(33-1)*4. 161 */ 162 .xinc_max = 32, 163 }, 164 165 .subrev = DISPC_AM65X, 166 167 .common = "common", 168 .common_regs = tidss_am65x_common_regs, 169 170 .num_vps = 2, 171 .vp_name = { "vp1", "vp2" }, 172 .ovr_name = { "ovr1", "ovr2" }, 173 .vpclk_name = { "vp1", "vp2" }, 174 .vp_bus_type = { DISPC_VP_OLDI, DISPC_VP_DPI }, 175 176 .vp_feat = { .color = { 177 .has_ctm = true, 178 .gamma_size = 256, 179 .gamma_type = TIDSS_GAMMA_8BIT, 180 }, 181 }, 182 183 .num_planes = 2, 184 /* note: vid is plane_id 0 and vidl1 is plane_id 1 */ 185 .vid_name = { "vid", "vidl1" }, 186 .vid_lite = { false, true, }, 187 .vid_order = { 1, 0 }, 188 }; 189 190 static const u16 tidss_j721e_common_regs[DISPC_COMMON_REG_TABLE_LEN] = { 191 [DSS_REVISION_OFF] = 0x4, 192 [DSS_SYSCONFIG_OFF] = 0x8, 193 [DSS_SYSSTATUS_OFF] = 0x20, 194 [DISPC_IRQ_EOI_OFF] = 0x80, 195 [DISPC_IRQSTATUS_RAW_OFF] = 0x28, 196 [DISPC_IRQSTATUS_OFF] = 0x2c, 197 [DISPC_IRQENABLE_SET_OFF] = 0x30, 198 [DISPC_IRQENABLE_CLR_OFF] = 0x34, 199 [DISPC_VID_IRQENABLE_OFF] = 0x38, 200 [DISPC_VID_IRQSTATUS_OFF] = 0x48, 201 [DISPC_VP_IRQENABLE_OFF] = 0x58, 202 [DISPC_VP_IRQSTATUS_OFF] = 0x68, 203 204 [WB_IRQENABLE_OFF] = 0x78, 205 [WB_IRQSTATUS_OFF] = 0x7c, 206 207 [DISPC_GLOBAL_MFLAG_ATTRIBUTE_OFF] = 0x98, 208 [DISPC_GLOBAL_OUTPUT_ENABLE_OFF] = 0x9c, 209 [DISPC_GLOBAL_BUFFER_OFF] = 0xa0, 210 [DSS_CBA_CFG_OFF] = 0xa4, 211 [DISPC_DBG_CONTROL_OFF] = 0xa8, 212 [DISPC_DBG_STATUS_OFF] = 0xac, 213 [DISPC_CLKGATING_DISABLE_OFF] = 0xb0, 214 [DISPC_SECURE_DISABLE_OFF] = 0x90, 215 216 [FBDC_REVISION_1_OFF] = 0xb8, 217 [FBDC_REVISION_2_OFF] = 0xbc, 218 [FBDC_REVISION_3_OFF] = 0xc0, 219 [FBDC_REVISION_4_OFF] = 0xc4, 220 [FBDC_REVISION_5_OFF] = 0xc8, 221 [FBDC_REVISION_6_OFF] = 0xcc, 222 [FBDC_COMMON_CONTROL_OFF] = 0xd0, 223 [FBDC_CONSTANT_COLOR_0_OFF] = 0xd4, 224 [FBDC_CONSTANT_COLOR_1_OFF] = 0xd8, 225 [DISPC_CONNECTIONS_OFF] = 0xe4, 226 [DISPC_MSS_VP1_OFF] = 0xe8, 227 [DISPC_MSS_VP3_OFF] = 0xec, 228 }; 229 230 const struct dispc_features dispc_j721e_feats = { 231 .max_pclk_khz = { 232 [DISPC_VP_DPI] = 170000, 233 [DISPC_VP_INTERNAL] = 600000, 234 }, 235 236 .scaling = { 237 .in_width_max_5tap_rgb = 2048, 238 .in_width_max_3tap_rgb = 4096, 239 .in_width_max_5tap_yuv = 4096, 240 .in_width_max_3tap_yuv = 4096, 241 .upscale_limit = 16, 242 .downscale_limit_5tap = 4, 243 .downscale_limit_3tap = 2, 244 /* 245 * The max supported pixel inc value is 255. The value 246 * of pixel inc is calculated like this: 1+(xinc-1)*bpp. 247 * The maximum bpp of all formats supported by the HW 248 * is 8. So the maximum supported xinc value is 32, 249 * because 1+(32-1)*8 < 255 < 1+(33-1)*4. 250 */ 251 .xinc_max = 32, 252 }, 253 254 .subrev = DISPC_J721E, 255 256 .common = "common_m", 257 .common_regs = tidss_j721e_common_regs, 258 259 .num_vps = 4, 260 .vp_name = { "vp1", "vp2", "vp3", "vp4" }, 261 .ovr_name = { "ovr1", "ovr2", "ovr3", "ovr4" }, 262 .vpclk_name = { "vp1", "vp2", "vp3", "vp4" }, 263 /* Currently hard coded VP routing (see dispc_initial_config()) */ 264 .vp_bus_type = { DISPC_VP_INTERNAL, DISPC_VP_DPI, 265 DISPC_VP_INTERNAL, DISPC_VP_DPI, }, 266 .vp_feat = { .color = { 267 .has_ctm = true, 268 .gamma_size = 1024, 269 .gamma_type = TIDSS_GAMMA_10BIT, 270 }, 271 }, 272 .num_planes = 4, 273 .vid_name = { "vid1", "vidl1", "vid2", "vidl2" }, 274 .vid_lite = { 0, 1, 0, 1, }, 275 .vid_order = { 1, 3, 0, 2 }, 276 }; 277 278 const struct dispc_features dispc_am625_feats = { 279 .max_pclk_khz = { 280 [DISPC_VP_DPI] = 165000, 281 [DISPC_VP_INTERNAL] = 170000, 282 }, 283 284 .scaling = { 285 .in_width_max_5tap_rgb = 1280, 286 .in_width_max_3tap_rgb = 2560, 287 .in_width_max_5tap_yuv = 2560, 288 .in_width_max_3tap_yuv = 4096, 289 .upscale_limit = 16, 290 .downscale_limit_5tap = 4, 291 .downscale_limit_3tap = 2, 292 /* 293 * The max supported pixel inc value is 255. The value 294 * of pixel inc is calculated like this: 1+(xinc-1)*bpp. 295 * The maximum bpp of all formats supported by the HW 296 * is 8. So the maximum supported xinc value is 32, 297 * because 1+(32-1)*8 < 255 < 1+(33-1)*4. 298 */ 299 .xinc_max = 32, 300 }, 301 302 .subrev = DISPC_AM625, 303 304 .common = "common", 305 .common_regs = tidss_am65x_common_regs, 306 307 .num_vps = 2, 308 .vp_name = { "vp1", "vp2" }, 309 .ovr_name = { "ovr1", "ovr2" }, 310 .vpclk_name = { "vp1", "vp2" }, 311 .vp_bus_type = { DISPC_VP_INTERNAL, DISPC_VP_DPI }, 312 313 .vp_feat = { .color = { 314 .has_ctm = true, 315 .gamma_size = 256, 316 .gamma_type = TIDSS_GAMMA_8BIT, 317 }, 318 }, 319 320 .num_planes = 2, 321 /* note: vid is plane_id 0 and vidl1 is plane_id 1 */ 322 .vid_name = { "vid", "vidl1" }, 323 .vid_lite = { false, true, }, 324 .vid_order = { 1, 0 }, 325 }; 326 327 static const u16 *dispc_common_regmap; 328 329 struct dss_vp_data { 330 u32 *gamma_table; 331 }; 332 333 struct dispc_device { 334 struct tidss_device *tidss; 335 struct device *dev; 336 337 void __iomem *base_common; 338 void __iomem *base_vid[TIDSS_MAX_PLANES]; 339 void __iomem *base_ovr[TIDSS_MAX_PORTS]; 340 void __iomem *base_vp[TIDSS_MAX_PORTS]; 341 342 struct regmap *oldi_io_ctrl; 343 344 struct clk *vp_clk[TIDSS_MAX_PORTS]; 345 346 const struct dispc_features *feat; 347 348 struct clk *fclk; 349 350 bool is_enabled; 351 352 struct dss_vp_data vp_data[TIDSS_MAX_PORTS]; 353 354 u32 *fourccs; 355 u32 num_fourccs; 356 357 u32 memory_bandwidth_limit; 358 359 struct dispc_errata errata; 360 }; 361 362 static void dispc_write(struct dispc_device *dispc, u16 reg, u32 val) 363 { 364 iowrite32(val, dispc->base_common + reg); 365 } 366 367 static u32 dispc_read(struct dispc_device *dispc, u16 reg) 368 { 369 return ioread32(dispc->base_common + reg); 370 } 371 372 static 373 void dispc_vid_write(struct dispc_device *dispc, u32 hw_plane, u16 reg, u32 val) 374 { 375 void __iomem *base = dispc->base_vid[hw_plane]; 376 377 iowrite32(val, base + reg); 378 } 379 380 static u32 dispc_vid_read(struct dispc_device *dispc, u32 hw_plane, u16 reg) 381 { 382 void __iomem *base = dispc->base_vid[hw_plane]; 383 384 return ioread32(base + reg); 385 } 386 387 static void dispc_ovr_write(struct dispc_device *dispc, u32 hw_videoport, 388 u16 reg, u32 val) 389 { 390 void __iomem *base = dispc->base_ovr[hw_videoport]; 391 392 iowrite32(val, base + reg); 393 } 394 395 static u32 dispc_ovr_read(struct dispc_device *dispc, u32 hw_videoport, u16 reg) 396 { 397 void __iomem *base = dispc->base_ovr[hw_videoport]; 398 399 return ioread32(base + reg); 400 } 401 402 static void dispc_vp_write(struct dispc_device *dispc, u32 hw_videoport, 403 u16 reg, u32 val) 404 { 405 void __iomem *base = dispc->base_vp[hw_videoport]; 406 407 iowrite32(val, base + reg); 408 } 409 410 static u32 dispc_vp_read(struct dispc_device *dispc, u32 hw_videoport, u16 reg) 411 { 412 void __iomem *base = dispc->base_vp[hw_videoport]; 413 414 return ioread32(base + reg); 415 } 416 417 /* 418 * TRM gives bitfields as start:end, where start is the higher bit 419 * number. For example 7:0 420 */ 421 422 static u32 FLD_MASK(u32 start, u32 end) 423 { 424 return ((1 << (start - end + 1)) - 1) << end; 425 } 426 427 static u32 FLD_VAL(u32 val, u32 start, u32 end) 428 { 429 return (val << end) & FLD_MASK(start, end); 430 } 431 432 static u32 FLD_GET(u32 val, u32 start, u32 end) 433 { 434 return (val & FLD_MASK(start, end)) >> end; 435 } 436 437 static u32 FLD_MOD(u32 orig, u32 val, u32 start, u32 end) 438 { 439 return (orig & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end); 440 } 441 442 static u32 REG_GET(struct dispc_device *dispc, u32 idx, u32 start, u32 end) 443 { 444 return FLD_GET(dispc_read(dispc, idx), start, end); 445 } 446 447 static void REG_FLD_MOD(struct dispc_device *dispc, u32 idx, u32 val, 448 u32 start, u32 end) 449 { 450 dispc_write(dispc, idx, FLD_MOD(dispc_read(dispc, idx), val, 451 start, end)); 452 } 453 454 static u32 VID_REG_GET(struct dispc_device *dispc, u32 hw_plane, u32 idx, 455 u32 start, u32 end) 456 { 457 return FLD_GET(dispc_vid_read(dispc, hw_plane, idx), start, end); 458 } 459 460 static void VID_REG_FLD_MOD(struct dispc_device *dispc, u32 hw_plane, u32 idx, 461 u32 val, u32 start, u32 end) 462 { 463 dispc_vid_write(dispc, hw_plane, idx, 464 FLD_MOD(dispc_vid_read(dispc, hw_plane, idx), 465 val, start, end)); 466 } 467 468 static u32 VP_REG_GET(struct dispc_device *dispc, u32 vp, u32 idx, 469 u32 start, u32 end) 470 { 471 return FLD_GET(dispc_vp_read(dispc, vp, idx), start, end); 472 } 473 474 static void VP_REG_FLD_MOD(struct dispc_device *dispc, u32 vp, u32 idx, u32 val, 475 u32 start, u32 end) 476 { 477 dispc_vp_write(dispc, vp, idx, FLD_MOD(dispc_vp_read(dispc, vp, idx), 478 val, start, end)); 479 } 480 481 __maybe_unused 482 static u32 OVR_REG_GET(struct dispc_device *dispc, u32 ovr, u32 idx, 483 u32 start, u32 end) 484 { 485 return FLD_GET(dispc_ovr_read(dispc, ovr, idx), start, end); 486 } 487 488 static void OVR_REG_FLD_MOD(struct dispc_device *dispc, u32 ovr, u32 idx, 489 u32 val, u32 start, u32 end) 490 { 491 dispc_ovr_write(dispc, ovr, idx, 492 FLD_MOD(dispc_ovr_read(dispc, ovr, idx), 493 val, start, end)); 494 } 495 496 static dispc_irq_t dispc_vp_irq_from_raw(u32 stat, u32 hw_videoport) 497 { 498 dispc_irq_t vp_stat = 0; 499 500 if (stat & BIT(0)) 501 vp_stat |= DSS_IRQ_VP_FRAME_DONE(hw_videoport); 502 if (stat & BIT(1)) 503 vp_stat |= DSS_IRQ_VP_VSYNC_EVEN(hw_videoport); 504 if (stat & BIT(2)) 505 vp_stat |= DSS_IRQ_VP_VSYNC_ODD(hw_videoport); 506 if (stat & BIT(4)) 507 vp_stat |= DSS_IRQ_VP_SYNC_LOST(hw_videoport); 508 509 return vp_stat; 510 } 511 512 static u32 dispc_vp_irq_to_raw(dispc_irq_t vpstat, u32 hw_videoport) 513 { 514 u32 stat = 0; 515 516 if (vpstat & DSS_IRQ_VP_FRAME_DONE(hw_videoport)) 517 stat |= BIT(0); 518 if (vpstat & DSS_IRQ_VP_VSYNC_EVEN(hw_videoport)) 519 stat |= BIT(1); 520 if (vpstat & DSS_IRQ_VP_VSYNC_ODD(hw_videoport)) 521 stat |= BIT(2); 522 if (vpstat & DSS_IRQ_VP_SYNC_LOST(hw_videoport)) 523 stat |= BIT(4); 524 525 return stat; 526 } 527 528 static dispc_irq_t dispc_vid_irq_from_raw(u32 stat, u32 hw_plane) 529 { 530 dispc_irq_t vid_stat = 0; 531 532 if (stat & BIT(0)) 533 vid_stat |= DSS_IRQ_PLANE_FIFO_UNDERFLOW(hw_plane); 534 535 return vid_stat; 536 } 537 538 static u32 dispc_vid_irq_to_raw(dispc_irq_t vidstat, u32 hw_plane) 539 { 540 u32 stat = 0; 541 542 if (vidstat & DSS_IRQ_PLANE_FIFO_UNDERFLOW(hw_plane)) 543 stat |= BIT(0); 544 545 return stat; 546 } 547 548 static dispc_irq_t dispc_k2g_vp_read_irqstatus(struct dispc_device *dispc, 549 u32 hw_videoport) 550 { 551 u32 stat = dispc_vp_read(dispc, hw_videoport, DISPC_VP_K2G_IRQSTATUS); 552 553 return dispc_vp_irq_from_raw(stat, hw_videoport); 554 } 555 556 static void dispc_k2g_vp_write_irqstatus(struct dispc_device *dispc, 557 u32 hw_videoport, dispc_irq_t vpstat) 558 { 559 u32 stat = dispc_vp_irq_to_raw(vpstat, hw_videoport); 560 561 dispc_vp_write(dispc, hw_videoport, DISPC_VP_K2G_IRQSTATUS, stat); 562 } 563 564 static dispc_irq_t dispc_k2g_vid_read_irqstatus(struct dispc_device *dispc, 565 u32 hw_plane) 566 { 567 u32 stat = dispc_vid_read(dispc, hw_plane, DISPC_VID_K2G_IRQSTATUS); 568 569 return dispc_vid_irq_from_raw(stat, hw_plane); 570 } 571 572 static void dispc_k2g_vid_write_irqstatus(struct dispc_device *dispc, 573 u32 hw_plane, dispc_irq_t vidstat) 574 { 575 u32 stat = dispc_vid_irq_to_raw(vidstat, hw_plane); 576 577 dispc_vid_write(dispc, hw_plane, DISPC_VID_K2G_IRQSTATUS, stat); 578 } 579 580 static dispc_irq_t dispc_k2g_vp_read_irqenable(struct dispc_device *dispc, 581 u32 hw_videoport) 582 { 583 u32 stat = dispc_vp_read(dispc, hw_videoport, DISPC_VP_K2G_IRQENABLE); 584 585 return dispc_vp_irq_from_raw(stat, hw_videoport); 586 } 587 588 static void dispc_k2g_vp_set_irqenable(struct dispc_device *dispc, 589 u32 hw_videoport, dispc_irq_t vpstat) 590 { 591 u32 stat = dispc_vp_irq_to_raw(vpstat, hw_videoport); 592 593 dispc_vp_write(dispc, hw_videoport, DISPC_VP_K2G_IRQENABLE, stat); 594 } 595 596 static dispc_irq_t dispc_k2g_vid_read_irqenable(struct dispc_device *dispc, 597 u32 hw_plane) 598 { 599 u32 stat = dispc_vid_read(dispc, hw_plane, DISPC_VID_K2G_IRQENABLE); 600 601 return dispc_vid_irq_from_raw(stat, hw_plane); 602 } 603 604 static void dispc_k2g_vid_set_irqenable(struct dispc_device *dispc, 605 u32 hw_plane, dispc_irq_t vidstat) 606 { 607 u32 stat = dispc_vid_irq_to_raw(vidstat, hw_plane); 608 609 dispc_vid_write(dispc, hw_plane, DISPC_VID_K2G_IRQENABLE, stat); 610 } 611 612 static void dispc_k2g_clear_irqstatus(struct dispc_device *dispc, 613 dispc_irq_t mask) 614 { 615 dispc_k2g_vp_write_irqstatus(dispc, 0, mask); 616 dispc_k2g_vid_write_irqstatus(dispc, 0, mask); 617 } 618 619 static 620 dispc_irq_t dispc_k2g_read_and_clear_irqstatus(struct dispc_device *dispc) 621 { 622 dispc_irq_t stat = 0; 623 624 /* always clear the top level irqstatus */ 625 dispc_write(dispc, DISPC_IRQSTATUS, 626 dispc_read(dispc, DISPC_IRQSTATUS)); 627 628 stat |= dispc_k2g_vp_read_irqstatus(dispc, 0); 629 stat |= dispc_k2g_vid_read_irqstatus(dispc, 0); 630 631 dispc_k2g_clear_irqstatus(dispc, stat); 632 633 return stat; 634 } 635 636 static dispc_irq_t dispc_k2g_read_irqenable(struct dispc_device *dispc) 637 { 638 dispc_irq_t stat = 0; 639 640 stat |= dispc_k2g_vp_read_irqenable(dispc, 0); 641 stat |= dispc_k2g_vid_read_irqenable(dispc, 0); 642 643 return stat; 644 } 645 646 static 647 void dispc_k2g_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask) 648 { 649 dispc_irq_t old_mask = dispc_k2g_read_irqenable(dispc); 650 651 /* clear the irqstatus for newly enabled irqs */ 652 dispc_k2g_clear_irqstatus(dispc, (mask ^ old_mask) & mask); 653 654 dispc_k2g_vp_set_irqenable(dispc, 0, mask); 655 dispc_k2g_vid_set_irqenable(dispc, 0, mask); 656 657 dispc_write(dispc, DISPC_IRQENABLE_SET, (1 << 0) | (1 << 7)); 658 659 /* flush posted write */ 660 dispc_k2g_read_irqenable(dispc); 661 } 662 663 static dispc_irq_t dispc_k3_vp_read_irqstatus(struct dispc_device *dispc, 664 u32 hw_videoport) 665 { 666 u32 stat = dispc_read(dispc, DISPC_VP_IRQSTATUS(hw_videoport)); 667 668 return dispc_vp_irq_from_raw(stat, hw_videoport); 669 } 670 671 static void dispc_k3_vp_write_irqstatus(struct dispc_device *dispc, 672 u32 hw_videoport, dispc_irq_t vpstat) 673 { 674 u32 stat = dispc_vp_irq_to_raw(vpstat, hw_videoport); 675 676 dispc_write(dispc, DISPC_VP_IRQSTATUS(hw_videoport), stat); 677 } 678 679 static dispc_irq_t dispc_k3_vid_read_irqstatus(struct dispc_device *dispc, 680 u32 hw_plane) 681 { 682 u32 stat = dispc_read(dispc, DISPC_VID_IRQSTATUS(hw_plane)); 683 684 return dispc_vid_irq_from_raw(stat, hw_plane); 685 } 686 687 static void dispc_k3_vid_write_irqstatus(struct dispc_device *dispc, 688 u32 hw_plane, dispc_irq_t vidstat) 689 { 690 u32 stat = dispc_vid_irq_to_raw(vidstat, hw_plane); 691 692 dispc_write(dispc, DISPC_VID_IRQSTATUS(hw_plane), stat); 693 } 694 695 static dispc_irq_t dispc_k3_vp_read_irqenable(struct dispc_device *dispc, 696 u32 hw_videoport) 697 { 698 u32 stat = dispc_read(dispc, DISPC_VP_IRQENABLE(hw_videoport)); 699 700 return dispc_vp_irq_from_raw(stat, hw_videoport); 701 } 702 703 static void dispc_k3_vp_set_irqenable(struct dispc_device *dispc, 704 u32 hw_videoport, dispc_irq_t vpstat) 705 { 706 u32 stat = dispc_vp_irq_to_raw(vpstat, hw_videoport); 707 708 dispc_write(dispc, DISPC_VP_IRQENABLE(hw_videoport), stat); 709 } 710 711 static dispc_irq_t dispc_k3_vid_read_irqenable(struct dispc_device *dispc, 712 u32 hw_plane) 713 { 714 u32 stat = dispc_read(dispc, DISPC_VID_IRQENABLE(hw_plane)); 715 716 return dispc_vid_irq_from_raw(stat, hw_plane); 717 } 718 719 static void dispc_k3_vid_set_irqenable(struct dispc_device *dispc, 720 u32 hw_plane, dispc_irq_t vidstat) 721 { 722 u32 stat = dispc_vid_irq_to_raw(vidstat, hw_plane); 723 724 dispc_write(dispc, DISPC_VID_IRQENABLE(hw_plane), stat); 725 } 726 727 static 728 void dispc_k3_clear_irqstatus(struct dispc_device *dispc, dispc_irq_t clearmask) 729 { 730 unsigned int i; 731 u32 top_clear = 0; 732 733 for (i = 0; i < dispc->feat->num_vps; ++i) { 734 if (clearmask & DSS_IRQ_VP_MASK(i)) { 735 dispc_k3_vp_write_irqstatus(dispc, i, clearmask); 736 top_clear |= BIT(i); 737 } 738 } 739 for (i = 0; i < dispc->feat->num_planes; ++i) { 740 if (clearmask & DSS_IRQ_PLANE_MASK(i)) { 741 dispc_k3_vid_write_irqstatus(dispc, i, clearmask); 742 top_clear |= BIT(4 + i); 743 } 744 } 745 if (dispc->feat->subrev == DISPC_K2G) 746 return; 747 748 dispc_write(dispc, DISPC_IRQSTATUS, top_clear); 749 750 /* Flush posted writes */ 751 dispc_read(dispc, DISPC_IRQSTATUS); 752 } 753 754 static 755 dispc_irq_t dispc_k3_read_and_clear_irqstatus(struct dispc_device *dispc) 756 { 757 dispc_irq_t status = 0; 758 unsigned int i; 759 760 for (i = 0; i < dispc->feat->num_vps; ++i) 761 status |= dispc_k3_vp_read_irqstatus(dispc, i); 762 763 for (i = 0; i < dispc->feat->num_planes; ++i) 764 status |= dispc_k3_vid_read_irqstatus(dispc, i); 765 766 dispc_k3_clear_irqstatus(dispc, status); 767 768 return status; 769 } 770 771 static dispc_irq_t dispc_k3_read_irqenable(struct dispc_device *dispc) 772 { 773 dispc_irq_t enable = 0; 774 unsigned int i; 775 776 for (i = 0; i < dispc->feat->num_vps; ++i) 777 enable |= dispc_k3_vp_read_irqenable(dispc, i); 778 779 for (i = 0; i < dispc->feat->num_planes; ++i) 780 enable |= dispc_k3_vid_read_irqenable(dispc, i); 781 782 return enable; 783 } 784 785 static void dispc_k3_set_irqenable(struct dispc_device *dispc, 786 dispc_irq_t mask) 787 { 788 unsigned int i; 789 u32 main_enable = 0, main_disable = 0; 790 dispc_irq_t old_mask; 791 792 old_mask = dispc_k3_read_irqenable(dispc); 793 794 /* clear the irqstatus for newly enabled irqs */ 795 dispc_k3_clear_irqstatus(dispc, (old_mask ^ mask) & mask); 796 797 for (i = 0; i < dispc->feat->num_vps; ++i) { 798 dispc_k3_vp_set_irqenable(dispc, i, mask); 799 if (mask & DSS_IRQ_VP_MASK(i)) 800 main_enable |= BIT(i); /* VP IRQ */ 801 else 802 main_disable |= BIT(i); /* VP IRQ */ 803 } 804 805 for (i = 0; i < dispc->feat->num_planes; ++i) { 806 dispc_k3_vid_set_irqenable(dispc, i, mask); 807 if (mask & DSS_IRQ_PLANE_MASK(i)) 808 main_enable |= BIT(i + 4); /* VID IRQ */ 809 else 810 main_disable |= BIT(i + 4); /* VID IRQ */ 811 } 812 813 if (main_enable) 814 dispc_write(dispc, DISPC_IRQENABLE_SET, main_enable); 815 816 if (main_disable) 817 dispc_write(dispc, DISPC_IRQENABLE_CLR, main_disable); 818 819 /* Flush posted writes */ 820 dispc_read(dispc, DISPC_IRQENABLE_SET); 821 } 822 823 dispc_irq_t dispc_read_and_clear_irqstatus(struct dispc_device *dispc) 824 { 825 switch (dispc->feat->subrev) { 826 case DISPC_K2G: 827 return dispc_k2g_read_and_clear_irqstatus(dispc); 828 case DISPC_AM625: 829 case DISPC_AM65X: 830 case DISPC_J721E: 831 return dispc_k3_read_and_clear_irqstatus(dispc); 832 default: 833 WARN_ON(1); 834 return 0; 835 } 836 } 837 838 void dispc_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask) 839 { 840 switch (dispc->feat->subrev) { 841 case DISPC_K2G: 842 dispc_k2g_set_irqenable(dispc, mask); 843 break; 844 case DISPC_AM625: 845 case DISPC_AM65X: 846 case DISPC_J721E: 847 dispc_k3_set_irqenable(dispc, mask); 848 break; 849 default: 850 WARN_ON(1); 851 break; 852 } 853 } 854 855 enum dispc_oldi_mode_reg_val { SPWG_18 = 0, JEIDA_24 = 1, SPWG_24 = 2 }; 856 857 struct dispc_bus_format { 858 u32 bus_fmt; 859 u32 data_width; 860 bool is_oldi_fmt; 861 enum dispc_oldi_mode_reg_val oldi_mode_reg_val; 862 }; 863 864 static const struct dispc_bus_format dispc_bus_formats[] = { 865 { MEDIA_BUS_FMT_RGB444_1X12, 12, false, 0 }, 866 { MEDIA_BUS_FMT_RGB565_1X16, 16, false, 0 }, 867 { MEDIA_BUS_FMT_RGB666_1X18, 18, false, 0 }, 868 { MEDIA_BUS_FMT_RGB888_1X24, 24, false, 0 }, 869 { MEDIA_BUS_FMT_RGB101010_1X30, 30, false, 0 }, 870 { MEDIA_BUS_FMT_RGB121212_1X36, 36, false, 0 }, 871 { MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 18, true, SPWG_18 }, 872 { MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 24, true, SPWG_24 }, 873 { MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 24, true, JEIDA_24 }, 874 }; 875 876 static const 877 struct dispc_bus_format *dispc_vp_find_bus_fmt(struct dispc_device *dispc, 878 u32 hw_videoport, 879 u32 bus_fmt, u32 bus_flags) 880 { 881 unsigned int i; 882 883 for (i = 0; i < ARRAY_SIZE(dispc_bus_formats); ++i) { 884 if (dispc_bus_formats[i].bus_fmt == bus_fmt) 885 return &dispc_bus_formats[i]; 886 } 887 888 return NULL; 889 } 890 891 int dispc_vp_bus_check(struct dispc_device *dispc, u32 hw_videoport, 892 const struct drm_crtc_state *state) 893 { 894 const struct tidss_crtc_state *tstate = to_tidss_crtc_state(state); 895 const struct dispc_bus_format *fmt; 896 897 fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format, 898 tstate->bus_flags); 899 if (!fmt) { 900 dev_dbg(dispc->dev, "%s: Unsupported bus format: %u\n", 901 __func__, tstate->bus_format); 902 return -EINVAL; 903 } 904 905 if (dispc->feat->vp_bus_type[hw_videoport] != DISPC_VP_OLDI && 906 fmt->is_oldi_fmt) { 907 dev_dbg(dispc->dev, "%s: %s is not OLDI-port\n", 908 __func__, dispc->feat->vp_name[hw_videoport]); 909 return -EINVAL; 910 } 911 912 return 0; 913 } 914 915 static void dispc_oldi_tx_power(struct dispc_device *dispc, bool power) 916 { 917 u32 val = power ? 0 : OLDI_PWRDN_TX; 918 919 if (WARN_ON(!dispc->oldi_io_ctrl)) 920 return; 921 922 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT0_IO_CTRL, 923 OLDI_PWRDN_TX, val); 924 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT1_IO_CTRL, 925 OLDI_PWRDN_TX, val); 926 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT2_IO_CTRL, 927 OLDI_PWRDN_TX, val); 928 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT3_IO_CTRL, 929 OLDI_PWRDN_TX, val); 930 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_CLK_IO_CTRL, 931 OLDI_PWRDN_TX, val); 932 } 933 934 static void dispc_set_num_datalines(struct dispc_device *dispc, 935 u32 hw_videoport, int num_lines) 936 { 937 int v; 938 939 switch (num_lines) { 940 case 12: 941 v = 0; break; 942 case 16: 943 v = 1; break; 944 case 18: 945 v = 2; break; 946 case 24: 947 v = 3; break; 948 case 30: 949 v = 4; break; 950 case 36: 951 v = 5; break; 952 default: 953 WARN_ON(1); 954 v = 3; 955 } 956 957 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, v, 10, 8); 958 } 959 960 static void dispc_enable_oldi(struct dispc_device *dispc, u32 hw_videoport, 961 const struct dispc_bus_format *fmt) 962 { 963 u32 oldi_cfg = 0; 964 u32 oldi_reset_bit = BIT(5 + hw_videoport); 965 int count = 0; 966 967 /* 968 * For the moment DUALMODESYNC, MASTERSLAVE, MODE, and SRC 969 * bits of DISPC_VP_DSS_OLDI_CFG are set statically to 0. 970 */ 971 972 if (fmt->data_width == 24) 973 oldi_cfg |= BIT(8); /* MSB */ 974 else if (fmt->data_width != 18) 975 dev_warn(dispc->dev, "%s: %d port width not supported\n", 976 __func__, fmt->data_width); 977 978 oldi_cfg |= BIT(7); /* DEPOL */ 979 980 oldi_cfg = FLD_MOD(oldi_cfg, fmt->oldi_mode_reg_val, 3, 1); 981 982 oldi_cfg |= BIT(12); /* SOFTRST */ 983 984 oldi_cfg |= BIT(0); /* ENABLE */ 985 986 dispc_vp_write(dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, oldi_cfg); 987 988 while (!(oldi_reset_bit & dispc_read(dispc, DSS_SYSSTATUS)) && 989 count < 10000) 990 count++; 991 992 if (!(oldi_reset_bit & dispc_read(dispc, DSS_SYSSTATUS))) 993 dev_warn(dispc->dev, "%s: timeout waiting OLDI reset done\n", 994 __func__); 995 } 996 997 void dispc_vp_prepare(struct dispc_device *dispc, u32 hw_videoport, 998 const struct drm_crtc_state *state) 999 { 1000 const struct tidss_crtc_state *tstate = to_tidss_crtc_state(state); 1001 const struct dispc_bus_format *fmt; 1002 1003 fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format, 1004 tstate->bus_flags); 1005 1006 if (WARN_ON(!fmt)) 1007 return; 1008 1009 if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI) { 1010 dispc_oldi_tx_power(dispc, true); 1011 1012 dispc_enable_oldi(dispc, hw_videoport, fmt); 1013 } 1014 } 1015 1016 void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport, 1017 const struct drm_crtc_state *state) 1018 { 1019 const struct drm_display_mode *mode = &state->adjusted_mode; 1020 const struct tidss_crtc_state *tstate = to_tidss_crtc_state(state); 1021 bool align, onoff, rf, ieo, ipc, ihs, ivs; 1022 const struct dispc_bus_format *fmt; 1023 u32 hsw, hfp, hbp, vsw, vfp, vbp; 1024 1025 fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format, 1026 tstate->bus_flags); 1027 1028 if (WARN_ON(!fmt)) 1029 return; 1030 1031 dispc_set_num_datalines(dispc, hw_videoport, fmt->data_width); 1032 1033 hfp = mode->hsync_start - mode->hdisplay; 1034 hsw = mode->hsync_end - mode->hsync_start; 1035 hbp = mode->htotal - mode->hsync_end; 1036 1037 vfp = mode->vsync_start - mode->vdisplay; 1038 vsw = mode->vsync_end - mode->vsync_start; 1039 vbp = mode->vtotal - mode->vsync_end; 1040 1041 dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_H, 1042 FLD_VAL(hsw - 1, 7, 0) | 1043 FLD_VAL(hfp - 1, 19, 8) | 1044 FLD_VAL(hbp - 1, 31, 20)); 1045 1046 dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_V, 1047 FLD_VAL(vsw - 1, 7, 0) | 1048 FLD_VAL(vfp, 19, 8) | 1049 FLD_VAL(vbp, 31, 20)); 1050 1051 ivs = !!(mode->flags & DRM_MODE_FLAG_NVSYNC); 1052 1053 ihs = !!(mode->flags & DRM_MODE_FLAG_NHSYNC); 1054 1055 ieo = !!(tstate->bus_flags & DRM_BUS_FLAG_DE_LOW); 1056 1057 ipc = !!(tstate->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE); 1058 1059 /* always use the 'rf' setting */ 1060 onoff = true; 1061 1062 rf = !!(tstate->bus_flags & DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE); 1063 1064 /* always use aligned syncs */ 1065 align = true; 1066 1067 /* always use DE_HIGH for OLDI */ 1068 if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI) 1069 ieo = false; 1070 1071 dispc_vp_write(dispc, hw_videoport, DISPC_VP_POL_FREQ, 1072 FLD_VAL(align, 18, 18) | 1073 FLD_VAL(onoff, 17, 17) | 1074 FLD_VAL(rf, 16, 16) | 1075 FLD_VAL(ieo, 15, 15) | 1076 FLD_VAL(ipc, 14, 14) | 1077 FLD_VAL(ihs, 13, 13) | 1078 FLD_VAL(ivs, 12, 12)); 1079 1080 dispc_vp_write(dispc, hw_videoport, DISPC_VP_SIZE_SCREEN, 1081 FLD_VAL(mode->hdisplay - 1, 11, 0) | 1082 FLD_VAL(mode->vdisplay - 1, 27, 16)); 1083 1084 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 0, 0); 1085 } 1086 1087 void dispc_vp_disable(struct dispc_device *dispc, u32 hw_videoport) 1088 { 1089 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 0, 0, 0); 1090 } 1091 1092 void dispc_vp_unprepare(struct dispc_device *dispc, u32 hw_videoport) 1093 { 1094 if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI) { 1095 dispc_vp_write(dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, 0); 1096 1097 dispc_oldi_tx_power(dispc, false); 1098 } 1099 } 1100 1101 bool dispc_vp_go_busy(struct dispc_device *dispc, u32 hw_videoport) 1102 { 1103 return VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, 5, 5); 1104 } 1105 1106 void dispc_vp_go(struct dispc_device *dispc, u32 hw_videoport) 1107 { 1108 WARN_ON(VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, 5, 5)); 1109 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 5, 5); 1110 } 1111 1112 enum c8_to_c12_mode { C8_TO_C12_REPLICATE, C8_TO_C12_MAX, C8_TO_C12_MIN }; 1113 1114 static u16 c8_to_c12(u8 c8, enum c8_to_c12_mode mode) 1115 { 1116 u16 c12; 1117 1118 c12 = c8 << 4; 1119 1120 switch (mode) { 1121 case C8_TO_C12_REPLICATE: 1122 /* Copy c8 4 MSB to 4 LSB for full scale c12 */ 1123 c12 |= c8 >> 4; 1124 break; 1125 case C8_TO_C12_MAX: 1126 c12 |= 0xF; 1127 break; 1128 default: 1129 case C8_TO_C12_MIN: 1130 break; 1131 } 1132 1133 return c12; 1134 } 1135 1136 static u64 argb8888_to_argb12121212(u32 argb8888, enum c8_to_c12_mode m) 1137 { 1138 u8 a, r, g, b; 1139 u64 v; 1140 1141 a = (argb8888 >> 24) & 0xff; 1142 r = (argb8888 >> 16) & 0xff; 1143 g = (argb8888 >> 8) & 0xff; 1144 b = (argb8888 >> 0) & 0xff; 1145 1146 v = ((u64)c8_to_c12(a, m) << 36) | ((u64)c8_to_c12(r, m) << 24) | 1147 ((u64)c8_to_c12(g, m) << 12) | (u64)c8_to_c12(b, m); 1148 1149 return v; 1150 } 1151 1152 static void dispc_vp_set_default_color(struct dispc_device *dispc, 1153 u32 hw_videoport, u32 default_color) 1154 { 1155 u64 v; 1156 1157 v = argb8888_to_argb12121212(default_color, C8_TO_C12_REPLICATE); 1158 1159 dispc_ovr_write(dispc, hw_videoport, 1160 DISPC_OVR_DEFAULT_COLOR, v & 0xffffffff); 1161 dispc_ovr_write(dispc, hw_videoport, 1162 DISPC_OVR_DEFAULT_COLOR2, (v >> 32) & 0xffff); 1163 } 1164 1165 enum drm_mode_status dispc_vp_mode_valid(struct dispc_device *dispc, 1166 u32 hw_videoport, 1167 const struct drm_display_mode *mode) 1168 { 1169 u32 hsw, hfp, hbp, vsw, vfp, vbp; 1170 enum dispc_vp_bus_type bus_type; 1171 int max_pclk; 1172 1173 bus_type = dispc->feat->vp_bus_type[hw_videoport]; 1174 1175 max_pclk = dispc->feat->max_pclk_khz[bus_type]; 1176 1177 if (WARN_ON(max_pclk == 0)) 1178 return MODE_BAD; 1179 1180 if (mode->clock < dispc->feat->min_pclk_khz) 1181 return MODE_CLOCK_LOW; 1182 1183 if (mode->clock > max_pclk) 1184 return MODE_CLOCK_HIGH; 1185 1186 if (mode->hdisplay > 4096) 1187 return MODE_BAD; 1188 1189 if (mode->vdisplay > 4096) 1190 return MODE_BAD; 1191 1192 /* TODO: add interlace support */ 1193 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1194 return MODE_NO_INTERLACE; 1195 1196 /* 1197 * Enforce the output width is divisible by 2. Actually this 1198 * is only needed in following cases: 1199 * - YUV output selected (BT656, BT1120) 1200 * - Dithering enabled 1201 * - TDM with TDMCycleFormat == 3 1202 * But for simplicity we enforce that always. 1203 */ 1204 if ((mode->hdisplay % 2) != 0) 1205 return MODE_BAD_HVALUE; 1206 1207 hfp = mode->hsync_start - mode->hdisplay; 1208 hsw = mode->hsync_end - mode->hsync_start; 1209 hbp = mode->htotal - mode->hsync_end; 1210 1211 vfp = mode->vsync_start - mode->vdisplay; 1212 vsw = mode->vsync_end - mode->vsync_start; 1213 vbp = mode->vtotal - mode->vsync_end; 1214 1215 if (hsw < 1 || hsw > 256 || 1216 hfp < 1 || hfp > 4096 || 1217 hbp < 1 || hbp > 4096) 1218 return MODE_BAD_HVALUE; 1219 1220 if (vsw < 1 || vsw > 256 || 1221 vfp > 4095 || vbp > 4095) 1222 return MODE_BAD_VVALUE; 1223 1224 if (dispc->memory_bandwidth_limit) { 1225 const unsigned int bpp = 4; 1226 u64 bandwidth; 1227 1228 bandwidth = 1000 * mode->clock; 1229 bandwidth = bandwidth * mode->hdisplay * mode->vdisplay * bpp; 1230 bandwidth = div_u64(bandwidth, mode->htotal * mode->vtotal); 1231 1232 if (dispc->memory_bandwidth_limit < bandwidth) 1233 return MODE_BAD; 1234 } 1235 1236 return MODE_OK; 1237 } 1238 1239 int dispc_vp_enable_clk(struct dispc_device *dispc, u32 hw_videoport) 1240 { 1241 int ret = clk_prepare_enable(dispc->vp_clk[hw_videoport]); 1242 1243 if (ret) 1244 dev_err(dispc->dev, "%s: enabling clk failed: %d\n", __func__, 1245 ret); 1246 1247 return ret; 1248 } 1249 1250 void dispc_vp_disable_clk(struct dispc_device *dispc, u32 hw_videoport) 1251 { 1252 clk_disable_unprepare(dispc->vp_clk[hw_videoport]); 1253 } 1254 1255 /* 1256 * Calculate the percentage difference between the requested pixel clock rate 1257 * and the effective rate resulting from calculating the clock divider value. 1258 */ 1259 static 1260 unsigned int dispc_pclk_diff(unsigned long rate, unsigned long real_rate) 1261 { 1262 int r = rate / 100, rr = real_rate / 100; 1263 1264 return (unsigned int)(abs(((rr - r) * 100) / r)); 1265 } 1266 1267 int dispc_vp_set_clk_rate(struct dispc_device *dispc, u32 hw_videoport, 1268 unsigned long rate) 1269 { 1270 int r; 1271 unsigned long new_rate; 1272 1273 r = clk_set_rate(dispc->vp_clk[hw_videoport], rate); 1274 if (r) { 1275 dev_err(dispc->dev, "vp%d: failed to set clk rate to %lu\n", 1276 hw_videoport, rate); 1277 return r; 1278 } 1279 1280 new_rate = clk_get_rate(dispc->vp_clk[hw_videoport]); 1281 1282 if (dispc_pclk_diff(rate, new_rate) > 5) 1283 dev_warn(dispc->dev, 1284 "vp%d: Clock rate %lu differs over 5%% from requested %lu\n", 1285 hw_videoport, new_rate, rate); 1286 1287 dev_dbg(dispc->dev, "vp%d: new rate %lu Hz (requested %lu Hz)\n", 1288 hw_videoport, clk_get_rate(dispc->vp_clk[hw_videoport]), rate); 1289 1290 return 0; 1291 } 1292 1293 /* OVR */ 1294 static void dispc_k2g_ovr_set_plane(struct dispc_device *dispc, 1295 u32 hw_plane, u32 hw_videoport, 1296 u32 x, u32 y, u32 layer) 1297 { 1298 /* On k2g there is only one plane and no need for ovr */ 1299 dispc_vid_write(dispc, hw_plane, DISPC_VID_K2G_POSITION, 1300 x | (y << 16)); 1301 } 1302 1303 static void dispc_am65x_ovr_set_plane(struct dispc_device *dispc, 1304 u32 hw_plane, u32 hw_videoport, 1305 u32 x, u32 y, u32 layer) 1306 { 1307 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), 1308 hw_plane, 4, 1); 1309 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), 1310 x, 17, 6); 1311 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), 1312 y, 30, 19); 1313 } 1314 1315 static void dispc_j721e_ovr_set_plane(struct dispc_device *dispc, 1316 u32 hw_plane, u32 hw_videoport, 1317 u32 x, u32 y, u32 layer) 1318 { 1319 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), 1320 hw_plane, 4, 1); 1321 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer), 1322 x, 13, 0); 1323 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer), 1324 y, 29, 16); 1325 } 1326 1327 void dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane, 1328 u32 hw_videoport, u32 x, u32 y, u32 layer) 1329 { 1330 switch (dispc->feat->subrev) { 1331 case DISPC_K2G: 1332 dispc_k2g_ovr_set_plane(dispc, hw_plane, hw_videoport, 1333 x, y, layer); 1334 break; 1335 case DISPC_AM625: 1336 case DISPC_AM65X: 1337 dispc_am65x_ovr_set_plane(dispc, hw_plane, hw_videoport, 1338 x, y, layer); 1339 break; 1340 case DISPC_J721E: 1341 dispc_j721e_ovr_set_plane(dispc, hw_plane, hw_videoport, 1342 x, y, layer); 1343 break; 1344 default: 1345 WARN_ON(1); 1346 break; 1347 } 1348 } 1349 1350 void dispc_ovr_enable_layer(struct dispc_device *dispc, 1351 u32 hw_videoport, u32 layer, bool enable) 1352 { 1353 if (dispc->feat->subrev == DISPC_K2G) 1354 return; 1355 1356 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), 1357 !!enable, 0, 0); 1358 } 1359 1360 /* CSC */ 1361 enum csc_ctm { 1362 CSC_RR, CSC_RG, CSC_RB, 1363 CSC_GR, CSC_GG, CSC_GB, 1364 CSC_BR, CSC_BG, CSC_BB, 1365 }; 1366 1367 enum csc_yuv2rgb { 1368 CSC_RY, CSC_RCB, CSC_RCR, 1369 CSC_GY, CSC_GCB, CSC_GCR, 1370 CSC_BY, CSC_BCB, CSC_BCR, 1371 }; 1372 1373 enum csc_rgb2yuv { 1374 CSC_YR, CSC_YG, CSC_YB, 1375 CSC_CBR, CSC_CBG, CSC_CBB, 1376 CSC_CRR, CSC_CRG, CSC_CRB, 1377 }; 1378 1379 struct dispc_csc_coef { 1380 void (*to_regval)(const struct dispc_csc_coef *csc, u32 *regval); 1381 int m[9]; 1382 int preoffset[3]; 1383 int postoffset[3]; 1384 enum { CLIP_LIMITED_RANGE = 0, CLIP_FULL_RANGE = 1, } cliping; 1385 const char *name; 1386 }; 1387 1388 #define DISPC_CSC_REGVAL_LEN 8 1389 1390 static 1391 void dispc_csc_offset_regval(const struct dispc_csc_coef *csc, u32 *regval) 1392 { 1393 #define OVAL(x, y) (FLD_VAL(x, 15, 3) | FLD_VAL(y, 31, 19)) 1394 regval[5] = OVAL(csc->preoffset[0], csc->preoffset[1]); 1395 regval[6] = OVAL(csc->preoffset[2], csc->postoffset[0]); 1396 regval[7] = OVAL(csc->postoffset[1], csc->postoffset[2]); 1397 #undef OVAL 1398 } 1399 1400 #define CVAL(x, y) (FLD_VAL(x, 10, 0) | FLD_VAL(y, 26, 16)) 1401 static 1402 void dispc_csc_yuv2rgb_regval(const struct dispc_csc_coef *csc, u32 *regval) 1403 { 1404 regval[0] = CVAL(csc->m[CSC_RY], csc->m[CSC_RCR]); 1405 regval[1] = CVAL(csc->m[CSC_RCB], csc->m[CSC_GY]); 1406 regval[2] = CVAL(csc->m[CSC_GCR], csc->m[CSC_GCB]); 1407 regval[3] = CVAL(csc->m[CSC_BY], csc->m[CSC_BCR]); 1408 regval[4] = CVAL(csc->m[CSC_BCB], 0); 1409 1410 dispc_csc_offset_regval(csc, regval); 1411 } 1412 1413 __maybe_unused static 1414 void dispc_csc_rgb2yuv_regval(const struct dispc_csc_coef *csc, u32 *regval) 1415 { 1416 regval[0] = CVAL(csc->m[CSC_YR], csc->m[CSC_YG]); 1417 regval[1] = CVAL(csc->m[CSC_YB], csc->m[CSC_CRR]); 1418 regval[2] = CVAL(csc->m[CSC_CRG], csc->m[CSC_CRB]); 1419 regval[3] = CVAL(csc->m[CSC_CBR], csc->m[CSC_CBG]); 1420 regval[4] = CVAL(csc->m[CSC_CBB], 0); 1421 1422 dispc_csc_offset_regval(csc, regval); 1423 } 1424 1425 static void dispc_csc_cpr_regval(const struct dispc_csc_coef *csc, 1426 u32 *regval) 1427 { 1428 regval[0] = CVAL(csc->m[CSC_RR], csc->m[CSC_RG]); 1429 regval[1] = CVAL(csc->m[CSC_RB], csc->m[CSC_GR]); 1430 regval[2] = CVAL(csc->m[CSC_GG], csc->m[CSC_GB]); 1431 regval[3] = CVAL(csc->m[CSC_BR], csc->m[CSC_BG]); 1432 regval[4] = CVAL(csc->m[CSC_BB], 0); 1433 1434 dispc_csc_offset_regval(csc, regval); 1435 } 1436 1437 #undef CVAL 1438 1439 static void dispc_k2g_vid_write_csc(struct dispc_device *dispc, u32 hw_plane, 1440 const struct dispc_csc_coef *csc) 1441 { 1442 static const u16 dispc_vid_csc_coef_reg[] = { 1443 DISPC_VID_CSC_COEF(0), DISPC_VID_CSC_COEF(1), 1444 DISPC_VID_CSC_COEF(2), DISPC_VID_CSC_COEF(3), 1445 DISPC_VID_CSC_COEF(4), DISPC_VID_CSC_COEF(5), 1446 DISPC_VID_CSC_COEF(6), /* K2G has no post offset support */ 1447 }; 1448 u32 regval[DISPC_CSC_REGVAL_LEN]; 1449 unsigned int i; 1450 1451 csc->to_regval(csc, regval); 1452 1453 if (regval[7] != 0) 1454 dev_warn(dispc->dev, "%s: No post offset support for %s\n", 1455 __func__, csc->name); 1456 1457 for (i = 0; i < ARRAY_SIZE(dispc_vid_csc_coef_reg); i++) 1458 dispc_vid_write(dispc, hw_plane, dispc_vid_csc_coef_reg[i], 1459 regval[i]); 1460 } 1461 1462 static void dispc_k3_vid_write_csc(struct dispc_device *dispc, u32 hw_plane, 1463 const struct dispc_csc_coef *csc) 1464 { 1465 static const u16 dispc_vid_csc_coef_reg[DISPC_CSC_REGVAL_LEN] = { 1466 DISPC_VID_CSC_COEF(0), DISPC_VID_CSC_COEF(1), 1467 DISPC_VID_CSC_COEF(2), DISPC_VID_CSC_COEF(3), 1468 DISPC_VID_CSC_COEF(4), DISPC_VID_CSC_COEF(5), 1469 DISPC_VID_CSC_COEF(6), DISPC_VID_CSC_COEF7, 1470 }; 1471 u32 regval[DISPC_CSC_REGVAL_LEN]; 1472 unsigned int i; 1473 1474 csc->to_regval(csc, regval); 1475 1476 for (i = 0; i < ARRAY_SIZE(dispc_vid_csc_coef_reg); i++) 1477 dispc_vid_write(dispc, hw_plane, dispc_vid_csc_coef_reg[i], 1478 regval[i]); 1479 } 1480 1481 /* YUV -> RGB, ITU-R BT.601, full range */ 1482 static const struct dispc_csc_coef csc_yuv2rgb_bt601_full = { 1483 dispc_csc_yuv2rgb_regval, 1484 { 256, 0, 358, /* ry, rcb, rcr |1.000 0.000 1.402|*/ 1485 256, -88, -182, /* gy, gcb, gcr |1.000 -0.344 -0.714|*/ 1486 256, 452, 0, }, /* by, bcb, bcr |1.000 1.772 0.000|*/ 1487 { 0, -2048, -2048, }, /* full range */ 1488 { 0, 0, 0, }, 1489 CLIP_FULL_RANGE, 1490 "BT.601 Full", 1491 }; 1492 1493 /* YUV -> RGB, ITU-R BT.601, limited range */ 1494 static const struct dispc_csc_coef csc_yuv2rgb_bt601_lim = { 1495 dispc_csc_yuv2rgb_regval, 1496 { 298, 0, 409, /* ry, rcb, rcr |1.164 0.000 1.596|*/ 1497 298, -100, -208, /* gy, gcb, gcr |1.164 -0.392 -0.813|*/ 1498 298, 516, 0, }, /* by, bcb, bcr |1.164 2.017 0.000|*/ 1499 { -256, -2048, -2048, }, /* limited range */ 1500 { 0, 0, 0, }, 1501 CLIP_FULL_RANGE, 1502 "BT.601 Limited", 1503 }; 1504 1505 /* YUV -> RGB, ITU-R BT.709, full range */ 1506 static const struct dispc_csc_coef csc_yuv2rgb_bt709_full = { 1507 dispc_csc_yuv2rgb_regval, 1508 { 256, 0, 402, /* ry, rcb, rcr |1.000 0.000 1.570|*/ 1509 256, -48, -120, /* gy, gcb, gcr |1.000 -0.187 -0.467|*/ 1510 256, 475, 0, }, /* by, bcb, bcr |1.000 1.856 0.000|*/ 1511 { 0, -2048, -2048, }, /* full range */ 1512 { 0, 0, 0, }, 1513 CLIP_FULL_RANGE, 1514 "BT.709 Full", 1515 }; 1516 1517 /* YUV -> RGB, ITU-R BT.709, limited range */ 1518 static const struct dispc_csc_coef csc_yuv2rgb_bt709_lim = { 1519 dispc_csc_yuv2rgb_regval, 1520 { 298, 0, 459, /* ry, rcb, rcr |1.164 0.000 1.793|*/ 1521 298, -55, -136, /* gy, gcb, gcr |1.164 -0.213 -0.533|*/ 1522 298, 541, 0, }, /* by, bcb, bcr |1.164 2.112 0.000|*/ 1523 { -256, -2048, -2048, }, /* limited range */ 1524 { 0, 0, 0, }, 1525 CLIP_FULL_RANGE, 1526 "BT.709 Limited", 1527 }; 1528 1529 static const struct { 1530 enum drm_color_encoding encoding; 1531 enum drm_color_range range; 1532 const struct dispc_csc_coef *csc; 1533 } dispc_csc_table[] = { 1534 { DRM_COLOR_YCBCR_BT601, DRM_COLOR_YCBCR_FULL_RANGE, 1535 &csc_yuv2rgb_bt601_full, }, 1536 { DRM_COLOR_YCBCR_BT601, DRM_COLOR_YCBCR_LIMITED_RANGE, 1537 &csc_yuv2rgb_bt601_lim, }, 1538 { DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_FULL_RANGE, 1539 &csc_yuv2rgb_bt709_full, }, 1540 { DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE, 1541 &csc_yuv2rgb_bt709_lim, }, 1542 }; 1543 1544 static const 1545 struct dispc_csc_coef *dispc_find_csc(enum drm_color_encoding encoding, 1546 enum drm_color_range range) 1547 { 1548 unsigned int i; 1549 1550 for (i = 0; i < ARRAY_SIZE(dispc_csc_table); i++) { 1551 if (dispc_csc_table[i].encoding == encoding && 1552 dispc_csc_table[i].range == range) { 1553 return dispc_csc_table[i].csc; 1554 } 1555 } 1556 return NULL; 1557 } 1558 1559 static void dispc_vid_csc_setup(struct dispc_device *dispc, u32 hw_plane, 1560 const struct drm_plane_state *state) 1561 { 1562 const struct dispc_csc_coef *coef; 1563 1564 coef = dispc_find_csc(state->color_encoding, state->color_range); 1565 if (!coef) { 1566 dev_err(dispc->dev, "%s: CSC (%u,%u) not found\n", 1567 __func__, state->color_encoding, state->color_range); 1568 return; 1569 } 1570 1571 if (dispc->feat->subrev == DISPC_K2G) 1572 dispc_k2g_vid_write_csc(dispc, hw_plane, coef); 1573 else 1574 dispc_k3_vid_write_csc(dispc, hw_plane, coef); 1575 } 1576 1577 static void dispc_vid_csc_enable(struct dispc_device *dispc, u32 hw_plane, 1578 bool enable) 1579 { 1580 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, 9, 9); 1581 } 1582 1583 /* SCALER */ 1584 1585 static u32 dispc_calc_fir_inc(u32 in, u32 out) 1586 { 1587 return (u32)div_u64(0x200000ull * in, out); 1588 } 1589 1590 enum dispc_vid_fir_coef_set { 1591 DISPC_VID_FIR_COEF_HORIZ, 1592 DISPC_VID_FIR_COEF_HORIZ_UV, 1593 DISPC_VID_FIR_COEF_VERT, 1594 DISPC_VID_FIR_COEF_VERT_UV, 1595 }; 1596 1597 static void dispc_vid_write_fir_coefs(struct dispc_device *dispc, 1598 u32 hw_plane, 1599 enum dispc_vid_fir_coef_set coef_set, 1600 const struct tidss_scale_coefs *coefs) 1601 { 1602 static const u16 c0_regs[] = { 1603 [DISPC_VID_FIR_COEF_HORIZ] = DISPC_VID_FIR_COEFS_H0, 1604 [DISPC_VID_FIR_COEF_HORIZ_UV] = DISPC_VID_FIR_COEFS_H0_C, 1605 [DISPC_VID_FIR_COEF_VERT] = DISPC_VID_FIR_COEFS_V0, 1606 [DISPC_VID_FIR_COEF_VERT_UV] = DISPC_VID_FIR_COEFS_V0_C, 1607 }; 1608 1609 static const u16 c12_regs[] = { 1610 [DISPC_VID_FIR_COEF_HORIZ] = DISPC_VID_FIR_COEFS_H12, 1611 [DISPC_VID_FIR_COEF_HORIZ_UV] = DISPC_VID_FIR_COEFS_H12_C, 1612 [DISPC_VID_FIR_COEF_VERT] = DISPC_VID_FIR_COEFS_V12, 1613 [DISPC_VID_FIR_COEF_VERT_UV] = DISPC_VID_FIR_COEFS_V12_C, 1614 }; 1615 1616 const u16 c0_base = c0_regs[coef_set]; 1617 const u16 c12_base = c12_regs[coef_set]; 1618 int phase; 1619 1620 if (!coefs) { 1621 dev_err(dispc->dev, "%s: No coefficients given.\n", __func__); 1622 return; 1623 } 1624 1625 for (phase = 0; phase <= 8; ++phase) { 1626 u16 reg = c0_base + phase * 4; 1627 u16 c0 = coefs->c0[phase]; 1628 1629 dispc_vid_write(dispc, hw_plane, reg, c0); 1630 } 1631 1632 for (phase = 0; phase <= 15; ++phase) { 1633 u16 reg = c12_base + phase * 4; 1634 s16 c1, c2; 1635 u32 c12; 1636 1637 c1 = coefs->c1[phase]; 1638 c2 = coefs->c2[phase]; 1639 c12 = FLD_VAL(c1, 19, 10) | FLD_VAL(c2, 29, 20); 1640 1641 dispc_vid_write(dispc, hw_plane, reg, c12); 1642 } 1643 } 1644 1645 static bool dispc_fourcc_is_yuv(u32 fourcc) 1646 { 1647 switch (fourcc) { 1648 case DRM_FORMAT_YUYV: 1649 case DRM_FORMAT_UYVY: 1650 case DRM_FORMAT_NV12: 1651 return true; 1652 default: 1653 return false; 1654 } 1655 } 1656 1657 struct dispc_scaling_params { 1658 int xinc, yinc; 1659 u32 in_w, in_h, in_w_uv, in_h_uv; 1660 u32 fir_xinc, fir_yinc, fir_xinc_uv, fir_yinc_uv; 1661 bool scale_x, scale_y; 1662 const struct tidss_scale_coefs *xcoef, *ycoef, *xcoef_uv, *ycoef_uv; 1663 bool five_taps; 1664 }; 1665 1666 static int dispc_vid_calc_scaling(struct dispc_device *dispc, 1667 const struct drm_plane_state *state, 1668 struct dispc_scaling_params *sp, 1669 bool lite_plane) 1670 { 1671 const struct dispc_features_scaling *f = &dispc->feat->scaling; 1672 u32 fourcc = state->fb->format->format; 1673 u32 in_width_max_5tap = f->in_width_max_5tap_rgb; 1674 u32 in_width_max_3tap = f->in_width_max_3tap_rgb; 1675 u32 downscale_limit; 1676 u32 in_width_max; 1677 1678 memset(sp, 0, sizeof(*sp)); 1679 sp->xinc = 1; 1680 sp->yinc = 1; 1681 sp->in_w = state->src_w >> 16; 1682 sp->in_w_uv = sp->in_w; 1683 sp->in_h = state->src_h >> 16; 1684 sp->in_h_uv = sp->in_h; 1685 1686 sp->scale_x = sp->in_w != state->crtc_w; 1687 sp->scale_y = sp->in_h != state->crtc_h; 1688 1689 if (dispc_fourcc_is_yuv(fourcc)) { 1690 in_width_max_5tap = f->in_width_max_5tap_yuv; 1691 in_width_max_3tap = f->in_width_max_3tap_yuv; 1692 1693 sp->in_w_uv >>= 1; 1694 sp->scale_x = true; 1695 1696 if (fourcc == DRM_FORMAT_NV12) { 1697 sp->in_h_uv >>= 1; 1698 sp->scale_y = true; 1699 } 1700 } 1701 1702 /* Skip the rest if no scaling is used */ 1703 if ((!sp->scale_x && !sp->scale_y) || lite_plane) 1704 return 0; 1705 1706 if (sp->in_w > in_width_max_5tap) { 1707 sp->five_taps = false; 1708 in_width_max = in_width_max_3tap; 1709 downscale_limit = f->downscale_limit_3tap; 1710 } else { 1711 sp->five_taps = true; 1712 in_width_max = in_width_max_5tap; 1713 downscale_limit = f->downscale_limit_5tap; 1714 } 1715 1716 if (sp->scale_x) { 1717 sp->fir_xinc = dispc_calc_fir_inc(sp->in_w, state->crtc_w); 1718 1719 if (sp->fir_xinc < dispc_calc_fir_inc(1, f->upscale_limit)) { 1720 dev_dbg(dispc->dev, 1721 "%s: X-scaling factor %u/%u > %u\n", 1722 __func__, state->crtc_w, state->src_w >> 16, 1723 f->upscale_limit); 1724 return -EINVAL; 1725 } 1726 1727 if (sp->fir_xinc >= dispc_calc_fir_inc(downscale_limit, 1)) { 1728 sp->xinc = DIV_ROUND_UP(DIV_ROUND_UP(sp->in_w, 1729 state->crtc_w), 1730 downscale_limit); 1731 1732 if (sp->xinc > f->xinc_max) { 1733 dev_dbg(dispc->dev, 1734 "%s: X-scaling factor %u/%u < 1/%u\n", 1735 __func__, state->crtc_w, 1736 state->src_w >> 16, 1737 downscale_limit * f->xinc_max); 1738 return -EINVAL; 1739 } 1740 1741 sp->in_w = (state->src_w >> 16) / sp->xinc; 1742 } 1743 1744 while (sp->in_w > in_width_max) { 1745 sp->xinc++; 1746 sp->in_w = (state->src_w >> 16) / sp->xinc; 1747 } 1748 1749 if (sp->xinc > f->xinc_max) { 1750 dev_dbg(dispc->dev, 1751 "%s: Too wide input buffer %u > %u\n", __func__, 1752 state->src_w >> 16, in_width_max * f->xinc_max); 1753 return -EINVAL; 1754 } 1755 1756 /* 1757 * We need even line length for YUV formats. Decimation 1758 * can lead to odd length, so we need to make it even 1759 * again. 1760 */ 1761 if (dispc_fourcc_is_yuv(fourcc)) 1762 sp->in_w &= ~1; 1763 1764 sp->fir_xinc = dispc_calc_fir_inc(sp->in_w, state->crtc_w); 1765 } 1766 1767 if (sp->scale_y) { 1768 sp->fir_yinc = dispc_calc_fir_inc(sp->in_h, state->crtc_h); 1769 1770 if (sp->fir_yinc < dispc_calc_fir_inc(1, f->upscale_limit)) { 1771 dev_dbg(dispc->dev, 1772 "%s: Y-scaling factor %u/%u > %u\n", 1773 __func__, state->crtc_h, state->src_h >> 16, 1774 f->upscale_limit); 1775 return -EINVAL; 1776 } 1777 1778 if (sp->fir_yinc >= dispc_calc_fir_inc(downscale_limit, 1)) { 1779 sp->yinc = DIV_ROUND_UP(DIV_ROUND_UP(sp->in_h, 1780 state->crtc_h), 1781 downscale_limit); 1782 1783 sp->in_h /= sp->yinc; 1784 sp->fir_yinc = dispc_calc_fir_inc(sp->in_h, 1785 state->crtc_h); 1786 } 1787 } 1788 1789 dev_dbg(dispc->dev, 1790 "%s: %ux%u decim %ux%u -> %ux%u firinc %u.%03ux%u.%03u taps %u -> %ux%u\n", 1791 __func__, state->src_w >> 16, state->src_h >> 16, 1792 sp->xinc, sp->yinc, sp->in_w, sp->in_h, 1793 sp->fir_xinc / 0x200000u, 1794 ((sp->fir_xinc & 0x1FFFFFu) * 999u) / 0x1FFFFFu, 1795 sp->fir_yinc / 0x200000u, 1796 ((sp->fir_yinc & 0x1FFFFFu) * 999u) / 0x1FFFFFu, 1797 sp->five_taps ? 5 : 3, 1798 state->crtc_w, state->crtc_h); 1799 1800 if (dispc_fourcc_is_yuv(fourcc)) { 1801 if (sp->scale_x) { 1802 sp->in_w_uv /= sp->xinc; 1803 sp->fir_xinc_uv = dispc_calc_fir_inc(sp->in_w_uv, 1804 state->crtc_w); 1805 sp->xcoef_uv = tidss_get_scale_coefs(dispc->dev, 1806 sp->fir_xinc_uv, 1807 true); 1808 } 1809 if (sp->scale_y) { 1810 sp->in_h_uv /= sp->yinc; 1811 sp->fir_yinc_uv = dispc_calc_fir_inc(sp->in_h_uv, 1812 state->crtc_h); 1813 sp->ycoef_uv = tidss_get_scale_coefs(dispc->dev, 1814 sp->fir_yinc_uv, 1815 sp->five_taps); 1816 } 1817 } 1818 1819 if (sp->scale_x) 1820 sp->xcoef = tidss_get_scale_coefs(dispc->dev, sp->fir_xinc, 1821 true); 1822 1823 if (sp->scale_y) 1824 sp->ycoef = tidss_get_scale_coefs(dispc->dev, sp->fir_yinc, 1825 sp->five_taps); 1826 1827 return 0; 1828 } 1829 1830 static void dispc_vid_set_scaling(struct dispc_device *dispc, 1831 u32 hw_plane, 1832 struct dispc_scaling_params *sp, 1833 u32 fourcc) 1834 { 1835 /* HORIZONTAL RESIZE ENABLE */ 1836 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1837 sp->scale_x, 7, 7); 1838 1839 /* VERTICAL RESIZE ENABLE */ 1840 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1841 sp->scale_y, 8, 8); 1842 1843 /* Skip the rest if no scaling is used */ 1844 if (!sp->scale_x && !sp->scale_y) 1845 return; 1846 1847 /* VERTICAL 5-TAPS */ 1848 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1849 sp->five_taps, 21, 21); 1850 1851 if (dispc_fourcc_is_yuv(fourcc)) { 1852 if (sp->scale_x) { 1853 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRH2, 1854 sp->fir_xinc_uv); 1855 dispc_vid_write_fir_coefs(dispc, hw_plane, 1856 DISPC_VID_FIR_COEF_HORIZ_UV, 1857 sp->xcoef_uv); 1858 } 1859 if (sp->scale_y) { 1860 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRV2, 1861 sp->fir_yinc_uv); 1862 dispc_vid_write_fir_coefs(dispc, hw_plane, 1863 DISPC_VID_FIR_COEF_VERT_UV, 1864 sp->ycoef_uv); 1865 } 1866 } 1867 1868 if (sp->scale_x) { 1869 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRH, sp->fir_xinc); 1870 dispc_vid_write_fir_coefs(dispc, hw_plane, 1871 DISPC_VID_FIR_COEF_HORIZ, 1872 sp->xcoef); 1873 } 1874 1875 if (sp->scale_y) { 1876 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRV, sp->fir_yinc); 1877 dispc_vid_write_fir_coefs(dispc, hw_plane, 1878 DISPC_VID_FIR_COEF_VERT, sp->ycoef); 1879 } 1880 } 1881 1882 /* OTHER */ 1883 1884 static const struct { 1885 u32 fourcc; 1886 u8 dss_code; 1887 } dispc_color_formats[] = { 1888 { DRM_FORMAT_ARGB4444, 0x0, }, 1889 { DRM_FORMAT_ABGR4444, 0x1, }, 1890 { DRM_FORMAT_RGBA4444, 0x2, }, 1891 1892 { DRM_FORMAT_RGB565, 0x3, }, 1893 { DRM_FORMAT_BGR565, 0x4, }, 1894 1895 { DRM_FORMAT_ARGB1555, 0x5, }, 1896 { DRM_FORMAT_ABGR1555, 0x6, }, 1897 1898 { DRM_FORMAT_ARGB8888, 0x7, }, 1899 { DRM_FORMAT_ABGR8888, 0x8, }, 1900 { DRM_FORMAT_RGBA8888, 0x9, }, 1901 { DRM_FORMAT_BGRA8888, 0xa, }, 1902 1903 { DRM_FORMAT_RGB888, 0xb, }, 1904 { DRM_FORMAT_BGR888, 0xc, }, 1905 1906 { DRM_FORMAT_ARGB2101010, 0xe, }, 1907 { DRM_FORMAT_ABGR2101010, 0xf, }, 1908 1909 { DRM_FORMAT_XRGB4444, 0x20, }, 1910 { DRM_FORMAT_XBGR4444, 0x21, }, 1911 { DRM_FORMAT_RGBX4444, 0x22, }, 1912 1913 { DRM_FORMAT_XRGB1555, 0x25, }, 1914 { DRM_FORMAT_XBGR1555, 0x26, }, 1915 1916 { DRM_FORMAT_XRGB8888, 0x27, }, 1917 { DRM_FORMAT_XBGR8888, 0x28, }, 1918 { DRM_FORMAT_RGBX8888, 0x29, }, 1919 { DRM_FORMAT_BGRX8888, 0x2a, }, 1920 1921 { DRM_FORMAT_XRGB2101010, 0x2e, }, 1922 { DRM_FORMAT_XBGR2101010, 0x2f, }, 1923 1924 { DRM_FORMAT_YUYV, 0x3e, }, 1925 { DRM_FORMAT_UYVY, 0x3f, }, 1926 1927 { DRM_FORMAT_NV12, 0x3d, }, 1928 }; 1929 1930 static void dispc_plane_set_pixel_format(struct dispc_device *dispc, 1931 u32 hw_plane, u32 fourcc) 1932 { 1933 unsigned int i; 1934 1935 for (i = 0; i < ARRAY_SIZE(dispc_color_formats); ++i) { 1936 if (dispc_color_formats[i].fourcc == fourcc) { 1937 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1938 dispc_color_formats[i].dss_code, 1939 6, 1); 1940 return; 1941 } 1942 } 1943 1944 WARN_ON(1); 1945 } 1946 1947 const u32 *dispc_plane_formats(struct dispc_device *dispc, unsigned int *len) 1948 { 1949 WARN_ON(!dispc->fourccs); 1950 1951 *len = dispc->num_fourccs; 1952 1953 return dispc->fourccs; 1954 } 1955 1956 static s32 pixinc(int pixels, u8 ps) 1957 { 1958 if (pixels == 1) 1959 return 1; 1960 else if (pixels > 1) 1961 return 1 + (pixels - 1) * ps; 1962 else if (pixels < 0) 1963 return 1 - (-pixels + 1) * ps; 1964 1965 WARN_ON(1); 1966 return 0; 1967 } 1968 1969 int dispc_plane_check(struct dispc_device *dispc, u32 hw_plane, 1970 const struct drm_plane_state *state, 1971 u32 hw_videoport) 1972 { 1973 bool lite = dispc->feat->vid_lite[hw_plane]; 1974 u32 fourcc = state->fb->format->format; 1975 bool need_scaling = state->src_w >> 16 != state->crtc_w || 1976 state->src_h >> 16 != state->crtc_h; 1977 struct dispc_scaling_params scaling; 1978 int ret; 1979 1980 if (dispc_fourcc_is_yuv(fourcc)) { 1981 if (!dispc_find_csc(state->color_encoding, 1982 state->color_range)) { 1983 dev_dbg(dispc->dev, 1984 "%s: Unsupported CSC (%u,%u) for HW plane %u\n", 1985 __func__, state->color_encoding, 1986 state->color_range, hw_plane); 1987 return -EINVAL; 1988 } 1989 } 1990 1991 if (need_scaling) { 1992 if (lite) { 1993 dev_dbg(dispc->dev, 1994 "%s: Lite plane %u can't scale %ux%u!=%ux%u\n", 1995 __func__, hw_plane, 1996 state->src_w >> 16, state->src_h >> 16, 1997 state->crtc_w, state->crtc_h); 1998 return -EINVAL; 1999 } 2000 ret = dispc_vid_calc_scaling(dispc, state, &scaling, false); 2001 if (ret) 2002 return ret; 2003 } 2004 2005 return 0; 2006 } 2007 2008 static 2009 dma_addr_t dispc_plane_state_dma_addr(const struct drm_plane_state *state) 2010 { 2011 struct drm_framebuffer *fb = state->fb; 2012 struct drm_gem_dma_object *gem; 2013 u32 x = state->src_x >> 16; 2014 u32 y = state->src_y >> 16; 2015 2016 gem = drm_fb_dma_get_gem_obj(state->fb, 0); 2017 2018 return gem->dma_addr + fb->offsets[0] + x * fb->format->cpp[0] + 2019 y * fb->pitches[0]; 2020 } 2021 2022 static 2023 dma_addr_t dispc_plane_state_p_uv_addr(const struct drm_plane_state *state) 2024 { 2025 struct drm_framebuffer *fb = state->fb; 2026 struct drm_gem_dma_object *gem; 2027 u32 x = state->src_x >> 16; 2028 u32 y = state->src_y >> 16; 2029 2030 if (WARN_ON(state->fb->format->num_planes != 2)) 2031 return 0; 2032 2033 gem = drm_fb_dma_get_gem_obj(fb, 1); 2034 2035 return gem->dma_addr + fb->offsets[1] + 2036 (x * fb->format->cpp[1] / fb->format->hsub) + 2037 (y * fb->pitches[1] / fb->format->vsub); 2038 } 2039 2040 void dispc_plane_setup(struct dispc_device *dispc, u32 hw_plane, 2041 const struct drm_plane_state *state, 2042 u32 hw_videoport) 2043 { 2044 bool lite = dispc->feat->vid_lite[hw_plane]; 2045 u32 fourcc = state->fb->format->format; 2046 u16 cpp = state->fb->format->cpp[0]; 2047 u32 fb_width = state->fb->pitches[0] / cpp; 2048 dma_addr_t dma_addr = dispc_plane_state_dma_addr(state); 2049 struct dispc_scaling_params scale; 2050 2051 dispc_vid_calc_scaling(dispc, state, &scale, lite); 2052 2053 dispc_plane_set_pixel_format(dispc, hw_plane, fourcc); 2054 2055 dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_0, dma_addr & 0xffffffff); 2056 dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_0, (u64)dma_addr >> 32); 2057 dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_1, dma_addr & 0xffffffff); 2058 dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_1, (u64)dma_addr >> 32); 2059 2060 dispc_vid_write(dispc, hw_plane, DISPC_VID_PICTURE_SIZE, 2061 (scale.in_w - 1) | ((scale.in_h - 1) << 16)); 2062 2063 /* For YUV422 format we use the macropixel size for pixel inc */ 2064 if (fourcc == DRM_FORMAT_YUYV || fourcc == DRM_FORMAT_UYVY) 2065 dispc_vid_write(dispc, hw_plane, DISPC_VID_PIXEL_INC, 2066 pixinc(scale.xinc, cpp * 2)); 2067 else 2068 dispc_vid_write(dispc, hw_plane, DISPC_VID_PIXEL_INC, 2069 pixinc(scale.xinc, cpp)); 2070 2071 dispc_vid_write(dispc, hw_plane, DISPC_VID_ROW_INC, 2072 pixinc(1 + (scale.yinc * fb_width - 2073 scale.xinc * scale.in_w), 2074 cpp)); 2075 2076 if (state->fb->format->num_planes == 2) { 2077 u16 cpp_uv = state->fb->format->cpp[1]; 2078 u32 fb_width_uv = state->fb->pitches[1] / cpp_uv; 2079 dma_addr_t p_uv_addr = dispc_plane_state_p_uv_addr(state); 2080 2081 dispc_vid_write(dispc, hw_plane, 2082 DISPC_VID_BA_UV_0, p_uv_addr & 0xffffffff); 2083 dispc_vid_write(dispc, hw_plane, 2084 DISPC_VID_BA_UV_EXT_0, (u64)p_uv_addr >> 32); 2085 dispc_vid_write(dispc, hw_plane, 2086 DISPC_VID_BA_UV_1, p_uv_addr & 0xffffffff); 2087 dispc_vid_write(dispc, hw_plane, 2088 DISPC_VID_BA_UV_EXT_1, (u64)p_uv_addr >> 32); 2089 2090 dispc_vid_write(dispc, hw_plane, DISPC_VID_ROW_INC_UV, 2091 pixinc(1 + (scale.yinc * fb_width_uv - 2092 scale.xinc * scale.in_w_uv), 2093 cpp_uv)); 2094 } 2095 2096 if (!lite) { 2097 dispc_vid_write(dispc, hw_plane, DISPC_VID_SIZE, 2098 (state->crtc_w - 1) | 2099 ((state->crtc_h - 1) << 16)); 2100 2101 dispc_vid_set_scaling(dispc, hw_plane, &scale, fourcc); 2102 } 2103 2104 /* enable YUV->RGB color conversion */ 2105 if (dispc_fourcc_is_yuv(fourcc)) { 2106 dispc_vid_csc_setup(dispc, hw_plane, state); 2107 dispc_vid_csc_enable(dispc, hw_plane, true); 2108 } else { 2109 dispc_vid_csc_enable(dispc, hw_plane, false); 2110 } 2111 2112 dispc_vid_write(dispc, hw_plane, DISPC_VID_GLOBAL_ALPHA, 2113 0xFF & (state->alpha >> 8)); 2114 2115 if (state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) 2116 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1, 2117 28, 28); 2118 else 2119 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 0, 2120 28, 28); 2121 } 2122 2123 void dispc_plane_enable(struct dispc_device *dispc, u32 hw_plane, bool enable) 2124 { 2125 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, 0, 0); 2126 } 2127 2128 static u32 dispc_vid_get_fifo_size(struct dispc_device *dispc, u32 hw_plane) 2129 { 2130 return VID_REG_GET(dispc, hw_plane, DISPC_VID_BUF_SIZE_STATUS, 15, 0); 2131 } 2132 2133 static void dispc_vid_set_mflag_threshold(struct dispc_device *dispc, 2134 u32 hw_plane, u32 low, u32 high) 2135 { 2136 dispc_vid_write(dispc, hw_plane, DISPC_VID_MFLAG_THRESHOLD, 2137 FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0)); 2138 } 2139 2140 static void dispc_vid_set_buf_threshold(struct dispc_device *dispc, 2141 u32 hw_plane, u32 low, u32 high) 2142 { 2143 dispc_vid_write(dispc, hw_plane, DISPC_VID_BUF_THRESHOLD, 2144 FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0)); 2145 } 2146 2147 static void dispc_k2g_plane_init(struct dispc_device *dispc) 2148 { 2149 unsigned int hw_plane; 2150 2151 dev_dbg(dispc->dev, "%s()\n", __func__); 2152 2153 /* MFLAG_CTRL = ENABLED */ 2154 REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, 1, 0); 2155 /* MFLAG_START = MFLAGNORMALSTARTMODE */ 2156 REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, 6, 6); 2157 2158 for (hw_plane = 0; hw_plane < dispc->feat->num_planes; hw_plane++) { 2159 u32 size = dispc_vid_get_fifo_size(dispc, hw_plane); 2160 u32 thr_low, thr_high; 2161 u32 mflag_low, mflag_high; 2162 u32 preload; 2163 2164 thr_high = size - 1; 2165 thr_low = size / 2; 2166 2167 mflag_high = size * 2 / 3; 2168 mflag_low = size / 3; 2169 2170 preload = thr_low; 2171 2172 dev_dbg(dispc->dev, 2173 "%s: bufsize %u, buf_threshold %u/%u, mflag threshold %u/%u preload %u\n", 2174 dispc->feat->vid_name[hw_plane], 2175 size, 2176 thr_high, thr_low, 2177 mflag_high, mflag_low, 2178 preload); 2179 2180 dispc_vid_set_buf_threshold(dispc, hw_plane, 2181 thr_low, thr_high); 2182 dispc_vid_set_mflag_threshold(dispc, hw_plane, 2183 mflag_low, mflag_high); 2184 2185 dispc_vid_write(dispc, hw_plane, DISPC_VID_PRELOAD, preload); 2186 2187 /* 2188 * Prefetch up to fifo high-threshold value to minimize the 2189 * possibility of underflows. Note that this means the PRELOAD 2190 * register is ignored. 2191 */ 2192 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1, 2193 19, 19); 2194 } 2195 } 2196 2197 static void dispc_k3_plane_init(struct dispc_device *dispc) 2198 { 2199 unsigned int hw_plane; 2200 u32 cba_lo_pri = 1; 2201 u32 cba_hi_pri = 0; 2202 2203 dev_dbg(dispc->dev, "%s()\n", __func__); 2204 2205 REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_lo_pri, 2, 0); 2206 REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_hi_pri, 5, 3); 2207 2208 /* MFLAG_CTRL = ENABLED */ 2209 REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, 1, 0); 2210 /* MFLAG_START = MFLAGNORMALSTARTMODE */ 2211 REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, 6, 6); 2212 2213 for (hw_plane = 0; hw_plane < dispc->feat->num_planes; hw_plane++) { 2214 u32 size = dispc_vid_get_fifo_size(dispc, hw_plane); 2215 u32 thr_low, thr_high; 2216 u32 mflag_low, mflag_high; 2217 u32 preload; 2218 2219 thr_high = size - 1; 2220 thr_low = size / 2; 2221 2222 mflag_high = size * 2 / 3; 2223 mflag_low = size / 3; 2224 2225 preload = thr_low; 2226 2227 dev_dbg(dispc->dev, 2228 "%s: bufsize %u, buf_threshold %u/%u, mflag threshold %u/%u preload %u\n", 2229 dispc->feat->vid_name[hw_plane], 2230 size, 2231 thr_high, thr_low, 2232 mflag_high, mflag_low, 2233 preload); 2234 2235 dispc_vid_set_buf_threshold(dispc, hw_plane, 2236 thr_low, thr_high); 2237 dispc_vid_set_mflag_threshold(dispc, hw_plane, 2238 mflag_low, mflag_high); 2239 2240 dispc_vid_write(dispc, hw_plane, DISPC_VID_PRELOAD, preload); 2241 2242 /* Prefech up to PRELOAD value */ 2243 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 0, 2244 19, 19); 2245 } 2246 } 2247 2248 static void dispc_plane_init(struct dispc_device *dispc) 2249 { 2250 switch (dispc->feat->subrev) { 2251 case DISPC_K2G: 2252 dispc_k2g_plane_init(dispc); 2253 break; 2254 case DISPC_AM625: 2255 case DISPC_AM65X: 2256 case DISPC_J721E: 2257 dispc_k3_plane_init(dispc); 2258 break; 2259 default: 2260 WARN_ON(1); 2261 } 2262 } 2263 2264 static void dispc_vp_init(struct dispc_device *dispc) 2265 { 2266 unsigned int i; 2267 2268 dev_dbg(dispc->dev, "%s()\n", __func__); 2269 2270 /* Enable the gamma Shadow bit-field for all VPs*/ 2271 for (i = 0; i < dispc->feat->num_vps; i++) 2272 VP_REG_FLD_MOD(dispc, i, DISPC_VP_CONFIG, 1, 2, 2); 2273 } 2274 2275 static void dispc_initial_config(struct dispc_device *dispc) 2276 { 2277 dispc_plane_init(dispc); 2278 dispc_vp_init(dispc); 2279 2280 /* Note: Hardcoded DPI routing on J721E for now */ 2281 if (dispc->feat->subrev == DISPC_J721E) { 2282 dispc_write(dispc, DISPC_CONNECTIONS, 2283 FLD_VAL(2, 3, 0) | /* VP1 to DPI0 */ 2284 FLD_VAL(8, 7, 4) /* VP3 to DPI1 */ 2285 ); 2286 } 2287 } 2288 2289 static void dispc_k2g_vp_write_gamma_table(struct dispc_device *dispc, 2290 u32 hw_videoport) 2291 { 2292 u32 *table = dispc->vp_data[hw_videoport].gamma_table; 2293 u32 hwlen = dispc->feat->vp_feat.color.gamma_size; 2294 unsigned int i; 2295 2296 dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport); 2297 2298 if (WARN_ON(dispc->feat->vp_feat.color.gamma_type != TIDSS_GAMMA_8BIT)) 2299 return; 2300 2301 for (i = 0; i < hwlen; ++i) { 2302 u32 v = table[i]; 2303 2304 v |= i << 24; 2305 2306 dispc_vp_write(dispc, hw_videoport, DISPC_VP_K2G_GAMMA_TABLE, 2307 v); 2308 } 2309 } 2310 2311 static void dispc_am65x_vp_write_gamma_table(struct dispc_device *dispc, 2312 u32 hw_videoport) 2313 { 2314 u32 *table = dispc->vp_data[hw_videoport].gamma_table; 2315 u32 hwlen = dispc->feat->vp_feat.color.gamma_size; 2316 unsigned int i; 2317 2318 dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport); 2319 2320 if (WARN_ON(dispc->feat->vp_feat.color.gamma_type != TIDSS_GAMMA_8BIT)) 2321 return; 2322 2323 for (i = 0; i < hwlen; ++i) { 2324 u32 v = table[i]; 2325 2326 v |= i << 24; 2327 2328 dispc_vp_write(dispc, hw_videoport, DISPC_VP_GAMMA_TABLE, v); 2329 } 2330 } 2331 2332 static void dispc_j721e_vp_write_gamma_table(struct dispc_device *dispc, 2333 u32 hw_videoport) 2334 { 2335 u32 *table = dispc->vp_data[hw_videoport].gamma_table; 2336 u32 hwlen = dispc->feat->vp_feat.color.gamma_size; 2337 unsigned int i; 2338 2339 dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport); 2340 2341 if (WARN_ON(dispc->feat->vp_feat.color.gamma_type != TIDSS_GAMMA_10BIT)) 2342 return; 2343 2344 for (i = 0; i < hwlen; ++i) { 2345 u32 v = table[i]; 2346 2347 if (i == 0) 2348 v |= 1 << 31; 2349 2350 dispc_vp_write(dispc, hw_videoport, DISPC_VP_GAMMA_TABLE, v); 2351 } 2352 } 2353 2354 static void dispc_vp_write_gamma_table(struct dispc_device *dispc, 2355 u32 hw_videoport) 2356 { 2357 switch (dispc->feat->subrev) { 2358 case DISPC_K2G: 2359 dispc_k2g_vp_write_gamma_table(dispc, hw_videoport); 2360 break; 2361 case DISPC_AM625: 2362 case DISPC_AM65X: 2363 dispc_am65x_vp_write_gamma_table(dispc, hw_videoport); 2364 break; 2365 case DISPC_J721E: 2366 dispc_j721e_vp_write_gamma_table(dispc, hw_videoport); 2367 break; 2368 default: 2369 WARN_ON(1); 2370 break; 2371 } 2372 } 2373 2374 static const struct drm_color_lut dispc_vp_gamma_default_lut[] = { 2375 { .red = 0, .green = 0, .blue = 0, }, 2376 { .red = U16_MAX, .green = U16_MAX, .blue = U16_MAX, }, 2377 }; 2378 2379 static void dispc_vp_set_gamma(struct dispc_device *dispc, 2380 u32 hw_videoport, 2381 const struct drm_color_lut *lut, 2382 unsigned int length) 2383 { 2384 u32 *table = dispc->vp_data[hw_videoport].gamma_table; 2385 u32 hwlen = dispc->feat->vp_feat.color.gamma_size; 2386 u32 hwbits; 2387 unsigned int i; 2388 2389 dev_dbg(dispc->dev, "%s: hw_videoport %d, lut len %u, hw len %u\n", 2390 __func__, hw_videoport, length, hwlen); 2391 2392 if (dispc->feat->vp_feat.color.gamma_type == TIDSS_GAMMA_10BIT) 2393 hwbits = 10; 2394 else 2395 hwbits = 8; 2396 2397 if (!lut || length < 2) { 2398 lut = dispc_vp_gamma_default_lut; 2399 length = ARRAY_SIZE(dispc_vp_gamma_default_lut); 2400 } 2401 2402 for (i = 0; i < length - 1; ++i) { 2403 unsigned int first = i * (hwlen - 1) / (length - 1); 2404 unsigned int last = (i + 1) * (hwlen - 1) / (length - 1); 2405 unsigned int w = last - first; 2406 u16 r, g, b; 2407 unsigned int j; 2408 2409 if (w == 0) 2410 continue; 2411 2412 for (j = 0; j <= w; j++) { 2413 r = (lut[i].red * (w - j) + lut[i + 1].red * j) / w; 2414 g = (lut[i].green * (w - j) + lut[i + 1].green * j) / w; 2415 b = (lut[i].blue * (w - j) + lut[i + 1].blue * j) / w; 2416 2417 r >>= 16 - hwbits; 2418 g >>= 16 - hwbits; 2419 b >>= 16 - hwbits; 2420 2421 table[first + j] = (r << (hwbits * 2)) | 2422 (g << hwbits) | b; 2423 } 2424 } 2425 2426 dispc_vp_write_gamma_table(dispc, hw_videoport); 2427 } 2428 2429 static s16 dispc_S31_32_to_s2_8(s64 coef) 2430 { 2431 u64 sign_bit = 1ULL << 63; 2432 u64 cbits = (u64)coef; 2433 s16 ret; 2434 2435 if (cbits & sign_bit) 2436 ret = -clamp_val(((cbits & ~sign_bit) >> 24), 0, 0x200); 2437 else 2438 ret = clamp_val(((cbits & ~sign_bit) >> 24), 0, 0x1FF); 2439 2440 return ret; 2441 } 2442 2443 static void dispc_k2g_cpr_from_ctm(const struct drm_color_ctm *ctm, 2444 struct dispc_csc_coef *cpr) 2445 { 2446 memset(cpr, 0, sizeof(*cpr)); 2447 2448 cpr->to_regval = dispc_csc_cpr_regval; 2449 cpr->m[CSC_RR] = dispc_S31_32_to_s2_8(ctm->matrix[0]); 2450 cpr->m[CSC_RG] = dispc_S31_32_to_s2_8(ctm->matrix[1]); 2451 cpr->m[CSC_RB] = dispc_S31_32_to_s2_8(ctm->matrix[2]); 2452 cpr->m[CSC_GR] = dispc_S31_32_to_s2_8(ctm->matrix[3]); 2453 cpr->m[CSC_GG] = dispc_S31_32_to_s2_8(ctm->matrix[4]); 2454 cpr->m[CSC_GB] = dispc_S31_32_to_s2_8(ctm->matrix[5]); 2455 cpr->m[CSC_BR] = dispc_S31_32_to_s2_8(ctm->matrix[6]); 2456 cpr->m[CSC_BG] = dispc_S31_32_to_s2_8(ctm->matrix[7]); 2457 cpr->m[CSC_BB] = dispc_S31_32_to_s2_8(ctm->matrix[8]); 2458 } 2459 2460 #define CVAL(xR, xG, xB) (FLD_VAL(xR, 9, 0) | FLD_VAL(xG, 20, 11) | \ 2461 FLD_VAL(xB, 31, 22)) 2462 2463 static void dispc_k2g_vp_csc_cpr_regval(const struct dispc_csc_coef *csc, 2464 u32 *regval) 2465 { 2466 regval[0] = CVAL(csc->m[CSC_BB], csc->m[CSC_BG], csc->m[CSC_BR]); 2467 regval[1] = CVAL(csc->m[CSC_GB], csc->m[CSC_GG], csc->m[CSC_GR]); 2468 regval[2] = CVAL(csc->m[CSC_RB], csc->m[CSC_RG], csc->m[CSC_RR]); 2469 } 2470 2471 #undef CVAL 2472 2473 static void dispc_k2g_vp_write_csc(struct dispc_device *dispc, u32 hw_videoport, 2474 const struct dispc_csc_coef *csc) 2475 { 2476 static const u16 dispc_vp_cpr_coef_reg[] = { 2477 DISPC_VP_CSC_COEF0, DISPC_VP_CSC_COEF1, DISPC_VP_CSC_COEF2, 2478 /* K2G CPR is packed to three registers. */ 2479 }; 2480 u32 regval[DISPC_CSC_REGVAL_LEN]; 2481 unsigned int i; 2482 2483 dispc_k2g_vp_csc_cpr_regval(csc, regval); 2484 2485 for (i = 0; i < ARRAY_SIZE(dispc_vp_cpr_coef_reg); i++) 2486 dispc_vp_write(dispc, hw_videoport, dispc_vp_cpr_coef_reg[i], 2487 regval[i]); 2488 } 2489 2490 static void dispc_k2g_vp_set_ctm(struct dispc_device *dispc, u32 hw_videoport, 2491 struct drm_color_ctm *ctm) 2492 { 2493 u32 cprenable = 0; 2494 2495 if (ctm) { 2496 struct dispc_csc_coef cpr; 2497 2498 dispc_k2g_cpr_from_ctm(ctm, &cpr); 2499 dispc_k2g_vp_write_csc(dispc, hw_videoport, &cpr); 2500 cprenable = 1; 2501 } 2502 2503 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG, 2504 cprenable, 15, 15); 2505 } 2506 2507 static s16 dispc_S31_32_to_s3_8(s64 coef) 2508 { 2509 u64 sign_bit = 1ULL << 63; 2510 u64 cbits = (u64)coef; 2511 s16 ret; 2512 2513 if (cbits & sign_bit) 2514 ret = -clamp_val(((cbits & ~sign_bit) >> 24), 0, 0x400); 2515 else 2516 ret = clamp_val(((cbits & ~sign_bit) >> 24), 0, 0x3FF); 2517 2518 return ret; 2519 } 2520 2521 static void dispc_csc_from_ctm(const struct drm_color_ctm *ctm, 2522 struct dispc_csc_coef *cpr) 2523 { 2524 memset(cpr, 0, sizeof(*cpr)); 2525 2526 cpr->to_regval = dispc_csc_cpr_regval; 2527 cpr->m[CSC_RR] = dispc_S31_32_to_s3_8(ctm->matrix[0]); 2528 cpr->m[CSC_RG] = dispc_S31_32_to_s3_8(ctm->matrix[1]); 2529 cpr->m[CSC_RB] = dispc_S31_32_to_s3_8(ctm->matrix[2]); 2530 cpr->m[CSC_GR] = dispc_S31_32_to_s3_8(ctm->matrix[3]); 2531 cpr->m[CSC_GG] = dispc_S31_32_to_s3_8(ctm->matrix[4]); 2532 cpr->m[CSC_GB] = dispc_S31_32_to_s3_8(ctm->matrix[5]); 2533 cpr->m[CSC_BR] = dispc_S31_32_to_s3_8(ctm->matrix[6]); 2534 cpr->m[CSC_BG] = dispc_S31_32_to_s3_8(ctm->matrix[7]); 2535 cpr->m[CSC_BB] = dispc_S31_32_to_s3_8(ctm->matrix[8]); 2536 } 2537 2538 static void dispc_k3_vp_write_csc(struct dispc_device *dispc, u32 hw_videoport, 2539 const struct dispc_csc_coef *csc) 2540 { 2541 static const u16 dispc_vp_csc_coef_reg[DISPC_CSC_REGVAL_LEN] = { 2542 DISPC_VP_CSC_COEF0, DISPC_VP_CSC_COEF1, DISPC_VP_CSC_COEF2, 2543 DISPC_VP_CSC_COEF3, DISPC_VP_CSC_COEF4, DISPC_VP_CSC_COEF5, 2544 DISPC_VP_CSC_COEF6, DISPC_VP_CSC_COEF7, 2545 }; 2546 u32 regval[DISPC_CSC_REGVAL_LEN]; 2547 unsigned int i; 2548 2549 csc->to_regval(csc, regval); 2550 2551 for (i = 0; i < ARRAY_SIZE(regval); i++) 2552 dispc_vp_write(dispc, hw_videoport, dispc_vp_csc_coef_reg[i], 2553 regval[i]); 2554 } 2555 2556 static void dispc_k3_vp_set_ctm(struct dispc_device *dispc, u32 hw_videoport, 2557 struct drm_color_ctm *ctm) 2558 { 2559 u32 colorconvenable = 0; 2560 2561 if (ctm) { 2562 struct dispc_csc_coef csc; 2563 2564 dispc_csc_from_ctm(ctm, &csc); 2565 dispc_k3_vp_write_csc(dispc, hw_videoport, &csc); 2566 colorconvenable = 1; 2567 } 2568 2569 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG, 2570 colorconvenable, 24, 24); 2571 } 2572 2573 static void dispc_vp_set_color_mgmt(struct dispc_device *dispc, 2574 u32 hw_videoport, 2575 const struct drm_crtc_state *state, 2576 bool newmodeset) 2577 { 2578 struct drm_color_lut *lut = NULL; 2579 struct drm_color_ctm *ctm = NULL; 2580 unsigned int length = 0; 2581 2582 if (!(state->color_mgmt_changed || newmodeset)) 2583 return; 2584 2585 if (state->gamma_lut) { 2586 lut = (struct drm_color_lut *)state->gamma_lut->data; 2587 length = state->gamma_lut->length / sizeof(*lut); 2588 } 2589 2590 dispc_vp_set_gamma(dispc, hw_videoport, lut, length); 2591 2592 if (state->ctm) 2593 ctm = (struct drm_color_ctm *)state->ctm->data; 2594 2595 if (dispc->feat->subrev == DISPC_K2G) 2596 dispc_k2g_vp_set_ctm(dispc, hw_videoport, ctm); 2597 else 2598 dispc_k3_vp_set_ctm(dispc, hw_videoport, ctm); 2599 } 2600 2601 void dispc_vp_setup(struct dispc_device *dispc, u32 hw_videoport, 2602 const struct drm_crtc_state *state, bool newmodeset) 2603 { 2604 dispc_vp_set_default_color(dispc, hw_videoport, 0); 2605 dispc_vp_set_color_mgmt(dispc, hw_videoport, state, newmodeset); 2606 } 2607 2608 int dispc_runtime_suspend(struct dispc_device *dispc) 2609 { 2610 dev_dbg(dispc->dev, "suspend\n"); 2611 2612 dispc->is_enabled = false; 2613 2614 clk_disable_unprepare(dispc->fclk); 2615 2616 return 0; 2617 } 2618 2619 int dispc_runtime_resume(struct dispc_device *dispc) 2620 { 2621 dev_dbg(dispc->dev, "resume\n"); 2622 2623 clk_prepare_enable(dispc->fclk); 2624 2625 if (REG_GET(dispc, DSS_SYSSTATUS, 0, 0) == 0) 2626 dev_warn(dispc->dev, "DSS FUNC RESET not done!\n"); 2627 2628 dev_dbg(dispc->dev, "OMAP DSS7 rev 0x%x\n", 2629 dispc_read(dispc, DSS_REVISION)); 2630 2631 dev_dbg(dispc->dev, "VP RESETDONE %d,%d,%d\n", 2632 REG_GET(dispc, DSS_SYSSTATUS, 1, 1), 2633 REG_GET(dispc, DSS_SYSSTATUS, 2, 2), 2634 REG_GET(dispc, DSS_SYSSTATUS, 3, 3)); 2635 2636 if (dispc->feat->subrev == DISPC_AM625 || 2637 dispc->feat->subrev == DISPC_AM65X) 2638 dev_dbg(dispc->dev, "OLDI RESETDONE %d,%d,%d\n", 2639 REG_GET(dispc, DSS_SYSSTATUS, 5, 5), 2640 REG_GET(dispc, DSS_SYSSTATUS, 6, 6), 2641 REG_GET(dispc, DSS_SYSSTATUS, 7, 7)); 2642 2643 dev_dbg(dispc->dev, "DISPC IDLE %d\n", 2644 REG_GET(dispc, DSS_SYSSTATUS, 9, 9)); 2645 2646 dispc_initial_config(dispc); 2647 2648 dispc->is_enabled = true; 2649 2650 tidss_irq_resume(dispc->tidss); 2651 2652 return 0; 2653 } 2654 2655 void dispc_remove(struct tidss_device *tidss) 2656 { 2657 dev_dbg(tidss->dev, "%s\n", __func__); 2658 2659 tidss->dispc = NULL; 2660 } 2661 2662 static int dispc_iomap_resource(struct platform_device *pdev, const char *name, 2663 void __iomem **base) 2664 { 2665 void __iomem *b; 2666 2667 b = devm_platform_ioremap_resource_byname(pdev, name); 2668 if (IS_ERR(b)) { 2669 dev_err(&pdev->dev, "cannot ioremap resource '%s'\n", name); 2670 return PTR_ERR(b); 2671 } 2672 2673 *base = b; 2674 2675 return 0; 2676 } 2677 2678 static int dispc_init_am65x_oldi_io_ctrl(struct device *dev, 2679 struct dispc_device *dispc) 2680 { 2681 dispc->oldi_io_ctrl = 2682 syscon_regmap_lookup_by_phandle(dev->of_node, 2683 "ti,am65x-oldi-io-ctrl"); 2684 if (PTR_ERR(dispc->oldi_io_ctrl) == -ENODEV) { 2685 dispc->oldi_io_ctrl = NULL; 2686 } else if (IS_ERR(dispc->oldi_io_ctrl)) { 2687 dev_err(dev, "%s: syscon_regmap_lookup_by_phandle failed %ld\n", 2688 __func__, PTR_ERR(dispc->oldi_io_ctrl)); 2689 return PTR_ERR(dispc->oldi_io_ctrl); 2690 } 2691 return 0; 2692 } 2693 2694 static void dispc_init_errata(struct dispc_device *dispc) 2695 { 2696 static const struct soc_device_attribute am65x_sr10_soc_devices[] = { 2697 { .family = "AM65X", .revision = "SR1.0" }, 2698 { /* sentinel */ } 2699 }; 2700 2701 if (soc_device_match(am65x_sr10_soc_devices)) { 2702 dispc->errata.i2000 = true; 2703 dev_info(dispc->dev, "WA for erratum i2000: YUV formats disabled\n"); 2704 } 2705 } 2706 2707 static void dispc_softreset(struct dispc_device *dispc) 2708 { 2709 u32 val; 2710 int ret = 0; 2711 2712 /* Soft reset */ 2713 REG_FLD_MOD(dispc, DSS_SYSCONFIG, 1, 1, 1); 2714 /* Wait for reset to complete */ 2715 ret = readl_poll_timeout(dispc->base_common + DSS_SYSSTATUS, 2716 val, val & 1, 100, 5000); 2717 if (ret) 2718 dev_warn(dispc->dev, "failed to reset dispc\n"); 2719 } 2720 2721 int dispc_init(struct tidss_device *tidss) 2722 { 2723 struct device *dev = tidss->dev; 2724 struct platform_device *pdev = to_platform_device(dev); 2725 struct dispc_device *dispc; 2726 const struct dispc_features *feat; 2727 unsigned int i, num_fourccs; 2728 int r = 0; 2729 2730 dev_dbg(dev, "%s\n", __func__); 2731 2732 feat = tidss->feat; 2733 2734 if (feat->subrev != DISPC_K2G) { 2735 r = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)); 2736 if (r) 2737 dev_warn(dev, "cannot set DMA masks to 48-bit\n"); 2738 } 2739 2740 dma_set_max_seg_size(dev, UINT_MAX); 2741 2742 dispc = devm_kzalloc(dev, sizeof(*dispc), GFP_KERNEL); 2743 if (!dispc) 2744 return -ENOMEM; 2745 2746 dispc->tidss = tidss; 2747 dispc->dev = dev; 2748 dispc->feat = feat; 2749 2750 dispc_init_errata(dispc); 2751 2752 dispc->fourccs = devm_kcalloc(dev, ARRAY_SIZE(dispc_color_formats), 2753 sizeof(*dispc->fourccs), GFP_KERNEL); 2754 if (!dispc->fourccs) 2755 return -ENOMEM; 2756 2757 num_fourccs = 0; 2758 for (i = 0; i < ARRAY_SIZE(dispc_color_formats); ++i) { 2759 if (dispc->errata.i2000 && 2760 dispc_fourcc_is_yuv(dispc_color_formats[i].fourcc)) { 2761 continue; 2762 } 2763 dispc->fourccs[num_fourccs++] = dispc_color_formats[i].fourcc; 2764 } 2765 2766 dispc->num_fourccs = num_fourccs; 2767 2768 dispc_common_regmap = dispc->feat->common_regs; 2769 2770 r = dispc_iomap_resource(pdev, dispc->feat->common, 2771 &dispc->base_common); 2772 if (r) 2773 return r; 2774 2775 for (i = 0; i < dispc->feat->num_planes; i++) { 2776 r = dispc_iomap_resource(pdev, dispc->feat->vid_name[i], 2777 &dispc->base_vid[i]); 2778 if (r) 2779 return r; 2780 } 2781 2782 /* K2G display controller does not support soft reset */ 2783 if (feat->subrev != DISPC_K2G) 2784 dispc_softreset(dispc); 2785 2786 for (i = 0; i < dispc->feat->num_vps; i++) { 2787 u32 gamma_size = dispc->feat->vp_feat.color.gamma_size; 2788 u32 *gamma_table; 2789 struct clk *clk; 2790 2791 r = dispc_iomap_resource(pdev, dispc->feat->ovr_name[i], 2792 &dispc->base_ovr[i]); 2793 if (r) 2794 return r; 2795 2796 r = dispc_iomap_resource(pdev, dispc->feat->vp_name[i], 2797 &dispc->base_vp[i]); 2798 if (r) 2799 return r; 2800 2801 clk = devm_clk_get(dev, dispc->feat->vpclk_name[i]); 2802 if (IS_ERR(clk)) { 2803 dev_err(dev, "%s: Failed to get clk %s:%ld\n", __func__, 2804 dispc->feat->vpclk_name[i], PTR_ERR(clk)); 2805 return PTR_ERR(clk); 2806 } 2807 dispc->vp_clk[i] = clk; 2808 2809 gamma_table = devm_kmalloc_array(dev, gamma_size, 2810 sizeof(*gamma_table), 2811 GFP_KERNEL); 2812 if (!gamma_table) 2813 return -ENOMEM; 2814 dispc->vp_data[i].gamma_table = gamma_table; 2815 } 2816 2817 if (feat->subrev == DISPC_AM65X) { 2818 r = dispc_init_am65x_oldi_io_ctrl(dev, dispc); 2819 if (r) 2820 return r; 2821 } 2822 2823 dispc->fclk = devm_clk_get(dev, "fck"); 2824 if (IS_ERR(dispc->fclk)) { 2825 dev_err(dev, "%s: Failed to get fclk: %ld\n", 2826 __func__, PTR_ERR(dispc->fclk)); 2827 return PTR_ERR(dispc->fclk); 2828 } 2829 dev_dbg(dev, "DSS fclk %lu Hz\n", clk_get_rate(dispc->fclk)); 2830 2831 of_property_read_u32(dispc->dev->of_node, "max-memory-bandwidth", 2832 &dispc->memory_bandwidth_limit); 2833 2834 tidss->dispc = dispc; 2835 2836 return 0; 2837 } 2838