1 /* 2 * Copyright (C) 2012 Avionic Design GmbH 3 * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 */ 9 10 #include <linux/bitops.h> 11 #include <linux/host1x.h> 12 #include <linux/idr.h> 13 #include <linux/iommu.h> 14 15 #include <drm/drm_atomic.h> 16 #include <drm/drm_atomic_helper.h> 17 18 #include "drm.h" 19 #include "gem.h" 20 21 #define DRIVER_NAME "tegra" 22 #define DRIVER_DESC "NVIDIA Tegra graphics" 23 #define DRIVER_DATE "20120330" 24 #define DRIVER_MAJOR 0 25 #define DRIVER_MINOR 0 26 #define DRIVER_PATCHLEVEL 0 27 28 #define CARVEOUT_SZ SZ_64M 29 #define CDMA_GATHER_FETCHES_MAX_NB 16383 30 31 struct tegra_drm_file { 32 struct idr contexts; 33 struct mutex lock; 34 }; 35 36 static void tegra_atomic_schedule(struct tegra_drm *tegra, 37 struct drm_atomic_state *state) 38 { 39 tegra->commit.state = state; 40 schedule_work(&tegra->commit.work); 41 } 42 43 static void tegra_atomic_complete(struct tegra_drm *tegra, 44 struct drm_atomic_state *state) 45 { 46 struct drm_device *drm = tegra->drm; 47 48 /* 49 * Everything below can be run asynchronously without the need to grab 50 * any modeset locks at all under one condition: It must be guaranteed 51 * that the asynchronous work has either been cancelled (if the driver 52 * supports it, which at least requires that the framebuffers get 53 * cleaned up with drm_atomic_helper_cleanup_planes()) or completed 54 * before the new state gets committed on the software side with 55 * drm_atomic_helper_swap_state(). 56 * 57 * This scheme allows new atomic state updates to be prepared and 58 * checked in parallel to the asynchronous completion of the previous 59 * update. Which is important since compositors need to figure out the 60 * composition of the next frame right after having submitted the 61 * current layout. 62 */ 63 64 drm_atomic_helper_commit_modeset_disables(drm, state); 65 drm_atomic_helper_commit_modeset_enables(drm, state); 66 drm_atomic_helper_commit_planes(drm, state, 67 DRM_PLANE_COMMIT_ACTIVE_ONLY); 68 69 drm_atomic_helper_wait_for_vblanks(drm, state); 70 71 drm_atomic_helper_cleanup_planes(drm, state); 72 drm_atomic_state_put(state); 73 } 74 75 static void tegra_atomic_work(struct work_struct *work) 76 { 77 struct tegra_drm *tegra = container_of(work, struct tegra_drm, 78 commit.work); 79 80 tegra_atomic_complete(tegra, tegra->commit.state); 81 } 82 83 static int tegra_atomic_commit(struct drm_device *drm, 84 struct drm_atomic_state *state, bool nonblock) 85 { 86 struct tegra_drm *tegra = drm->dev_private; 87 int err; 88 89 err = drm_atomic_helper_prepare_planes(drm, state); 90 if (err) 91 return err; 92 93 /* serialize outstanding nonblocking commits */ 94 mutex_lock(&tegra->commit.lock); 95 flush_work(&tegra->commit.work); 96 97 /* 98 * This is the point of no return - everything below never fails except 99 * when the hw goes bonghits. Which means we can commit the new state on 100 * the software side now. 101 */ 102 103 err = drm_atomic_helper_swap_state(state, true); 104 if (err) { 105 mutex_unlock(&tegra->commit.lock); 106 drm_atomic_helper_cleanup_planes(drm, state); 107 return err; 108 } 109 110 drm_atomic_state_get(state); 111 if (nonblock) 112 tegra_atomic_schedule(tegra, state); 113 else 114 tegra_atomic_complete(tegra, state); 115 116 mutex_unlock(&tegra->commit.lock); 117 return 0; 118 } 119 120 static const struct drm_mode_config_funcs tegra_drm_mode_funcs = { 121 .fb_create = tegra_fb_create, 122 #ifdef CONFIG_DRM_FBDEV_EMULATION 123 .output_poll_changed = tegra_fb_output_poll_changed, 124 #endif 125 .atomic_check = drm_atomic_helper_check, 126 .atomic_commit = tegra_atomic_commit, 127 }; 128 129 static int tegra_drm_load(struct drm_device *drm, unsigned long flags) 130 { 131 struct host1x_device *device = to_host1x_device(drm->dev); 132 struct tegra_drm *tegra; 133 int err; 134 135 tegra = kzalloc(sizeof(*tegra), GFP_KERNEL); 136 if (!tegra) 137 return -ENOMEM; 138 139 if (iommu_present(&platform_bus_type)) { 140 u64 carveout_start, carveout_end, gem_start, gem_end; 141 struct iommu_domain_geometry *geometry; 142 unsigned long order; 143 144 tegra->domain = iommu_domain_alloc(&platform_bus_type); 145 if (!tegra->domain) { 146 err = -ENOMEM; 147 goto free; 148 } 149 150 geometry = &tegra->domain->geometry; 151 gem_start = geometry->aperture_start; 152 gem_end = geometry->aperture_end - CARVEOUT_SZ; 153 carveout_start = gem_end + 1; 154 carveout_end = geometry->aperture_end; 155 156 order = __ffs(tegra->domain->pgsize_bitmap); 157 init_iova_domain(&tegra->carveout.domain, 1UL << order, 158 carveout_start >> order); 159 160 tegra->carveout.shift = iova_shift(&tegra->carveout.domain); 161 tegra->carveout.limit = carveout_end >> tegra->carveout.shift; 162 163 drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1); 164 mutex_init(&tegra->mm_lock); 165 166 DRM_DEBUG("IOMMU apertures:\n"); 167 DRM_DEBUG(" GEM: %#llx-%#llx\n", gem_start, gem_end); 168 DRM_DEBUG(" Carveout: %#llx-%#llx\n", carveout_start, 169 carveout_end); 170 } 171 172 mutex_init(&tegra->clients_lock); 173 INIT_LIST_HEAD(&tegra->clients); 174 175 mutex_init(&tegra->commit.lock); 176 INIT_WORK(&tegra->commit.work, tegra_atomic_work); 177 178 drm->dev_private = tegra; 179 tegra->drm = drm; 180 181 drm_mode_config_init(drm); 182 183 drm->mode_config.min_width = 0; 184 drm->mode_config.min_height = 0; 185 186 drm->mode_config.max_width = 4096; 187 drm->mode_config.max_height = 4096; 188 189 drm->mode_config.allow_fb_modifiers = true; 190 191 drm->mode_config.funcs = &tegra_drm_mode_funcs; 192 193 err = tegra_drm_fb_prepare(drm); 194 if (err < 0) 195 goto config; 196 197 drm_kms_helper_poll_init(drm); 198 199 err = host1x_device_init(device); 200 if (err < 0) 201 goto fbdev; 202 203 /* 204 * We don't use the drm_irq_install() helpers provided by the DRM 205 * core, so we need to set this manually in order to allow the 206 * DRM_IOCTL_WAIT_VBLANK to operate correctly. 207 */ 208 drm->irq_enabled = true; 209 210 /* syncpoints are used for full 32-bit hardware VBLANK counters */ 211 drm->max_vblank_count = 0xffffffff; 212 213 err = drm_vblank_init(drm, drm->mode_config.num_crtc); 214 if (err < 0) 215 goto device; 216 217 drm_mode_config_reset(drm); 218 219 err = tegra_drm_fb_init(drm); 220 if (err < 0) 221 goto device; 222 223 return 0; 224 225 device: 226 host1x_device_exit(device); 227 fbdev: 228 drm_kms_helper_poll_fini(drm); 229 tegra_drm_fb_free(drm); 230 config: 231 drm_mode_config_cleanup(drm); 232 233 if (tegra->domain) { 234 iommu_domain_free(tegra->domain); 235 drm_mm_takedown(&tegra->mm); 236 mutex_destroy(&tegra->mm_lock); 237 put_iova_domain(&tegra->carveout.domain); 238 } 239 free: 240 kfree(tegra); 241 return err; 242 } 243 244 static void tegra_drm_unload(struct drm_device *drm) 245 { 246 struct host1x_device *device = to_host1x_device(drm->dev); 247 struct tegra_drm *tegra = drm->dev_private; 248 int err; 249 250 drm_kms_helper_poll_fini(drm); 251 tegra_drm_fb_exit(drm); 252 drm_mode_config_cleanup(drm); 253 254 err = host1x_device_exit(device); 255 if (err < 0) 256 return; 257 258 if (tegra->domain) { 259 iommu_domain_free(tegra->domain); 260 drm_mm_takedown(&tegra->mm); 261 mutex_destroy(&tegra->mm_lock); 262 put_iova_domain(&tegra->carveout.domain); 263 } 264 265 kfree(tegra); 266 } 267 268 static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp) 269 { 270 struct tegra_drm_file *fpriv; 271 272 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 273 if (!fpriv) 274 return -ENOMEM; 275 276 idr_init(&fpriv->contexts); 277 mutex_init(&fpriv->lock); 278 filp->driver_priv = fpriv; 279 280 return 0; 281 } 282 283 static void tegra_drm_context_free(struct tegra_drm_context *context) 284 { 285 context->client->ops->close_channel(context); 286 kfree(context); 287 } 288 289 static void tegra_drm_lastclose(struct drm_device *drm) 290 { 291 #ifdef CONFIG_DRM_FBDEV_EMULATION 292 struct tegra_drm *tegra = drm->dev_private; 293 294 tegra_fbdev_restore_mode(tegra->fbdev); 295 #endif 296 } 297 298 static struct host1x_bo * 299 host1x_bo_lookup(struct drm_file *file, u32 handle) 300 { 301 struct drm_gem_object *gem; 302 struct tegra_bo *bo; 303 304 gem = drm_gem_object_lookup(file, handle); 305 if (!gem) 306 return NULL; 307 308 bo = to_tegra_bo(gem); 309 return &bo->base; 310 } 311 312 static int host1x_reloc_copy_from_user(struct host1x_reloc *dest, 313 struct drm_tegra_reloc __user *src, 314 struct drm_device *drm, 315 struct drm_file *file) 316 { 317 u32 cmdbuf, target; 318 int err; 319 320 err = get_user(cmdbuf, &src->cmdbuf.handle); 321 if (err < 0) 322 return err; 323 324 err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset); 325 if (err < 0) 326 return err; 327 328 err = get_user(target, &src->target.handle); 329 if (err < 0) 330 return err; 331 332 err = get_user(dest->target.offset, &src->target.offset); 333 if (err < 0) 334 return err; 335 336 err = get_user(dest->shift, &src->shift); 337 if (err < 0) 338 return err; 339 340 dest->cmdbuf.bo = host1x_bo_lookup(file, cmdbuf); 341 if (!dest->cmdbuf.bo) 342 return -ENOENT; 343 344 dest->target.bo = host1x_bo_lookup(file, target); 345 if (!dest->target.bo) 346 return -ENOENT; 347 348 return 0; 349 } 350 351 static int host1x_waitchk_copy_from_user(struct host1x_waitchk *dest, 352 struct drm_tegra_waitchk __user *src, 353 struct drm_file *file) 354 { 355 u32 cmdbuf; 356 int err; 357 358 err = get_user(cmdbuf, &src->handle); 359 if (err < 0) 360 return err; 361 362 err = get_user(dest->offset, &src->offset); 363 if (err < 0) 364 return err; 365 366 err = get_user(dest->syncpt_id, &src->syncpt); 367 if (err < 0) 368 return err; 369 370 err = get_user(dest->thresh, &src->thresh); 371 if (err < 0) 372 return err; 373 374 dest->bo = host1x_bo_lookup(file, cmdbuf); 375 if (!dest->bo) 376 return -ENOENT; 377 378 return 0; 379 } 380 381 int tegra_drm_submit(struct tegra_drm_context *context, 382 struct drm_tegra_submit *args, struct drm_device *drm, 383 struct drm_file *file) 384 { 385 unsigned int num_cmdbufs = args->num_cmdbufs; 386 unsigned int num_relocs = args->num_relocs; 387 unsigned int num_waitchks = args->num_waitchks; 388 struct drm_tegra_cmdbuf __user *cmdbufs = 389 (void __user *)(uintptr_t)args->cmdbufs; 390 struct drm_tegra_reloc __user *relocs = 391 (void __user *)(uintptr_t)args->relocs; 392 struct drm_tegra_waitchk __user *waitchks = 393 (void __user *)(uintptr_t)args->waitchks; 394 struct drm_tegra_syncpt syncpt; 395 struct host1x *host1x = dev_get_drvdata(drm->dev->parent); 396 struct drm_gem_object **refs; 397 struct host1x_syncpt *sp; 398 struct host1x_job *job; 399 unsigned int num_refs; 400 int err; 401 402 /* We don't yet support other than one syncpt_incr struct per submit */ 403 if (args->num_syncpts != 1) 404 return -EINVAL; 405 406 /* We don't yet support waitchks */ 407 if (args->num_waitchks != 0) 408 return -EINVAL; 409 410 job = host1x_job_alloc(context->channel, args->num_cmdbufs, 411 args->num_relocs, args->num_waitchks); 412 if (!job) 413 return -ENOMEM; 414 415 job->num_relocs = args->num_relocs; 416 job->num_waitchk = args->num_waitchks; 417 job->client = (u32)args->context; 418 job->class = context->client->base.class; 419 job->serialize = true; 420 421 /* 422 * Track referenced BOs so that they can be unreferenced after the 423 * submission is complete. 424 */ 425 num_refs = num_cmdbufs + num_relocs * 2 + num_waitchks; 426 427 refs = kmalloc_array(num_refs, sizeof(*refs), GFP_KERNEL); 428 if (!refs) { 429 err = -ENOMEM; 430 goto put; 431 } 432 433 /* reuse as an iterator later */ 434 num_refs = 0; 435 436 while (num_cmdbufs) { 437 struct drm_tegra_cmdbuf cmdbuf; 438 struct host1x_bo *bo; 439 struct tegra_bo *obj; 440 u64 offset; 441 442 if (copy_from_user(&cmdbuf, cmdbufs, sizeof(cmdbuf))) { 443 err = -EFAULT; 444 goto fail; 445 } 446 447 /* 448 * The maximum number of CDMA gather fetches is 16383, a higher 449 * value means the words count is malformed. 450 */ 451 if (cmdbuf.words > CDMA_GATHER_FETCHES_MAX_NB) { 452 err = -EINVAL; 453 goto fail; 454 } 455 456 bo = host1x_bo_lookup(file, cmdbuf.handle); 457 if (!bo) { 458 err = -ENOENT; 459 goto fail; 460 } 461 462 offset = (u64)cmdbuf.offset + (u64)cmdbuf.words * sizeof(u32); 463 obj = host1x_to_tegra_bo(bo); 464 refs[num_refs++] = &obj->gem; 465 466 /* 467 * Gather buffer base address must be 4-bytes aligned, 468 * unaligned offset is malformed and cause commands stream 469 * corruption on the buffer address relocation. 470 */ 471 if (offset & 3 || offset >= obj->gem.size) { 472 err = -EINVAL; 473 goto fail; 474 } 475 476 host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset); 477 num_cmdbufs--; 478 cmdbufs++; 479 } 480 481 /* copy and resolve relocations from submit */ 482 while (num_relocs--) { 483 struct host1x_reloc *reloc; 484 struct tegra_bo *obj; 485 486 err = host1x_reloc_copy_from_user(&job->relocarray[num_relocs], 487 &relocs[num_relocs], drm, 488 file); 489 if (err < 0) 490 goto fail; 491 492 reloc = &job->relocarray[num_relocs]; 493 obj = host1x_to_tegra_bo(reloc->cmdbuf.bo); 494 refs[num_refs++] = &obj->gem; 495 496 /* 497 * The unaligned cmdbuf offset will cause an unaligned write 498 * during of the relocations patching, corrupting the commands 499 * stream. 500 */ 501 if (reloc->cmdbuf.offset & 3 || 502 reloc->cmdbuf.offset >= obj->gem.size) { 503 err = -EINVAL; 504 goto fail; 505 } 506 507 obj = host1x_to_tegra_bo(reloc->target.bo); 508 refs[num_refs++] = &obj->gem; 509 510 if (reloc->target.offset >= obj->gem.size) { 511 err = -EINVAL; 512 goto fail; 513 } 514 } 515 516 /* copy and resolve waitchks from submit */ 517 while (num_waitchks--) { 518 struct host1x_waitchk *wait = &job->waitchk[num_waitchks]; 519 struct tegra_bo *obj; 520 521 err = host1x_waitchk_copy_from_user(wait, 522 &waitchks[num_waitchks], 523 file); 524 if (err < 0) 525 goto fail; 526 527 obj = host1x_to_tegra_bo(wait->bo); 528 refs[num_refs++] = &obj->gem; 529 530 /* 531 * The unaligned offset will cause an unaligned write during 532 * of the waitchks patching, corrupting the commands stream. 533 */ 534 if (wait->offset & 3 || 535 wait->offset >= obj->gem.size) { 536 err = -EINVAL; 537 goto fail; 538 } 539 } 540 541 if (copy_from_user(&syncpt, (void __user *)(uintptr_t)args->syncpts, 542 sizeof(syncpt))) { 543 err = -EFAULT; 544 goto fail; 545 } 546 547 /* check whether syncpoint ID is valid */ 548 sp = host1x_syncpt_get(host1x, syncpt.id); 549 if (!sp) { 550 err = -ENOENT; 551 goto fail; 552 } 553 554 job->is_addr_reg = context->client->ops->is_addr_reg; 555 job->is_valid_class = context->client->ops->is_valid_class; 556 job->syncpt_incrs = syncpt.incrs; 557 job->syncpt_id = syncpt.id; 558 job->timeout = 10000; 559 560 if (args->timeout && args->timeout < 10000) 561 job->timeout = args->timeout; 562 563 err = host1x_job_pin(job, context->client->base.dev); 564 if (err) 565 goto fail; 566 567 err = host1x_job_submit(job); 568 if (err) { 569 host1x_job_unpin(job); 570 goto fail; 571 } 572 573 args->fence = job->syncpt_end; 574 575 fail: 576 while (num_refs--) 577 drm_gem_object_put_unlocked(refs[num_refs]); 578 579 kfree(refs); 580 581 put: 582 host1x_job_put(job); 583 return err; 584 } 585 586 587 #ifdef CONFIG_DRM_TEGRA_STAGING 588 static int tegra_gem_create(struct drm_device *drm, void *data, 589 struct drm_file *file) 590 { 591 struct drm_tegra_gem_create *args = data; 592 struct tegra_bo *bo; 593 594 bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags, 595 &args->handle); 596 if (IS_ERR(bo)) 597 return PTR_ERR(bo); 598 599 return 0; 600 } 601 602 static int tegra_gem_mmap(struct drm_device *drm, void *data, 603 struct drm_file *file) 604 { 605 struct drm_tegra_gem_mmap *args = data; 606 struct drm_gem_object *gem; 607 struct tegra_bo *bo; 608 609 gem = drm_gem_object_lookup(file, args->handle); 610 if (!gem) 611 return -EINVAL; 612 613 bo = to_tegra_bo(gem); 614 615 args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node); 616 617 drm_gem_object_put_unlocked(gem); 618 619 return 0; 620 } 621 622 static int tegra_syncpt_read(struct drm_device *drm, void *data, 623 struct drm_file *file) 624 { 625 struct host1x *host = dev_get_drvdata(drm->dev->parent); 626 struct drm_tegra_syncpt_read *args = data; 627 struct host1x_syncpt *sp; 628 629 sp = host1x_syncpt_get(host, args->id); 630 if (!sp) 631 return -EINVAL; 632 633 args->value = host1x_syncpt_read_min(sp); 634 return 0; 635 } 636 637 static int tegra_syncpt_incr(struct drm_device *drm, void *data, 638 struct drm_file *file) 639 { 640 struct host1x *host1x = dev_get_drvdata(drm->dev->parent); 641 struct drm_tegra_syncpt_incr *args = data; 642 struct host1x_syncpt *sp; 643 644 sp = host1x_syncpt_get(host1x, args->id); 645 if (!sp) 646 return -EINVAL; 647 648 return host1x_syncpt_incr(sp); 649 } 650 651 static int tegra_syncpt_wait(struct drm_device *drm, void *data, 652 struct drm_file *file) 653 { 654 struct host1x *host1x = dev_get_drvdata(drm->dev->parent); 655 struct drm_tegra_syncpt_wait *args = data; 656 struct host1x_syncpt *sp; 657 658 sp = host1x_syncpt_get(host1x, args->id); 659 if (!sp) 660 return -EINVAL; 661 662 return host1x_syncpt_wait(sp, args->thresh, args->timeout, 663 &args->value); 664 } 665 666 static int tegra_client_open(struct tegra_drm_file *fpriv, 667 struct tegra_drm_client *client, 668 struct tegra_drm_context *context) 669 { 670 int err; 671 672 err = client->ops->open_channel(client, context); 673 if (err < 0) 674 return err; 675 676 err = idr_alloc(&fpriv->contexts, context, 1, 0, GFP_KERNEL); 677 if (err < 0) { 678 client->ops->close_channel(context); 679 return err; 680 } 681 682 context->client = client; 683 context->id = err; 684 685 return 0; 686 } 687 688 static int tegra_open_channel(struct drm_device *drm, void *data, 689 struct drm_file *file) 690 { 691 struct tegra_drm_file *fpriv = file->driver_priv; 692 struct tegra_drm *tegra = drm->dev_private; 693 struct drm_tegra_open_channel *args = data; 694 struct tegra_drm_context *context; 695 struct tegra_drm_client *client; 696 int err = -ENODEV; 697 698 context = kzalloc(sizeof(*context), GFP_KERNEL); 699 if (!context) 700 return -ENOMEM; 701 702 mutex_lock(&fpriv->lock); 703 704 list_for_each_entry(client, &tegra->clients, list) 705 if (client->base.class == args->client) { 706 err = tegra_client_open(fpriv, client, context); 707 if (err < 0) 708 break; 709 710 args->context = context->id; 711 break; 712 } 713 714 if (err < 0) 715 kfree(context); 716 717 mutex_unlock(&fpriv->lock); 718 return err; 719 } 720 721 static int tegra_close_channel(struct drm_device *drm, void *data, 722 struct drm_file *file) 723 { 724 struct tegra_drm_file *fpriv = file->driver_priv; 725 struct drm_tegra_close_channel *args = data; 726 struct tegra_drm_context *context; 727 int err = 0; 728 729 mutex_lock(&fpriv->lock); 730 731 context = idr_find(&fpriv->contexts, args->context); 732 if (!context) { 733 err = -EINVAL; 734 goto unlock; 735 } 736 737 idr_remove(&fpriv->contexts, context->id); 738 tegra_drm_context_free(context); 739 740 unlock: 741 mutex_unlock(&fpriv->lock); 742 return err; 743 } 744 745 static int tegra_get_syncpt(struct drm_device *drm, void *data, 746 struct drm_file *file) 747 { 748 struct tegra_drm_file *fpriv = file->driver_priv; 749 struct drm_tegra_get_syncpt *args = data; 750 struct tegra_drm_context *context; 751 struct host1x_syncpt *syncpt; 752 int err = 0; 753 754 mutex_lock(&fpriv->lock); 755 756 context = idr_find(&fpriv->contexts, args->context); 757 if (!context) { 758 err = -ENODEV; 759 goto unlock; 760 } 761 762 if (args->index >= context->client->base.num_syncpts) { 763 err = -EINVAL; 764 goto unlock; 765 } 766 767 syncpt = context->client->base.syncpts[args->index]; 768 args->id = host1x_syncpt_id(syncpt); 769 770 unlock: 771 mutex_unlock(&fpriv->lock); 772 return err; 773 } 774 775 static int tegra_submit(struct drm_device *drm, void *data, 776 struct drm_file *file) 777 { 778 struct tegra_drm_file *fpriv = file->driver_priv; 779 struct drm_tegra_submit *args = data; 780 struct tegra_drm_context *context; 781 int err; 782 783 mutex_lock(&fpriv->lock); 784 785 context = idr_find(&fpriv->contexts, args->context); 786 if (!context) { 787 err = -ENODEV; 788 goto unlock; 789 } 790 791 err = context->client->ops->submit(context, args, drm, file); 792 793 unlock: 794 mutex_unlock(&fpriv->lock); 795 return err; 796 } 797 798 static int tegra_get_syncpt_base(struct drm_device *drm, void *data, 799 struct drm_file *file) 800 { 801 struct tegra_drm_file *fpriv = file->driver_priv; 802 struct drm_tegra_get_syncpt_base *args = data; 803 struct tegra_drm_context *context; 804 struct host1x_syncpt_base *base; 805 struct host1x_syncpt *syncpt; 806 int err = 0; 807 808 mutex_lock(&fpriv->lock); 809 810 context = idr_find(&fpriv->contexts, args->context); 811 if (!context) { 812 err = -ENODEV; 813 goto unlock; 814 } 815 816 if (args->syncpt >= context->client->base.num_syncpts) { 817 err = -EINVAL; 818 goto unlock; 819 } 820 821 syncpt = context->client->base.syncpts[args->syncpt]; 822 823 base = host1x_syncpt_get_base(syncpt); 824 if (!base) { 825 err = -ENXIO; 826 goto unlock; 827 } 828 829 args->id = host1x_syncpt_base_id(base); 830 831 unlock: 832 mutex_unlock(&fpriv->lock); 833 return err; 834 } 835 836 static int tegra_gem_set_tiling(struct drm_device *drm, void *data, 837 struct drm_file *file) 838 { 839 struct drm_tegra_gem_set_tiling *args = data; 840 enum tegra_bo_tiling_mode mode; 841 struct drm_gem_object *gem; 842 unsigned long value = 0; 843 struct tegra_bo *bo; 844 845 switch (args->mode) { 846 case DRM_TEGRA_GEM_TILING_MODE_PITCH: 847 mode = TEGRA_BO_TILING_MODE_PITCH; 848 849 if (args->value != 0) 850 return -EINVAL; 851 852 break; 853 854 case DRM_TEGRA_GEM_TILING_MODE_TILED: 855 mode = TEGRA_BO_TILING_MODE_TILED; 856 857 if (args->value != 0) 858 return -EINVAL; 859 860 break; 861 862 case DRM_TEGRA_GEM_TILING_MODE_BLOCK: 863 mode = TEGRA_BO_TILING_MODE_BLOCK; 864 865 if (args->value > 5) 866 return -EINVAL; 867 868 value = args->value; 869 break; 870 871 default: 872 return -EINVAL; 873 } 874 875 gem = drm_gem_object_lookup(file, args->handle); 876 if (!gem) 877 return -ENOENT; 878 879 bo = to_tegra_bo(gem); 880 881 bo->tiling.mode = mode; 882 bo->tiling.value = value; 883 884 drm_gem_object_put_unlocked(gem); 885 886 return 0; 887 } 888 889 static int tegra_gem_get_tiling(struct drm_device *drm, void *data, 890 struct drm_file *file) 891 { 892 struct drm_tegra_gem_get_tiling *args = data; 893 struct drm_gem_object *gem; 894 struct tegra_bo *bo; 895 int err = 0; 896 897 gem = drm_gem_object_lookup(file, args->handle); 898 if (!gem) 899 return -ENOENT; 900 901 bo = to_tegra_bo(gem); 902 903 switch (bo->tiling.mode) { 904 case TEGRA_BO_TILING_MODE_PITCH: 905 args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH; 906 args->value = 0; 907 break; 908 909 case TEGRA_BO_TILING_MODE_TILED: 910 args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED; 911 args->value = 0; 912 break; 913 914 case TEGRA_BO_TILING_MODE_BLOCK: 915 args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK; 916 args->value = bo->tiling.value; 917 break; 918 919 default: 920 err = -EINVAL; 921 break; 922 } 923 924 drm_gem_object_put_unlocked(gem); 925 926 return err; 927 } 928 929 static int tegra_gem_set_flags(struct drm_device *drm, void *data, 930 struct drm_file *file) 931 { 932 struct drm_tegra_gem_set_flags *args = data; 933 struct drm_gem_object *gem; 934 struct tegra_bo *bo; 935 936 if (args->flags & ~DRM_TEGRA_GEM_FLAGS) 937 return -EINVAL; 938 939 gem = drm_gem_object_lookup(file, args->handle); 940 if (!gem) 941 return -ENOENT; 942 943 bo = to_tegra_bo(gem); 944 bo->flags = 0; 945 946 if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP) 947 bo->flags |= TEGRA_BO_BOTTOM_UP; 948 949 drm_gem_object_put_unlocked(gem); 950 951 return 0; 952 } 953 954 static int tegra_gem_get_flags(struct drm_device *drm, void *data, 955 struct drm_file *file) 956 { 957 struct drm_tegra_gem_get_flags *args = data; 958 struct drm_gem_object *gem; 959 struct tegra_bo *bo; 960 961 gem = drm_gem_object_lookup(file, args->handle); 962 if (!gem) 963 return -ENOENT; 964 965 bo = to_tegra_bo(gem); 966 args->flags = 0; 967 968 if (bo->flags & TEGRA_BO_BOTTOM_UP) 969 args->flags |= DRM_TEGRA_GEM_BOTTOM_UP; 970 971 drm_gem_object_put_unlocked(gem); 972 973 return 0; 974 } 975 #endif 976 977 static const struct drm_ioctl_desc tegra_drm_ioctls[] = { 978 #ifdef CONFIG_DRM_TEGRA_STAGING 979 DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create, 980 DRM_UNLOCKED | DRM_RENDER_ALLOW), 981 DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap, 982 DRM_UNLOCKED | DRM_RENDER_ALLOW), 983 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read, 984 DRM_UNLOCKED | DRM_RENDER_ALLOW), 985 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr, 986 DRM_UNLOCKED | DRM_RENDER_ALLOW), 987 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait, 988 DRM_UNLOCKED | DRM_RENDER_ALLOW), 989 DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel, 990 DRM_UNLOCKED | DRM_RENDER_ALLOW), 991 DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel, 992 DRM_UNLOCKED | DRM_RENDER_ALLOW), 993 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt, 994 DRM_UNLOCKED | DRM_RENDER_ALLOW), 995 DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit, 996 DRM_UNLOCKED | DRM_RENDER_ALLOW), 997 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base, 998 DRM_UNLOCKED | DRM_RENDER_ALLOW), 999 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling, 1000 DRM_UNLOCKED | DRM_RENDER_ALLOW), 1001 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling, 1002 DRM_UNLOCKED | DRM_RENDER_ALLOW), 1003 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags, 1004 DRM_UNLOCKED | DRM_RENDER_ALLOW), 1005 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags, 1006 DRM_UNLOCKED | DRM_RENDER_ALLOW), 1007 #endif 1008 }; 1009 1010 static const struct file_operations tegra_drm_fops = { 1011 .owner = THIS_MODULE, 1012 .open = drm_open, 1013 .release = drm_release, 1014 .unlocked_ioctl = drm_ioctl, 1015 .mmap = tegra_drm_mmap, 1016 .poll = drm_poll, 1017 .read = drm_read, 1018 .compat_ioctl = drm_compat_ioctl, 1019 .llseek = noop_llseek, 1020 }; 1021 1022 static int tegra_drm_context_cleanup(int id, void *p, void *data) 1023 { 1024 struct tegra_drm_context *context = p; 1025 1026 tegra_drm_context_free(context); 1027 1028 return 0; 1029 } 1030 1031 static void tegra_drm_postclose(struct drm_device *drm, struct drm_file *file) 1032 { 1033 struct tegra_drm_file *fpriv = file->driver_priv; 1034 1035 mutex_lock(&fpriv->lock); 1036 idr_for_each(&fpriv->contexts, tegra_drm_context_cleanup, NULL); 1037 mutex_unlock(&fpriv->lock); 1038 1039 idr_destroy(&fpriv->contexts); 1040 mutex_destroy(&fpriv->lock); 1041 kfree(fpriv); 1042 } 1043 1044 #ifdef CONFIG_DEBUG_FS 1045 static int tegra_debugfs_framebuffers(struct seq_file *s, void *data) 1046 { 1047 struct drm_info_node *node = (struct drm_info_node *)s->private; 1048 struct drm_device *drm = node->minor->dev; 1049 struct drm_framebuffer *fb; 1050 1051 mutex_lock(&drm->mode_config.fb_lock); 1052 1053 list_for_each_entry(fb, &drm->mode_config.fb_list, head) { 1054 seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n", 1055 fb->base.id, fb->width, fb->height, 1056 fb->format->depth, 1057 fb->format->cpp[0] * 8, 1058 drm_framebuffer_read_refcount(fb)); 1059 } 1060 1061 mutex_unlock(&drm->mode_config.fb_lock); 1062 1063 return 0; 1064 } 1065 1066 static int tegra_debugfs_iova(struct seq_file *s, void *data) 1067 { 1068 struct drm_info_node *node = (struct drm_info_node *)s->private; 1069 struct drm_device *drm = node->minor->dev; 1070 struct tegra_drm *tegra = drm->dev_private; 1071 struct drm_printer p = drm_seq_file_printer(s); 1072 1073 if (tegra->domain) { 1074 mutex_lock(&tegra->mm_lock); 1075 drm_mm_print(&tegra->mm, &p); 1076 mutex_unlock(&tegra->mm_lock); 1077 } 1078 1079 return 0; 1080 } 1081 1082 static struct drm_info_list tegra_debugfs_list[] = { 1083 { "framebuffers", tegra_debugfs_framebuffers, 0 }, 1084 { "iova", tegra_debugfs_iova, 0 }, 1085 }; 1086 1087 static int tegra_debugfs_init(struct drm_minor *minor) 1088 { 1089 return drm_debugfs_create_files(tegra_debugfs_list, 1090 ARRAY_SIZE(tegra_debugfs_list), 1091 minor->debugfs_root, minor); 1092 } 1093 #endif 1094 1095 static struct drm_driver tegra_drm_driver = { 1096 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME | 1097 DRIVER_ATOMIC | DRIVER_RENDER, 1098 .load = tegra_drm_load, 1099 .unload = tegra_drm_unload, 1100 .open = tegra_drm_open, 1101 .postclose = tegra_drm_postclose, 1102 .lastclose = tegra_drm_lastclose, 1103 1104 #if defined(CONFIG_DEBUG_FS) 1105 .debugfs_init = tegra_debugfs_init, 1106 #endif 1107 1108 .gem_free_object_unlocked = tegra_bo_free_object, 1109 .gem_vm_ops = &tegra_bo_vm_ops, 1110 1111 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 1112 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 1113 .gem_prime_export = tegra_gem_prime_export, 1114 .gem_prime_import = tegra_gem_prime_import, 1115 1116 .dumb_create = tegra_bo_dumb_create, 1117 1118 .ioctls = tegra_drm_ioctls, 1119 .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls), 1120 .fops = &tegra_drm_fops, 1121 1122 .name = DRIVER_NAME, 1123 .desc = DRIVER_DESC, 1124 .date = DRIVER_DATE, 1125 .major = DRIVER_MAJOR, 1126 .minor = DRIVER_MINOR, 1127 .patchlevel = DRIVER_PATCHLEVEL, 1128 }; 1129 1130 int tegra_drm_register_client(struct tegra_drm *tegra, 1131 struct tegra_drm_client *client) 1132 { 1133 mutex_lock(&tegra->clients_lock); 1134 list_add_tail(&client->list, &tegra->clients); 1135 mutex_unlock(&tegra->clients_lock); 1136 1137 return 0; 1138 } 1139 1140 int tegra_drm_unregister_client(struct tegra_drm *tegra, 1141 struct tegra_drm_client *client) 1142 { 1143 mutex_lock(&tegra->clients_lock); 1144 list_del_init(&client->list); 1145 mutex_unlock(&tegra->clients_lock); 1146 1147 return 0; 1148 } 1149 1150 void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size, 1151 dma_addr_t *dma) 1152 { 1153 struct iova *alloc; 1154 void *virt; 1155 gfp_t gfp; 1156 int err; 1157 1158 if (tegra->domain) 1159 size = iova_align(&tegra->carveout.domain, size); 1160 else 1161 size = PAGE_ALIGN(size); 1162 1163 gfp = GFP_KERNEL | __GFP_ZERO; 1164 if (!tegra->domain) { 1165 /* 1166 * Many units only support 32-bit addresses, even on 64-bit 1167 * SoCs. If there is no IOMMU to translate into a 32-bit IO 1168 * virtual address space, force allocations to be in the 1169 * lower 32-bit range. 1170 */ 1171 gfp |= GFP_DMA; 1172 } 1173 1174 virt = (void *)__get_free_pages(gfp, get_order(size)); 1175 if (!virt) 1176 return ERR_PTR(-ENOMEM); 1177 1178 if (!tegra->domain) { 1179 /* 1180 * If IOMMU is disabled, devices address physical memory 1181 * directly. 1182 */ 1183 *dma = virt_to_phys(virt); 1184 return virt; 1185 } 1186 1187 alloc = alloc_iova(&tegra->carveout.domain, 1188 size >> tegra->carveout.shift, 1189 tegra->carveout.limit, true); 1190 if (!alloc) { 1191 err = -EBUSY; 1192 goto free_pages; 1193 } 1194 1195 *dma = iova_dma_addr(&tegra->carveout.domain, alloc); 1196 err = iommu_map(tegra->domain, *dma, virt_to_phys(virt), 1197 size, IOMMU_READ | IOMMU_WRITE); 1198 if (err < 0) 1199 goto free_iova; 1200 1201 return virt; 1202 1203 free_iova: 1204 __free_iova(&tegra->carveout.domain, alloc); 1205 free_pages: 1206 free_pages((unsigned long)virt, get_order(size)); 1207 1208 return ERR_PTR(err); 1209 } 1210 1211 void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt, 1212 dma_addr_t dma) 1213 { 1214 if (tegra->domain) 1215 size = iova_align(&tegra->carveout.domain, size); 1216 else 1217 size = PAGE_ALIGN(size); 1218 1219 if (tegra->domain) { 1220 iommu_unmap(tegra->domain, dma, size); 1221 free_iova(&tegra->carveout.domain, 1222 iova_pfn(&tegra->carveout.domain, dma)); 1223 } 1224 1225 free_pages((unsigned long)virt, get_order(size)); 1226 } 1227 1228 static int host1x_drm_probe(struct host1x_device *dev) 1229 { 1230 struct drm_driver *driver = &tegra_drm_driver; 1231 struct drm_device *drm; 1232 int err; 1233 1234 drm = drm_dev_alloc(driver, &dev->dev); 1235 if (IS_ERR(drm)) 1236 return PTR_ERR(drm); 1237 1238 dev_set_drvdata(&dev->dev, drm); 1239 1240 err = drm_dev_register(drm, 0); 1241 if (err < 0) 1242 goto unref; 1243 1244 return 0; 1245 1246 unref: 1247 drm_dev_unref(drm); 1248 return err; 1249 } 1250 1251 static int host1x_drm_remove(struct host1x_device *dev) 1252 { 1253 struct drm_device *drm = dev_get_drvdata(&dev->dev); 1254 1255 drm_dev_unregister(drm); 1256 drm_dev_unref(drm); 1257 1258 return 0; 1259 } 1260 1261 #ifdef CONFIG_PM_SLEEP 1262 static int host1x_drm_suspend(struct device *dev) 1263 { 1264 struct drm_device *drm = dev_get_drvdata(dev); 1265 struct tegra_drm *tegra = drm->dev_private; 1266 1267 drm_kms_helper_poll_disable(drm); 1268 tegra_drm_fb_suspend(drm); 1269 1270 tegra->state = drm_atomic_helper_suspend(drm); 1271 if (IS_ERR(tegra->state)) { 1272 tegra_drm_fb_resume(drm); 1273 drm_kms_helper_poll_enable(drm); 1274 return PTR_ERR(tegra->state); 1275 } 1276 1277 return 0; 1278 } 1279 1280 static int host1x_drm_resume(struct device *dev) 1281 { 1282 struct drm_device *drm = dev_get_drvdata(dev); 1283 struct tegra_drm *tegra = drm->dev_private; 1284 1285 drm_atomic_helper_resume(drm, tegra->state); 1286 tegra_drm_fb_resume(drm); 1287 drm_kms_helper_poll_enable(drm); 1288 1289 return 0; 1290 } 1291 #endif 1292 1293 static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend, 1294 host1x_drm_resume); 1295 1296 static const struct of_device_id host1x_drm_subdevs[] = { 1297 { .compatible = "nvidia,tegra20-dc", }, 1298 { .compatible = "nvidia,tegra20-hdmi", }, 1299 { .compatible = "nvidia,tegra20-gr2d", }, 1300 { .compatible = "nvidia,tegra20-gr3d", }, 1301 { .compatible = "nvidia,tegra30-dc", }, 1302 { .compatible = "nvidia,tegra30-hdmi", }, 1303 { .compatible = "nvidia,tegra30-gr2d", }, 1304 { .compatible = "nvidia,tegra30-gr3d", }, 1305 { .compatible = "nvidia,tegra114-dsi", }, 1306 { .compatible = "nvidia,tegra114-hdmi", }, 1307 { .compatible = "nvidia,tegra114-gr3d", }, 1308 { .compatible = "nvidia,tegra124-dc", }, 1309 { .compatible = "nvidia,tegra124-sor", }, 1310 { .compatible = "nvidia,tegra124-hdmi", }, 1311 { .compatible = "nvidia,tegra124-dsi", }, 1312 { .compatible = "nvidia,tegra124-vic", }, 1313 { .compatible = "nvidia,tegra132-dsi", }, 1314 { .compatible = "nvidia,tegra210-dc", }, 1315 { .compatible = "nvidia,tegra210-dsi", }, 1316 { .compatible = "nvidia,tegra210-sor", }, 1317 { .compatible = "nvidia,tegra210-sor1", }, 1318 { .compatible = "nvidia,tegra210-vic", }, 1319 { /* sentinel */ } 1320 }; 1321 1322 static struct host1x_driver host1x_drm_driver = { 1323 .driver = { 1324 .name = "drm", 1325 .pm = &host1x_drm_pm_ops, 1326 }, 1327 .probe = host1x_drm_probe, 1328 .remove = host1x_drm_remove, 1329 .subdevs = host1x_drm_subdevs, 1330 }; 1331 1332 static struct platform_driver * const drivers[] = { 1333 &tegra_dc_driver, 1334 &tegra_hdmi_driver, 1335 &tegra_dsi_driver, 1336 &tegra_dpaux_driver, 1337 &tegra_sor_driver, 1338 &tegra_gr2d_driver, 1339 &tegra_gr3d_driver, 1340 &tegra_vic_driver, 1341 }; 1342 1343 static int __init host1x_drm_init(void) 1344 { 1345 int err; 1346 1347 err = host1x_driver_register(&host1x_drm_driver); 1348 if (err < 0) 1349 return err; 1350 1351 err = platform_register_drivers(drivers, ARRAY_SIZE(drivers)); 1352 if (err < 0) 1353 goto unregister_host1x; 1354 1355 return 0; 1356 1357 unregister_host1x: 1358 host1x_driver_unregister(&host1x_drm_driver); 1359 return err; 1360 } 1361 module_init(host1x_drm_init); 1362 1363 static void __exit host1x_drm_exit(void) 1364 { 1365 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers)); 1366 host1x_driver_unregister(&host1x_drm_driver); 1367 } 1368 module_exit(host1x_drm_exit); 1369 1370 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>"); 1371 MODULE_DESCRIPTION("NVIDIA Tegra DRM driver"); 1372 MODULE_LICENSE("GPL v2"); 1373