1 /* 2 * Copyright 2007-11 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include "drmP.h" 27 #include "drm_crtc_helper.h" 28 #include "radeon_drm.h" 29 #include "radeon.h" 30 #include "atom.h" 31 32 extern int atom_debug; 33 34 /* evil but including atombios.h is much worse */ 35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, 36 struct drm_display_mode *mode); 37 38 39 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder) 40 { 41 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 42 switch (radeon_encoder->encoder_id) { 43 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 44 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 45 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 46 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 47 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 48 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 49 case ENCODER_OBJECT_ID_INTERNAL_DDI: 50 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 51 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 52 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 53 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 54 return true; 55 default: 56 return false; 57 } 58 } 59 60 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, 61 struct drm_display_mode *mode, 62 struct drm_display_mode *adjusted_mode) 63 { 64 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 65 struct drm_device *dev = encoder->dev; 66 struct radeon_device *rdev = dev->dev_private; 67 68 /* set the active encoder to connector routing */ 69 radeon_encoder_set_active_device(encoder); 70 drm_mode_set_crtcinfo(adjusted_mode, 0); 71 72 /* hw bug */ 73 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) 74 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) 75 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; 76 77 /* get the native mode for LVDS */ 78 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) 79 radeon_panel_mode_fixup(encoder, adjusted_mode); 80 81 /* get the native mode for TV */ 82 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { 83 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; 84 if (tv_dac) { 85 if (tv_dac->tv_std == TV_STD_NTSC || 86 tv_dac->tv_std == TV_STD_NTSC_J || 87 tv_dac->tv_std == TV_STD_PAL_M) 88 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode); 89 else 90 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode); 91 } 92 } 93 94 if (ASIC_IS_DCE3(rdev) && 95 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 96 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) { 97 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 98 radeon_dp_set_link_config(connector, mode); 99 } 100 101 return true; 102 } 103 104 static void 105 atombios_dac_setup(struct drm_encoder *encoder, int action) 106 { 107 struct drm_device *dev = encoder->dev; 108 struct radeon_device *rdev = dev->dev_private; 109 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 110 DAC_ENCODER_CONTROL_PS_ALLOCATION args; 111 int index = 0; 112 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 113 114 memset(&args, 0, sizeof(args)); 115 116 switch (radeon_encoder->encoder_id) { 117 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 118 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 119 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); 120 break; 121 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 122 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 123 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); 124 break; 125 } 126 127 args.ucAction = action; 128 129 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT)) 130 args.ucDacStandard = ATOM_DAC1_PS2; 131 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 132 args.ucDacStandard = ATOM_DAC1_CV; 133 else { 134 switch (dac_info->tv_std) { 135 case TV_STD_PAL: 136 case TV_STD_PAL_M: 137 case TV_STD_SCART_PAL: 138 case TV_STD_SECAM: 139 case TV_STD_PAL_CN: 140 args.ucDacStandard = ATOM_DAC1_PAL; 141 break; 142 case TV_STD_NTSC: 143 case TV_STD_NTSC_J: 144 case TV_STD_PAL_60: 145 default: 146 args.ucDacStandard = ATOM_DAC1_NTSC; 147 break; 148 } 149 } 150 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 151 152 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 153 154 } 155 156 static void 157 atombios_tv_setup(struct drm_encoder *encoder, int action) 158 { 159 struct drm_device *dev = encoder->dev; 160 struct radeon_device *rdev = dev->dev_private; 161 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 162 TV_ENCODER_CONTROL_PS_ALLOCATION args; 163 int index = 0; 164 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 165 166 memset(&args, 0, sizeof(args)); 167 168 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); 169 170 args.sTVEncoder.ucAction = action; 171 172 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 173 args.sTVEncoder.ucTvStandard = ATOM_TV_CV; 174 else { 175 switch (dac_info->tv_std) { 176 case TV_STD_NTSC: 177 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 178 break; 179 case TV_STD_PAL: 180 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; 181 break; 182 case TV_STD_PAL_M: 183 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM; 184 break; 185 case TV_STD_PAL_60: 186 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60; 187 break; 188 case TV_STD_NTSC_J: 189 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ; 190 break; 191 case TV_STD_SCART_PAL: 192 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */ 193 break; 194 case TV_STD_SECAM: 195 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM; 196 break; 197 case TV_STD_PAL_CN: 198 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN; 199 break; 200 default: 201 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 202 break; 203 } 204 } 205 206 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 207 208 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 209 210 } 211 212 union dvo_encoder_control { 213 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds; 214 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo; 215 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3; 216 }; 217 218 void 219 atombios_dvo_setup(struct drm_encoder *encoder, int action) 220 { 221 struct drm_device *dev = encoder->dev; 222 struct radeon_device *rdev = dev->dev_private; 223 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 224 union dvo_encoder_control args; 225 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); 226 uint8_t frev, crev; 227 228 memset(&args, 0, sizeof(args)); 229 230 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 231 return; 232 233 switch (frev) { 234 case 1: 235 switch (crev) { 236 case 1: 237 /* R4xx, R5xx */ 238 args.ext_tmds.sXTmdsEncoder.ucEnable = action; 239 240 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 241 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL; 242 243 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB; 244 break; 245 case 2: 246 /* RS600/690/740 */ 247 args.dvo.sDVOEncoder.ucAction = action; 248 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 249 /* DFP1, CRT1, TV1 depending on the type of port */ 250 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX; 251 252 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 253 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL; 254 break; 255 case 3: 256 /* R6xx */ 257 args.dvo_v3.ucAction = action; 258 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 259 args.dvo_v3.ucDVOConfig = 0; /* XXX */ 260 break; 261 default: 262 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 263 break; 264 } 265 break; 266 default: 267 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 268 break; 269 } 270 271 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 272 } 273 274 union lvds_encoder_control { 275 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1; 276 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2; 277 }; 278 279 void 280 atombios_digital_setup(struct drm_encoder *encoder, int action) 281 { 282 struct drm_device *dev = encoder->dev; 283 struct radeon_device *rdev = dev->dev_private; 284 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 285 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 286 union lvds_encoder_control args; 287 int index = 0; 288 int hdmi_detected = 0; 289 uint8_t frev, crev; 290 291 if (!dig) 292 return; 293 294 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 295 hdmi_detected = 1; 296 297 memset(&args, 0, sizeof(args)); 298 299 switch (radeon_encoder->encoder_id) { 300 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 301 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 302 break; 303 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 304 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 305 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl); 306 break; 307 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 308 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 309 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 310 else 311 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl); 312 break; 313 } 314 315 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 316 return; 317 318 switch (frev) { 319 case 1: 320 case 2: 321 switch (crev) { 322 case 1: 323 args.v1.ucMisc = 0; 324 args.v1.ucAction = action; 325 if (hdmi_detected) 326 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 327 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 328 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 329 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) 330 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 331 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 332 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; 333 } else { 334 if (dig->linkb) 335 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 336 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 337 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 338 /*if (pScrn->rgbBits == 8) */ 339 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; 340 } 341 break; 342 case 2: 343 case 3: 344 args.v2.ucMisc = 0; 345 args.v2.ucAction = action; 346 if (crev == 3) { 347 if (dig->coherent_mode) 348 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; 349 } 350 if (hdmi_detected) 351 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 352 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 353 args.v2.ucTruncate = 0; 354 args.v2.ucSpatial = 0; 355 args.v2.ucTemporal = 0; 356 args.v2.ucFRC = 0; 357 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 358 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) 359 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 360 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) { 361 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN; 362 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 363 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH; 364 } 365 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) { 366 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN; 367 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 368 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH; 369 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2) 370 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; 371 } 372 } else { 373 if (dig->linkb) 374 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 375 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 376 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 377 } 378 break; 379 default: 380 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 381 break; 382 } 383 break; 384 default: 385 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 386 break; 387 } 388 389 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 390 } 391 392 int 393 atombios_get_encoder_mode(struct drm_encoder *encoder) 394 { 395 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 396 struct drm_connector *connector; 397 struct radeon_connector *radeon_connector; 398 struct radeon_connector_atom_dig *dig_connector; 399 400 /* dp bridges are always DP */ 401 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) 402 return ATOM_ENCODER_MODE_DP; 403 404 /* DVO is always DVO */ 405 if (radeon_encoder->encoder_id == ATOM_ENCODER_MODE_DVO) 406 return ATOM_ENCODER_MODE_DVO; 407 408 connector = radeon_get_connector_for_encoder(encoder); 409 /* if we don't have an active device yet, just use one of 410 * the connectors tied to the encoder. 411 */ 412 if (!connector) 413 connector = radeon_get_connector_for_encoder_init(encoder); 414 radeon_connector = to_radeon_connector(connector); 415 416 switch (connector->connector_type) { 417 case DRM_MODE_CONNECTOR_DVII: 418 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ 419 if (drm_detect_hdmi_monitor(radeon_connector->edid) && 420 radeon_audio) 421 return ATOM_ENCODER_MODE_HDMI; 422 else if (radeon_connector->use_digital) 423 return ATOM_ENCODER_MODE_DVI; 424 else 425 return ATOM_ENCODER_MODE_CRT; 426 break; 427 case DRM_MODE_CONNECTOR_DVID: 428 case DRM_MODE_CONNECTOR_HDMIA: 429 default: 430 if (drm_detect_hdmi_monitor(radeon_connector->edid) && 431 radeon_audio) 432 return ATOM_ENCODER_MODE_HDMI; 433 else 434 return ATOM_ENCODER_MODE_DVI; 435 break; 436 case DRM_MODE_CONNECTOR_LVDS: 437 return ATOM_ENCODER_MODE_LVDS; 438 break; 439 case DRM_MODE_CONNECTOR_DisplayPort: 440 dig_connector = radeon_connector->con_priv; 441 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 442 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) 443 return ATOM_ENCODER_MODE_DP; 444 else if (drm_detect_hdmi_monitor(radeon_connector->edid) && 445 radeon_audio) 446 return ATOM_ENCODER_MODE_HDMI; 447 else 448 return ATOM_ENCODER_MODE_DVI; 449 break; 450 case DRM_MODE_CONNECTOR_eDP: 451 return ATOM_ENCODER_MODE_DP; 452 case DRM_MODE_CONNECTOR_DVIA: 453 case DRM_MODE_CONNECTOR_VGA: 454 return ATOM_ENCODER_MODE_CRT; 455 break; 456 case DRM_MODE_CONNECTOR_Composite: 457 case DRM_MODE_CONNECTOR_SVIDEO: 458 case DRM_MODE_CONNECTOR_9PinDIN: 459 /* fix me */ 460 return ATOM_ENCODER_MODE_TV; 461 /*return ATOM_ENCODER_MODE_CV;*/ 462 break; 463 } 464 } 465 466 /* 467 * DIG Encoder/Transmitter Setup 468 * 469 * DCE 3.0/3.1 470 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA. 471 * Supports up to 3 digital outputs 472 * - 2 DIG encoder blocks. 473 * DIG1 can drive UNIPHY link A or link B 474 * DIG2 can drive UNIPHY link B or LVTMA 475 * 476 * DCE 3.2 477 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B). 478 * Supports up to 5 digital outputs 479 * - 2 DIG encoder blocks. 480 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 481 * 482 * DCE 4.0/5.0 483 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). 484 * Supports up to 6 digital outputs 485 * - 6 DIG encoder blocks. 486 * - DIG to PHY mapping is hardcoded 487 * DIG1 drives UNIPHY0 link A, A+B 488 * DIG2 drives UNIPHY0 link B 489 * DIG3 drives UNIPHY1 link A, A+B 490 * DIG4 drives UNIPHY1 link B 491 * DIG5 drives UNIPHY2 link A, A+B 492 * DIG6 drives UNIPHY2 link B 493 * 494 * DCE 4.1 495 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). 496 * Supports up to 6 digital outputs 497 * - 2 DIG encoder blocks. 498 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 499 * 500 * Routing 501 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links) 502 * Examples: 503 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI 504 * crtc1 -> dig1 -> UNIPHY0 link B -> DP 505 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS 506 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI 507 */ 508 509 union dig_encoder_control { 510 DIG_ENCODER_CONTROL_PS_ALLOCATION v1; 511 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2; 512 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; 513 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4; 514 }; 515 516 void 517 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode) 518 { 519 struct drm_device *dev = encoder->dev; 520 struct radeon_device *rdev = dev->dev_private; 521 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 522 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 523 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 524 union dig_encoder_control args; 525 int index = 0; 526 uint8_t frev, crev; 527 int dp_clock = 0; 528 int dp_lane_count = 0; 529 int hpd_id = RADEON_HPD_NONE; 530 int bpc = 8; 531 532 if (connector) { 533 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 534 struct radeon_connector_atom_dig *dig_connector = 535 radeon_connector->con_priv; 536 537 dp_clock = dig_connector->dp_clock; 538 dp_lane_count = dig_connector->dp_lane_count; 539 hpd_id = radeon_connector->hpd.hpd; 540 bpc = connector->display_info.bpc; 541 } 542 543 /* no dig encoder assigned */ 544 if (dig->dig_encoder == -1) 545 return; 546 547 memset(&args, 0, sizeof(args)); 548 549 if (ASIC_IS_DCE4(rdev)) 550 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl); 551 else { 552 if (dig->dig_encoder) 553 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); 554 else 555 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); 556 } 557 558 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 559 return; 560 561 switch (frev) { 562 case 1: 563 switch (crev) { 564 case 1: 565 args.v1.ucAction = action; 566 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 567 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 568 args.v3.ucPanelMode = panel_mode; 569 else 570 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder); 571 572 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) 573 args.v1.ucLaneNum = dp_lane_count; 574 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 575 args.v1.ucLaneNum = 8; 576 else 577 args.v1.ucLaneNum = 4; 578 579 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000)) 580 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 581 switch (radeon_encoder->encoder_id) { 582 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 583 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; 584 break; 585 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 586 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 587 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; 588 break; 589 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 590 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; 591 break; 592 } 593 if (dig->linkb) 594 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; 595 else 596 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; 597 break; 598 case 2: 599 case 3: 600 args.v3.ucAction = action; 601 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 602 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 603 args.v3.ucPanelMode = panel_mode; 604 else 605 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder); 606 607 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) 608 args.v3.ucLaneNum = dp_lane_count; 609 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 610 args.v3.ucLaneNum = 8; 611 else 612 args.v3.ucLaneNum = 4; 613 614 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000)) 615 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 616 args.v3.acConfig.ucDigSel = dig->dig_encoder; 617 switch (bpc) { 618 case 0: 619 args.v3.ucBitPerColor = PANEL_BPC_UNDEFINE; 620 break; 621 case 6: 622 args.v3.ucBitPerColor = PANEL_6BIT_PER_COLOR; 623 break; 624 case 8: 625 default: 626 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR; 627 break; 628 case 10: 629 args.v3.ucBitPerColor = PANEL_10BIT_PER_COLOR; 630 break; 631 case 12: 632 args.v3.ucBitPerColor = PANEL_12BIT_PER_COLOR; 633 break; 634 case 16: 635 args.v3.ucBitPerColor = PANEL_16BIT_PER_COLOR; 636 break; 637 } 638 break; 639 case 4: 640 args.v4.ucAction = action; 641 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 642 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 643 args.v4.ucPanelMode = panel_mode; 644 else 645 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder); 646 647 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) 648 args.v4.ucLaneNum = dp_lane_count; 649 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 650 args.v4.ucLaneNum = 8; 651 else 652 args.v4.ucLaneNum = 4; 653 654 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) { 655 if (dp_clock == 270000) 656 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ; 657 else if (dp_clock == 540000) 658 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ; 659 } 660 args.v4.acConfig.ucDigSel = dig->dig_encoder; 661 switch (bpc) { 662 case 0: 663 args.v4.ucBitPerColor = PANEL_BPC_UNDEFINE; 664 break; 665 case 6: 666 args.v4.ucBitPerColor = PANEL_6BIT_PER_COLOR; 667 break; 668 case 8: 669 default: 670 args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR; 671 break; 672 case 10: 673 args.v4.ucBitPerColor = PANEL_10BIT_PER_COLOR; 674 break; 675 case 12: 676 args.v4.ucBitPerColor = PANEL_12BIT_PER_COLOR; 677 break; 678 case 16: 679 args.v4.ucBitPerColor = PANEL_16BIT_PER_COLOR; 680 break; 681 } 682 if (hpd_id == RADEON_HPD_NONE) 683 args.v4.ucHPD_ID = 0; 684 else 685 args.v4.ucHPD_ID = hpd_id + 1; 686 break; 687 default: 688 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 689 break; 690 } 691 break; 692 default: 693 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 694 break; 695 } 696 697 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 698 699 } 700 701 union dig_transmitter_control { 702 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; 703 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; 704 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3; 705 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4; 706 }; 707 708 void 709 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set) 710 { 711 struct drm_device *dev = encoder->dev; 712 struct radeon_device *rdev = dev->dev_private; 713 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 714 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 715 struct drm_connector *connector; 716 union dig_transmitter_control args; 717 int index = 0; 718 uint8_t frev, crev; 719 bool is_dp = false; 720 int pll_id = 0; 721 int dp_clock = 0; 722 int dp_lane_count = 0; 723 int connector_object_id = 0; 724 int igp_lane_info = 0; 725 int dig_encoder = dig->dig_encoder; 726 727 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 728 connector = radeon_get_connector_for_encoder_init(encoder); 729 /* just needed to avoid bailing in the encoder check. the encoder 730 * isn't used for init 731 */ 732 dig_encoder = 0; 733 } else 734 connector = radeon_get_connector_for_encoder(encoder); 735 736 if (connector) { 737 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 738 struct radeon_connector_atom_dig *dig_connector = 739 radeon_connector->con_priv; 740 741 dp_clock = dig_connector->dp_clock; 742 dp_lane_count = dig_connector->dp_lane_count; 743 connector_object_id = 744 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 745 igp_lane_info = dig_connector->igp_lane_info; 746 } 747 748 if (encoder->crtc) { 749 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 750 pll_id = radeon_crtc->pll_id; 751 } 752 753 /* no dig encoder assigned */ 754 if (dig_encoder == -1) 755 return; 756 757 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder))) 758 is_dp = true; 759 760 memset(&args, 0, sizeof(args)); 761 762 switch (radeon_encoder->encoder_id) { 763 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 764 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 765 break; 766 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 767 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 768 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 769 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 770 break; 771 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 772 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl); 773 break; 774 } 775 776 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 777 return; 778 779 switch (frev) { 780 case 1: 781 switch (crev) { 782 case 1: 783 args.v1.ucAction = action; 784 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 785 args.v1.usInitInfo = cpu_to_le16(connector_object_id); 786 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 787 args.v1.asMode.ucLaneSel = lane_num; 788 args.v1.asMode.ucLaneSet = lane_set; 789 } else { 790 if (is_dp) 791 args.v1.usPixelClock = 792 cpu_to_le16(dp_clock / 10); 793 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 794 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 795 else 796 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 797 } 798 799 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; 800 801 if (dig_encoder) 802 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; 803 else 804 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; 805 806 if ((rdev->flags & RADEON_IS_IGP) && 807 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) { 808 if (is_dp || 809 !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) { 810 if (igp_lane_info & 0x1) 811 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; 812 else if (igp_lane_info & 0x2) 813 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; 814 else if (igp_lane_info & 0x4) 815 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; 816 else if (igp_lane_info & 0x8) 817 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; 818 } else { 819 if (igp_lane_info & 0x3) 820 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; 821 else if (igp_lane_info & 0xc) 822 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; 823 } 824 } 825 826 if (dig->linkb) 827 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB; 828 else 829 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; 830 831 if (is_dp) 832 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 833 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 834 if (dig->coherent_mode) 835 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 836 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 837 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK; 838 } 839 break; 840 case 2: 841 args.v2.ucAction = action; 842 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 843 args.v2.usInitInfo = cpu_to_le16(connector_object_id); 844 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 845 args.v2.asMode.ucLaneSel = lane_num; 846 args.v2.asMode.ucLaneSet = lane_set; 847 } else { 848 if (is_dp) 849 args.v2.usPixelClock = 850 cpu_to_le16(dp_clock / 10); 851 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 852 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 853 else 854 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 855 } 856 857 args.v2.acConfig.ucEncoderSel = dig_encoder; 858 if (dig->linkb) 859 args.v2.acConfig.ucLinkSel = 1; 860 861 switch (radeon_encoder->encoder_id) { 862 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 863 args.v2.acConfig.ucTransmitterSel = 0; 864 break; 865 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 866 args.v2.acConfig.ucTransmitterSel = 1; 867 break; 868 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 869 args.v2.acConfig.ucTransmitterSel = 2; 870 break; 871 } 872 873 if (is_dp) { 874 args.v2.acConfig.fCoherentMode = 1; 875 args.v2.acConfig.fDPConnector = 1; 876 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 877 if (dig->coherent_mode) 878 args.v2.acConfig.fCoherentMode = 1; 879 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 880 args.v2.acConfig.fDualLinkConnector = 1; 881 } 882 break; 883 case 3: 884 args.v3.ucAction = action; 885 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 886 args.v3.usInitInfo = cpu_to_le16(connector_object_id); 887 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 888 args.v3.asMode.ucLaneSel = lane_num; 889 args.v3.asMode.ucLaneSet = lane_set; 890 } else { 891 if (is_dp) 892 args.v3.usPixelClock = 893 cpu_to_le16(dp_clock / 10); 894 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 895 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 896 else 897 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 898 } 899 900 if (is_dp) 901 args.v3.ucLaneNum = dp_lane_count; 902 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 903 args.v3.ucLaneNum = 8; 904 else 905 args.v3.ucLaneNum = 4; 906 907 if (dig->linkb) 908 args.v3.acConfig.ucLinkSel = 1; 909 if (dig_encoder & 1) 910 args.v3.acConfig.ucEncoderSel = 1; 911 912 /* Select the PLL for the PHY 913 * DP PHY should be clocked from external src if there is 914 * one. 915 */ 916 /* On DCE4, if there is an external clock, it generates the DP ref clock */ 917 if (is_dp && rdev->clock.dp_extclk) 918 args.v3.acConfig.ucRefClkSource = 2; /* external src */ 919 else 920 args.v3.acConfig.ucRefClkSource = pll_id; 921 922 switch (radeon_encoder->encoder_id) { 923 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 924 args.v3.acConfig.ucTransmitterSel = 0; 925 break; 926 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 927 args.v3.acConfig.ucTransmitterSel = 1; 928 break; 929 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 930 args.v3.acConfig.ucTransmitterSel = 2; 931 break; 932 } 933 934 if (is_dp) 935 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */ 936 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 937 if (dig->coherent_mode) 938 args.v3.acConfig.fCoherentMode = 1; 939 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 940 args.v3.acConfig.fDualLinkConnector = 1; 941 } 942 break; 943 case 4: 944 args.v4.ucAction = action; 945 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 946 args.v4.usInitInfo = cpu_to_le16(connector_object_id); 947 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 948 args.v4.asMode.ucLaneSel = lane_num; 949 args.v4.asMode.ucLaneSet = lane_set; 950 } else { 951 if (is_dp) 952 args.v4.usPixelClock = 953 cpu_to_le16(dp_clock / 10); 954 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 955 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 956 else 957 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 958 } 959 960 if (is_dp) 961 args.v4.ucLaneNum = dp_lane_count; 962 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 963 args.v4.ucLaneNum = 8; 964 else 965 args.v4.ucLaneNum = 4; 966 967 if (dig->linkb) 968 args.v4.acConfig.ucLinkSel = 1; 969 if (dig_encoder & 1) 970 args.v4.acConfig.ucEncoderSel = 1; 971 972 /* Select the PLL for the PHY 973 * DP PHY should be clocked from external src if there is 974 * one. 975 */ 976 /* On DCE5 DCPLL usually generates the DP ref clock */ 977 if (is_dp) { 978 if (rdev->clock.dp_extclk) 979 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK; 980 else 981 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL; 982 } else 983 args.v4.acConfig.ucRefClkSource = pll_id; 984 985 switch (radeon_encoder->encoder_id) { 986 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 987 args.v4.acConfig.ucTransmitterSel = 0; 988 break; 989 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 990 args.v4.acConfig.ucTransmitterSel = 1; 991 break; 992 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 993 args.v4.acConfig.ucTransmitterSel = 2; 994 break; 995 } 996 997 if (is_dp) 998 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */ 999 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1000 if (dig->coherent_mode) 1001 args.v4.acConfig.fCoherentMode = 1; 1002 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1003 args.v4.acConfig.fDualLinkConnector = 1; 1004 } 1005 break; 1006 default: 1007 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1008 break; 1009 } 1010 break; 1011 default: 1012 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1013 break; 1014 } 1015 1016 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1017 } 1018 1019 bool 1020 atombios_set_edp_panel_power(struct drm_connector *connector, int action) 1021 { 1022 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1023 struct drm_device *dev = radeon_connector->base.dev; 1024 struct radeon_device *rdev = dev->dev_private; 1025 union dig_transmitter_control args; 1026 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 1027 uint8_t frev, crev; 1028 1029 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP) 1030 goto done; 1031 1032 if (!ASIC_IS_DCE4(rdev)) 1033 goto done; 1034 1035 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) && 1036 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF)) 1037 goto done; 1038 1039 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1040 goto done; 1041 1042 memset(&args, 0, sizeof(args)); 1043 1044 args.v1.ucAction = action; 1045 1046 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1047 1048 /* wait for the panel to power up */ 1049 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) { 1050 int i; 1051 1052 for (i = 0; i < 300; i++) { 1053 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) 1054 return true; 1055 mdelay(1); 1056 } 1057 return false; 1058 } 1059 done: 1060 return true; 1061 } 1062 1063 union external_encoder_control { 1064 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1; 1065 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3; 1066 }; 1067 1068 static void 1069 atombios_external_encoder_setup(struct drm_encoder *encoder, 1070 struct drm_encoder *ext_encoder, 1071 int action) 1072 { 1073 struct drm_device *dev = encoder->dev; 1074 struct radeon_device *rdev = dev->dev_private; 1075 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1076 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder); 1077 union external_encoder_control args; 1078 struct drm_connector *connector; 1079 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl); 1080 u8 frev, crev; 1081 int dp_clock = 0; 1082 int dp_lane_count = 0; 1083 int connector_object_id = 0; 1084 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 1085 int bpc = 8; 1086 1087 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) 1088 connector = radeon_get_connector_for_encoder_init(encoder); 1089 else 1090 connector = radeon_get_connector_for_encoder(encoder); 1091 1092 if (connector) { 1093 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1094 struct radeon_connector_atom_dig *dig_connector = 1095 radeon_connector->con_priv; 1096 1097 dp_clock = dig_connector->dp_clock; 1098 dp_lane_count = dig_connector->dp_lane_count; 1099 connector_object_id = 1100 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 1101 bpc = connector->display_info.bpc; 1102 } 1103 1104 memset(&args, 0, sizeof(args)); 1105 1106 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1107 return; 1108 1109 switch (frev) { 1110 case 1: 1111 /* no params on frev 1 */ 1112 break; 1113 case 2: 1114 switch (crev) { 1115 case 1: 1116 case 2: 1117 args.v1.sDigEncoder.ucAction = action; 1118 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1119 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); 1120 1121 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) { 1122 if (dp_clock == 270000) 1123 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 1124 args.v1.sDigEncoder.ucLaneNum = dp_lane_count; 1125 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1126 args.v1.sDigEncoder.ucLaneNum = 8; 1127 else 1128 args.v1.sDigEncoder.ucLaneNum = 4; 1129 break; 1130 case 3: 1131 args.v3.sExtEncoder.ucAction = action; 1132 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) 1133 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id); 1134 else 1135 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1136 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); 1137 1138 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) { 1139 if (dp_clock == 270000) 1140 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 1141 else if (dp_clock == 540000) 1142 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ; 1143 args.v3.sExtEncoder.ucLaneNum = dp_lane_count; 1144 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1145 args.v3.sExtEncoder.ucLaneNum = 8; 1146 else 1147 args.v3.sExtEncoder.ucLaneNum = 4; 1148 switch (ext_enum) { 1149 case GRAPH_OBJECT_ENUM_ID1: 1150 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1; 1151 break; 1152 case GRAPH_OBJECT_ENUM_ID2: 1153 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2; 1154 break; 1155 case GRAPH_OBJECT_ENUM_ID3: 1156 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3; 1157 break; 1158 } 1159 switch (bpc) { 1160 case 0: 1161 args.v3.sExtEncoder.ucBitPerColor = PANEL_BPC_UNDEFINE; 1162 break; 1163 case 6: 1164 args.v3.sExtEncoder.ucBitPerColor = PANEL_6BIT_PER_COLOR; 1165 break; 1166 case 8: 1167 default: 1168 args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR; 1169 break; 1170 case 10: 1171 args.v3.sExtEncoder.ucBitPerColor = PANEL_10BIT_PER_COLOR; 1172 break; 1173 case 12: 1174 args.v3.sExtEncoder.ucBitPerColor = PANEL_12BIT_PER_COLOR; 1175 break; 1176 case 16: 1177 args.v3.sExtEncoder.ucBitPerColor = PANEL_16BIT_PER_COLOR; 1178 break; 1179 } 1180 break; 1181 default: 1182 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1183 return; 1184 } 1185 break; 1186 default: 1187 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1188 return; 1189 } 1190 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1191 } 1192 1193 static void 1194 atombios_yuv_setup(struct drm_encoder *encoder, bool enable) 1195 { 1196 struct drm_device *dev = encoder->dev; 1197 struct radeon_device *rdev = dev->dev_private; 1198 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1199 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1200 ENABLE_YUV_PS_ALLOCATION args; 1201 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV); 1202 uint32_t temp, reg; 1203 1204 memset(&args, 0, sizeof(args)); 1205 1206 if (rdev->family >= CHIP_R600) 1207 reg = R600_BIOS_3_SCRATCH; 1208 else 1209 reg = RADEON_BIOS_3_SCRATCH; 1210 1211 /* XXX: fix up scratch reg handling */ 1212 temp = RREG32(reg); 1213 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1214 WREG32(reg, (ATOM_S3_TV1_ACTIVE | 1215 (radeon_crtc->crtc_id << 18))); 1216 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1217 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); 1218 else 1219 WREG32(reg, 0); 1220 1221 if (enable) 1222 args.ucEnable = ATOM_ENABLE; 1223 args.ucCRTC = radeon_crtc->crtc_id; 1224 1225 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1226 1227 WREG32(reg, temp); 1228 } 1229 1230 static void 1231 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode) 1232 { 1233 struct drm_device *dev = encoder->dev; 1234 struct radeon_device *rdev = dev->dev_private; 1235 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1236 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; 1237 int index = 0; 1238 1239 memset(&args, 0, sizeof(args)); 1240 1241 switch (radeon_encoder->encoder_id) { 1242 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1243 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1244 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl); 1245 break; 1246 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1247 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1248 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1249 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 1250 break; 1251 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1252 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 1253 break; 1254 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1255 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1256 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 1257 else 1258 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl); 1259 break; 1260 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1261 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1262 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1263 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 1264 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1265 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 1266 else 1267 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); 1268 break; 1269 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1270 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1271 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1272 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 1273 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1274 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 1275 else 1276 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); 1277 break; 1278 default: 1279 return; 1280 } 1281 1282 switch (mode) { 1283 case DRM_MODE_DPMS_ON: 1284 args.ucAction = ATOM_ENABLE; 1285 /* workaround for DVOOutputControl on some RS690 systems */ 1286 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) { 1287 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH); 1288 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE); 1289 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1290 WREG32(RADEON_BIOS_3_SCRATCH, reg); 1291 } else 1292 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1293 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1294 args.ucAction = ATOM_LCD_BLON; 1295 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1296 } 1297 break; 1298 case DRM_MODE_DPMS_STANDBY: 1299 case DRM_MODE_DPMS_SUSPEND: 1300 case DRM_MODE_DPMS_OFF: 1301 args.ucAction = ATOM_DISABLE; 1302 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1303 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1304 args.ucAction = ATOM_LCD_BLOFF; 1305 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1306 } 1307 break; 1308 } 1309 } 1310 1311 static void 1312 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode) 1313 { 1314 struct drm_device *dev = encoder->dev; 1315 struct radeon_device *rdev = dev->dev_private; 1316 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1317 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1318 struct radeon_connector *radeon_connector = NULL; 1319 struct radeon_connector_atom_dig *radeon_dig_connector = NULL; 1320 1321 if (connector) { 1322 radeon_connector = to_radeon_connector(connector); 1323 radeon_dig_connector = radeon_connector->con_priv; 1324 } 1325 1326 switch (mode) { 1327 case DRM_MODE_DPMS_ON: 1328 /* some early dce3.2 boards have a bug in their transmitter control table */ 1329 if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730) || 1330 ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) 1331 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1332 else 1333 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); 1334 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1335 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1336 atombios_set_edp_panel_power(connector, 1337 ATOM_TRANSMITTER_ACTION_POWER_ON); 1338 radeon_dig_connector->edp_on = true; 1339 } 1340 radeon_dp_link_train(encoder, connector); 1341 if (ASIC_IS_DCE4(rdev)) 1342 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0); 1343 } 1344 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1345 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); 1346 break; 1347 case DRM_MODE_DPMS_STANDBY: 1348 case DRM_MODE_DPMS_SUSPEND: 1349 case DRM_MODE_DPMS_OFF: 1350 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) 1351 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1352 else 1353 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0); 1354 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1355 if (ASIC_IS_DCE4(rdev)) 1356 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); 1357 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1358 atombios_set_edp_panel_power(connector, 1359 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1360 radeon_dig_connector->edp_on = false; 1361 } 1362 } 1363 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1364 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); 1365 break; 1366 } 1367 } 1368 1369 static void 1370 radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder, 1371 struct drm_encoder *ext_encoder, 1372 int mode) 1373 { 1374 struct drm_device *dev = encoder->dev; 1375 struct radeon_device *rdev = dev->dev_private; 1376 1377 switch (mode) { 1378 case DRM_MODE_DPMS_ON: 1379 default: 1380 if (ASIC_IS_DCE41(rdev)) { 1381 atombios_external_encoder_setup(encoder, ext_encoder, 1382 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT); 1383 atombios_external_encoder_setup(encoder, ext_encoder, 1384 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF); 1385 } else 1386 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE); 1387 break; 1388 case DRM_MODE_DPMS_STANDBY: 1389 case DRM_MODE_DPMS_SUSPEND: 1390 case DRM_MODE_DPMS_OFF: 1391 if (ASIC_IS_DCE41(rdev)) { 1392 atombios_external_encoder_setup(encoder, ext_encoder, 1393 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING); 1394 atombios_external_encoder_setup(encoder, ext_encoder, 1395 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT); 1396 } else 1397 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE); 1398 break; 1399 } 1400 } 1401 1402 static void 1403 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) 1404 { 1405 struct drm_device *dev = encoder->dev; 1406 struct radeon_device *rdev = dev->dev_private; 1407 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1408 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 1409 1410 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", 1411 radeon_encoder->encoder_id, mode, radeon_encoder->devices, 1412 radeon_encoder->active_device); 1413 switch (radeon_encoder->encoder_id) { 1414 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1415 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1416 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1417 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1418 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1419 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1420 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1421 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1422 radeon_atom_encoder_dpms_avivo(encoder, mode); 1423 break; 1424 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1425 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1426 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1427 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1428 radeon_atom_encoder_dpms_dig(encoder, mode); 1429 break; 1430 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1431 if (ASIC_IS_DCE5(rdev)) { 1432 switch (mode) { 1433 case DRM_MODE_DPMS_ON: 1434 atombios_dvo_setup(encoder, ATOM_ENABLE); 1435 break; 1436 case DRM_MODE_DPMS_STANDBY: 1437 case DRM_MODE_DPMS_SUSPEND: 1438 case DRM_MODE_DPMS_OFF: 1439 atombios_dvo_setup(encoder, ATOM_DISABLE); 1440 break; 1441 } 1442 } else if (ASIC_IS_DCE3(rdev)) 1443 radeon_atom_encoder_dpms_dig(encoder, mode); 1444 else 1445 radeon_atom_encoder_dpms_avivo(encoder, mode); 1446 break; 1447 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1448 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1449 if (ASIC_IS_DCE5(rdev)) { 1450 switch (mode) { 1451 case DRM_MODE_DPMS_ON: 1452 atombios_dac_setup(encoder, ATOM_ENABLE); 1453 break; 1454 case DRM_MODE_DPMS_STANDBY: 1455 case DRM_MODE_DPMS_SUSPEND: 1456 case DRM_MODE_DPMS_OFF: 1457 atombios_dac_setup(encoder, ATOM_DISABLE); 1458 break; 1459 } 1460 } else 1461 radeon_atom_encoder_dpms_avivo(encoder, mode); 1462 break; 1463 default: 1464 return; 1465 } 1466 1467 if (ext_encoder) 1468 radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode); 1469 1470 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 1471 1472 } 1473 1474 union crtc_source_param { 1475 SELECT_CRTC_SOURCE_PS_ALLOCATION v1; 1476 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2; 1477 }; 1478 1479 static void 1480 atombios_set_encoder_crtc_source(struct drm_encoder *encoder) 1481 { 1482 struct drm_device *dev = encoder->dev; 1483 struct radeon_device *rdev = dev->dev_private; 1484 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1485 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1486 union crtc_source_param args; 1487 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); 1488 uint8_t frev, crev; 1489 struct radeon_encoder_atom_dig *dig; 1490 1491 memset(&args, 0, sizeof(args)); 1492 1493 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1494 return; 1495 1496 switch (frev) { 1497 case 1: 1498 switch (crev) { 1499 case 1: 1500 default: 1501 if (ASIC_IS_AVIVO(rdev)) 1502 args.v1.ucCRTC = radeon_crtc->crtc_id; 1503 else { 1504 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) { 1505 args.v1.ucCRTC = radeon_crtc->crtc_id; 1506 } else { 1507 args.v1.ucCRTC = radeon_crtc->crtc_id << 2; 1508 } 1509 } 1510 switch (radeon_encoder->encoder_id) { 1511 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1512 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1513 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX; 1514 break; 1515 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1516 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1517 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) 1518 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX; 1519 else 1520 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX; 1521 break; 1522 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1523 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1524 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1525 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; 1526 break; 1527 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1528 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1529 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1530 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1531 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1532 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1533 else 1534 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; 1535 break; 1536 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1537 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1538 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1539 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1540 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1541 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1542 else 1543 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; 1544 break; 1545 } 1546 break; 1547 case 2: 1548 args.v2.ucCRTC = radeon_crtc->crtc_id; 1549 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) { 1550 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1551 1552 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS) 1553 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; 1554 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA) 1555 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT; 1556 else 1557 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); 1558 } else 1559 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); 1560 switch (radeon_encoder->encoder_id) { 1561 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1562 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1563 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1564 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1565 dig = radeon_encoder->enc_priv; 1566 switch (dig->dig_encoder) { 1567 case 0: 1568 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; 1569 break; 1570 case 1: 1571 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; 1572 break; 1573 case 2: 1574 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; 1575 break; 1576 case 3: 1577 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; 1578 break; 1579 case 4: 1580 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; 1581 break; 1582 case 5: 1583 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; 1584 break; 1585 } 1586 break; 1587 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1588 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; 1589 break; 1590 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1591 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1592 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1593 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1594 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1595 else 1596 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; 1597 break; 1598 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1599 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1600 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1601 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1602 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1603 else 1604 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; 1605 break; 1606 } 1607 break; 1608 } 1609 break; 1610 default: 1611 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1612 return; 1613 } 1614 1615 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1616 1617 /* update scratch regs with new routing */ 1618 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 1619 } 1620 1621 static void 1622 atombios_apply_encoder_quirks(struct drm_encoder *encoder, 1623 struct drm_display_mode *mode) 1624 { 1625 struct drm_device *dev = encoder->dev; 1626 struct radeon_device *rdev = dev->dev_private; 1627 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1628 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1629 1630 /* Funky macbooks */ 1631 if ((dev->pdev->device == 0x71C5) && 1632 (dev->pdev->subsystem_vendor == 0x106b) && 1633 (dev->pdev->subsystem_device == 0x0080)) { 1634 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 1635 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL); 1636 1637 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN; 1638 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; 1639 1640 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); 1641 } 1642 } 1643 1644 /* set scaler clears this on some chips */ 1645 if (ASIC_IS_AVIVO(rdev) && 1646 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) { 1647 if (ASIC_IS_DCE4(rdev)) { 1648 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1649 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 1650 EVERGREEN_INTERLEAVE_EN); 1651 else 1652 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 1653 } else { 1654 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1655 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 1656 AVIVO_D1MODE_INTERLEAVE_EN); 1657 else 1658 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 1659 } 1660 } 1661 } 1662 1663 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder) 1664 { 1665 struct drm_device *dev = encoder->dev; 1666 struct radeon_device *rdev = dev->dev_private; 1667 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1668 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1669 struct drm_encoder *test_encoder; 1670 struct radeon_encoder_atom_dig *dig; 1671 uint32_t dig_enc_in_use = 0; 1672 1673 /* DCE4/5 */ 1674 if (ASIC_IS_DCE4(rdev)) { 1675 dig = radeon_encoder->enc_priv; 1676 if (ASIC_IS_DCE41(rdev)) { 1677 /* ontario follows DCE4 */ 1678 if (rdev->family == CHIP_PALM) { 1679 if (dig->linkb) 1680 return 1; 1681 else 1682 return 0; 1683 } else 1684 /* llano follows DCE3.2 */ 1685 return radeon_crtc->crtc_id; 1686 } else { 1687 switch (radeon_encoder->encoder_id) { 1688 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1689 if (dig->linkb) 1690 return 1; 1691 else 1692 return 0; 1693 break; 1694 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1695 if (dig->linkb) 1696 return 3; 1697 else 1698 return 2; 1699 break; 1700 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1701 if (dig->linkb) 1702 return 5; 1703 else 1704 return 4; 1705 break; 1706 } 1707 } 1708 } 1709 1710 /* on DCE32 and encoder can driver any block so just crtc id */ 1711 if (ASIC_IS_DCE32(rdev)) { 1712 return radeon_crtc->crtc_id; 1713 } 1714 1715 /* on DCE3 - LVTMA can only be driven by DIGB */ 1716 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { 1717 struct radeon_encoder *radeon_test_encoder; 1718 1719 if (encoder == test_encoder) 1720 continue; 1721 1722 if (!radeon_encoder_is_digital(test_encoder)) 1723 continue; 1724 1725 radeon_test_encoder = to_radeon_encoder(test_encoder); 1726 dig = radeon_test_encoder->enc_priv; 1727 1728 if (dig->dig_encoder >= 0) 1729 dig_enc_in_use |= (1 << dig->dig_encoder); 1730 } 1731 1732 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) { 1733 if (dig_enc_in_use & 0x2) 1734 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n"); 1735 return 1; 1736 } 1737 if (!(dig_enc_in_use & 1)) 1738 return 0; 1739 return 1; 1740 } 1741 1742 /* This only needs to be called once at startup */ 1743 void 1744 radeon_atom_encoder_init(struct radeon_device *rdev) 1745 { 1746 struct drm_device *dev = rdev->ddev; 1747 struct drm_encoder *encoder; 1748 1749 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1750 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1751 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 1752 1753 switch (radeon_encoder->encoder_id) { 1754 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1755 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1756 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1757 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1758 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); 1759 break; 1760 default: 1761 break; 1762 } 1763 1764 if (ext_encoder && ASIC_IS_DCE41(rdev)) 1765 atombios_external_encoder_setup(encoder, ext_encoder, 1766 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT); 1767 } 1768 } 1769 1770 static void 1771 radeon_atom_encoder_mode_set(struct drm_encoder *encoder, 1772 struct drm_display_mode *mode, 1773 struct drm_display_mode *adjusted_mode) 1774 { 1775 struct drm_device *dev = encoder->dev; 1776 struct radeon_device *rdev = dev->dev_private; 1777 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1778 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 1779 1780 radeon_encoder->pixel_clock = adjusted_mode->clock; 1781 1782 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) { 1783 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) 1784 atombios_yuv_setup(encoder, true); 1785 else 1786 atombios_yuv_setup(encoder, false); 1787 } 1788 1789 switch (radeon_encoder->encoder_id) { 1790 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1791 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1792 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1793 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1794 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); 1795 break; 1796 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1797 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1798 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1799 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1800 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { 1801 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1802 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 1803 1804 if (!connector) 1805 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 1806 else 1807 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector); 1808 1809 /* setup and enable the encoder */ 1810 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); 1811 atombios_dig_encoder_setup(encoder, 1812 ATOM_ENCODER_CMD_SETUP_PANEL_MODE, 1813 dig->panel_mode); 1814 } else if (ASIC_IS_DCE4(rdev)) { 1815 /* disable the transmitter */ 1816 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1817 /* setup and enable the encoder */ 1818 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); 1819 1820 /* enable the transmitter */ 1821 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1822 } else { 1823 /* disable the encoder and transmitter */ 1824 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1825 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0); 1826 1827 /* setup and enable the encoder and transmitter */ 1828 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0); 1829 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); 1830 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1831 } 1832 break; 1833 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1834 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1835 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1836 atombios_dvo_setup(encoder, ATOM_ENABLE); 1837 break; 1838 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1839 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1840 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1841 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1842 atombios_dac_setup(encoder, ATOM_ENABLE); 1843 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) { 1844 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 1845 atombios_tv_setup(encoder, ATOM_ENABLE); 1846 else 1847 atombios_tv_setup(encoder, ATOM_DISABLE); 1848 } 1849 break; 1850 } 1851 1852 if (ext_encoder) { 1853 if (ASIC_IS_DCE41(rdev)) 1854 atombios_external_encoder_setup(encoder, ext_encoder, 1855 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP); 1856 else 1857 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE); 1858 } 1859 1860 atombios_apply_encoder_quirks(encoder, adjusted_mode); 1861 1862 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 1863 r600_hdmi_enable(encoder); 1864 r600_hdmi_setmode(encoder, adjusted_mode); 1865 } 1866 } 1867 1868 static bool 1869 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector) 1870 { 1871 struct drm_device *dev = encoder->dev; 1872 struct radeon_device *rdev = dev->dev_private; 1873 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1874 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1875 1876 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | 1877 ATOM_DEVICE_CV_SUPPORT | 1878 ATOM_DEVICE_CRT_SUPPORT)) { 1879 DAC_LOAD_DETECTION_PS_ALLOCATION args; 1880 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection); 1881 uint8_t frev, crev; 1882 1883 memset(&args, 0, sizeof(args)); 1884 1885 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1886 return false; 1887 1888 args.sDacload.ucMisc = 0; 1889 1890 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || 1891 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1)) 1892 args.sDacload.ucDacType = ATOM_DAC_A; 1893 else 1894 args.sDacload.ucDacType = ATOM_DAC_B; 1895 1896 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) 1897 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); 1898 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) 1899 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); 1900 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 1901 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); 1902 if (crev >= 3) 1903 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 1904 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 1905 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); 1906 if (crev >= 3) 1907 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 1908 } 1909 1910 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1911 1912 return true; 1913 } else 1914 return false; 1915 } 1916 1917 static enum drm_connector_status 1918 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) 1919 { 1920 struct drm_device *dev = encoder->dev; 1921 struct radeon_device *rdev = dev->dev_private; 1922 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1923 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1924 uint32_t bios_0_scratch; 1925 1926 if (!atombios_dac_load_detect(encoder, connector)) { 1927 DRM_DEBUG_KMS("detect returned false \n"); 1928 return connector_status_unknown; 1929 } 1930 1931 if (rdev->family >= CHIP_R600) 1932 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 1933 else 1934 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 1935 1936 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); 1937 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { 1938 if (bios_0_scratch & ATOM_S0_CRT1_MASK) 1939 return connector_status_connected; 1940 } 1941 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { 1942 if (bios_0_scratch & ATOM_S0_CRT2_MASK) 1943 return connector_status_connected; 1944 } 1945 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 1946 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) 1947 return connector_status_connected; 1948 } 1949 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 1950 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) 1951 return connector_status_connected; /* CTV */ 1952 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) 1953 return connector_status_connected; /* STV */ 1954 } 1955 return connector_status_disconnected; 1956 } 1957 1958 static enum drm_connector_status 1959 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector) 1960 { 1961 struct drm_device *dev = encoder->dev; 1962 struct radeon_device *rdev = dev->dev_private; 1963 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1964 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1965 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 1966 u32 bios_0_scratch; 1967 1968 if (!ASIC_IS_DCE4(rdev)) 1969 return connector_status_unknown; 1970 1971 if (!ext_encoder) 1972 return connector_status_unknown; 1973 1974 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0) 1975 return connector_status_unknown; 1976 1977 /* load detect on the dp bridge */ 1978 atombios_external_encoder_setup(encoder, ext_encoder, 1979 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION); 1980 1981 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 1982 1983 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); 1984 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { 1985 if (bios_0_scratch & ATOM_S0_CRT1_MASK) 1986 return connector_status_connected; 1987 } 1988 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { 1989 if (bios_0_scratch & ATOM_S0_CRT2_MASK) 1990 return connector_status_connected; 1991 } 1992 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 1993 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) 1994 return connector_status_connected; 1995 } 1996 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 1997 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) 1998 return connector_status_connected; /* CTV */ 1999 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) 2000 return connector_status_connected; /* STV */ 2001 } 2002 return connector_status_disconnected; 2003 } 2004 2005 void 2006 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder) 2007 { 2008 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2009 2010 if (ext_encoder) 2011 /* ddc_setup on the dp bridge */ 2012 atombios_external_encoder_setup(encoder, ext_encoder, 2013 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP); 2014 2015 } 2016 2017 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) 2018 { 2019 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2020 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 2021 2022 if ((radeon_encoder->active_device & 2023 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 2024 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != 2025 ENCODER_OBJECT_ID_NONE)) { 2026 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 2027 if (dig) 2028 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder); 2029 } 2030 2031 radeon_atom_output_lock(encoder, true); 2032 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 2033 2034 if (connector) { 2035 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2036 2037 /* select the clock/data port if it uses a router */ 2038 if (radeon_connector->router.cd_valid) 2039 radeon_router_select_cd_port(radeon_connector); 2040 2041 /* turn eDP panel on for mode set */ 2042 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 2043 atombios_set_edp_panel_power(connector, 2044 ATOM_TRANSMITTER_ACTION_POWER_ON); 2045 } 2046 2047 /* this is needed for the pll/ss setup to work correctly in some cases */ 2048 atombios_set_encoder_crtc_source(encoder); 2049 } 2050 2051 static void radeon_atom_encoder_commit(struct drm_encoder *encoder) 2052 { 2053 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 2054 radeon_atom_output_lock(encoder, false); 2055 } 2056 2057 static void radeon_atom_encoder_disable(struct drm_encoder *encoder) 2058 { 2059 struct drm_device *dev = encoder->dev; 2060 struct radeon_device *rdev = dev->dev_private; 2061 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2062 struct radeon_encoder_atom_dig *dig; 2063 2064 /* check for pre-DCE3 cards with shared encoders; 2065 * can't really use the links individually, so don't disable 2066 * the encoder if it's in use by another connector 2067 */ 2068 if (!ASIC_IS_DCE3(rdev)) { 2069 struct drm_encoder *other_encoder; 2070 struct radeon_encoder *other_radeon_encoder; 2071 2072 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) { 2073 other_radeon_encoder = to_radeon_encoder(other_encoder); 2074 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) && 2075 drm_helper_encoder_in_use(other_encoder)) 2076 goto disable_done; 2077 } 2078 } 2079 2080 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 2081 2082 switch (radeon_encoder->encoder_id) { 2083 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2084 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2085 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2086 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2087 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE); 2088 break; 2089 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2090 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2091 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2092 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2093 if (ASIC_IS_DCE4(rdev)) 2094 /* disable the transmitter */ 2095 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 2096 else { 2097 /* disable the encoder and transmitter */ 2098 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 2099 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0); 2100 } 2101 break; 2102 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2103 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2104 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2105 atombios_dvo_setup(encoder, ATOM_DISABLE); 2106 break; 2107 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2108 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2109 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2110 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2111 atombios_dac_setup(encoder, ATOM_DISABLE); 2112 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 2113 atombios_tv_setup(encoder, ATOM_DISABLE); 2114 break; 2115 } 2116 2117 disable_done: 2118 if (radeon_encoder_is_digital(encoder)) { 2119 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 2120 r600_hdmi_disable(encoder); 2121 dig = radeon_encoder->enc_priv; 2122 dig->dig_encoder = -1; 2123 } 2124 radeon_encoder->active_device = 0; 2125 } 2126 2127 /* these are handled by the primary encoders */ 2128 static void radeon_atom_ext_prepare(struct drm_encoder *encoder) 2129 { 2130 2131 } 2132 2133 static void radeon_atom_ext_commit(struct drm_encoder *encoder) 2134 { 2135 2136 } 2137 2138 static void 2139 radeon_atom_ext_mode_set(struct drm_encoder *encoder, 2140 struct drm_display_mode *mode, 2141 struct drm_display_mode *adjusted_mode) 2142 { 2143 2144 } 2145 2146 static void radeon_atom_ext_disable(struct drm_encoder *encoder) 2147 { 2148 2149 } 2150 2151 static void 2152 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode) 2153 { 2154 2155 } 2156 2157 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder, 2158 struct drm_display_mode *mode, 2159 struct drm_display_mode *adjusted_mode) 2160 { 2161 return true; 2162 } 2163 2164 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = { 2165 .dpms = radeon_atom_ext_dpms, 2166 .mode_fixup = radeon_atom_ext_mode_fixup, 2167 .prepare = radeon_atom_ext_prepare, 2168 .mode_set = radeon_atom_ext_mode_set, 2169 .commit = radeon_atom_ext_commit, 2170 .disable = radeon_atom_ext_disable, 2171 /* no detect for TMDS/LVDS yet */ 2172 }; 2173 2174 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { 2175 .dpms = radeon_atom_encoder_dpms, 2176 .mode_fixup = radeon_atom_mode_fixup, 2177 .prepare = radeon_atom_encoder_prepare, 2178 .mode_set = radeon_atom_encoder_mode_set, 2179 .commit = radeon_atom_encoder_commit, 2180 .disable = radeon_atom_encoder_disable, 2181 .detect = radeon_atom_dig_detect, 2182 }; 2183 2184 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = { 2185 .dpms = radeon_atom_encoder_dpms, 2186 .mode_fixup = radeon_atom_mode_fixup, 2187 .prepare = radeon_atom_encoder_prepare, 2188 .mode_set = radeon_atom_encoder_mode_set, 2189 .commit = radeon_atom_encoder_commit, 2190 .detect = radeon_atom_dac_detect, 2191 }; 2192 2193 void radeon_enc_destroy(struct drm_encoder *encoder) 2194 { 2195 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2196 kfree(radeon_encoder->enc_priv); 2197 drm_encoder_cleanup(encoder); 2198 kfree(radeon_encoder); 2199 } 2200 2201 static const struct drm_encoder_funcs radeon_atom_enc_funcs = { 2202 .destroy = radeon_enc_destroy, 2203 }; 2204 2205 struct radeon_encoder_atom_dac * 2206 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder) 2207 { 2208 struct drm_device *dev = radeon_encoder->base.dev; 2209 struct radeon_device *rdev = dev->dev_private; 2210 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL); 2211 2212 if (!dac) 2213 return NULL; 2214 2215 dac->tv_std = radeon_atombios_get_tv_info(rdev); 2216 return dac; 2217 } 2218 2219 struct radeon_encoder_atom_dig * 2220 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) 2221 { 2222 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 2223 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); 2224 2225 if (!dig) 2226 return NULL; 2227 2228 /* coherent mode by default */ 2229 dig->coherent_mode = true; 2230 dig->dig_encoder = -1; 2231 2232 if (encoder_enum == 2) 2233 dig->linkb = true; 2234 else 2235 dig->linkb = false; 2236 2237 return dig; 2238 } 2239 2240 void 2241 radeon_add_atom_encoder(struct drm_device *dev, 2242 uint32_t encoder_enum, 2243 uint32_t supported_device, 2244 u16 caps) 2245 { 2246 struct radeon_device *rdev = dev->dev_private; 2247 struct drm_encoder *encoder; 2248 struct radeon_encoder *radeon_encoder; 2249 2250 /* see if we already added it */ 2251 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2252 radeon_encoder = to_radeon_encoder(encoder); 2253 if (radeon_encoder->encoder_enum == encoder_enum) { 2254 radeon_encoder->devices |= supported_device; 2255 return; 2256 } 2257 2258 } 2259 2260 /* add a new one */ 2261 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL); 2262 if (!radeon_encoder) 2263 return; 2264 2265 encoder = &radeon_encoder->base; 2266 switch (rdev->num_crtc) { 2267 case 1: 2268 encoder->possible_crtcs = 0x1; 2269 break; 2270 case 2: 2271 default: 2272 encoder->possible_crtcs = 0x3; 2273 break; 2274 case 4: 2275 encoder->possible_crtcs = 0xf; 2276 break; 2277 case 6: 2278 encoder->possible_crtcs = 0x3f; 2279 break; 2280 } 2281 2282 radeon_encoder->enc_priv = NULL; 2283 2284 radeon_encoder->encoder_enum = encoder_enum; 2285 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 2286 radeon_encoder->devices = supported_device; 2287 radeon_encoder->rmx_type = RMX_OFF; 2288 radeon_encoder->underscan_type = UNDERSCAN_OFF; 2289 radeon_encoder->is_ext_encoder = false; 2290 radeon_encoder->caps = caps; 2291 2292 switch (radeon_encoder->encoder_id) { 2293 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2294 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2295 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2296 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2297 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 2298 radeon_encoder->rmx_type = RMX_FULL; 2299 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); 2300 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 2301 } else { 2302 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 2303 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2304 } 2305 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 2306 break; 2307 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2308 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); 2309 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); 2310 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 2311 break; 2312 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2313 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2314 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2315 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC); 2316 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); 2317 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 2318 break; 2319 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2320 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2321 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2322 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2323 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2324 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2325 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2326 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 2327 radeon_encoder->rmx_type = RMX_FULL; 2328 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); 2329 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 2330 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 2331 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); 2332 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2333 } else { 2334 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 2335 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2336 } 2337 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 2338 break; 2339 case ENCODER_OBJECT_ID_SI170B: 2340 case ENCODER_OBJECT_ID_CH7303: 2341 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 2342 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 2343 case ENCODER_OBJECT_ID_TITFP513: 2344 case ENCODER_OBJECT_ID_VT1623: 2345 case ENCODER_OBJECT_ID_HDMI_SI1930: 2346 case ENCODER_OBJECT_ID_TRAVIS: 2347 case ENCODER_OBJECT_ID_NUTMEG: 2348 /* these are handled by the primary encoders */ 2349 radeon_encoder->is_ext_encoder = true; 2350 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 2351 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); 2352 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 2353 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); 2354 else 2355 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 2356 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs); 2357 break; 2358 } 2359 } 2360