1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright 2018 Marty E. Plummer <hanetzer@startmail.com> */ 3 /* Copyright 2019 Linaro, Ltd, Rob Herring <robh@kernel.org> */ 4 5 #ifndef __PANFROST_DEVICE_H__ 6 #define __PANFROST_DEVICE_H__ 7 8 #include <linux/atomic.h> 9 #include <linux/io-pgtable.h> 10 #include <linux/pm.h> 11 #include <linux/regulator/consumer.h> 12 #include <linux/spinlock.h> 13 #include <drm/drm_auth.h> 14 #include <drm/drm_device.h> 15 #include <drm/drm_mm.h> 16 #include <drm/gpu_scheduler.h> 17 18 #include "panfrost_devfreq.h" 19 #include "panfrost_job.h" 20 21 struct panfrost_device; 22 struct panfrost_mmu; 23 struct panfrost_job_slot; 24 struct panfrost_job; 25 struct panfrost_perfcnt; 26 27 #define MAX_PM_DOMAINS 5 28 29 enum panfrost_drv_comp_bits { 30 PANFROST_COMP_BIT_GPU, 31 PANFROST_COMP_BIT_JOB, 32 PANFROST_COMP_BIT_MMU, 33 PANFROST_COMP_BIT_MAX 34 }; 35 36 /** 37 * enum panfrost_gpu_pm - Supported kernel power management features 38 * @GPU_PM_CLK_DIS: Allow disabling clocks during system suspend 39 * @GPU_PM_VREG_OFF: Allow turning off regulators during system suspend 40 * @GPU_PM_RT: Allow disabling clocks and asserting the reset control during 41 * system runtime suspend 42 */ 43 enum panfrost_gpu_pm { 44 GPU_PM_CLK_DIS, 45 GPU_PM_VREG_OFF, 46 GPU_PM_RT 47 }; 48 49 /** 50 * enum panfrost_gpu_quirks - GPU optional quirks 51 * @GPU_QUIRK_FORCE_AARCH64_PGTABLE: Use AARCH64_4K page table format 52 */ 53 enum panfrost_gpu_quirks { 54 GPU_QUIRK_FORCE_AARCH64_PGTABLE, 55 }; 56 57 struct panfrost_features { 58 u16 id; 59 u16 revision; 60 61 u64 shader_present; 62 u64 tiler_present; 63 u64 l2_present; 64 u64 stack_present; 65 u32 as_present; 66 u32 js_present; 67 68 u32 l2_features; 69 u32 core_features; 70 u32 tiler_features; 71 u32 mem_features; 72 u32 mmu_features; 73 u32 thread_features; 74 u32 max_threads; 75 u32 thread_max_workgroup_sz; 76 u32 thread_max_barrier_sz; 77 u32 coherency_features; 78 u32 afbc_features; 79 u32 texture_features[4]; 80 u32 js_features[16]; 81 82 u32 nr_core_groups; 83 u32 thread_tls_alloc; 84 85 unsigned long hw_features[64 / BITS_PER_LONG]; 86 unsigned long hw_issues[64 / BITS_PER_LONG]; 87 }; 88 89 /* 90 * Features that cannot be automatically detected and need matching using the 91 * compatible string, typically SoC-specific. 92 */ 93 struct panfrost_compatible { 94 /* Supplies count and names. */ 95 int num_supplies; 96 const char * const *supply_names; 97 /* 98 * Number of power domains required, note that values 0 and 1 are 99 * handled identically, as only values > 1 need special handling. 100 */ 101 int num_pm_domains; 102 /* Only required if num_pm_domains > 1. */ 103 const char * const *pm_domain_names; 104 105 /* Vendor implementation quirks callback */ 106 void (*vendor_quirk)(struct panfrost_device *pfdev); 107 108 /* Allowed PM features */ 109 u8 pm_features; 110 111 /* GPU configuration quirks */ 112 u8 gpu_quirks; 113 }; 114 115 /** 116 * struct panfrost_device_debugfs - Device-wide DebugFS tracking structures 117 */ 118 struct panfrost_device_debugfs { 119 /** @gems_list: Device-wide list of GEM objects owned by at least one file. */ 120 struct list_head gems_list; 121 122 /** @gems_lock: Serializes access to the device-wide list of GEM objects. */ 123 struct mutex gems_lock; 124 }; 125 126 struct panfrost_device { 127 struct device *dev; 128 struct drm_device *ddev; 129 struct platform_device *pdev; 130 int gpu_irq; 131 int mmu_irq; 132 133 void __iomem *iomem; 134 struct clk *clock; 135 struct clk *bus_clock; 136 struct regulator_bulk_data *regulators; 137 struct reset_control *rstc; 138 /* pm_domains for devices with more than one. */ 139 struct device *pm_domain_devs[MAX_PM_DOMAINS]; 140 struct device_link *pm_domain_links[MAX_PM_DOMAINS]; 141 bool coherent; 142 143 struct panfrost_features features; 144 const struct panfrost_compatible *comp; 145 DECLARE_BITMAP(is_suspended, PANFROST_COMP_BIT_MAX); 146 147 spinlock_t as_lock; 148 unsigned long as_in_use_mask; 149 unsigned long as_alloc_mask; 150 unsigned long as_faulty_mask; 151 struct list_head as_lru_list; 152 153 struct panfrost_job_slot *js; 154 155 struct panfrost_job *jobs[NUM_JOB_SLOTS][2]; 156 struct list_head scheduled_jobs; 157 158 struct panfrost_perfcnt *perfcnt; 159 bool profile_mode; 160 161 struct mutex sched_lock; 162 163 struct { 164 struct workqueue_struct *wq; 165 struct work_struct work; 166 atomic_t pending; 167 } reset; 168 169 struct mutex shrinker_lock; 170 struct list_head shrinker_list; 171 struct shrinker *shrinker; 172 173 struct panfrost_devfreq pfdevfreq; 174 175 struct { 176 atomic_t use_count; 177 spinlock_t lock; 178 } cycle_counter; 179 180 #ifdef CONFIG_DEBUG_FS 181 struct panfrost_device_debugfs debugfs; 182 #endif 183 }; 184 185 struct panfrost_mmu { 186 struct panfrost_device *pfdev; 187 struct kref refcount; 188 struct io_pgtable_cfg pgtbl_cfg; 189 struct io_pgtable_ops *pgtbl_ops; 190 struct drm_mm mm; 191 spinlock_t mm_lock; 192 int as; 193 atomic_t as_count; 194 struct list_head list; 195 struct { 196 u64 transtab; 197 u64 memattr; 198 u64 transcfg; 199 } cfg; 200 }; 201 202 struct panfrost_engine_usage { 203 unsigned long long elapsed_ns[NUM_JOB_SLOTS]; 204 unsigned long long cycles[NUM_JOB_SLOTS]; 205 }; 206 207 struct panfrost_file_priv { 208 struct panfrost_device *pfdev; 209 210 struct xarray jm_ctxs; 211 212 struct panfrost_mmu *mmu; 213 214 struct panfrost_engine_usage engine_usage; 215 }; 216 217 static inline bool panfrost_high_prio_allowed(struct drm_file *file) 218 { 219 /* Higher priorities require CAP_SYS_NICE or DRM_MASTER */ 220 return (capable(CAP_SYS_NICE) || drm_is_current_master(file)); 221 } 222 223 static inline struct panfrost_device *to_panfrost_device(struct drm_device *ddev) 224 { 225 return ddev->dev_private; 226 } 227 228 static inline int panfrost_model_cmp(struct panfrost_device *pfdev, s32 id) 229 { 230 s32 match_id = pfdev->features.id; 231 232 if (match_id & 0xf000) 233 match_id &= 0xf00f; 234 return match_id - id; 235 } 236 237 static inline bool panfrost_model_is_bifrost(struct panfrost_device *pfdev) 238 { 239 return panfrost_model_cmp(pfdev, 0x1000) >= 0; 240 } 241 242 static inline bool panfrost_model_eq(struct panfrost_device *pfdev, s32 id) 243 { 244 return !panfrost_model_cmp(pfdev, id); 245 } 246 247 int panfrost_unstable_ioctl_check(void); 248 249 int panfrost_device_init(struct panfrost_device *pfdev); 250 void panfrost_device_fini(struct panfrost_device *pfdev); 251 void panfrost_device_reset(struct panfrost_device *pfdev); 252 253 extern const struct dev_pm_ops panfrost_pm_ops; 254 255 enum drm_panfrost_exception_type { 256 DRM_PANFROST_EXCEPTION_OK = 0x00, 257 DRM_PANFROST_EXCEPTION_DONE = 0x01, 258 DRM_PANFROST_EXCEPTION_INTERRUPTED = 0x02, 259 DRM_PANFROST_EXCEPTION_STOPPED = 0x03, 260 DRM_PANFROST_EXCEPTION_TERMINATED = 0x04, 261 DRM_PANFROST_EXCEPTION_KABOOM = 0x05, 262 DRM_PANFROST_EXCEPTION_EUREKA = 0x06, 263 DRM_PANFROST_EXCEPTION_ACTIVE = 0x08, 264 DRM_PANFROST_EXCEPTION_MAX_NON_FAULT = 0x3f, 265 DRM_PANFROST_EXCEPTION_JOB_CONFIG_FAULT = 0x40, 266 DRM_PANFROST_EXCEPTION_JOB_POWER_FAULT = 0x41, 267 DRM_PANFROST_EXCEPTION_JOB_READ_FAULT = 0x42, 268 DRM_PANFROST_EXCEPTION_JOB_WRITE_FAULT = 0x43, 269 DRM_PANFROST_EXCEPTION_JOB_AFFINITY_FAULT = 0x44, 270 DRM_PANFROST_EXCEPTION_JOB_BUS_FAULT = 0x48, 271 DRM_PANFROST_EXCEPTION_INSTR_INVALID_PC = 0x50, 272 DRM_PANFROST_EXCEPTION_INSTR_INVALID_ENC = 0x51, 273 DRM_PANFROST_EXCEPTION_INSTR_TYPE_MISMATCH = 0x52, 274 DRM_PANFROST_EXCEPTION_INSTR_OPERAND_FAULT = 0x53, 275 DRM_PANFROST_EXCEPTION_INSTR_TLS_FAULT = 0x54, 276 DRM_PANFROST_EXCEPTION_INSTR_BARRIER_FAULT = 0x55, 277 DRM_PANFROST_EXCEPTION_INSTR_ALIGN_FAULT = 0x56, 278 DRM_PANFROST_EXCEPTION_DATA_INVALID_FAULT = 0x58, 279 DRM_PANFROST_EXCEPTION_TILE_RANGE_FAULT = 0x59, 280 DRM_PANFROST_EXCEPTION_ADDR_RANGE_FAULT = 0x5a, 281 DRM_PANFROST_EXCEPTION_IMPRECISE_FAULT = 0x5b, 282 DRM_PANFROST_EXCEPTION_OOM = 0x60, 283 DRM_PANFROST_EXCEPTION_OOM_AFBC = 0x61, 284 DRM_PANFROST_EXCEPTION_UNKNOWN = 0x7f, 285 DRM_PANFROST_EXCEPTION_DELAYED_BUS_FAULT = 0x80, 286 DRM_PANFROST_EXCEPTION_GPU_SHAREABILITY_FAULT = 0x88, 287 DRM_PANFROST_EXCEPTION_SYS_SHAREABILITY_FAULT = 0x89, 288 DRM_PANFROST_EXCEPTION_GPU_CACHEABILITY_FAULT = 0x8a, 289 DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_0 = 0xc0, 290 DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_1 = 0xc1, 291 DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_2 = 0xc2, 292 DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_3 = 0xc3, 293 DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_4 = 0xc4, 294 DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_IDENTITY = 0xc7, 295 DRM_PANFROST_EXCEPTION_PERM_FAULT_0 = 0xc8, 296 DRM_PANFROST_EXCEPTION_PERM_FAULT_1 = 0xc9, 297 DRM_PANFROST_EXCEPTION_PERM_FAULT_2 = 0xca, 298 DRM_PANFROST_EXCEPTION_PERM_FAULT_3 = 0xcb, 299 DRM_PANFROST_EXCEPTION_TRANSTAB_BUS_FAULT_0 = 0xd0, 300 DRM_PANFROST_EXCEPTION_TRANSTAB_BUS_FAULT_1 = 0xd1, 301 DRM_PANFROST_EXCEPTION_TRANSTAB_BUS_FAULT_2 = 0xd2, 302 DRM_PANFROST_EXCEPTION_TRANSTAB_BUS_FAULT_3 = 0xd3, 303 DRM_PANFROST_EXCEPTION_ACCESS_FLAG_0 = 0xd8, 304 DRM_PANFROST_EXCEPTION_ACCESS_FLAG_1 = 0xd9, 305 DRM_PANFROST_EXCEPTION_ACCESS_FLAG_2 = 0xda, 306 DRM_PANFROST_EXCEPTION_ACCESS_FLAG_3 = 0xdb, 307 DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_IN0 = 0xe0, 308 DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_IN1 = 0xe1, 309 DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_IN2 = 0xe2, 310 DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_IN3 = 0xe3, 311 DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_OUT0 = 0xe4, 312 DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_OUT1 = 0xe5, 313 DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_OUT2 = 0xe6, 314 DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_OUT3 = 0xe7, 315 DRM_PANFROST_EXCEPTION_MEM_ATTR_FAULT_0 = 0xe8, 316 DRM_PANFROST_EXCEPTION_MEM_ATTR_FAULT_1 = 0xe9, 317 DRM_PANFROST_EXCEPTION_MEM_ATTR_FAULT_2 = 0xea, 318 DRM_PANFROST_EXCEPTION_MEM_ATTR_FAULT_3 = 0xeb, 319 DRM_PANFROST_EXCEPTION_MEM_ATTR_NONCACHE_0 = 0xec, 320 DRM_PANFROST_EXCEPTION_MEM_ATTR_NONCACHE_1 = 0xed, 321 DRM_PANFROST_EXCEPTION_MEM_ATTR_NONCACHE_2 = 0xee, 322 DRM_PANFROST_EXCEPTION_MEM_ATTR_NONCACHE_3 = 0xef, 323 }; 324 325 static inline bool 326 panfrost_exception_is_fault(u32 exception_code) 327 { 328 return exception_code > DRM_PANFROST_EXCEPTION_MAX_NON_FAULT; 329 } 330 331 const char *panfrost_exception_name(u32 exception_code); 332 bool panfrost_exception_needs_reset(const struct panfrost_device *pfdev, 333 u32 exception_code); 334 335 static inline void 336 panfrost_device_schedule_reset(struct panfrost_device *pfdev) 337 { 338 atomic_set(&pfdev->reset.pending, 1); 339 queue_work(pfdev->reset.wq, &pfdev->reset.work); 340 } 341 342 #endif 343