1*b7019ac5SIlia Mirkin /* SPDX-License-Identifier: MIT */ 2c39f472eSBen Skeggs #ifndef __NVBIOS_M0203_H__ 3c39f472eSBen Skeggs #define __NVBIOS_M0203_H__ 4c39f472eSBen Skeggs struct nvbios_M0203T { 5c39f472eSBen Skeggs #define M0203T_TYPE_RAMCFG 0x00 6c39f472eSBen Skeggs u8 type; 7c39f472eSBen Skeggs u16 pointer; 8c39f472eSBen Skeggs }; 9c39f472eSBen Skeggs 10d390b480SBen Skeggs u32 nvbios_M0203Te(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len); 11d390b480SBen Skeggs u32 nvbios_M0203Tp(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, 12c39f472eSBen Skeggs struct nvbios_M0203T *); 13c39f472eSBen Skeggs 14c39f472eSBen Skeggs struct nvbios_M0203E { 15c39f472eSBen Skeggs #define M0203E_TYPE_DDR2 0x0 16c39f472eSBen Skeggs #define M0203E_TYPE_DDR3 0x1 17c39f472eSBen Skeggs #define M0203E_TYPE_GDDR3 0x2 18c39f472eSBen Skeggs #define M0203E_TYPE_GDDR5 0x3 192d5257b7SBen Skeggs #define M0203E_TYPE_HBM2 0x6 202d5257b7SBen Skeggs #define M0203E_TYPE_GDDR5X 0x8 212d5257b7SBen Skeggs #define M0203E_TYPE_GDDR6 0x9 22c39f472eSBen Skeggs #define M0203E_TYPE_SKIP 0xf 23c39f472eSBen Skeggs u8 type; 24c39f472eSBen Skeggs u8 strap; 25c39f472eSBen Skeggs u8 group; 26c39f472eSBen Skeggs }; 27c39f472eSBen Skeggs 28d390b480SBen Skeggs u32 nvbios_M0203Ee(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr); 29d390b480SBen Skeggs u32 nvbios_M0203Ep(struct nvkm_bios *, int idx, u8 *ver, u8 *hdr, 30c39f472eSBen Skeggs struct nvbios_M0203E *); 31d390b480SBen Skeggs u32 nvbios_M0203Em(struct nvkm_bios *, u8 ramcfg, u8 *ver, u8 *hdr, 32c39f472eSBen Skeggs struct nvbios_M0203E *); 33c39f472eSBen Skeggs #endif 34