1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #ifndef __MSM_DRV_H__ 9 #define __MSM_DRV_H__ 10 11 #include <linux/kernel.h> 12 #include <linux/clk.h> 13 #include <linux/cpufreq.h> 14 #include <linux/devfreq.h> 15 #include <linux/module.h> 16 #include <linux/component.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/slab.h> 21 #include <linux/list.h> 22 #include <linux/iommu.h> 23 #include <linux/types.h> 24 #include <linux/of_graph.h> 25 #include <linux/of_device.h> 26 #include <linux/sizes.h> 27 #include <linux/kthread.h> 28 29 #include <drm/drm_atomic.h> 30 #include <drm/drm_atomic_helper.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/display/drm_dsc.h> 33 #include <drm/msm_drm.h> 34 #include <drm/drm_gem.h> 35 36 extern struct fault_attr fail_gem_alloc; 37 extern struct fault_attr fail_gem_iova; 38 39 struct drm_fb_helper; 40 struct drm_fb_helper_surface_size; 41 42 struct msm_kms; 43 struct msm_gpu; 44 struct msm_mmu; 45 struct msm_mdss; 46 struct msm_rd_state; 47 struct msm_perf_state; 48 struct msm_gem_submit; 49 struct msm_fence_context; 50 struct msm_gem_address_space; 51 struct msm_gem_vma; 52 struct msm_disp_state; 53 54 #define MAX_CRTCS 8 55 #define MAX_BRIDGES 8 56 57 #define FRAC_16_16(mult, div) (((mult) << 16) / (div)) 58 59 enum msm_dp_controller { 60 MSM_DP_CONTROLLER_0, 61 MSM_DP_CONTROLLER_1, 62 MSM_DP_CONTROLLER_2, 63 MSM_DP_CONTROLLER_3, 64 MSM_DP_CONTROLLER_COUNT, 65 }; 66 67 enum msm_dsi_controller { 68 MSM_DSI_CONTROLLER_0, 69 MSM_DSI_CONTROLLER_1, 70 MSM_DSI_CONTROLLER_COUNT, 71 }; 72 73 #define MSM_GPU_MAX_RINGS 4 74 #define MAX_H_TILES_PER_DISPLAY 2 75 76 /** 77 * struct msm_display_topology - defines a display topology pipeline 78 * @num_lm: number of layer mixers used 79 * @num_intf: number of interfaces the panel is mounted on 80 * @num_dspp: number of dspp blocks used 81 * @num_dsc: number of Display Stream Compression (DSC) blocks used 82 * @needs_cdm: indicates whether cdm block is needed for this display topology 83 */ 84 struct msm_display_topology { 85 u32 num_lm; 86 u32 num_intf; 87 u32 num_dspp; 88 u32 num_dsc; 89 bool needs_cdm; 90 }; 91 92 /* Commit/Event thread specific structure */ 93 struct msm_drm_thread { 94 struct drm_device *dev; 95 struct kthread_worker *worker; 96 }; 97 98 struct msm_drm_private { 99 100 struct drm_device *dev; 101 102 struct msm_kms *kms; 103 int (*kms_init)(struct drm_device *dev); 104 105 /* subordinate devices, if present: */ 106 struct platform_device *gpu_pdev; 107 108 /* possibly this should be in the kms component, but it is 109 * shared by both mdp4 and mdp5.. 110 */ 111 struct hdmi *hdmi; 112 113 /* DSI is shared by mdp4 and mdp5 */ 114 struct msm_dsi *dsi[MSM_DSI_CONTROLLER_COUNT]; 115 116 struct msm_dp *dp[MSM_DP_CONTROLLER_COUNT]; 117 118 /* when we have more than one 'msm_gpu' these need to be an array: */ 119 struct msm_gpu *gpu; 120 121 /* gpu is only set on open(), but we need this info earlier */ 122 bool is_a2xx; 123 bool has_cached_coherent; 124 125 struct msm_rd_state *rd; /* debugfs to dump all submits */ 126 struct msm_rd_state *hangrd; /* debugfs to dump hanging submits */ 127 struct msm_perf_state *perf; 128 129 /** 130 * total_mem: Total/global amount of memory backing GEM objects. 131 */ 132 atomic64_t total_mem; 133 134 /** 135 * List of all GEM objects (mainly for debugfs, protected by obj_lock 136 * (acquire before per GEM object lock) 137 */ 138 struct list_head objects; 139 struct mutex obj_lock; 140 141 /** 142 * lru: 143 * 144 * The various LRU's that a GEM object is in at various stages of 145 * it's lifetime. Objects start out in the unbacked LRU. When 146 * pinned (for scannout or permanently mapped GPU buffers, like 147 * ringbuffer, memptr, fw, etc) it moves to the pinned LRU. When 148 * unpinned, it moves into willneed or dontneed LRU depending on 149 * madvise state. When backing pages are evicted (willneed) or 150 * purged (dontneed) it moves back into the unbacked LRU. 151 * 152 * The dontneed LRU is considered by the shrinker for objects 153 * that are candidate for purging, and the willneed LRU is 154 * considered for objects that could be evicted. 155 */ 156 struct { 157 /** 158 * unbacked: 159 * 160 * The LRU for GEM objects without backing pages allocated. 161 * This mostly exists so that objects are always is one 162 * LRU. 163 */ 164 struct drm_gem_lru unbacked; 165 166 /** 167 * pinned: 168 * 169 * The LRU for pinned GEM objects 170 */ 171 struct drm_gem_lru pinned; 172 173 /** 174 * willneed: 175 * 176 * The LRU for unpinned GEM objects which are in madvise 177 * WILLNEED state (ie. can be evicted) 178 */ 179 struct drm_gem_lru willneed; 180 181 /** 182 * dontneed: 183 * 184 * The LRU for unpinned GEM objects which are in madvise 185 * DONTNEED state (ie. can be purged) 186 */ 187 struct drm_gem_lru dontneed; 188 189 /** 190 * lock: 191 * 192 * Protects manipulation of all of the LRUs. 193 */ 194 struct mutex lock; 195 } lru; 196 197 struct workqueue_struct *wq; 198 199 unsigned int num_crtcs; 200 201 struct msm_drm_thread event_thread[MAX_CRTCS]; 202 203 /* VRAM carveout, used when no IOMMU: */ 204 struct { 205 unsigned long size; 206 dma_addr_t paddr; 207 /* NOTE: mm managed at the page level, size is in # of pages 208 * and position mm_node->start is in # of pages: 209 */ 210 struct drm_mm mm; 211 spinlock_t lock; /* Protects drm_mm node allocation/removal */ 212 } vram; 213 214 struct notifier_block vmap_notifier; 215 struct shrinker *shrinker; 216 217 /** 218 * hangcheck_period: For hang detection, in ms 219 * 220 * Note that in practice, a submit/job will get at least two hangcheck 221 * periods, due to checking for progress being implemented as simply 222 * "have the CP position registers changed since last time?" 223 */ 224 unsigned int hangcheck_period; 225 226 /** gpu_devfreq_config: Devfreq tuning config for the GPU. */ 227 struct devfreq_simple_ondemand_data gpu_devfreq_config; 228 229 /** 230 * gpu_clamp_to_idle: Enable clamping to idle freq when inactive 231 */ 232 bool gpu_clamp_to_idle; 233 234 /** 235 * disable_err_irq: 236 * 237 * Disable handling of GPU hw error interrupts, to force fallback to 238 * sw hangcheck timer. Written (via debugfs) by igt tests to test 239 * the sw hangcheck mechanism. 240 */ 241 bool disable_err_irq; 242 }; 243 244 const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format, uint64_t modifier); 245 246 struct msm_pending_timer; 247 248 int msm_atomic_init_pending_timer(struct msm_pending_timer *timer, 249 struct msm_kms *kms, int crtc_idx); 250 void msm_atomic_destroy_pending_timer(struct msm_pending_timer *timer); 251 void msm_atomic_commit_tail(struct drm_atomic_state *state); 252 int msm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state); 253 struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev); 254 255 int msm_crtc_enable_vblank(struct drm_crtc *crtc); 256 void msm_crtc_disable_vblank(struct drm_crtc *crtc); 257 258 int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu); 259 void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu); 260 261 struct msm_gem_address_space *msm_kms_init_aspace(struct drm_device *dev); 262 bool msm_use_mmu(struct drm_device *dev); 263 264 int msm_ioctl_gem_submit(struct drm_device *dev, void *data, 265 struct drm_file *file); 266 267 #ifdef CONFIG_DEBUG_FS 268 unsigned long msm_gem_shrinker_shrink(struct drm_device *dev, unsigned long nr_to_scan); 269 #endif 270 271 int msm_gem_shrinker_init(struct drm_device *dev); 272 void msm_gem_shrinker_cleanup(struct drm_device *dev); 273 274 struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj); 275 int msm_gem_prime_vmap(struct drm_gem_object *obj, struct iosys_map *map); 276 void msm_gem_prime_vunmap(struct drm_gem_object *obj, struct iosys_map *map); 277 struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev, 278 struct dma_buf_attachment *attach, struct sg_table *sg); 279 int msm_gem_prime_pin(struct drm_gem_object *obj); 280 void msm_gem_prime_unpin(struct drm_gem_object *obj); 281 282 int msm_framebuffer_prepare(struct drm_framebuffer *fb, 283 struct msm_gem_address_space *aspace, bool needs_dirtyfb); 284 void msm_framebuffer_cleanup(struct drm_framebuffer *fb, 285 struct msm_gem_address_space *aspace, bool needed_dirtyfb); 286 uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, 287 struct msm_gem_address_space *aspace, int plane); 288 struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane); 289 const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb); 290 struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev, 291 struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd); 292 struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev, 293 int w, int h, int p, uint32_t format); 294 295 #ifdef CONFIG_DRM_FBDEV_EMULATION 296 int msm_fbdev_driver_fbdev_probe(struct drm_fb_helper *helper, 297 struct drm_fb_helper_surface_size *sizes); 298 #define MSM_FBDEV_DRIVER_OPS \ 299 .fbdev_probe = msm_fbdev_driver_fbdev_probe 300 #else 301 #define MSM_FBDEV_DRIVER_OPS \ 302 .fbdev_probe = NULL 303 #endif 304 305 struct hdmi; 306 #ifdef CONFIG_DRM_MSM_HDMI 307 int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev, 308 struct drm_encoder *encoder); 309 void __init msm_hdmi_register(void); 310 void __exit msm_hdmi_unregister(void); 311 #else 312 static inline int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev, 313 struct drm_encoder *encoder) 314 { 315 return -EINVAL; 316 } 317 static inline void __init msm_hdmi_register(void) {} 318 static inline void __exit msm_hdmi_unregister(void) {} 319 #endif 320 321 struct msm_dsi; 322 #ifdef CONFIG_DRM_MSM_DSI 323 int dsi_dev_attach(struct platform_device *pdev); 324 void dsi_dev_detach(struct platform_device *pdev); 325 void __init msm_dsi_register(void); 326 void __exit msm_dsi_unregister(void); 327 int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev, 328 struct drm_encoder *encoder); 329 void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi); 330 bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi); 331 bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi); 332 bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi); 333 bool msm_dsi_wide_bus_enabled(struct msm_dsi *msm_dsi); 334 struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi); 335 const char *msm_dsi_get_te_source(struct msm_dsi *msm_dsi); 336 #else 337 static inline void __init msm_dsi_register(void) 338 { 339 } 340 static inline void __exit msm_dsi_unregister(void) 341 { 342 } 343 static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, 344 struct drm_device *dev, 345 struct drm_encoder *encoder) 346 { 347 return -EINVAL; 348 } 349 static inline void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi) 350 { 351 } 352 static inline bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi) 353 { 354 return false; 355 } 356 static inline bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi) 357 { 358 return false; 359 } 360 static inline bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi) 361 { 362 return false; 363 } 364 static inline bool msm_dsi_wide_bus_enabled(struct msm_dsi *msm_dsi) 365 { 366 return false; 367 } 368 369 static inline struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi) 370 { 371 return NULL; 372 } 373 374 static inline const char *msm_dsi_get_te_source(struct msm_dsi *msm_dsi) 375 { 376 return NULL; 377 } 378 #endif 379 380 #ifdef CONFIG_DRM_MSM_DP 381 int __init msm_dp_register(void); 382 void __exit msm_dp_unregister(void); 383 int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev, 384 struct drm_encoder *encoder, bool yuv_supported); 385 void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display); 386 bool msm_dp_is_yuv_420_enabled(const struct msm_dp *dp_display, 387 const struct drm_display_mode *mode); 388 bool msm_dp_needs_periph_flush(const struct msm_dp *dp_display, 389 const struct drm_display_mode *mode); 390 bool msm_dp_wide_bus_available(const struct msm_dp *dp_display); 391 392 #else 393 static inline int __init msm_dp_register(void) 394 { 395 return -EINVAL; 396 } 397 static inline void __exit msm_dp_unregister(void) 398 { 399 } 400 static inline int msm_dp_modeset_init(struct msm_dp *dp_display, 401 struct drm_device *dev, 402 struct drm_encoder *encoder, 403 bool yuv_supported) 404 { 405 return -EINVAL; 406 } 407 408 static inline void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display) 409 { 410 } 411 412 static inline bool msm_dp_is_yuv_420_enabled(const struct msm_dp *dp_display, 413 const struct drm_display_mode *mode) 414 { 415 return false; 416 } 417 418 static inline bool msm_dp_needs_periph_flush(const struct msm_dp *dp_display, 419 const struct drm_display_mode *mode) 420 { 421 return false; 422 } 423 424 static inline bool msm_dp_wide_bus_available(const struct msm_dp *dp_display) 425 { 426 return false; 427 } 428 429 #endif 430 431 #ifdef CONFIG_DRM_MSM_MDP4 432 void msm_mdp4_register(void); 433 void msm_mdp4_unregister(void); 434 #else 435 static inline void msm_mdp4_register(void) {} 436 static inline void msm_mdp4_unregister(void) {} 437 #endif 438 439 #ifdef CONFIG_DRM_MSM_MDP5 440 void msm_mdp_register(void); 441 void msm_mdp_unregister(void); 442 #else 443 static inline void msm_mdp_register(void) {} 444 static inline void msm_mdp_unregister(void) {} 445 #endif 446 447 #ifdef CONFIG_DRM_MSM_DPU 448 void msm_dpu_register(void); 449 void msm_dpu_unregister(void); 450 #else 451 static inline void msm_dpu_register(void) {} 452 static inline void msm_dpu_unregister(void) {} 453 #endif 454 455 #ifdef CONFIG_DRM_MSM_MDSS 456 void msm_mdss_register(void); 457 void msm_mdss_unregister(void); 458 #else 459 static inline void msm_mdss_register(void) {} 460 static inline void msm_mdss_unregister(void) {} 461 #endif 462 463 #ifdef CONFIG_DEBUG_FS 464 void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m); 465 int msm_debugfs_late_init(struct drm_device *dev); 466 int msm_rd_debugfs_init(struct drm_minor *minor); 467 void msm_rd_debugfs_cleanup(struct msm_drm_private *priv); 468 __printf(3, 4) 469 void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit, 470 const char *fmt, ...); 471 int msm_perf_debugfs_init(struct drm_minor *minor); 472 void msm_perf_debugfs_cleanup(struct msm_drm_private *priv); 473 #else 474 static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; } 475 __printf(3, 4) 476 static inline void msm_rd_dump_submit(struct msm_rd_state *rd, 477 struct msm_gem_submit *submit, 478 const char *fmt, ...) {} 479 static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {} 480 static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {} 481 #endif 482 483 struct clk *msm_clk_get(struct platform_device *pdev, const char *name); 484 485 struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count, 486 const char *name); 487 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name); 488 void __iomem *msm_ioremap_size(struct platform_device *pdev, const char *name, 489 phys_addr_t *size); 490 void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name); 491 void __iomem *msm_ioremap_mdss(struct platform_device *mdss_pdev, 492 struct platform_device *dev, 493 const char *name); 494 495 struct icc_path *msm_icc_get(struct device *dev, const char *name); 496 497 static inline void msm_rmw(void __iomem *addr, u32 mask, u32 or) 498 { 499 u32 val = readl(addr); 500 501 val &= ~mask; 502 writel(val | or, addr); 503 } 504 505 /** 506 * struct msm_hrtimer_work - a helper to combine an hrtimer with kthread_work 507 * 508 * @timer: hrtimer to control when the kthread work is triggered 509 * @work: the kthread work 510 * @worker: the kthread worker the work will be scheduled on 511 */ 512 struct msm_hrtimer_work { 513 struct hrtimer timer; 514 struct kthread_work work; 515 struct kthread_worker *worker; 516 }; 517 518 void msm_hrtimer_queue_work(struct msm_hrtimer_work *work, 519 ktime_t wakeup_time, 520 enum hrtimer_mode mode); 521 void msm_hrtimer_work_init(struct msm_hrtimer_work *work, 522 struct kthread_worker *worker, 523 kthread_work_func_t fn, 524 clockid_t clock_id, 525 enum hrtimer_mode mode); 526 527 #define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) 528 #define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) 529 530 static inline int align_pitch(int width, int bpp) 531 { 532 int bytespp = (bpp + 7) / 8; 533 /* adreno needs pitch aligned to 32 pixels: */ 534 return bytespp * ALIGN(width, 32); 535 } 536 537 /* for the generated headers: */ 538 #define INVALID_IDX(idx) ({BUG(); 0;}) 539 #define fui(x) ({BUG(); 0;}) 540 #define _mesa_float_to_half(x) ({BUG(); 0;}) 541 542 543 #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT) 544 545 /* for conditionally setting boolean flag(s): */ 546 #define COND(bool, val) ((bool) ? (val) : 0) 547 548 static inline unsigned long timeout_to_jiffies(const ktime_t *timeout) 549 { 550 ktime_t now = ktime_get(); 551 s64 remaining_jiffies; 552 553 if (ktime_compare(*timeout, now) < 0) { 554 remaining_jiffies = 0; 555 } else { 556 ktime_t rem = ktime_sub(*timeout, now); 557 remaining_jiffies = ktime_divns(rem, NSEC_PER_SEC / HZ); 558 } 559 560 return clamp(remaining_jiffies, 1LL, (s64)INT_MAX); 561 } 562 563 /* Driver helpers */ 564 565 extern const struct component_master_ops msm_drm_ops; 566 567 int msm_kms_pm_prepare(struct device *dev); 568 void msm_kms_pm_complete(struct device *dev); 569 570 int msm_drv_probe(struct device *dev, 571 int (*kms_init)(struct drm_device *dev), 572 struct msm_kms *kms); 573 void msm_kms_shutdown(struct platform_device *pdev); 574 575 bool msm_disp_drv_should_bind(struct device *dev, bool dpu_driver); 576 577 #endif /* __MSM_DRV_H__ */ 578