197fb5e8dSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 291143873SJessica Zhang /* 33313c23fSJessica Zhang * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. 491143873SJessica Zhang * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 525fdd593SJeykumar Sankaran */ 625fdd593SJeykumar Sankaran 725fdd593SJeykumar Sankaran #ifndef _DPU_HW_INTF_H 825fdd593SJeykumar Sankaran #define _DPU_HW_INTF_H 925fdd593SJeykumar Sankaran 1025fdd593SJeykumar Sankaran #include "dpu_hw_catalog.h" 1125fdd593SJeykumar Sankaran #include "dpu_hw_mdss.h" 1225fdd593SJeykumar Sankaran #include "dpu_hw_util.h" 1325fdd593SJeykumar Sankaran 1425fdd593SJeykumar Sankaran struct dpu_hw_intf; 1525fdd593SJeykumar Sankaran 1625fdd593SJeykumar Sankaran /* intf timing settings */ 174c6df9a4SAbhinav Kumar struct dpu_hw_intf_timing_params { 1825fdd593SJeykumar Sankaran u32 width; /* active width */ 1925fdd593SJeykumar Sankaran u32 height; /* active height */ 2025fdd593SJeykumar Sankaran u32 xres; /* Display panel width */ 2125fdd593SJeykumar Sankaran u32 yres; /* Display panel height */ 2225fdd593SJeykumar Sankaran 2325fdd593SJeykumar Sankaran u32 h_back_porch; 2425fdd593SJeykumar Sankaran u32 h_front_porch; 2525fdd593SJeykumar Sankaran u32 v_back_porch; 2625fdd593SJeykumar Sankaran u32 v_front_porch; 2725fdd593SJeykumar Sankaran u32 hsync_pulse_width; 2825fdd593SJeykumar Sankaran u32 vsync_pulse_width; 2925fdd593SJeykumar Sankaran u32 hsync_polarity; 3025fdd593SJeykumar Sankaran u32 vsync_polarity; 3125fdd593SJeykumar Sankaran u32 border_clr; 3225fdd593SJeykumar Sankaran u32 underflow_clr; 3325fdd593SJeykumar Sankaran u32 hsync_skew; 343309a756SKuogee Hsieh 353309a756SKuogee Hsieh bool wide_bus_en; 362f4a67a3SAbhinav Kumar bool compression_en; 3725fdd593SJeykumar Sankaran }; 3825fdd593SJeykumar Sankaran 394c6df9a4SAbhinav Kumar struct dpu_hw_intf_prog_fetch { 4025fdd593SJeykumar Sankaran u8 enable; 4125fdd593SJeykumar Sankaran /* vsync counter for the front porch pixel line */ 4225fdd593SJeykumar Sankaran u32 fetch_start; 4325fdd593SJeykumar Sankaran }; 4425fdd593SJeykumar Sankaran 454c6df9a4SAbhinav Kumar struct dpu_hw_intf_status { 4625fdd593SJeykumar Sankaran u8 is_en; /* interface timing engine is enabled or not */ 4773743e72SKalyan Thota u8 is_prog_fetch_en; /* interface prog fetch counter is enabled or not */ 4825fdd593SJeykumar Sankaran u32 frame_count; /* frame count since timing engine enabled */ 4925fdd593SJeykumar Sankaran u32 line_count; /* current line count including blanking */ 5025fdd593SJeykumar Sankaran }; 5125fdd593SJeykumar Sankaran 52143dfccaSAbhinav Kumar struct dpu_hw_intf_cmd_mode_cfg { 53143dfccaSAbhinav Kumar u8 data_compress; /* enable data compress between dpu and dsi */ 5497f038dbSJessica Zhang u8 wide_bus_en; /* enable databus widen mode */ 55143dfccaSAbhinav Kumar }; 56143dfccaSAbhinav Kumar 5725fdd593SJeykumar Sankaran /** 5825fdd593SJeykumar Sankaran * struct dpu_hw_intf_ops : Interface to the interface Hw driver functions 5925fdd593SJeykumar Sankaran * Assumption is these functions will be called after clocks are enabled 6025fdd593SJeykumar Sankaran * @ setup_timing_gen : programs the timing engine 6125fdd593SJeykumar Sankaran * @ setup_prog_fetch : enables/disables the programmable fetch logic 6225fdd593SJeykumar Sankaran * @ enable_timing: enable/disable timing engine 6325fdd593SJeykumar Sankaran * @ get_status: returns if timing engine is enabled or not 6425fdd593SJeykumar Sankaran * @ get_line_count: reads current vertical line counter 6573bfb790SKalyan Thota * @bind_pingpong_blk: enable/disable the connection with pingpong which will 6673bfb790SKalyan Thota * feed pixels to this interface 6791143873SJessica Zhang * @setup_misr: enable/disable MISR 6891143873SJessica Zhang * @collect_misr: read MISR signature 69e955a3f0SMarijn Suijten * @enable_tearcheck: Enables vsync generation and sets up init value of read 70e955a3f0SMarijn Suijten * pointer and programs the tear check configuration 71e955a3f0SMarijn Suijten * @disable_tearcheck: Disables tearcheck block 72e955a3f0SMarijn Suijten * @connect_external_te: Read, modify, write to either set or clear listening to external TE 73e955a3f0SMarijn Suijten * Return: 1 if TE was originally connected, 0 if not, or -ERROR 74e955a3f0SMarijn Suijten * @get_vsync_info: Provides the programmed and current line_count 75e955a3f0SMarijn Suijten * @setup_autorefresh: Configure and enable the autorefresh config 76e955a3f0SMarijn Suijten * @get_autorefresh: Retrieve autorefresh config from hardware 77e955a3f0SMarijn Suijten * Return: 0 on success, -ETIMEDOUT on timeout 78e955a3f0SMarijn Suijten * @vsync_sel: Select vsync signal for tear-effect configuration 79143dfccaSAbhinav Kumar * @program_intf_cmd_cfg: Program the DPU to interface datapath for command mode 8025fdd593SJeykumar Sankaran */ 8125fdd593SJeykumar Sankaran struct dpu_hw_intf_ops { 8225fdd593SJeykumar Sankaran void (*setup_timing_gen)(struct dpu_hw_intf *intf, 834c6df9a4SAbhinav Kumar const struct dpu_hw_intf_timing_params *p, 8406355723SJun Nie const struct msm_format *fmt, 8506355723SJun Nie const struct dpu_mdss_version *mdss_ver); 8625fdd593SJeykumar Sankaran 8725fdd593SJeykumar Sankaran void (*setup_prg_fetch)(struct dpu_hw_intf *intf, 884c6df9a4SAbhinav Kumar const struct dpu_hw_intf_prog_fetch *fetch); 8925fdd593SJeykumar Sankaran 9025fdd593SJeykumar Sankaran void (*enable_timing)(struct dpu_hw_intf *intf, 9125fdd593SJeykumar Sankaran u8 enable); 9225fdd593SJeykumar Sankaran 9325fdd593SJeykumar Sankaran void (*get_status)(struct dpu_hw_intf *intf, 944c6df9a4SAbhinav Kumar struct dpu_hw_intf_status *status); 9525fdd593SJeykumar Sankaran 9625fdd593SJeykumar Sankaran u32 (*get_line_count)(struct dpu_hw_intf *intf); 9773bfb790SKalyan Thota 9873bfb790SKalyan Thota void (*bind_pingpong_blk)(struct dpu_hw_intf *intf, 9973bfb790SKalyan Thota const enum dpu_pingpong pp); 1003313c23fSJessica Zhang void (*setup_misr)(struct dpu_hw_intf *intf); 10191143873SJessica Zhang int (*collect_misr)(struct dpu_hw_intf *intf, u32 *misr_value); 102e955a3f0SMarijn Suijten 103e955a3f0SMarijn Suijten // Tearcheck on INTF since DPU 5.0.0 104e955a3f0SMarijn Suijten 105e955a3f0SMarijn Suijten int (*enable_tearcheck)(struct dpu_hw_intf *intf, struct dpu_hw_tear_check *cfg); 106e955a3f0SMarijn Suijten 107e955a3f0SMarijn Suijten int (*disable_tearcheck)(struct dpu_hw_intf *intf); 108e955a3f0SMarijn Suijten 109e955a3f0SMarijn Suijten int (*connect_external_te)(struct dpu_hw_intf *intf, bool enable_external_te); 110e955a3f0SMarijn Suijten 111*548eb2bcSDmitry Baryshkov void (*vsync_sel)(struct dpu_hw_intf *intf, enum dpu_vsync_source vsync_source); 112e955a3f0SMarijn Suijten 113e955a3f0SMarijn Suijten /** 114e955a3f0SMarijn Suijten * Disable autorefresh if enabled 115e955a3f0SMarijn Suijten */ 116e955a3f0SMarijn Suijten void (*disable_autorefresh)(struct dpu_hw_intf *intf, uint32_t encoder_id, u16 vdisplay); 1171642b580SJessica Zhang 118143dfccaSAbhinav Kumar void (*program_intf_cmd_cfg)(struct dpu_hw_intf *intf, 119143dfccaSAbhinav Kumar struct dpu_hw_intf_cmd_mode_cfg *cmd_mode_cfg); 12025fdd593SJeykumar Sankaran }; 12125fdd593SJeykumar Sankaran 12225fdd593SJeykumar Sankaran struct dpu_hw_intf { 12325fdd593SJeykumar Sankaran struct dpu_hw_blk_reg_map hw; 12425fdd593SJeykumar Sankaran 12525fdd593SJeykumar Sankaran /* intf */ 12625fdd593SJeykumar Sankaran enum dpu_intf idx; 12725fdd593SJeykumar Sankaran const struct dpu_intf_cfg *cap; 12825fdd593SJeykumar Sankaran 12925fdd593SJeykumar Sankaran /* ops */ 13025fdd593SJeykumar Sankaran struct dpu_hw_intf_ops ops; 13125fdd593SJeykumar Sankaran }; 13225fdd593SJeykumar Sankaran 13325fdd593SJeykumar Sankaran /** 134babdb815SMarijn Suijten * dpu_hw_intf_init() - Initializes the INTF driver for the passed 135babdb815SMarijn Suijten * interface catalog entry. 136a106ed98SDmitry Baryshkov * @dev: Corresponding device for devres management 137babdb815SMarijn Suijten * @cfg: interface catalog entry for which driver object is required 13825fdd593SJeykumar Sankaran * @addr: mapped register io address of MDP 13951e9b25cSAbhinav Kumar * @mdss_rev: dpu core's major and minor versions 14025fdd593SJeykumar Sankaran */ 141a106ed98SDmitry Baryshkov struct dpu_hw_intf *dpu_hw_intf_init(struct drm_device *dev, 142a106ed98SDmitry Baryshkov const struct dpu_intf_cfg *cfg, 143a106ed98SDmitry Baryshkov void __iomem *addr, 144a106ed98SDmitry Baryshkov const struct dpu_mdss_version *mdss_rev); 14525fdd593SJeykumar Sankaran 14625fdd593SJeykumar Sankaran #endif /*_DPU_HW_INTF_H */ 147