1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #ifndef _I915_DRV_H_ 31 #define _I915_DRV_H_ 32 33 #include "i915_reg.h" 34 #include "intel_bios.h" 35 #include "intel_ringbuffer.h" 36 #include <linux/io-mapping.h> 37 #include <linux/i2c.h> 38 #include <drm/intel-gtt.h> 39 #include <linux/backlight.h> 40 41 /* General customization: 42 */ 43 44 #define DRIVER_AUTHOR "Tungsten Graphics, Inc." 45 46 #define DRIVER_NAME "i915" 47 #define DRIVER_DESC "Intel Graphics" 48 #define DRIVER_DATE "20080730" 49 50 enum pipe { 51 PIPE_A = 0, 52 PIPE_B, 53 PIPE_C, 54 I915_MAX_PIPES 55 }; 56 #define pipe_name(p) ((p) + 'A') 57 58 enum plane { 59 PLANE_A = 0, 60 PLANE_B, 61 PLANE_C, 62 }; 63 #define plane_name(p) ((p) + 'A') 64 65 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) 66 67 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++) 68 69 /* Interface history: 70 * 71 * 1.1: Original. 72 * 1.2: Add Power Management 73 * 1.3: Add vblank support 74 * 1.4: Fix cmdbuffer path, add heap destroy 75 * 1.5: Add vblank pipe configuration 76 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 77 * - Support vertical blank on secondary display pipe 78 */ 79 #define DRIVER_MAJOR 1 80 #define DRIVER_MINOR 6 81 #define DRIVER_PATCHLEVEL 0 82 83 #define WATCH_COHERENCY 0 84 #define WATCH_LISTS 0 85 86 #define I915_GEM_PHYS_CURSOR_0 1 87 #define I915_GEM_PHYS_CURSOR_1 2 88 #define I915_GEM_PHYS_OVERLAY_REGS 3 89 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) 90 91 struct drm_i915_gem_phys_object { 92 int id; 93 struct page **page_list; 94 drm_dma_handle_t *handle; 95 struct drm_i915_gem_object *cur_obj; 96 }; 97 98 struct mem_block { 99 struct mem_block *next; 100 struct mem_block *prev; 101 int start; 102 int size; 103 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ 104 }; 105 106 struct opregion_header; 107 struct opregion_acpi; 108 struct opregion_swsci; 109 struct opregion_asle; 110 struct drm_i915_private; 111 112 struct intel_opregion { 113 struct opregion_header *header; 114 struct opregion_acpi *acpi; 115 struct opregion_swsci *swsci; 116 struct opregion_asle *asle; 117 void *vbt; 118 u32 __iomem *lid_state; 119 }; 120 #define OPREGION_SIZE (8*1024) 121 122 struct intel_overlay; 123 struct intel_overlay_error_state; 124 125 struct drm_i915_master_private { 126 drm_local_map_t *sarea; 127 struct _drm_i915_sarea *sarea_priv; 128 }; 129 #define I915_FENCE_REG_NONE -1 130 #define I915_MAX_NUM_FENCES 16 131 /* 16 fences + sign bit for FENCE_REG_NONE */ 132 #define I915_MAX_NUM_FENCE_BITS 5 133 134 struct drm_i915_fence_reg { 135 struct list_head lru_list; 136 struct drm_i915_gem_object *obj; 137 uint32_t setup_seqno; 138 }; 139 140 struct sdvo_device_mapping { 141 u8 initialized; 142 u8 dvo_port; 143 u8 slave_addr; 144 u8 dvo_wiring; 145 u8 i2c_pin; 146 u8 ddc_pin; 147 }; 148 149 struct intel_display_error_state; 150 151 struct drm_i915_error_state { 152 u32 eir; 153 u32 pgtbl_er; 154 u32 pipestat[I915_MAX_PIPES]; 155 u32 ipeir; 156 u32 ipehr; 157 u32 instdone; 158 u32 acthd; 159 u32 error; /* gen6+ */ 160 u32 bcs_acthd; /* gen6+ blt engine */ 161 u32 bcs_ipehr; 162 u32 bcs_ipeir; 163 u32 bcs_instdone; 164 u32 bcs_seqno; 165 u32 vcs_acthd; /* gen6+ bsd engine */ 166 u32 vcs_ipehr; 167 u32 vcs_ipeir; 168 u32 vcs_instdone; 169 u32 vcs_seqno; 170 u32 instpm; 171 u32 instps; 172 u32 instdone1; 173 u32 seqno; 174 u64 bbaddr; 175 u64 fence[I915_MAX_NUM_FENCES]; 176 struct timeval time; 177 struct drm_i915_error_object { 178 int page_count; 179 u32 gtt_offset; 180 u32 *pages[0]; 181 } *ringbuffer[I915_NUM_RINGS], *batchbuffer[I915_NUM_RINGS]; 182 struct drm_i915_error_buffer { 183 u32 size; 184 u32 name; 185 u32 seqno; 186 u32 gtt_offset; 187 u32 read_domains; 188 u32 write_domain; 189 s32 fence_reg:I915_MAX_NUM_FENCE_BITS; 190 s32 pinned:2; 191 u32 tiling:2; 192 u32 dirty:1; 193 u32 purgeable:1; 194 u32 ring:4; 195 u32 cache_level:2; 196 } *active_bo, *pinned_bo; 197 u32 active_bo_count, pinned_bo_count; 198 struct intel_overlay_error_state *overlay; 199 struct intel_display_error_state *display; 200 }; 201 202 struct drm_i915_display_funcs { 203 void (*dpms)(struct drm_crtc *crtc, int mode); 204 bool (*fbc_enabled)(struct drm_device *dev); 205 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); 206 void (*disable_fbc)(struct drm_device *dev); 207 int (*get_display_clock_speed)(struct drm_device *dev); 208 int (*get_fifo_size)(struct drm_device *dev, int plane); 209 void (*update_wm)(struct drm_device *dev); 210 void (*update_sprite_wm)(struct drm_device *dev, int pipe, 211 uint32_t sprite_width, int pixel_size); 212 int (*crtc_mode_set)(struct drm_crtc *crtc, 213 struct drm_display_mode *mode, 214 struct drm_display_mode *adjusted_mode, 215 int x, int y, 216 struct drm_framebuffer *old_fb); 217 void (*write_eld)(struct drm_connector *connector, 218 struct drm_crtc *crtc); 219 void (*fdi_link_train)(struct drm_crtc *crtc); 220 void (*init_clock_gating)(struct drm_device *dev); 221 void (*init_pch_clock_gating)(struct drm_device *dev); 222 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, 223 struct drm_framebuffer *fb, 224 struct drm_i915_gem_object *obj); 225 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, 226 int x, int y); 227 void (*force_wake_get)(struct drm_i915_private *dev_priv); 228 void (*force_wake_put)(struct drm_i915_private *dev_priv); 229 /* clock updates for mode set */ 230 /* cursor updates */ 231 /* render clock increase/decrease */ 232 /* display clock increase/decrease */ 233 /* pll clock increase/decrease */ 234 }; 235 236 struct intel_device_info { 237 u8 gen; 238 u8 is_mobile:1; 239 u8 is_i85x:1; 240 u8 is_i915g:1; 241 u8 is_i945gm:1; 242 u8 is_g33:1; 243 u8 need_gfx_hws:1; 244 u8 is_g4x:1; 245 u8 is_pineview:1; 246 u8 is_broadwater:1; 247 u8 is_crestline:1; 248 u8 is_ivybridge:1; 249 u8 has_fbc:1; 250 u8 has_pipe_cxsr:1; 251 u8 has_hotplug:1; 252 u8 cursor_needs_physical:1; 253 u8 has_overlay:1; 254 u8 overlay_needs_physical:1; 255 u8 supports_tv:1; 256 u8 has_bsd_ring:1; 257 u8 has_blt_ring:1; 258 }; 259 260 enum no_fbc_reason { 261 FBC_NO_OUTPUT, /* no outputs enabled to compress */ 262 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ 263 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ 264 FBC_MODE_TOO_LARGE, /* mode too large for compression */ 265 FBC_BAD_PLANE, /* fbc not supported on plane */ 266 FBC_NOT_TILED, /* buffer not tiled */ 267 FBC_MULTIPLE_PIPES, /* more than one pipe active */ 268 FBC_MODULE_PARAM, 269 }; 270 271 enum intel_pch { 272 PCH_IBX, /* Ibexpeak PCH */ 273 PCH_CPT, /* Cougarpoint PCH */ 274 }; 275 276 #define QUIRK_PIPEA_FORCE (1<<0) 277 #define QUIRK_LVDS_SSC_DISABLE (1<<1) 278 279 struct intel_fbdev; 280 struct intel_fbc_work; 281 282 typedef struct drm_i915_private { 283 struct drm_device *dev; 284 285 const struct intel_device_info *info; 286 287 int has_gem; 288 int relative_constants_mode; 289 290 void __iomem *regs; 291 /** gt_fifo_count and the subsequent register write are synchronized 292 * with dev->struct_mutex. */ 293 unsigned gt_fifo_count; 294 /** forcewake_count is protected by gt_lock */ 295 unsigned forcewake_count; 296 /** gt_lock is also taken in irq contexts. */ 297 struct spinlock gt_lock; 298 299 struct intel_gmbus { 300 struct i2c_adapter adapter; 301 struct i2c_adapter *force_bit; 302 u32 reg0; 303 } *gmbus; 304 305 struct pci_dev *bridge_dev; 306 struct intel_ring_buffer ring[I915_NUM_RINGS]; 307 uint32_t next_seqno; 308 309 drm_dma_handle_t *status_page_dmah; 310 uint32_t counter; 311 drm_local_map_t hws_map; 312 struct drm_i915_gem_object *pwrctx; 313 struct drm_i915_gem_object *renderctx; 314 315 struct resource mch_res; 316 317 unsigned int cpp; 318 int back_offset; 319 int front_offset; 320 int current_page; 321 int page_flipping; 322 323 atomic_t irq_received; 324 325 /* protects the irq masks */ 326 spinlock_t irq_lock; 327 /** Cached value of IMR to avoid reads in updating the bitfield */ 328 u32 pipestat[2]; 329 u32 irq_mask; 330 u32 gt_irq_mask; 331 u32 pch_irq_mask; 332 333 u32 hotplug_supported_mask; 334 struct work_struct hotplug_work; 335 336 int tex_lru_log_granularity; 337 int allow_batchbuffer; 338 struct mem_block *agp_heap; 339 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; 340 int vblank_pipe; 341 int num_pipe; 342 343 /* For hangcheck timer */ 344 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ 345 struct timer_list hangcheck_timer; 346 int hangcheck_count; 347 uint32_t last_acthd; 348 uint32_t last_acthd_bsd; 349 uint32_t last_acthd_blt; 350 uint32_t last_instdone; 351 uint32_t last_instdone1; 352 353 unsigned long cfb_size; 354 unsigned int cfb_fb; 355 enum plane cfb_plane; 356 int cfb_y; 357 struct intel_fbc_work *fbc_work; 358 359 struct intel_opregion opregion; 360 361 /* overlay */ 362 struct intel_overlay *overlay; 363 bool sprite_scaling_enabled; 364 365 /* LVDS info */ 366 int backlight_level; /* restore backlight to this value */ 367 bool backlight_enabled; 368 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 369 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 370 371 /* Feature bits from the VBIOS */ 372 unsigned int int_tv_support:1; 373 unsigned int lvds_dither:1; 374 unsigned int lvds_vbt:1; 375 unsigned int int_crt_support:1; 376 unsigned int lvds_use_ssc:1; 377 unsigned int display_clock_mode:1; 378 int lvds_ssc_freq; 379 struct { 380 int rate; 381 int lanes; 382 int preemphasis; 383 int vswing; 384 385 bool initialized; 386 bool support; 387 int bpp; 388 struct edp_power_seq pps; 389 } edp; 390 bool no_aux_handshake; 391 392 struct notifier_block lid_notifier; 393 394 int crt_ddc_pin; 395 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ 396 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ 397 int num_fence_regs; /* 8 on pre-965, 16 otherwise */ 398 399 unsigned int fsb_freq, mem_freq, is_ddr3; 400 401 spinlock_t error_lock; 402 struct drm_i915_error_state *first_error; 403 struct work_struct error_work; 404 struct completion error_completion; 405 struct workqueue_struct *wq; 406 407 /* Display functions */ 408 struct drm_i915_display_funcs display; 409 410 /* PCH chipset type */ 411 enum intel_pch pch_type; 412 413 unsigned long quirks; 414 415 /* Register state */ 416 bool modeset_on_lid; 417 u8 saveLBB; 418 u32 saveDSPACNTR; 419 u32 saveDSPBCNTR; 420 u32 saveDSPARB; 421 u32 saveHWS; 422 u32 savePIPEACONF; 423 u32 savePIPEBCONF; 424 u32 savePIPEASRC; 425 u32 savePIPEBSRC; 426 u32 saveFPA0; 427 u32 saveFPA1; 428 u32 saveDPLL_A; 429 u32 saveDPLL_A_MD; 430 u32 saveHTOTAL_A; 431 u32 saveHBLANK_A; 432 u32 saveHSYNC_A; 433 u32 saveVTOTAL_A; 434 u32 saveVBLANK_A; 435 u32 saveVSYNC_A; 436 u32 saveBCLRPAT_A; 437 u32 saveTRANSACONF; 438 u32 saveTRANS_HTOTAL_A; 439 u32 saveTRANS_HBLANK_A; 440 u32 saveTRANS_HSYNC_A; 441 u32 saveTRANS_VTOTAL_A; 442 u32 saveTRANS_VBLANK_A; 443 u32 saveTRANS_VSYNC_A; 444 u32 savePIPEASTAT; 445 u32 saveDSPASTRIDE; 446 u32 saveDSPASIZE; 447 u32 saveDSPAPOS; 448 u32 saveDSPAADDR; 449 u32 saveDSPASURF; 450 u32 saveDSPATILEOFF; 451 u32 savePFIT_PGM_RATIOS; 452 u32 saveBLC_HIST_CTL; 453 u32 saveBLC_PWM_CTL; 454 u32 saveBLC_PWM_CTL2; 455 u32 saveBLC_CPU_PWM_CTL; 456 u32 saveBLC_CPU_PWM_CTL2; 457 u32 saveFPB0; 458 u32 saveFPB1; 459 u32 saveDPLL_B; 460 u32 saveDPLL_B_MD; 461 u32 saveHTOTAL_B; 462 u32 saveHBLANK_B; 463 u32 saveHSYNC_B; 464 u32 saveVTOTAL_B; 465 u32 saveVBLANK_B; 466 u32 saveVSYNC_B; 467 u32 saveBCLRPAT_B; 468 u32 saveTRANSBCONF; 469 u32 saveTRANS_HTOTAL_B; 470 u32 saveTRANS_HBLANK_B; 471 u32 saveTRANS_HSYNC_B; 472 u32 saveTRANS_VTOTAL_B; 473 u32 saveTRANS_VBLANK_B; 474 u32 saveTRANS_VSYNC_B; 475 u32 savePIPEBSTAT; 476 u32 saveDSPBSTRIDE; 477 u32 saveDSPBSIZE; 478 u32 saveDSPBPOS; 479 u32 saveDSPBADDR; 480 u32 saveDSPBSURF; 481 u32 saveDSPBTILEOFF; 482 u32 saveVGA0; 483 u32 saveVGA1; 484 u32 saveVGA_PD; 485 u32 saveVGACNTRL; 486 u32 saveADPA; 487 u32 saveLVDS; 488 u32 savePP_ON_DELAYS; 489 u32 savePP_OFF_DELAYS; 490 u32 saveDVOA; 491 u32 saveDVOB; 492 u32 saveDVOC; 493 u32 savePP_ON; 494 u32 savePP_OFF; 495 u32 savePP_CONTROL; 496 u32 savePP_DIVISOR; 497 u32 savePFIT_CONTROL; 498 u32 save_palette_a[256]; 499 u32 save_palette_b[256]; 500 u32 saveDPFC_CB_BASE; 501 u32 saveFBC_CFB_BASE; 502 u32 saveFBC_LL_BASE; 503 u32 saveFBC_CONTROL; 504 u32 saveFBC_CONTROL2; 505 u32 saveIER; 506 u32 saveIIR; 507 u32 saveIMR; 508 u32 saveDEIER; 509 u32 saveDEIMR; 510 u32 saveGTIER; 511 u32 saveGTIMR; 512 u32 saveFDI_RXA_IMR; 513 u32 saveFDI_RXB_IMR; 514 u32 saveCACHE_MODE_0; 515 u32 saveMI_ARB_STATE; 516 u32 saveSWF0[16]; 517 u32 saveSWF1[16]; 518 u32 saveSWF2[3]; 519 u8 saveMSR; 520 u8 saveSR[8]; 521 u8 saveGR[25]; 522 u8 saveAR_INDEX; 523 u8 saveAR[21]; 524 u8 saveDACMASK; 525 u8 saveCR[37]; 526 uint64_t saveFENCE[I915_MAX_NUM_FENCES]; 527 u32 saveCURACNTR; 528 u32 saveCURAPOS; 529 u32 saveCURABASE; 530 u32 saveCURBCNTR; 531 u32 saveCURBPOS; 532 u32 saveCURBBASE; 533 u32 saveCURSIZE; 534 u32 saveDP_B; 535 u32 saveDP_C; 536 u32 saveDP_D; 537 u32 savePIPEA_GMCH_DATA_M; 538 u32 savePIPEB_GMCH_DATA_M; 539 u32 savePIPEA_GMCH_DATA_N; 540 u32 savePIPEB_GMCH_DATA_N; 541 u32 savePIPEA_DP_LINK_M; 542 u32 savePIPEB_DP_LINK_M; 543 u32 savePIPEA_DP_LINK_N; 544 u32 savePIPEB_DP_LINK_N; 545 u32 saveFDI_RXA_CTL; 546 u32 saveFDI_TXA_CTL; 547 u32 saveFDI_RXB_CTL; 548 u32 saveFDI_TXB_CTL; 549 u32 savePFA_CTL_1; 550 u32 savePFB_CTL_1; 551 u32 savePFA_WIN_SZ; 552 u32 savePFB_WIN_SZ; 553 u32 savePFA_WIN_POS; 554 u32 savePFB_WIN_POS; 555 u32 savePCH_DREF_CONTROL; 556 u32 saveDISP_ARB_CTL; 557 u32 savePIPEA_DATA_M1; 558 u32 savePIPEA_DATA_N1; 559 u32 savePIPEA_LINK_M1; 560 u32 savePIPEA_LINK_N1; 561 u32 savePIPEB_DATA_M1; 562 u32 savePIPEB_DATA_N1; 563 u32 savePIPEB_LINK_M1; 564 u32 savePIPEB_LINK_N1; 565 u32 saveMCHBAR_RENDER_STANDBY; 566 u32 savePCH_PORT_HOTPLUG; 567 568 struct { 569 /** Bridge to intel-gtt-ko */ 570 const struct intel_gtt *gtt; 571 /** Memory allocator for GTT stolen memory */ 572 struct drm_mm stolen; 573 /** Memory allocator for GTT */ 574 struct drm_mm gtt_space; 575 /** List of all objects in gtt_space. Used to restore gtt 576 * mappings on resume */ 577 struct list_head gtt_list; 578 579 /** Usable portion of the GTT for GEM */ 580 unsigned long gtt_start; 581 unsigned long gtt_mappable_end; 582 unsigned long gtt_end; 583 584 struct io_mapping *gtt_mapping; 585 int gtt_mtrr; 586 587 struct shrinker inactive_shrinker; 588 589 /** 590 * List of objects currently involved in rendering. 591 * 592 * Includes buffers having the contents of their GPU caches 593 * flushed, not necessarily primitives. last_rendering_seqno 594 * represents when the rendering involved will be completed. 595 * 596 * A reference is held on the buffer while on this list. 597 */ 598 struct list_head active_list; 599 600 /** 601 * List of objects which are not in the ringbuffer but which 602 * still have a write_domain which needs to be flushed before 603 * unbinding. 604 * 605 * last_rendering_seqno is 0 while an object is in this list. 606 * 607 * A reference is held on the buffer while on this list. 608 */ 609 struct list_head flushing_list; 610 611 /** 612 * LRU list of objects which are not in the ringbuffer and 613 * are ready to unbind, but are still in the GTT. 614 * 615 * last_rendering_seqno is 0 while an object is in this list. 616 * 617 * A reference is not held on the buffer while on this list, 618 * as merely being GTT-bound shouldn't prevent its being 619 * freed, and we'll pull it off the list in the free path. 620 */ 621 struct list_head inactive_list; 622 623 /** 624 * LRU list of objects which are not in the ringbuffer but 625 * are still pinned in the GTT. 626 */ 627 struct list_head pinned_list; 628 629 /** LRU list of objects with fence regs on them. */ 630 struct list_head fence_list; 631 632 /** 633 * List of objects currently pending being freed. 634 * 635 * These objects are no longer in use, but due to a signal 636 * we were prevented from freeing them at the appointed time. 637 */ 638 struct list_head deferred_free_list; 639 640 /** 641 * We leave the user IRQ off as much as possible, 642 * but this means that requests will finish and never 643 * be retired once the system goes idle. Set a timer to 644 * fire periodically while the ring is running. When it 645 * fires, go retire requests. 646 */ 647 struct delayed_work retire_work; 648 649 /** 650 * Are we in a non-interruptible section of code like 651 * modesetting? 652 */ 653 bool interruptible; 654 655 /** 656 * Flag if the X Server, and thus DRM, is not currently in 657 * control of the device. 658 * 659 * This is set between LeaveVT and EnterVT. It needs to be 660 * replaced with a semaphore. It also needs to be 661 * transitioned away from for kernel modesetting. 662 */ 663 int suspended; 664 665 /** 666 * Flag if the hardware appears to be wedged. 667 * 668 * This is set when attempts to idle the device timeout. 669 * It prevents command submission from occurring and makes 670 * every pending request fail 671 */ 672 atomic_t wedged; 673 674 /** Bit 6 swizzling required for X tiling */ 675 uint32_t bit_6_swizzle_x; 676 /** Bit 6 swizzling required for Y tiling */ 677 uint32_t bit_6_swizzle_y; 678 679 /* storage for physical objects */ 680 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; 681 682 /* accounting, useful for userland debugging */ 683 size_t gtt_total; 684 size_t mappable_gtt_total; 685 size_t object_memory; 686 u32 object_count; 687 } mm; 688 struct sdvo_device_mapping sdvo_mappings[2]; 689 /* indicate whether the LVDS_BORDER should be enabled or not */ 690 unsigned int lvds_border_bits; 691 /* Panel fitter placement and size for Ironlake+ */ 692 u32 pch_pf_pos, pch_pf_size; 693 694 struct drm_crtc *plane_to_crtc_mapping[3]; 695 struct drm_crtc *pipe_to_crtc_mapping[3]; 696 wait_queue_head_t pending_flip_queue; 697 bool flip_pending_is_done; 698 699 /* Reclocking support */ 700 bool render_reclock_avail; 701 bool lvds_downclock_avail; 702 /* indicates the reduced downclock for LVDS*/ 703 int lvds_downclock; 704 struct work_struct idle_work; 705 struct timer_list idle_timer; 706 bool busy; 707 u16 orig_clock; 708 int child_dev_num; 709 struct child_device_config *child_dev; 710 struct drm_connector *int_lvds_connector; 711 struct drm_connector *int_edp_connector; 712 713 bool mchbar_need_disable; 714 715 struct work_struct rps_work; 716 spinlock_t rps_lock; 717 u32 pm_iir; 718 719 u8 cur_delay; 720 u8 min_delay; 721 u8 max_delay; 722 u8 fmax; 723 u8 fstart; 724 725 u64 last_count1; 726 unsigned long last_time1; 727 unsigned long chipset_power; 728 u64 last_count2; 729 struct timespec last_time2; 730 unsigned long gfx_power; 731 int c_m; 732 int r_t; 733 u8 corr; 734 spinlock_t *mchdev_lock; 735 736 enum no_fbc_reason no_fbc_reason; 737 738 struct drm_mm_node *compressed_fb; 739 struct drm_mm_node *compressed_llb; 740 741 unsigned long last_gpu_reset; 742 743 /* list of fbdev register on this device */ 744 struct intel_fbdev *fbdev; 745 746 struct backlight_device *backlight; 747 748 struct drm_property *broadcast_rgb_property; 749 struct drm_property *force_audio_property; 750 } drm_i915_private_t; 751 752 enum i915_cache_level { 753 I915_CACHE_NONE, 754 I915_CACHE_LLC, 755 I915_CACHE_LLC_MLC, /* gen6+ */ 756 }; 757 758 struct drm_i915_gem_object { 759 struct drm_gem_object base; 760 761 /** Current space allocated to this object in the GTT, if any. */ 762 struct drm_mm_node *gtt_space; 763 struct list_head gtt_list; 764 765 /** This object's place on the active/flushing/inactive lists */ 766 struct list_head ring_list; 767 struct list_head mm_list; 768 /** This object's place on GPU write list */ 769 struct list_head gpu_write_list; 770 /** This object's place in the batchbuffer or on the eviction list */ 771 struct list_head exec_list; 772 773 /** 774 * This is set if the object is on the active or flushing lists 775 * (has pending rendering), and is not set if it's on inactive (ready 776 * to be unbound). 777 */ 778 unsigned int active:1; 779 780 /** 781 * This is set if the object has been written to since last bound 782 * to the GTT 783 */ 784 unsigned int dirty:1; 785 786 /** 787 * This is set if the object has been written to since the last 788 * GPU flush. 789 */ 790 unsigned int pending_gpu_write:1; 791 792 /** 793 * Fence register bits (if any) for this object. Will be set 794 * as needed when mapped into the GTT. 795 * Protected by dev->struct_mutex. 796 */ 797 signed int fence_reg:I915_MAX_NUM_FENCE_BITS; 798 799 /** 800 * Advice: are the backing pages purgeable? 801 */ 802 unsigned int madv:2; 803 804 /** 805 * Current tiling mode for the object. 806 */ 807 unsigned int tiling_mode:2; 808 unsigned int tiling_changed:1; 809 810 /** How many users have pinned this object in GTT space. The following 811 * users can each hold at most one reference: pwrite/pread, pin_ioctl 812 * (via user_pin_count), execbuffer (objects are not allowed multiple 813 * times for the same batchbuffer), and the framebuffer code. When 814 * switching/pageflipping, the framebuffer code has at most two buffers 815 * pinned per crtc. 816 * 817 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 818 * bits with absolutely no headroom. So use 4 bits. */ 819 unsigned int pin_count:4; 820 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf 821 822 /** 823 * Is the object at the current location in the gtt mappable and 824 * fenceable? Used to avoid costly recalculations. 825 */ 826 unsigned int map_and_fenceable:1; 827 828 /** 829 * Whether the current gtt mapping needs to be mappable (and isn't just 830 * mappable by accident). Track pin and fault separate for a more 831 * accurate mappable working set. 832 */ 833 unsigned int fault_mappable:1; 834 unsigned int pin_mappable:1; 835 836 /* 837 * Is the GPU currently using a fence to access this buffer, 838 */ 839 unsigned int pending_fenced_gpu_access:1; 840 unsigned int fenced_gpu_access:1; 841 842 unsigned int cache_level:2; 843 844 struct page **pages; 845 846 /** 847 * DMAR support 848 */ 849 struct scatterlist *sg_list; 850 int num_sg; 851 852 /** 853 * Used for performing relocations during execbuffer insertion. 854 */ 855 struct hlist_node exec_node; 856 unsigned long exec_handle; 857 struct drm_i915_gem_exec_object2 *exec_entry; 858 859 /** 860 * Current offset of the object in GTT space. 861 * 862 * This is the same as gtt_space->start 863 */ 864 uint32_t gtt_offset; 865 866 /** Breadcrumb of last rendering to the buffer. */ 867 uint32_t last_rendering_seqno; 868 struct intel_ring_buffer *ring; 869 870 /** Breadcrumb of last fenced GPU access to the buffer. */ 871 uint32_t last_fenced_seqno; 872 struct intel_ring_buffer *last_fenced_ring; 873 874 /** Current tiling stride for the object, if it's tiled. */ 875 uint32_t stride; 876 877 /** Record of address bit 17 of each page at last unbind. */ 878 unsigned long *bit_17; 879 880 881 /** 882 * If present, while GEM_DOMAIN_CPU is in the read domain this array 883 * flags which individual pages are valid. 884 */ 885 uint8_t *page_cpu_valid; 886 887 /** User space pin count and filp owning the pin */ 888 uint32_t user_pin_count; 889 struct drm_file *pin_filp; 890 891 /** for phy allocated objects */ 892 struct drm_i915_gem_phys_object *phys_obj; 893 894 /** 895 * Number of crtcs where this object is currently the fb, but 896 * will be page flipped away on the next vblank. When it 897 * reaches 0, dev_priv->pending_flip_queue will be woken up. 898 */ 899 atomic_t pending_flip; 900 }; 901 902 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) 903 904 /** 905 * Request queue structure. 906 * 907 * The request queue allows us to note sequence numbers that have been emitted 908 * and may be associated with active buffers to be retired. 909 * 910 * By keeping this list, we can avoid having to do questionable 911 * sequence-number comparisons on buffer last_rendering_seqnos, and associate 912 * an emission time with seqnos for tracking how far ahead of the GPU we are. 913 */ 914 struct drm_i915_gem_request { 915 /** On Which ring this request was generated */ 916 struct intel_ring_buffer *ring; 917 918 /** GEM sequence number associated with this request. */ 919 uint32_t seqno; 920 921 /** Time at which this request was emitted, in jiffies. */ 922 unsigned long emitted_jiffies; 923 924 /** global list entry for this request */ 925 struct list_head list; 926 927 struct drm_i915_file_private *file_priv; 928 /** file_priv list entry for this request */ 929 struct list_head client_list; 930 }; 931 932 struct drm_i915_file_private { 933 struct { 934 struct spinlock lock; 935 struct list_head request_list; 936 } mm; 937 }; 938 939 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) 940 941 #define IS_I830(dev) ((dev)->pci_device == 0x3577) 942 #define IS_845G(dev) ((dev)->pci_device == 0x2562) 943 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) 944 #define IS_I865G(dev) ((dev)->pci_device == 0x2572) 945 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) 946 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) 947 #define IS_I945G(dev) ((dev)->pci_device == 0x2772) 948 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) 949 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) 950 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) 951 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) 952 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) 953 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) 954 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) 955 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) 956 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) 957 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) 958 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) 959 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) 960 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) 961 962 /* 963 * The genX designation typically refers to the render engine, so render 964 * capability related checks should use IS_GEN, while display and other checks 965 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular 966 * chips, etc.). 967 */ 968 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) 969 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) 970 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) 971 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) 972 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) 973 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) 974 975 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) 976 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) 977 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) 978 979 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) 980 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) 981 982 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 983 * rows, which changed the alignment requirements and fence programming. 984 */ 985 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ 986 IS_I915GM(dev))) 987 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) 988 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) 989 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) 990 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) 991 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) 992 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) 993 /* dsparb controlled by hw only */ 994 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) 995 996 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) 997 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) 998 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) 999 1000 #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) 1001 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5) 1002 1003 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) 1004 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) 1005 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) 1006 1007 #include "i915_trace.h" 1008 1009 extern struct drm_ioctl_desc i915_ioctls[]; 1010 extern int i915_max_ioctl; 1011 extern unsigned int i915_fbpercrtc __always_unused; 1012 extern int i915_panel_ignore_lid __read_mostly; 1013 extern unsigned int i915_powersave __read_mostly; 1014 extern int i915_semaphores __read_mostly; 1015 extern unsigned int i915_lvds_downclock __read_mostly; 1016 extern int i915_panel_use_ssc __read_mostly; 1017 extern int i915_vbt_sdvo_panel_type __read_mostly; 1018 extern int i915_enable_rc6 __read_mostly; 1019 extern int i915_enable_fbc __read_mostly; 1020 extern bool i915_enable_hangcheck __read_mostly; 1021 1022 extern int i915_suspend(struct drm_device *dev, pm_message_t state); 1023 extern int i915_resume(struct drm_device *dev); 1024 extern int i915_master_create(struct drm_device *dev, struct drm_master *master); 1025 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); 1026 1027 /* i915_dma.c */ 1028 extern void i915_kernel_lost_context(struct drm_device * dev); 1029 extern int i915_driver_load(struct drm_device *, unsigned long flags); 1030 extern int i915_driver_unload(struct drm_device *); 1031 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); 1032 extern void i915_driver_lastclose(struct drm_device * dev); 1033 extern void i915_driver_preclose(struct drm_device *dev, 1034 struct drm_file *file_priv); 1035 extern void i915_driver_postclose(struct drm_device *dev, 1036 struct drm_file *file_priv); 1037 extern int i915_driver_device_is_agp(struct drm_device * dev); 1038 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 1039 unsigned long arg); 1040 extern int i915_emit_box(struct drm_device *dev, 1041 struct drm_clip_rect *box, 1042 int DR1, int DR4); 1043 extern int i915_reset(struct drm_device *dev, u8 flags); 1044 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); 1045 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); 1046 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); 1047 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); 1048 1049 1050 /* i915_irq.c */ 1051 void i915_hangcheck_elapsed(unsigned long data); 1052 void i915_handle_error(struct drm_device *dev, bool wedged); 1053 extern int i915_irq_emit(struct drm_device *dev, void *data, 1054 struct drm_file *file_priv); 1055 extern int i915_irq_wait(struct drm_device *dev, void *data, 1056 struct drm_file *file_priv); 1057 1058 extern void intel_irq_init(struct drm_device *dev); 1059 1060 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, 1061 struct drm_file *file_priv); 1062 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, 1063 struct drm_file *file_priv); 1064 extern int i915_vblank_swap(struct drm_device *dev, void *data, 1065 struct drm_file *file_priv); 1066 1067 void 1068 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1069 1070 void 1071 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1072 1073 void intel_enable_asle(struct drm_device *dev); 1074 1075 #ifdef CONFIG_DEBUG_FS 1076 extern void i915_destroy_error_state(struct drm_device *dev); 1077 #else 1078 #define i915_destroy_error_state(x) 1079 #endif 1080 1081 1082 /* i915_mem.c */ 1083 extern int i915_mem_alloc(struct drm_device *dev, void *data, 1084 struct drm_file *file_priv); 1085 extern int i915_mem_free(struct drm_device *dev, void *data, 1086 struct drm_file *file_priv); 1087 extern int i915_mem_init_heap(struct drm_device *dev, void *data, 1088 struct drm_file *file_priv); 1089 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data, 1090 struct drm_file *file_priv); 1091 extern void i915_mem_takedown(struct mem_block **heap); 1092 extern void i915_mem_release(struct drm_device * dev, 1093 struct drm_file *file_priv, struct mem_block *heap); 1094 /* i915_gem.c */ 1095 int i915_gem_init_ioctl(struct drm_device *dev, void *data, 1096 struct drm_file *file_priv); 1097 int i915_gem_create_ioctl(struct drm_device *dev, void *data, 1098 struct drm_file *file_priv); 1099 int i915_gem_pread_ioctl(struct drm_device *dev, void *data, 1100 struct drm_file *file_priv); 1101 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, 1102 struct drm_file *file_priv); 1103 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 1104 struct drm_file *file_priv); 1105 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, 1106 struct drm_file *file_priv); 1107 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, 1108 struct drm_file *file_priv); 1109 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, 1110 struct drm_file *file_priv); 1111 int i915_gem_execbuffer(struct drm_device *dev, void *data, 1112 struct drm_file *file_priv); 1113 int i915_gem_execbuffer2(struct drm_device *dev, void *data, 1114 struct drm_file *file_priv); 1115 int i915_gem_pin_ioctl(struct drm_device *dev, void *data, 1116 struct drm_file *file_priv); 1117 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, 1118 struct drm_file *file_priv); 1119 int i915_gem_busy_ioctl(struct drm_device *dev, void *data, 1120 struct drm_file *file_priv); 1121 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 1122 struct drm_file *file_priv); 1123 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, 1124 struct drm_file *file_priv); 1125 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, 1126 struct drm_file *file_priv); 1127 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, 1128 struct drm_file *file_priv); 1129 int i915_gem_set_tiling(struct drm_device *dev, void *data, 1130 struct drm_file *file_priv); 1131 int i915_gem_get_tiling(struct drm_device *dev, void *data, 1132 struct drm_file *file_priv); 1133 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, 1134 struct drm_file *file_priv); 1135 void i915_gem_load(struct drm_device *dev); 1136 int i915_gem_init_object(struct drm_gem_object *obj); 1137 int __must_check i915_gem_flush_ring(struct intel_ring_buffer *ring, 1138 uint32_t invalidate_domains, 1139 uint32_t flush_domains); 1140 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, 1141 size_t size); 1142 void i915_gem_free_object(struct drm_gem_object *obj); 1143 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, 1144 uint32_t alignment, 1145 bool map_and_fenceable); 1146 void i915_gem_object_unpin(struct drm_i915_gem_object *obj); 1147 int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj); 1148 void i915_gem_release_mmap(struct drm_i915_gem_object *obj); 1149 void i915_gem_lastclose(struct drm_device *dev); 1150 1151 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); 1152 int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj); 1153 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, 1154 struct intel_ring_buffer *ring, 1155 u32 seqno); 1156 1157 int i915_gem_dumb_create(struct drm_file *file_priv, 1158 struct drm_device *dev, 1159 struct drm_mode_create_dumb *args); 1160 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, 1161 uint32_t handle, uint64_t *offset); 1162 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev, 1163 uint32_t handle); 1164 /** 1165 * Returns true if seq1 is later than seq2. 1166 */ 1167 static inline bool 1168 i915_seqno_passed(uint32_t seq1, uint32_t seq2) 1169 { 1170 return (int32_t)(seq1 - seq2) >= 0; 1171 } 1172 1173 static inline u32 1174 i915_gem_next_request_seqno(struct intel_ring_buffer *ring) 1175 { 1176 drm_i915_private_t *dev_priv = ring->dev->dev_private; 1177 return ring->outstanding_lazy_request = dev_priv->next_seqno; 1178 } 1179 1180 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj, 1181 struct intel_ring_buffer *pipelined); 1182 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); 1183 1184 void i915_gem_retire_requests(struct drm_device *dev); 1185 void i915_gem_reset(struct drm_device *dev); 1186 void i915_gem_clflush_object(struct drm_i915_gem_object *obj); 1187 int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj, 1188 uint32_t read_domains, 1189 uint32_t write_domain); 1190 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); 1191 int __must_check i915_gem_init_ringbuffer(struct drm_device *dev); 1192 void i915_gem_cleanup_ringbuffer(struct drm_device *dev); 1193 void i915_gem_do_init(struct drm_device *dev, 1194 unsigned long start, 1195 unsigned long mappable_end, 1196 unsigned long end); 1197 int __must_check i915_gpu_idle(struct drm_device *dev); 1198 int __must_check i915_gem_idle(struct drm_device *dev); 1199 int __must_check i915_add_request(struct intel_ring_buffer *ring, 1200 struct drm_file *file, 1201 struct drm_i915_gem_request *request); 1202 int __must_check i915_wait_request(struct intel_ring_buffer *ring, 1203 uint32_t seqno); 1204 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); 1205 int __must_check 1206 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, 1207 bool write); 1208 int __must_check 1209 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, 1210 u32 alignment, 1211 struct intel_ring_buffer *pipelined); 1212 int i915_gem_attach_phys_object(struct drm_device *dev, 1213 struct drm_i915_gem_object *obj, 1214 int id, 1215 int align); 1216 void i915_gem_detach_phys_object(struct drm_device *dev, 1217 struct drm_i915_gem_object *obj); 1218 void i915_gem_free_all_phys_object(struct drm_device *dev); 1219 void i915_gem_release(struct drm_device *dev, struct drm_file *file); 1220 1221 uint32_t 1222 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, 1223 uint32_t size, 1224 int tiling_mode); 1225 1226 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 1227 enum i915_cache_level cache_level); 1228 1229 /* i915_gem_gtt.c */ 1230 void i915_gem_restore_gtt_mappings(struct drm_device *dev); 1231 int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj); 1232 void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj, 1233 enum i915_cache_level cache_level); 1234 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); 1235 1236 /* i915_gem_evict.c */ 1237 int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size, 1238 unsigned alignment, bool mappable); 1239 int __must_check i915_gem_evict_everything(struct drm_device *dev, 1240 bool purgeable_only); 1241 int __must_check i915_gem_evict_inactive(struct drm_device *dev, 1242 bool purgeable_only); 1243 1244 /* i915_gem_tiling.c */ 1245 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 1246 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); 1247 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); 1248 1249 /* i915_gem_debug.c */ 1250 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, 1251 const char *where, uint32_t mark); 1252 #if WATCH_LISTS 1253 int i915_verify_lists(struct drm_device *dev); 1254 #else 1255 #define i915_verify_lists(dev) 0 1256 #endif 1257 void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj, 1258 int handle); 1259 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, 1260 const char *where, uint32_t mark); 1261 1262 /* i915_debugfs.c */ 1263 int i915_debugfs_init(struct drm_minor *minor); 1264 void i915_debugfs_cleanup(struct drm_minor *minor); 1265 1266 /* i915_suspend.c */ 1267 extern int i915_save_state(struct drm_device *dev); 1268 extern int i915_restore_state(struct drm_device *dev); 1269 1270 /* i915_suspend.c */ 1271 extern int i915_save_state(struct drm_device *dev); 1272 extern int i915_restore_state(struct drm_device *dev); 1273 1274 /* intel_i2c.c */ 1275 extern int intel_setup_gmbus(struct drm_device *dev); 1276 extern void intel_teardown_gmbus(struct drm_device *dev); 1277 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); 1278 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); 1279 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) 1280 { 1281 return container_of(adapter, struct intel_gmbus, adapter)->force_bit; 1282 } 1283 extern void intel_i2c_reset(struct drm_device *dev); 1284 1285 /* intel_opregion.c */ 1286 extern int intel_opregion_setup(struct drm_device *dev); 1287 #ifdef CONFIG_ACPI 1288 extern void intel_opregion_init(struct drm_device *dev); 1289 extern void intel_opregion_fini(struct drm_device *dev); 1290 extern void intel_opregion_asle_intr(struct drm_device *dev); 1291 extern void intel_opregion_gse_intr(struct drm_device *dev); 1292 extern void intel_opregion_enable_asle(struct drm_device *dev); 1293 #else 1294 static inline void intel_opregion_init(struct drm_device *dev) { return; } 1295 static inline void intel_opregion_fini(struct drm_device *dev) { return; } 1296 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } 1297 static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; } 1298 static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; } 1299 #endif 1300 1301 /* intel_acpi.c */ 1302 #ifdef CONFIG_ACPI 1303 extern void intel_register_dsm_handler(void); 1304 extern void intel_unregister_dsm_handler(void); 1305 #else 1306 static inline void intel_register_dsm_handler(void) { return; } 1307 static inline void intel_unregister_dsm_handler(void) { return; } 1308 #endif /* CONFIG_ACPI */ 1309 1310 /* modesetting */ 1311 extern void intel_modeset_init(struct drm_device *dev); 1312 extern void intel_modeset_gem_init(struct drm_device *dev); 1313 extern void intel_modeset_cleanup(struct drm_device *dev); 1314 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); 1315 extern bool intel_fbc_enabled(struct drm_device *dev); 1316 extern void intel_disable_fbc(struct drm_device *dev); 1317 extern bool ironlake_set_drps(struct drm_device *dev, u8 val); 1318 extern void ironlake_init_pch_refclk(struct drm_device *dev); 1319 extern void ironlake_enable_rc6(struct drm_device *dev); 1320 extern void gen6_set_rps(struct drm_device *dev, u8 val); 1321 extern void intel_detect_pch(struct drm_device *dev); 1322 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); 1323 1324 extern void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); 1325 extern void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv); 1326 extern void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); 1327 extern void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv); 1328 1329 /* overlay */ 1330 #ifdef CONFIG_DEBUG_FS 1331 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); 1332 extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error); 1333 1334 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); 1335 extern void intel_display_print_error_state(struct seq_file *m, 1336 struct drm_device *dev, 1337 struct intel_display_error_state *error); 1338 #endif 1339 1340 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS]) 1341 1342 #define BEGIN_LP_RING(n) \ 1343 intel_ring_begin(LP_RING(dev_priv), (n)) 1344 1345 #define OUT_RING(x) \ 1346 intel_ring_emit(LP_RING(dev_priv), x) 1347 1348 #define ADVANCE_LP_RING() \ 1349 intel_ring_advance(LP_RING(dev_priv)) 1350 1351 /** 1352 * Lock test for when it's just for synchronization of ring access. 1353 * 1354 * In that case, we don't need to do it when GEM is initialized as nobody else 1355 * has access to the ring. 1356 */ 1357 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \ 1358 if (LP_RING(dev->dev_private)->obj == NULL) \ 1359 LOCK_TEST_WITH_RETURN(dev, file); \ 1360 } while (0) 1361 1362 /* On SNB platform, before reading ring registers forcewake bit 1363 * must be set to prevent GT core from power down and stale values being 1364 * returned. 1365 */ 1366 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); 1367 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); 1368 void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); 1369 1370 /* We give fast paths for the really cool registers */ 1371 #define NEEDS_FORCE_WAKE(dev_priv, reg) \ 1372 (((dev_priv)->info->gen >= 6) && \ 1373 ((reg) < 0x40000) && \ 1374 ((reg) != FORCEWAKE)) 1375 1376 #define __i915_read(x, y) \ 1377 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg); 1378 1379 __i915_read(8, b) 1380 __i915_read(16, w) 1381 __i915_read(32, l) 1382 __i915_read(64, q) 1383 #undef __i915_read 1384 1385 #define __i915_write(x, y) \ 1386 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val); 1387 1388 __i915_write(8, b) 1389 __i915_write(16, w) 1390 __i915_write(32, l) 1391 __i915_write(64, q) 1392 #undef __i915_write 1393 1394 #define I915_READ8(reg) i915_read8(dev_priv, (reg)) 1395 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val)) 1396 1397 #define I915_READ16(reg) i915_read16(dev_priv, (reg)) 1398 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val)) 1399 #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg)) 1400 #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg)) 1401 1402 #define I915_READ(reg) i915_read32(dev_priv, (reg)) 1403 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val)) 1404 #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg)) 1405 #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg)) 1406 1407 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val)) 1408 #define I915_READ64(reg) i915_read64(dev_priv, (reg)) 1409 1410 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) 1411 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) 1412 1413 1414 #endif 1415