1 /* 2 * KVMGT - the implementation of Intel mediated pass-through framework for KVM 3 * 4 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 23 * SOFTWARE. 24 * 25 * Authors: 26 * Kevin Tian <kevin.tian@intel.com> 27 * Jike Song <jike.song@intel.com> 28 * Xiaoguang Chen <xiaoguang.chen@intel.com> 29 * Eddie Dong <eddie.dong@intel.com> 30 * 31 * Contributors: 32 * Niu Bing <bing.niu@intel.com> 33 * Zhi Wang <zhi.a.wang@intel.com> 34 */ 35 36 #include <linux/init.h> 37 #include <linux/mm.h> 38 #include <linux/kthread.h> 39 #include <linux/sched/mm.h> 40 #include <linux/types.h> 41 #include <linux/list.h> 42 #include <linux/rbtree.h> 43 #include <linux/spinlock.h> 44 #include <linux/eventfd.h> 45 #include <linux/mdev.h> 46 #include <linux/debugfs.h> 47 48 #include <linux/nospec.h> 49 50 #include <drm/drm_edid.h> 51 #include <drm/drm_print.h> 52 53 #include "i915_drv.h" 54 #include "intel_gvt.h" 55 #include "gvt.h" 56 57 MODULE_IMPORT_NS("DMA_BUF"); 58 MODULE_IMPORT_NS("I915_GVT"); 59 60 /* helper macros copied from vfio-pci */ 61 #define VFIO_PCI_OFFSET_SHIFT 40 62 #define VFIO_PCI_OFFSET_TO_INDEX(off) (off >> VFIO_PCI_OFFSET_SHIFT) 63 #define VFIO_PCI_INDEX_TO_OFFSET(index) ((u64)(index) << VFIO_PCI_OFFSET_SHIFT) 64 #define VFIO_PCI_OFFSET_MASK (((u64)(1) << VFIO_PCI_OFFSET_SHIFT) - 1) 65 66 #define EDID_BLOB_OFFSET (PAGE_SIZE/2) 67 68 #define OPREGION_SIGNATURE "IntelGraphicsMem" 69 70 struct vfio_region; 71 struct intel_vgpu_regops { 72 size_t (*rw)(struct intel_vgpu *vgpu, char *buf, 73 size_t count, loff_t *ppos, bool iswrite); 74 void (*release)(struct intel_vgpu *vgpu, 75 struct vfio_region *region); 76 }; 77 78 struct vfio_region { 79 u32 type; 80 u32 subtype; 81 size_t size; 82 u32 flags; 83 const struct intel_vgpu_regops *ops; 84 void *data; 85 }; 86 87 struct vfio_edid_region { 88 struct vfio_region_gfx_edid vfio_edid_regs; 89 void *edid_blob; 90 }; 91 92 struct kvmgt_pgfn { 93 gfn_t gfn; 94 struct hlist_node hnode; 95 }; 96 97 struct gvt_dma { 98 struct intel_vgpu *vgpu; 99 struct rb_node gfn_node; 100 struct rb_node dma_addr_node; 101 gfn_t gfn; 102 dma_addr_t dma_addr; 103 unsigned long size; 104 struct kref ref; 105 }; 106 107 #define vfio_dev_to_vgpu(vfio_dev) \ 108 container_of((vfio_dev), struct intel_vgpu, vfio_device) 109 110 static void kvmgt_page_track_write(gpa_t gpa, const u8 *val, int len, 111 struct kvm_page_track_notifier_node *node); 112 static void kvmgt_page_track_remove_region(gfn_t gfn, unsigned long nr_pages, 113 struct kvm_page_track_notifier_node *node); 114 115 static ssize_t intel_vgpu_show_description(struct mdev_type *mtype, char *buf) 116 { 117 struct intel_vgpu_type *type = 118 container_of(mtype, struct intel_vgpu_type, type); 119 120 return sprintf(buf, "low_gm_size: %dMB\nhigh_gm_size: %dMB\n" 121 "fence: %d\nresolution: %s\n" 122 "weight: %d\n", 123 BYTES_TO_MB(type->conf->low_mm), 124 BYTES_TO_MB(type->conf->high_mm), 125 type->conf->fence, vgpu_edid_str(type->conf->edid), 126 type->conf->weight); 127 } 128 129 static void gvt_unpin_guest_page(struct intel_vgpu *vgpu, unsigned long gfn, 130 unsigned long size) 131 { 132 vfio_unpin_pages(&vgpu->vfio_device, gfn << PAGE_SHIFT, 133 DIV_ROUND_UP(size, PAGE_SIZE)); 134 } 135 136 /* Pin a normal or compound guest page for dma. */ 137 static int gvt_pin_guest_page(struct intel_vgpu *vgpu, unsigned long gfn, 138 unsigned long size, struct page **page) 139 { 140 int total_pages = DIV_ROUND_UP(size, PAGE_SIZE); 141 struct page *base_page = NULL; 142 int npage; 143 int ret; 144 145 /* 146 * We pin the pages one-by-one to avoid allocating a big array 147 * on stack to hold pfns. 148 */ 149 for (npage = 0; npage < total_pages; npage++) { 150 dma_addr_t cur_iova = (gfn + npage) << PAGE_SHIFT; 151 struct page *cur_page; 152 153 ret = vfio_pin_pages(&vgpu->vfio_device, cur_iova, 1, 154 IOMMU_READ | IOMMU_WRITE, &cur_page); 155 if (ret != 1) { 156 gvt_vgpu_err("vfio_pin_pages failed for iova %pad, ret %d\n", 157 &cur_iova, ret); 158 goto err; 159 } 160 161 if (npage == 0) 162 base_page = cur_page; 163 else if (page_to_pfn(base_page) + npage != page_to_pfn(cur_page)) { 164 ret = -EINVAL; 165 npage++; 166 goto err; 167 } 168 } 169 170 *page = base_page; 171 return 0; 172 err: 173 if (npage) 174 gvt_unpin_guest_page(vgpu, gfn, npage * PAGE_SIZE); 175 return ret; 176 } 177 178 static int gvt_dma_map_page(struct intel_vgpu *vgpu, unsigned long gfn, 179 dma_addr_t *dma_addr, unsigned long size) 180 { 181 struct device *dev = vgpu->gvt->gt->i915->drm.dev; 182 struct page *page = NULL; 183 int ret; 184 185 ret = gvt_pin_guest_page(vgpu, gfn, size, &page); 186 if (ret) 187 return ret; 188 189 /* Setup DMA mapping. */ 190 *dma_addr = dma_map_page(dev, page, 0, size, DMA_BIDIRECTIONAL); 191 if (dma_mapping_error(dev, *dma_addr)) { 192 gvt_vgpu_err("DMA mapping failed for pfn 0x%lx, ret %d\n", 193 page_to_pfn(page), ret); 194 gvt_unpin_guest_page(vgpu, gfn, size); 195 return -ENOMEM; 196 } 197 198 return 0; 199 } 200 201 static void gvt_dma_unmap_page(struct intel_vgpu *vgpu, unsigned long gfn, 202 dma_addr_t dma_addr, unsigned long size) 203 { 204 struct device *dev = vgpu->gvt->gt->i915->drm.dev; 205 206 dma_unmap_page(dev, dma_addr, size, DMA_BIDIRECTIONAL); 207 gvt_unpin_guest_page(vgpu, gfn, size); 208 } 209 210 static struct gvt_dma *__gvt_cache_find_dma_addr(struct intel_vgpu *vgpu, 211 dma_addr_t dma_addr) 212 { 213 struct rb_node *node = vgpu->dma_addr_cache.rb_node; 214 struct gvt_dma *itr; 215 216 while (node) { 217 itr = rb_entry(node, struct gvt_dma, dma_addr_node); 218 219 if (dma_addr < itr->dma_addr) 220 node = node->rb_left; 221 else if (dma_addr > itr->dma_addr) 222 node = node->rb_right; 223 else 224 return itr; 225 } 226 return NULL; 227 } 228 229 static struct gvt_dma *__gvt_cache_find_gfn(struct intel_vgpu *vgpu, gfn_t gfn) 230 { 231 struct rb_node *node = vgpu->gfn_cache.rb_node; 232 struct gvt_dma *itr; 233 234 while (node) { 235 itr = rb_entry(node, struct gvt_dma, gfn_node); 236 237 if (gfn < itr->gfn) 238 node = node->rb_left; 239 else if (gfn > itr->gfn) 240 node = node->rb_right; 241 else 242 return itr; 243 } 244 return NULL; 245 } 246 247 static int __gvt_cache_add(struct intel_vgpu *vgpu, gfn_t gfn, 248 dma_addr_t dma_addr, unsigned long size) 249 { 250 struct gvt_dma *new, *itr; 251 struct rb_node **link, *parent = NULL; 252 253 new = kzalloc(sizeof(struct gvt_dma), GFP_KERNEL); 254 if (!new) 255 return -ENOMEM; 256 257 new->vgpu = vgpu; 258 new->gfn = gfn; 259 new->dma_addr = dma_addr; 260 new->size = size; 261 kref_init(&new->ref); 262 263 /* gfn_cache maps gfn to struct gvt_dma. */ 264 link = &vgpu->gfn_cache.rb_node; 265 while (*link) { 266 parent = *link; 267 itr = rb_entry(parent, struct gvt_dma, gfn_node); 268 269 if (gfn < itr->gfn) 270 link = &parent->rb_left; 271 else 272 link = &parent->rb_right; 273 } 274 rb_link_node(&new->gfn_node, parent, link); 275 rb_insert_color(&new->gfn_node, &vgpu->gfn_cache); 276 277 /* dma_addr_cache maps dma addr to struct gvt_dma. */ 278 parent = NULL; 279 link = &vgpu->dma_addr_cache.rb_node; 280 while (*link) { 281 parent = *link; 282 itr = rb_entry(parent, struct gvt_dma, dma_addr_node); 283 284 if (dma_addr < itr->dma_addr) 285 link = &parent->rb_left; 286 else 287 link = &parent->rb_right; 288 } 289 rb_link_node(&new->dma_addr_node, parent, link); 290 rb_insert_color(&new->dma_addr_node, &vgpu->dma_addr_cache); 291 292 vgpu->nr_cache_entries++; 293 return 0; 294 } 295 296 static void __gvt_cache_remove_entry(struct intel_vgpu *vgpu, 297 struct gvt_dma *entry) 298 { 299 rb_erase(&entry->gfn_node, &vgpu->gfn_cache); 300 rb_erase(&entry->dma_addr_node, &vgpu->dma_addr_cache); 301 kfree(entry); 302 vgpu->nr_cache_entries--; 303 } 304 305 static void gvt_cache_destroy(struct intel_vgpu *vgpu) 306 { 307 struct gvt_dma *dma; 308 struct rb_node *node = NULL; 309 310 for (;;) { 311 mutex_lock(&vgpu->cache_lock); 312 node = rb_first(&vgpu->gfn_cache); 313 if (!node) { 314 mutex_unlock(&vgpu->cache_lock); 315 break; 316 } 317 dma = rb_entry(node, struct gvt_dma, gfn_node); 318 gvt_dma_unmap_page(vgpu, dma->gfn, dma->dma_addr, dma->size); 319 __gvt_cache_remove_entry(vgpu, dma); 320 mutex_unlock(&vgpu->cache_lock); 321 } 322 } 323 324 static void gvt_cache_init(struct intel_vgpu *vgpu) 325 { 326 vgpu->gfn_cache = RB_ROOT; 327 vgpu->dma_addr_cache = RB_ROOT; 328 vgpu->nr_cache_entries = 0; 329 mutex_init(&vgpu->cache_lock); 330 } 331 332 static void kvmgt_protect_table_init(struct intel_vgpu *info) 333 { 334 hash_init(info->ptable); 335 } 336 337 static void kvmgt_protect_table_destroy(struct intel_vgpu *info) 338 { 339 struct kvmgt_pgfn *p; 340 struct hlist_node *tmp; 341 int i; 342 343 hash_for_each_safe(info->ptable, i, tmp, p, hnode) { 344 hash_del(&p->hnode); 345 kfree(p); 346 } 347 } 348 349 static struct kvmgt_pgfn * 350 __kvmgt_protect_table_find(struct intel_vgpu *info, gfn_t gfn) 351 { 352 struct kvmgt_pgfn *p, *res = NULL; 353 354 lockdep_assert_held(&info->vgpu_lock); 355 356 hash_for_each_possible(info->ptable, p, hnode, gfn) { 357 if (gfn == p->gfn) { 358 res = p; 359 break; 360 } 361 } 362 363 return res; 364 } 365 366 static bool kvmgt_gfn_is_write_protected(struct intel_vgpu *info, gfn_t gfn) 367 { 368 struct kvmgt_pgfn *p; 369 370 p = __kvmgt_protect_table_find(info, gfn); 371 return !!p; 372 } 373 374 static void kvmgt_protect_table_add(struct intel_vgpu *info, gfn_t gfn) 375 { 376 struct kvmgt_pgfn *p; 377 378 if (kvmgt_gfn_is_write_protected(info, gfn)) 379 return; 380 381 p = kzalloc(sizeof(struct kvmgt_pgfn), GFP_ATOMIC); 382 if (WARN(!p, "gfn: 0x%llx\n", gfn)) 383 return; 384 385 p->gfn = gfn; 386 hash_add(info->ptable, &p->hnode, gfn); 387 } 388 389 static void kvmgt_protect_table_del(struct intel_vgpu *info, gfn_t gfn) 390 { 391 struct kvmgt_pgfn *p; 392 393 p = __kvmgt_protect_table_find(info, gfn); 394 if (p) { 395 hash_del(&p->hnode); 396 kfree(p); 397 } 398 } 399 400 static size_t intel_vgpu_reg_rw_opregion(struct intel_vgpu *vgpu, char *buf, 401 size_t count, loff_t *ppos, bool iswrite) 402 { 403 unsigned int i = VFIO_PCI_OFFSET_TO_INDEX(*ppos) - 404 VFIO_PCI_NUM_REGIONS; 405 void *base = vgpu->region[i].data; 406 loff_t pos = *ppos & VFIO_PCI_OFFSET_MASK; 407 408 409 if (pos >= vgpu->region[i].size || iswrite) { 410 gvt_vgpu_err("invalid op or offset for Intel vgpu OpRegion\n"); 411 return -EINVAL; 412 } 413 count = min(count, (size_t)(vgpu->region[i].size - pos)); 414 memcpy(buf, base + pos, count); 415 416 return count; 417 } 418 419 static void intel_vgpu_reg_release_opregion(struct intel_vgpu *vgpu, 420 struct vfio_region *region) 421 { 422 } 423 424 static const struct intel_vgpu_regops intel_vgpu_regops_opregion = { 425 .rw = intel_vgpu_reg_rw_opregion, 426 .release = intel_vgpu_reg_release_opregion, 427 }; 428 429 static bool edid_valid(const void *edid, size_t size) 430 { 431 const struct drm_edid *drm_edid; 432 bool is_valid; 433 434 drm_edid = drm_edid_alloc(edid, size); 435 is_valid = drm_edid_valid(drm_edid); 436 drm_edid_free(drm_edid); 437 438 return is_valid; 439 } 440 441 static int handle_edid_regs(struct intel_vgpu *vgpu, 442 struct vfio_edid_region *region, char *buf, 443 size_t count, u16 offset, bool is_write) 444 { 445 struct vfio_region_gfx_edid *regs = ®ion->vfio_edid_regs; 446 unsigned int data; 447 448 if (offset + count > sizeof(*regs)) 449 return -EINVAL; 450 451 if (count != 4) 452 return -EINVAL; 453 454 if (is_write) { 455 data = *((unsigned int *)buf); 456 switch (offset) { 457 case offsetof(struct vfio_region_gfx_edid, link_state): 458 if (data == VFIO_DEVICE_GFX_LINK_STATE_UP) { 459 if (!edid_valid(region->edid_blob, EDID_SIZE)) { 460 gvt_vgpu_err("invalid EDID blob\n"); 461 return -EINVAL; 462 } 463 intel_vgpu_emulate_hotplug(vgpu, true); 464 } else if (data == VFIO_DEVICE_GFX_LINK_STATE_DOWN) 465 intel_vgpu_emulate_hotplug(vgpu, false); 466 else { 467 gvt_vgpu_err("invalid EDID link state %d\n", 468 regs->link_state); 469 return -EINVAL; 470 } 471 regs->link_state = data; 472 break; 473 case offsetof(struct vfio_region_gfx_edid, edid_size): 474 if (data > regs->edid_max_size) { 475 gvt_vgpu_err("EDID size is bigger than %d!\n", 476 regs->edid_max_size); 477 return -EINVAL; 478 } 479 regs->edid_size = data; 480 break; 481 default: 482 /* read-only regs */ 483 gvt_vgpu_err("write read-only EDID region at offset %d\n", 484 offset); 485 return -EPERM; 486 } 487 } else { 488 memcpy(buf, (char *)regs + offset, count); 489 } 490 491 return count; 492 } 493 494 static int handle_edid_blob(struct vfio_edid_region *region, char *buf, 495 size_t count, u16 offset, bool is_write) 496 { 497 if (offset + count > region->vfio_edid_regs.edid_size) 498 return -EINVAL; 499 500 if (is_write) 501 memcpy(region->edid_blob + offset, buf, count); 502 else 503 memcpy(buf, region->edid_blob + offset, count); 504 505 return count; 506 } 507 508 static size_t intel_vgpu_reg_rw_edid(struct intel_vgpu *vgpu, char *buf, 509 size_t count, loff_t *ppos, bool iswrite) 510 { 511 int ret; 512 unsigned int i = VFIO_PCI_OFFSET_TO_INDEX(*ppos) - 513 VFIO_PCI_NUM_REGIONS; 514 struct vfio_edid_region *region = vgpu->region[i].data; 515 loff_t pos = *ppos & VFIO_PCI_OFFSET_MASK; 516 517 if (pos < region->vfio_edid_regs.edid_offset) { 518 ret = handle_edid_regs(vgpu, region, buf, count, pos, iswrite); 519 } else { 520 pos -= EDID_BLOB_OFFSET; 521 ret = handle_edid_blob(region, buf, count, pos, iswrite); 522 } 523 524 if (ret < 0) 525 gvt_vgpu_err("failed to access EDID region\n"); 526 527 return ret; 528 } 529 530 static void intel_vgpu_reg_release_edid(struct intel_vgpu *vgpu, 531 struct vfio_region *region) 532 { 533 kfree(region->data); 534 } 535 536 static const struct intel_vgpu_regops intel_vgpu_regops_edid = { 537 .rw = intel_vgpu_reg_rw_edid, 538 .release = intel_vgpu_reg_release_edid, 539 }; 540 541 static int intel_vgpu_register_reg(struct intel_vgpu *vgpu, 542 unsigned int type, unsigned int subtype, 543 const struct intel_vgpu_regops *ops, 544 size_t size, u32 flags, void *data) 545 { 546 struct vfio_region *region; 547 548 region = krealloc(vgpu->region, 549 (vgpu->num_regions + 1) * sizeof(*region), 550 GFP_KERNEL); 551 if (!region) 552 return -ENOMEM; 553 554 vgpu->region = region; 555 vgpu->region[vgpu->num_regions].type = type; 556 vgpu->region[vgpu->num_regions].subtype = subtype; 557 vgpu->region[vgpu->num_regions].ops = ops; 558 vgpu->region[vgpu->num_regions].size = size; 559 vgpu->region[vgpu->num_regions].flags = flags; 560 vgpu->region[vgpu->num_regions].data = data; 561 vgpu->num_regions++; 562 return 0; 563 } 564 565 int intel_gvt_set_opregion(struct intel_vgpu *vgpu) 566 { 567 void *base; 568 int ret; 569 570 /* Each vgpu has its own opregion, although VFIO would create another 571 * one later. This one is used to expose opregion to VFIO. And the 572 * other one created by VFIO later, is used by guest actually. 573 */ 574 base = vgpu_opregion(vgpu)->va; 575 if (!base) 576 return -ENOMEM; 577 578 if (memcmp(base, OPREGION_SIGNATURE, 16)) { 579 memunmap(base); 580 return -EINVAL; 581 } 582 583 ret = intel_vgpu_register_reg(vgpu, 584 PCI_VENDOR_ID_INTEL | VFIO_REGION_TYPE_PCI_VENDOR_TYPE, 585 VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION, 586 &intel_vgpu_regops_opregion, INTEL_GVT_OPREGION_SIZE, 587 VFIO_REGION_INFO_FLAG_READ, base); 588 589 return ret; 590 } 591 592 int intel_gvt_set_edid(struct intel_vgpu *vgpu, int port_num) 593 { 594 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num); 595 struct vfio_edid_region *base; 596 int ret; 597 598 base = kzalloc(sizeof(*base), GFP_KERNEL); 599 if (!base) 600 return -ENOMEM; 601 602 /* TODO: Add multi-port and EDID extension block support */ 603 base->vfio_edid_regs.edid_offset = EDID_BLOB_OFFSET; 604 base->vfio_edid_regs.edid_max_size = EDID_SIZE; 605 base->vfio_edid_regs.edid_size = EDID_SIZE; 606 base->vfio_edid_regs.max_xres = vgpu_edid_xres(port->id); 607 base->vfio_edid_regs.max_yres = vgpu_edid_yres(port->id); 608 base->edid_blob = port->edid->edid_block; 609 610 ret = intel_vgpu_register_reg(vgpu, 611 VFIO_REGION_TYPE_GFX, 612 VFIO_REGION_SUBTYPE_GFX_EDID, 613 &intel_vgpu_regops_edid, EDID_SIZE, 614 VFIO_REGION_INFO_FLAG_READ | 615 VFIO_REGION_INFO_FLAG_WRITE | 616 VFIO_REGION_INFO_FLAG_CAPS, base); 617 618 return ret; 619 } 620 621 static void intel_vgpu_dma_unmap(struct vfio_device *vfio_dev, u64 iova, 622 u64 length) 623 { 624 struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); 625 struct gvt_dma *entry; 626 u64 iov_pfn = iova >> PAGE_SHIFT; 627 u64 end_iov_pfn = iov_pfn + length / PAGE_SIZE; 628 629 mutex_lock(&vgpu->cache_lock); 630 for (; iov_pfn < end_iov_pfn; iov_pfn++) { 631 entry = __gvt_cache_find_gfn(vgpu, iov_pfn); 632 if (!entry) 633 continue; 634 635 gvt_dma_unmap_page(vgpu, entry->gfn, entry->dma_addr, 636 entry->size); 637 __gvt_cache_remove_entry(vgpu, entry); 638 } 639 mutex_unlock(&vgpu->cache_lock); 640 } 641 642 static bool __kvmgt_vgpu_exist(struct intel_vgpu *vgpu) 643 { 644 struct intel_vgpu *itr; 645 int id; 646 bool ret = false; 647 648 mutex_lock(&vgpu->gvt->lock); 649 for_each_active_vgpu(vgpu->gvt, itr, id) { 650 if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, itr->status)) 651 continue; 652 653 if (vgpu->vfio_device.kvm == itr->vfio_device.kvm) { 654 ret = true; 655 goto out; 656 } 657 } 658 out: 659 mutex_unlock(&vgpu->gvt->lock); 660 return ret; 661 } 662 663 static int intel_vgpu_open_device(struct vfio_device *vfio_dev) 664 { 665 struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); 666 int ret; 667 668 if (__kvmgt_vgpu_exist(vgpu)) 669 return -EEXIST; 670 671 vgpu->track_node.track_write = kvmgt_page_track_write; 672 vgpu->track_node.track_remove_region = kvmgt_page_track_remove_region; 673 ret = kvm_page_track_register_notifier(vgpu->vfio_device.kvm, 674 &vgpu->track_node); 675 if (ret) { 676 gvt_vgpu_err("KVM is required to use Intel vGPU\n"); 677 return ret; 678 } 679 680 set_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu->status); 681 682 debugfs_create_ulong(KVMGT_DEBUGFS_FILENAME, 0444, vgpu->debugfs, 683 &vgpu->nr_cache_entries); 684 685 intel_gvt_activate_vgpu(vgpu); 686 687 return 0; 688 } 689 690 static void intel_vgpu_release_msi_eventfd_ctx(struct intel_vgpu *vgpu) 691 { 692 struct eventfd_ctx *trigger; 693 694 trigger = vgpu->msi_trigger; 695 if (trigger) { 696 eventfd_ctx_put(trigger); 697 vgpu->msi_trigger = NULL; 698 } 699 } 700 701 static void intel_vgpu_close_device(struct vfio_device *vfio_dev) 702 { 703 struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); 704 705 intel_gvt_release_vgpu(vgpu); 706 707 clear_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu->status); 708 709 debugfs_lookup_and_remove(KVMGT_DEBUGFS_FILENAME, vgpu->debugfs); 710 711 kvm_page_track_unregister_notifier(vgpu->vfio_device.kvm, 712 &vgpu->track_node); 713 714 kvmgt_protect_table_destroy(vgpu); 715 gvt_cache_destroy(vgpu); 716 717 WARN_ON(vgpu->nr_cache_entries); 718 719 vgpu->gfn_cache = RB_ROOT; 720 vgpu->dma_addr_cache = RB_ROOT; 721 722 intel_vgpu_release_msi_eventfd_ctx(vgpu); 723 } 724 725 static u64 intel_vgpu_get_bar_addr(struct intel_vgpu *vgpu, int bar) 726 { 727 u32 start_lo, start_hi; 728 u32 mem_type; 729 730 start_lo = (*(u32 *)(vgpu->cfg_space.virtual_cfg_space + bar)) & 731 PCI_BASE_ADDRESS_MEM_MASK; 732 mem_type = (*(u32 *)(vgpu->cfg_space.virtual_cfg_space + bar)) & 733 PCI_BASE_ADDRESS_MEM_TYPE_MASK; 734 735 switch (mem_type) { 736 case PCI_BASE_ADDRESS_MEM_TYPE_64: 737 start_hi = (*(u32 *)(vgpu->cfg_space.virtual_cfg_space 738 + bar + 4)); 739 break; 740 case PCI_BASE_ADDRESS_MEM_TYPE_32: 741 case PCI_BASE_ADDRESS_MEM_TYPE_1M: 742 /* 1M mem BAR treated as 32-bit BAR */ 743 default: 744 /* mem unknown type treated as 32-bit BAR */ 745 start_hi = 0; 746 break; 747 } 748 749 return ((u64)start_hi << 32) | start_lo; 750 } 751 752 static int intel_vgpu_bar_rw(struct intel_vgpu *vgpu, int bar, u64 off, 753 void *buf, unsigned int count, bool is_write) 754 { 755 u64 bar_start = intel_vgpu_get_bar_addr(vgpu, bar); 756 int ret; 757 758 if (is_write) 759 ret = intel_vgpu_emulate_mmio_write(vgpu, 760 bar_start + off, buf, count); 761 else 762 ret = intel_vgpu_emulate_mmio_read(vgpu, 763 bar_start + off, buf, count); 764 return ret; 765 } 766 767 static inline bool intel_vgpu_in_aperture(struct intel_vgpu *vgpu, u64 off) 768 { 769 return off >= vgpu_aperture_offset(vgpu) && 770 off < vgpu_aperture_offset(vgpu) + vgpu_aperture_sz(vgpu); 771 } 772 773 static int intel_vgpu_aperture_rw(struct intel_vgpu *vgpu, u64 off, 774 void *buf, unsigned long count, bool is_write) 775 { 776 void __iomem *aperture_va; 777 778 if (!intel_vgpu_in_aperture(vgpu, off) || 779 !intel_vgpu_in_aperture(vgpu, off + count)) { 780 gvt_vgpu_err("Invalid aperture offset %llu\n", off); 781 return -EINVAL; 782 } 783 784 aperture_va = io_mapping_map_wc(&vgpu->gvt->gt->ggtt->iomap, 785 ALIGN_DOWN(off, PAGE_SIZE), 786 count + offset_in_page(off)); 787 if (!aperture_va) 788 return -EIO; 789 790 if (is_write) 791 memcpy_toio(aperture_va + offset_in_page(off), buf, count); 792 else 793 memcpy_fromio(buf, aperture_va + offset_in_page(off), count); 794 795 io_mapping_unmap(aperture_va); 796 797 return 0; 798 } 799 800 static ssize_t intel_vgpu_rw(struct intel_vgpu *vgpu, char *buf, 801 size_t count, loff_t *ppos, bool is_write) 802 { 803 unsigned int index = VFIO_PCI_OFFSET_TO_INDEX(*ppos); 804 u64 pos = *ppos & VFIO_PCI_OFFSET_MASK; 805 int ret = -EINVAL; 806 807 808 if (index >= VFIO_PCI_NUM_REGIONS + vgpu->num_regions) { 809 gvt_vgpu_err("invalid index: %u\n", index); 810 return -EINVAL; 811 } 812 813 switch (index) { 814 case VFIO_PCI_CONFIG_REGION_INDEX: 815 if (is_write) 816 ret = intel_vgpu_emulate_cfg_write(vgpu, pos, 817 buf, count); 818 else 819 ret = intel_vgpu_emulate_cfg_read(vgpu, pos, 820 buf, count); 821 break; 822 case VFIO_PCI_BAR0_REGION_INDEX: 823 ret = intel_vgpu_bar_rw(vgpu, PCI_BASE_ADDRESS_0, pos, 824 buf, count, is_write); 825 break; 826 case VFIO_PCI_BAR2_REGION_INDEX: 827 ret = intel_vgpu_aperture_rw(vgpu, pos, buf, count, is_write); 828 break; 829 case VFIO_PCI_BAR1_REGION_INDEX: 830 case VFIO_PCI_BAR3_REGION_INDEX: 831 case VFIO_PCI_BAR4_REGION_INDEX: 832 case VFIO_PCI_BAR5_REGION_INDEX: 833 case VFIO_PCI_VGA_REGION_INDEX: 834 case VFIO_PCI_ROM_REGION_INDEX: 835 break; 836 default: 837 if (index >= VFIO_PCI_NUM_REGIONS + vgpu->num_regions) 838 return -EINVAL; 839 840 index -= VFIO_PCI_NUM_REGIONS; 841 return vgpu->region[index].ops->rw(vgpu, buf, count, 842 ppos, is_write); 843 } 844 845 return ret == 0 ? count : ret; 846 } 847 848 static bool gtt_entry(struct intel_vgpu *vgpu, loff_t *ppos) 849 { 850 unsigned int index = VFIO_PCI_OFFSET_TO_INDEX(*ppos); 851 struct intel_gvt *gvt = vgpu->gvt; 852 int offset; 853 854 /* Only allow MMIO GGTT entry access */ 855 if (index != PCI_BASE_ADDRESS_0) 856 return false; 857 858 offset = (u64)(*ppos & VFIO_PCI_OFFSET_MASK) - 859 intel_vgpu_get_bar_gpa(vgpu, PCI_BASE_ADDRESS_0); 860 861 return (offset >= gvt->device_info.gtt_start_offset && 862 offset < gvt->device_info.gtt_start_offset + gvt_ggtt_sz(gvt)) ? 863 true : false; 864 } 865 866 static ssize_t intel_vgpu_read(struct vfio_device *vfio_dev, char __user *buf, 867 size_t count, loff_t *ppos) 868 { 869 struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); 870 unsigned int done = 0; 871 int ret; 872 873 while (count) { 874 size_t filled; 875 876 /* Only support GGTT entry 8 bytes read */ 877 if (count >= 8 && !(*ppos % 8) && 878 gtt_entry(vgpu, ppos)) { 879 u64 val; 880 881 ret = intel_vgpu_rw(vgpu, (char *)&val, sizeof(val), 882 ppos, false); 883 if (ret <= 0) 884 goto read_err; 885 886 if (copy_to_user(buf, &val, sizeof(val))) 887 goto read_err; 888 889 filled = 8; 890 } else if (count >= 4 && !(*ppos % 4)) { 891 u32 val; 892 893 ret = intel_vgpu_rw(vgpu, (char *)&val, sizeof(val), 894 ppos, false); 895 if (ret <= 0) 896 goto read_err; 897 898 if (copy_to_user(buf, &val, sizeof(val))) 899 goto read_err; 900 901 filled = 4; 902 } else if (count >= 2 && !(*ppos % 2)) { 903 u16 val; 904 905 ret = intel_vgpu_rw(vgpu, (char *)&val, sizeof(val), 906 ppos, false); 907 if (ret <= 0) 908 goto read_err; 909 910 if (copy_to_user(buf, &val, sizeof(val))) 911 goto read_err; 912 913 filled = 2; 914 } else { 915 u8 val; 916 917 ret = intel_vgpu_rw(vgpu, &val, sizeof(val), ppos, 918 false); 919 if (ret <= 0) 920 goto read_err; 921 922 if (copy_to_user(buf, &val, sizeof(val))) 923 goto read_err; 924 925 filled = 1; 926 } 927 928 count -= filled; 929 done += filled; 930 *ppos += filled; 931 buf += filled; 932 } 933 934 return done; 935 936 read_err: 937 return -EFAULT; 938 } 939 940 static ssize_t intel_vgpu_write(struct vfio_device *vfio_dev, 941 const char __user *buf, 942 size_t count, loff_t *ppos) 943 { 944 struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); 945 unsigned int done = 0; 946 int ret; 947 948 while (count) { 949 size_t filled; 950 951 /* Only support GGTT entry 8 bytes write */ 952 if (count >= 8 && !(*ppos % 8) && 953 gtt_entry(vgpu, ppos)) { 954 u64 val; 955 956 if (copy_from_user(&val, buf, sizeof(val))) 957 goto write_err; 958 959 ret = intel_vgpu_rw(vgpu, (char *)&val, sizeof(val), 960 ppos, true); 961 if (ret <= 0) 962 goto write_err; 963 964 filled = 8; 965 } else if (count >= 4 && !(*ppos % 4)) { 966 u32 val; 967 968 if (copy_from_user(&val, buf, sizeof(val))) 969 goto write_err; 970 971 ret = intel_vgpu_rw(vgpu, (char *)&val, sizeof(val), 972 ppos, true); 973 if (ret <= 0) 974 goto write_err; 975 976 filled = 4; 977 } else if (count >= 2 && !(*ppos % 2)) { 978 u16 val; 979 980 if (copy_from_user(&val, buf, sizeof(val))) 981 goto write_err; 982 983 ret = intel_vgpu_rw(vgpu, (char *)&val, 984 sizeof(val), ppos, true); 985 if (ret <= 0) 986 goto write_err; 987 988 filled = 2; 989 } else { 990 u8 val; 991 992 if (copy_from_user(&val, buf, sizeof(val))) 993 goto write_err; 994 995 ret = intel_vgpu_rw(vgpu, &val, sizeof(val), 996 ppos, true); 997 if (ret <= 0) 998 goto write_err; 999 1000 filled = 1; 1001 } 1002 1003 count -= filled; 1004 done += filled; 1005 *ppos += filled; 1006 buf += filled; 1007 } 1008 1009 return done; 1010 write_err: 1011 return -EFAULT; 1012 } 1013 1014 static int intel_vgpu_mmap(struct vfio_device *vfio_dev, 1015 struct vm_area_struct *vma) 1016 { 1017 struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); 1018 unsigned int index; 1019 u64 virtaddr; 1020 unsigned long req_size, pgoff, req_start; 1021 pgprot_t pg_prot; 1022 1023 index = vma->vm_pgoff >> (VFIO_PCI_OFFSET_SHIFT - PAGE_SHIFT); 1024 if (index >= VFIO_PCI_ROM_REGION_INDEX) 1025 return -EINVAL; 1026 1027 if (vma->vm_end < vma->vm_start) 1028 return -EINVAL; 1029 if ((vma->vm_flags & VM_SHARED) == 0) 1030 return -EINVAL; 1031 if (index != VFIO_PCI_BAR2_REGION_INDEX) 1032 return -EINVAL; 1033 1034 pg_prot = vma->vm_page_prot; 1035 virtaddr = vma->vm_start; 1036 req_size = vma->vm_end - vma->vm_start; 1037 pgoff = vma->vm_pgoff & 1038 ((1U << (VFIO_PCI_OFFSET_SHIFT - PAGE_SHIFT)) - 1); 1039 req_start = pgoff << PAGE_SHIFT; 1040 1041 if (!intel_vgpu_in_aperture(vgpu, req_start)) 1042 return -EINVAL; 1043 if (req_start + req_size > 1044 vgpu_aperture_offset(vgpu) + vgpu_aperture_sz(vgpu)) 1045 return -EINVAL; 1046 1047 pgoff = (gvt_aperture_pa_base(vgpu->gvt) >> PAGE_SHIFT) + pgoff; 1048 1049 return remap_pfn_range(vma, virtaddr, pgoff, req_size, pg_prot); 1050 } 1051 1052 static int intel_vgpu_get_irq_count(struct intel_vgpu *vgpu, int type) 1053 { 1054 if (type == VFIO_PCI_INTX_IRQ_INDEX || type == VFIO_PCI_MSI_IRQ_INDEX) 1055 return 1; 1056 1057 return 0; 1058 } 1059 1060 static int intel_vgpu_set_intx_mask(struct intel_vgpu *vgpu, 1061 unsigned int index, unsigned int start, 1062 unsigned int count, u32 flags, 1063 void *data) 1064 { 1065 return 0; 1066 } 1067 1068 static int intel_vgpu_set_intx_unmask(struct intel_vgpu *vgpu, 1069 unsigned int index, unsigned int start, 1070 unsigned int count, u32 flags, void *data) 1071 { 1072 return 0; 1073 } 1074 1075 static int intel_vgpu_set_intx_trigger(struct intel_vgpu *vgpu, 1076 unsigned int index, unsigned int start, unsigned int count, 1077 u32 flags, void *data) 1078 { 1079 return 0; 1080 } 1081 1082 static int intel_vgpu_set_msi_trigger(struct intel_vgpu *vgpu, 1083 unsigned int index, unsigned int start, unsigned int count, 1084 u32 flags, void *data) 1085 { 1086 struct eventfd_ctx *trigger; 1087 1088 if (flags & VFIO_IRQ_SET_DATA_EVENTFD) { 1089 int fd = *(int *)data; 1090 1091 trigger = eventfd_ctx_fdget(fd); 1092 if (IS_ERR(trigger)) { 1093 gvt_vgpu_err("eventfd_ctx_fdget failed\n"); 1094 return PTR_ERR(trigger); 1095 } 1096 vgpu->msi_trigger = trigger; 1097 } else if ((flags & VFIO_IRQ_SET_DATA_NONE) && !count) 1098 intel_vgpu_release_msi_eventfd_ctx(vgpu); 1099 1100 return 0; 1101 } 1102 1103 static int intel_vgpu_set_irqs(struct intel_vgpu *vgpu, u32 flags, 1104 unsigned int index, unsigned int start, unsigned int count, 1105 void *data) 1106 { 1107 int (*func)(struct intel_vgpu *vgpu, unsigned int index, 1108 unsigned int start, unsigned int count, u32 flags, 1109 void *data) = NULL; 1110 1111 switch (index) { 1112 case VFIO_PCI_INTX_IRQ_INDEX: 1113 switch (flags & VFIO_IRQ_SET_ACTION_TYPE_MASK) { 1114 case VFIO_IRQ_SET_ACTION_MASK: 1115 func = intel_vgpu_set_intx_mask; 1116 break; 1117 case VFIO_IRQ_SET_ACTION_UNMASK: 1118 func = intel_vgpu_set_intx_unmask; 1119 break; 1120 case VFIO_IRQ_SET_ACTION_TRIGGER: 1121 func = intel_vgpu_set_intx_trigger; 1122 break; 1123 } 1124 break; 1125 case VFIO_PCI_MSI_IRQ_INDEX: 1126 switch (flags & VFIO_IRQ_SET_ACTION_TYPE_MASK) { 1127 case VFIO_IRQ_SET_ACTION_MASK: 1128 case VFIO_IRQ_SET_ACTION_UNMASK: 1129 /* XXX Need masking support exported */ 1130 break; 1131 case VFIO_IRQ_SET_ACTION_TRIGGER: 1132 func = intel_vgpu_set_msi_trigger; 1133 break; 1134 } 1135 break; 1136 } 1137 1138 if (!func) 1139 return -ENOTTY; 1140 1141 return func(vgpu, index, start, count, flags, data); 1142 } 1143 1144 static long intel_vgpu_ioctl(struct vfio_device *vfio_dev, unsigned int cmd, 1145 unsigned long arg) 1146 { 1147 struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); 1148 unsigned long minsz; 1149 1150 gvt_dbg_core("vgpu%d ioctl, cmd: %d\n", vgpu->id, cmd); 1151 1152 if (cmd == VFIO_DEVICE_GET_INFO) { 1153 struct vfio_device_info info; 1154 1155 minsz = offsetofend(struct vfio_device_info, num_irqs); 1156 1157 if (copy_from_user(&info, (void __user *)arg, minsz)) 1158 return -EFAULT; 1159 1160 if (info.argsz < minsz) 1161 return -EINVAL; 1162 1163 info.flags = VFIO_DEVICE_FLAGS_PCI; 1164 info.flags |= VFIO_DEVICE_FLAGS_RESET; 1165 info.num_regions = VFIO_PCI_NUM_REGIONS + 1166 vgpu->num_regions; 1167 info.num_irqs = VFIO_PCI_NUM_IRQS; 1168 1169 return copy_to_user((void __user *)arg, &info, minsz) ? 1170 -EFAULT : 0; 1171 1172 } else if (cmd == VFIO_DEVICE_GET_REGION_INFO) { 1173 struct vfio_region_info info; 1174 struct vfio_info_cap caps = { .buf = NULL, .size = 0 }; 1175 unsigned int i; 1176 int ret; 1177 struct vfio_region_info_cap_sparse_mmap *sparse = NULL; 1178 int nr_areas = 1; 1179 int cap_type_id; 1180 1181 minsz = offsetofend(struct vfio_region_info, offset); 1182 1183 if (copy_from_user(&info, (void __user *)arg, minsz)) 1184 return -EFAULT; 1185 1186 if (info.argsz < minsz) 1187 return -EINVAL; 1188 1189 switch (info.index) { 1190 case VFIO_PCI_CONFIG_REGION_INDEX: 1191 info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); 1192 info.size = vgpu->gvt->device_info.cfg_space_size; 1193 info.flags = VFIO_REGION_INFO_FLAG_READ | 1194 VFIO_REGION_INFO_FLAG_WRITE; 1195 break; 1196 case VFIO_PCI_BAR0_REGION_INDEX: 1197 info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); 1198 info.size = vgpu->cfg_space.bar[info.index].size; 1199 if (!info.size) { 1200 info.flags = 0; 1201 break; 1202 } 1203 1204 info.flags = VFIO_REGION_INFO_FLAG_READ | 1205 VFIO_REGION_INFO_FLAG_WRITE; 1206 break; 1207 case VFIO_PCI_BAR1_REGION_INDEX: 1208 info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); 1209 info.size = 0; 1210 info.flags = 0; 1211 break; 1212 case VFIO_PCI_BAR2_REGION_INDEX: 1213 info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); 1214 info.flags = VFIO_REGION_INFO_FLAG_CAPS | 1215 VFIO_REGION_INFO_FLAG_MMAP | 1216 VFIO_REGION_INFO_FLAG_READ | 1217 VFIO_REGION_INFO_FLAG_WRITE; 1218 info.size = gvt_aperture_sz(vgpu->gvt); 1219 1220 sparse = kzalloc(struct_size(sparse, areas, nr_areas), 1221 GFP_KERNEL); 1222 if (!sparse) 1223 return -ENOMEM; 1224 1225 sparse->header.id = VFIO_REGION_INFO_CAP_SPARSE_MMAP; 1226 sparse->header.version = 1; 1227 sparse->nr_areas = nr_areas; 1228 cap_type_id = VFIO_REGION_INFO_CAP_SPARSE_MMAP; 1229 sparse->areas[0].offset = 1230 PAGE_ALIGN(vgpu_aperture_offset(vgpu)); 1231 sparse->areas[0].size = vgpu_aperture_sz(vgpu); 1232 break; 1233 1234 case VFIO_PCI_BAR3_REGION_INDEX ... VFIO_PCI_BAR5_REGION_INDEX: 1235 info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); 1236 info.size = 0; 1237 info.flags = 0; 1238 1239 gvt_dbg_core("get region info bar:%d\n", info.index); 1240 break; 1241 1242 case VFIO_PCI_ROM_REGION_INDEX: 1243 case VFIO_PCI_VGA_REGION_INDEX: 1244 info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); 1245 info.size = 0; 1246 info.flags = 0; 1247 1248 gvt_dbg_core("get region info index:%d\n", info.index); 1249 break; 1250 default: 1251 { 1252 struct vfio_region_info_cap_type cap_type = { 1253 .header.id = VFIO_REGION_INFO_CAP_TYPE, 1254 .header.version = 1 }; 1255 1256 if (info.index >= VFIO_PCI_NUM_REGIONS + 1257 vgpu->num_regions) 1258 return -EINVAL; 1259 info.index = 1260 array_index_nospec(info.index, 1261 VFIO_PCI_NUM_REGIONS + 1262 vgpu->num_regions); 1263 1264 i = info.index - VFIO_PCI_NUM_REGIONS; 1265 1266 info.offset = 1267 VFIO_PCI_INDEX_TO_OFFSET(info.index); 1268 info.size = vgpu->region[i].size; 1269 info.flags = vgpu->region[i].flags; 1270 1271 cap_type.type = vgpu->region[i].type; 1272 cap_type.subtype = vgpu->region[i].subtype; 1273 1274 ret = vfio_info_add_capability(&caps, 1275 &cap_type.header, 1276 sizeof(cap_type)); 1277 if (ret) 1278 return ret; 1279 } 1280 } 1281 1282 if ((info.flags & VFIO_REGION_INFO_FLAG_CAPS) && sparse) { 1283 switch (cap_type_id) { 1284 case VFIO_REGION_INFO_CAP_SPARSE_MMAP: 1285 ret = vfio_info_add_capability(&caps, 1286 &sparse->header, 1287 struct_size(sparse, areas, 1288 sparse->nr_areas)); 1289 if (ret) { 1290 kfree(sparse); 1291 return ret; 1292 } 1293 break; 1294 default: 1295 kfree(sparse); 1296 return -EINVAL; 1297 } 1298 } 1299 1300 if (caps.size) { 1301 info.flags |= VFIO_REGION_INFO_FLAG_CAPS; 1302 if (info.argsz < sizeof(info) + caps.size) { 1303 info.argsz = sizeof(info) + caps.size; 1304 info.cap_offset = 0; 1305 } else { 1306 vfio_info_cap_shift(&caps, sizeof(info)); 1307 if (copy_to_user((void __user *)arg + 1308 sizeof(info), caps.buf, 1309 caps.size)) { 1310 kfree(caps.buf); 1311 kfree(sparse); 1312 return -EFAULT; 1313 } 1314 info.cap_offset = sizeof(info); 1315 } 1316 1317 kfree(caps.buf); 1318 } 1319 1320 kfree(sparse); 1321 return copy_to_user((void __user *)arg, &info, minsz) ? 1322 -EFAULT : 0; 1323 } else if (cmd == VFIO_DEVICE_GET_IRQ_INFO) { 1324 struct vfio_irq_info info; 1325 1326 minsz = offsetofend(struct vfio_irq_info, count); 1327 1328 if (copy_from_user(&info, (void __user *)arg, minsz)) 1329 return -EFAULT; 1330 1331 if (info.argsz < minsz || info.index >= VFIO_PCI_NUM_IRQS) 1332 return -EINVAL; 1333 1334 switch (info.index) { 1335 case VFIO_PCI_INTX_IRQ_INDEX: 1336 case VFIO_PCI_MSI_IRQ_INDEX: 1337 break; 1338 default: 1339 return -EINVAL; 1340 } 1341 1342 info.flags = VFIO_IRQ_INFO_EVENTFD; 1343 1344 info.count = intel_vgpu_get_irq_count(vgpu, info.index); 1345 1346 if (info.index == VFIO_PCI_INTX_IRQ_INDEX) 1347 info.flags |= (VFIO_IRQ_INFO_MASKABLE | 1348 VFIO_IRQ_INFO_AUTOMASKED); 1349 else 1350 info.flags |= VFIO_IRQ_INFO_NORESIZE; 1351 1352 return copy_to_user((void __user *)arg, &info, minsz) ? 1353 -EFAULT : 0; 1354 } else if (cmd == VFIO_DEVICE_SET_IRQS) { 1355 struct vfio_irq_set hdr; 1356 u8 *data = NULL; 1357 int ret = 0; 1358 size_t data_size = 0; 1359 1360 minsz = offsetofend(struct vfio_irq_set, count); 1361 1362 if (copy_from_user(&hdr, (void __user *)arg, minsz)) 1363 return -EFAULT; 1364 1365 if (!(hdr.flags & VFIO_IRQ_SET_DATA_NONE)) { 1366 int max = intel_vgpu_get_irq_count(vgpu, hdr.index); 1367 1368 ret = vfio_set_irqs_validate_and_prepare(&hdr, max, 1369 VFIO_PCI_NUM_IRQS, &data_size); 1370 if (ret) { 1371 gvt_vgpu_err("intel:vfio_set_irqs_validate_and_prepare failed\n"); 1372 return -EINVAL; 1373 } 1374 if (data_size) { 1375 data = memdup_user((void __user *)(arg + minsz), 1376 data_size); 1377 if (IS_ERR(data)) 1378 return PTR_ERR(data); 1379 } 1380 } 1381 1382 ret = intel_vgpu_set_irqs(vgpu, hdr.flags, hdr.index, 1383 hdr.start, hdr.count, data); 1384 kfree(data); 1385 1386 return ret; 1387 } else if (cmd == VFIO_DEVICE_RESET) { 1388 intel_gvt_reset_vgpu(vgpu); 1389 return 0; 1390 } else if (cmd == VFIO_DEVICE_QUERY_GFX_PLANE) { 1391 struct vfio_device_gfx_plane_info dmabuf = {}; 1392 int ret = 0; 1393 1394 minsz = offsetofend(struct vfio_device_gfx_plane_info, 1395 dmabuf_id); 1396 if (copy_from_user(&dmabuf, (void __user *)arg, minsz)) 1397 return -EFAULT; 1398 if (dmabuf.argsz < minsz) 1399 return -EINVAL; 1400 1401 ret = intel_vgpu_query_plane(vgpu, &dmabuf); 1402 if (ret != 0) 1403 return ret; 1404 1405 return copy_to_user((void __user *)arg, &dmabuf, minsz) ? 1406 -EFAULT : 0; 1407 } else if (cmd == VFIO_DEVICE_GET_GFX_DMABUF) { 1408 __u32 dmabuf_id; 1409 1410 if (get_user(dmabuf_id, (__u32 __user *)arg)) 1411 return -EFAULT; 1412 return intel_vgpu_get_dmabuf(vgpu, dmabuf_id); 1413 } 1414 1415 return -ENOTTY; 1416 } 1417 1418 static ssize_t 1419 vgpu_id_show(struct device *dev, struct device_attribute *attr, 1420 char *buf) 1421 { 1422 struct intel_vgpu *vgpu = dev_get_drvdata(dev); 1423 1424 return sprintf(buf, "%d\n", vgpu->id); 1425 } 1426 1427 static DEVICE_ATTR_RO(vgpu_id); 1428 1429 static struct attribute *intel_vgpu_attrs[] = { 1430 &dev_attr_vgpu_id.attr, 1431 NULL 1432 }; 1433 1434 static const struct attribute_group intel_vgpu_group = { 1435 .name = "intel_vgpu", 1436 .attrs = intel_vgpu_attrs, 1437 }; 1438 1439 static const struct attribute_group *intel_vgpu_groups[] = { 1440 &intel_vgpu_group, 1441 NULL, 1442 }; 1443 1444 static int intel_vgpu_init_dev(struct vfio_device *vfio_dev) 1445 { 1446 struct mdev_device *mdev = to_mdev_device(vfio_dev->dev); 1447 struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); 1448 struct intel_vgpu_type *type = 1449 container_of(mdev->type, struct intel_vgpu_type, type); 1450 int ret; 1451 1452 vgpu->gvt = kdev_to_i915(mdev->type->parent->dev)->gvt; 1453 ret = intel_gvt_create_vgpu(vgpu, type->conf); 1454 if (ret) 1455 return ret; 1456 1457 kvmgt_protect_table_init(vgpu); 1458 gvt_cache_init(vgpu); 1459 1460 return 0; 1461 } 1462 1463 static void intel_vgpu_release_dev(struct vfio_device *vfio_dev) 1464 { 1465 struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); 1466 1467 intel_gvt_destroy_vgpu(vgpu); 1468 } 1469 1470 static const struct vfio_device_ops intel_vgpu_dev_ops = { 1471 .init = intel_vgpu_init_dev, 1472 .release = intel_vgpu_release_dev, 1473 .open_device = intel_vgpu_open_device, 1474 .close_device = intel_vgpu_close_device, 1475 .read = intel_vgpu_read, 1476 .write = intel_vgpu_write, 1477 .mmap = intel_vgpu_mmap, 1478 .ioctl = intel_vgpu_ioctl, 1479 .dma_unmap = intel_vgpu_dma_unmap, 1480 .bind_iommufd = vfio_iommufd_emulated_bind, 1481 .unbind_iommufd = vfio_iommufd_emulated_unbind, 1482 .attach_ioas = vfio_iommufd_emulated_attach_ioas, 1483 .detach_ioas = vfio_iommufd_emulated_detach_ioas, 1484 }; 1485 1486 static int intel_vgpu_probe(struct mdev_device *mdev) 1487 { 1488 struct intel_vgpu *vgpu; 1489 int ret; 1490 1491 vgpu = vfio_alloc_device(intel_vgpu, vfio_device, &mdev->dev, 1492 &intel_vgpu_dev_ops); 1493 if (IS_ERR(vgpu)) { 1494 gvt_err("failed to create intel vgpu: %ld\n", PTR_ERR(vgpu)); 1495 return PTR_ERR(vgpu); 1496 } 1497 1498 dev_set_drvdata(&mdev->dev, vgpu); 1499 ret = vfio_register_emulated_iommu_dev(&vgpu->vfio_device); 1500 if (ret) 1501 goto out_put_vdev; 1502 1503 gvt_dbg_core("intel_vgpu_create succeeded for mdev: %s\n", 1504 dev_name(mdev_dev(mdev))); 1505 return 0; 1506 1507 out_put_vdev: 1508 vfio_put_device(&vgpu->vfio_device); 1509 return ret; 1510 } 1511 1512 static void intel_vgpu_remove(struct mdev_device *mdev) 1513 { 1514 struct intel_vgpu *vgpu = dev_get_drvdata(&mdev->dev); 1515 1516 vfio_unregister_group_dev(&vgpu->vfio_device); 1517 vfio_put_device(&vgpu->vfio_device); 1518 } 1519 1520 static unsigned int intel_vgpu_get_available(struct mdev_type *mtype) 1521 { 1522 struct intel_vgpu_type *type = 1523 container_of(mtype, struct intel_vgpu_type, type); 1524 struct intel_gvt *gvt = kdev_to_i915(mtype->parent->dev)->gvt; 1525 unsigned int low_gm_avail, high_gm_avail, fence_avail; 1526 1527 mutex_lock(&gvt->lock); 1528 low_gm_avail = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE - 1529 gvt->gm.vgpu_allocated_low_gm_size; 1530 high_gm_avail = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE - 1531 gvt->gm.vgpu_allocated_high_gm_size; 1532 fence_avail = gvt_fence_sz(gvt) - HOST_FENCE - 1533 gvt->fence.vgpu_allocated_fence_num; 1534 mutex_unlock(&gvt->lock); 1535 1536 return min3(low_gm_avail / type->conf->low_mm, 1537 high_gm_avail / type->conf->high_mm, 1538 fence_avail / type->conf->fence); 1539 } 1540 1541 static struct mdev_driver intel_vgpu_mdev_driver = { 1542 .device_api = VFIO_DEVICE_API_PCI_STRING, 1543 .driver = { 1544 .name = "intel_vgpu_mdev", 1545 .owner = THIS_MODULE, 1546 .dev_groups = intel_vgpu_groups, 1547 }, 1548 .probe = intel_vgpu_probe, 1549 .remove = intel_vgpu_remove, 1550 .get_available = intel_vgpu_get_available, 1551 .show_description = intel_vgpu_show_description, 1552 }; 1553 1554 int intel_gvt_page_track_add(struct intel_vgpu *info, u64 gfn) 1555 { 1556 int r; 1557 1558 if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, info->status)) 1559 return -ESRCH; 1560 1561 if (kvmgt_gfn_is_write_protected(info, gfn)) 1562 return 0; 1563 1564 r = kvm_write_track_add_gfn(info->vfio_device.kvm, gfn); 1565 if (r) 1566 return r; 1567 1568 kvmgt_protect_table_add(info, gfn); 1569 return 0; 1570 } 1571 1572 int intel_gvt_page_track_remove(struct intel_vgpu *info, u64 gfn) 1573 { 1574 int r; 1575 1576 if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, info->status)) 1577 return -ESRCH; 1578 1579 if (!kvmgt_gfn_is_write_protected(info, gfn)) 1580 return 0; 1581 1582 r = kvm_write_track_remove_gfn(info->vfio_device.kvm, gfn); 1583 if (r) 1584 return r; 1585 1586 kvmgt_protect_table_del(info, gfn); 1587 return 0; 1588 } 1589 1590 static void kvmgt_page_track_write(gpa_t gpa, const u8 *val, int len, 1591 struct kvm_page_track_notifier_node *node) 1592 { 1593 struct intel_vgpu *info = 1594 container_of(node, struct intel_vgpu, track_node); 1595 1596 mutex_lock(&info->vgpu_lock); 1597 1598 if (kvmgt_gfn_is_write_protected(info, gpa >> PAGE_SHIFT)) 1599 intel_vgpu_page_track_handler(info, gpa, 1600 (void *)val, len); 1601 1602 mutex_unlock(&info->vgpu_lock); 1603 } 1604 1605 static void kvmgt_page_track_remove_region(gfn_t gfn, unsigned long nr_pages, 1606 struct kvm_page_track_notifier_node *node) 1607 { 1608 unsigned long i; 1609 struct intel_vgpu *info = 1610 container_of(node, struct intel_vgpu, track_node); 1611 1612 mutex_lock(&info->vgpu_lock); 1613 1614 for (i = 0; i < nr_pages; i++) { 1615 if (kvmgt_gfn_is_write_protected(info, gfn + i)) 1616 kvmgt_protect_table_del(info, gfn + i); 1617 } 1618 1619 mutex_unlock(&info->vgpu_lock); 1620 } 1621 1622 void intel_vgpu_detach_regions(struct intel_vgpu *vgpu) 1623 { 1624 int i; 1625 1626 if (!vgpu->region) 1627 return; 1628 1629 for (i = 0; i < vgpu->num_regions; i++) 1630 if (vgpu->region[i].ops->release) 1631 vgpu->region[i].ops->release(vgpu, 1632 &vgpu->region[i]); 1633 vgpu->num_regions = 0; 1634 kfree(vgpu->region); 1635 vgpu->region = NULL; 1636 } 1637 1638 int intel_gvt_dma_map_guest_page(struct intel_vgpu *vgpu, unsigned long gfn, 1639 unsigned long size, dma_addr_t *dma_addr) 1640 { 1641 struct gvt_dma *entry; 1642 int ret; 1643 1644 if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu->status)) 1645 return -EINVAL; 1646 1647 mutex_lock(&vgpu->cache_lock); 1648 1649 entry = __gvt_cache_find_gfn(vgpu, gfn); 1650 if (!entry) { 1651 ret = gvt_dma_map_page(vgpu, gfn, dma_addr, size); 1652 if (ret) 1653 goto err_unlock; 1654 1655 ret = __gvt_cache_add(vgpu, gfn, *dma_addr, size); 1656 if (ret) 1657 goto err_unmap; 1658 } else if (entry->size != size) { 1659 /* the same gfn with different size: unmap and re-map */ 1660 gvt_dma_unmap_page(vgpu, gfn, entry->dma_addr, entry->size); 1661 __gvt_cache_remove_entry(vgpu, entry); 1662 1663 ret = gvt_dma_map_page(vgpu, gfn, dma_addr, size); 1664 if (ret) 1665 goto err_unlock; 1666 1667 ret = __gvt_cache_add(vgpu, gfn, *dma_addr, size); 1668 if (ret) 1669 goto err_unmap; 1670 } else { 1671 kref_get(&entry->ref); 1672 *dma_addr = entry->dma_addr; 1673 } 1674 1675 mutex_unlock(&vgpu->cache_lock); 1676 return 0; 1677 1678 err_unmap: 1679 gvt_dma_unmap_page(vgpu, gfn, *dma_addr, size); 1680 err_unlock: 1681 mutex_unlock(&vgpu->cache_lock); 1682 return ret; 1683 } 1684 1685 int intel_gvt_dma_pin_guest_page(struct intel_vgpu *vgpu, dma_addr_t dma_addr) 1686 { 1687 struct gvt_dma *entry; 1688 int ret = 0; 1689 1690 if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu->status)) 1691 return -EINVAL; 1692 1693 mutex_lock(&vgpu->cache_lock); 1694 entry = __gvt_cache_find_dma_addr(vgpu, dma_addr); 1695 if (entry) 1696 kref_get(&entry->ref); 1697 else 1698 ret = -ENOMEM; 1699 mutex_unlock(&vgpu->cache_lock); 1700 1701 return ret; 1702 } 1703 1704 static void __gvt_dma_release(struct kref *ref) 1705 { 1706 struct gvt_dma *entry = container_of(ref, typeof(*entry), ref); 1707 1708 gvt_dma_unmap_page(entry->vgpu, entry->gfn, entry->dma_addr, 1709 entry->size); 1710 __gvt_cache_remove_entry(entry->vgpu, entry); 1711 } 1712 1713 void intel_gvt_dma_unmap_guest_page(struct intel_vgpu *vgpu, 1714 dma_addr_t dma_addr) 1715 { 1716 struct gvt_dma *entry; 1717 1718 if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu->status)) 1719 return; 1720 1721 mutex_lock(&vgpu->cache_lock); 1722 entry = __gvt_cache_find_dma_addr(vgpu, dma_addr); 1723 if (entry) 1724 kref_put(&entry->ref, __gvt_dma_release); 1725 mutex_unlock(&vgpu->cache_lock); 1726 } 1727 1728 static void init_device_info(struct intel_gvt *gvt) 1729 { 1730 struct intel_gvt_device_info *info = &gvt->device_info; 1731 struct pci_dev *pdev = to_pci_dev(gvt->gt->i915->drm.dev); 1732 1733 info->max_support_vgpus = 8; 1734 info->cfg_space_size = PCI_CFG_SPACE_EXP_SIZE; 1735 info->mmio_size = 2 * 1024 * 1024; 1736 info->mmio_bar = 0; 1737 info->gtt_start_offset = 8 * 1024 * 1024; 1738 info->gtt_entry_size = 8; 1739 info->gtt_entry_size_shift = 3; 1740 info->gmadr_bytes_in_cmd = 8; 1741 info->max_surface_size = 36 * 1024 * 1024; 1742 info->msi_cap_offset = pdev->msi_cap; 1743 } 1744 1745 static void intel_gvt_test_and_emulate_vblank(struct intel_gvt *gvt) 1746 { 1747 struct intel_vgpu *vgpu; 1748 int id; 1749 1750 mutex_lock(&gvt->lock); 1751 idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) { 1752 if (test_and_clear_bit(INTEL_GVT_REQUEST_EMULATE_VBLANK + id, 1753 (void *)&gvt->service_request)) { 1754 if (test_bit(INTEL_VGPU_STATUS_ACTIVE, vgpu->status)) 1755 intel_vgpu_emulate_vblank(vgpu); 1756 } 1757 } 1758 mutex_unlock(&gvt->lock); 1759 } 1760 1761 static int gvt_service_thread(void *data) 1762 { 1763 struct intel_gvt *gvt = (struct intel_gvt *)data; 1764 int ret; 1765 1766 gvt_dbg_core("service thread start\n"); 1767 1768 while (!kthread_should_stop()) { 1769 ret = wait_event_interruptible(gvt->service_thread_wq, 1770 kthread_should_stop() || gvt->service_request); 1771 1772 if (kthread_should_stop()) 1773 break; 1774 1775 if (WARN_ONCE(ret, "service thread is waken up by signal.\n")) 1776 continue; 1777 1778 intel_gvt_test_and_emulate_vblank(gvt); 1779 1780 if (test_bit(INTEL_GVT_REQUEST_SCHED, 1781 (void *)&gvt->service_request) || 1782 test_bit(INTEL_GVT_REQUEST_EVENT_SCHED, 1783 (void *)&gvt->service_request)) { 1784 intel_gvt_schedule(gvt); 1785 } 1786 } 1787 1788 return 0; 1789 } 1790 1791 static void clean_service_thread(struct intel_gvt *gvt) 1792 { 1793 kthread_stop(gvt->service_thread); 1794 } 1795 1796 static int init_service_thread(struct intel_gvt *gvt) 1797 { 1798 init_waitqueue_head(&gvt->service_thread_wq); 1799 1800 gvt->service_thread = kthread_run(gvt_service_thread, 1801 gvt, "gvt_service_thread"); 1802 if (IS_ERR(gvt->service_thread)) { 1803 gvt_err("fail to start service thread.\n"); 1804 return PTR_ERR(gvt->service_thread); 1805 } 1806 return 0; 1807 } 1808 1809 /** 1810 * intel_gvt_clean_device - clean a GVT device 1811 * @i915: i915 private 1812 * 1813 * This function is called at the driver unloading stage, to free the 1814 * resources owned by a GVT device. 1815 * 1816 */ 1817 static void intel_gvt_clean_device(struct drm_i915_private *i915) 1818 { 1819 struct intel_gvt *gvt = fetch_and_zero(&i915->gvt); 1820 1821 if (drm_WARN_ON(&i915->drm, !gvt)) 1822 return; 1823 1824 mdev_unregister_parent(&gvt->parent); 1825 intel_gvt_destroy_idle_vgpu(gvt->idle_vgpu); 1826 intel_gvt_clean_vgpu_types(gvt); 1827 1828 intel_gvt_debugfs_clean(gvt); 1829 clean_service_thread(gvt); 1830 intel_gvt_clean_cmd_parser(gvt); 1831 intel_gvt_clean_sched_policy(gvt); 1832 intel_gvt_clean_workload_scheduler(gvt); 1833 intel_gvt_clean_gtt(gvt); 1834 intel_gvt_free_firmware(gvt); 1835 intel_gvt_clean_mmio_info(gvt); 1836 idr_destroy(&gvt->vgpu_idr); 1837 1838 kfree(i915->gvt); 1839 } 1840 1841 /** 1842 * intel_gvt_init_device - initialize a GVT device 1843 * @i915: drm i915 private data 1844 * 1845 * This function is called at the initialization stage, to initialize 1846 * necessary GVT components. 1847 * 1848 * Returns: 1849 * Zero on success, negative error code if failed. 1850 * 1851 */ 1852 static int intel_gvt_init_device(struct drm_i915_private *i915) 1853 { 1854 struct intel_gvt *gvt; 1855 struct intel_vgpu *vgpu; 1856 int ret; 1857 1858 if (drm_WARN_ON(&i915->drm, i915->gvt)) 1859 return -EEXIST; 1860 1861 gvt = kzalloc(sizeof(struct intel_gvt), GFP_KERNEL); 1862 if (!gvt) 1863 return -ENOMEM; 1864 1865 gvt_dbg_core("init gvt device\n"); 1866 1867 idr_init_base(&gvt->vgpu_idr, 1); 1868 spin_lock_init(&gvt->scheduler.mmio_context_lock); 1869 mutex_init(&gvt->lock); 1870 mutex_init(&gvt->sched_lock); 1871 gvt->gt = to_gt(i915); 1872 i915->gvt = gvt; 1873 1874 init_device_info(gvt); 1875 1876 ret = intel_gvt_setup_mmio_info(gvt); 1877 if (ret) 1878 goto out_clean_idr; 1879 1880 intel_gvt_init_engine_mmio_context(gvt); 1881 1882 ret = intel_gvt_load_firmware(gvt); 1883 if (ret) 1884 goto out_clean_mmio_info; 1885 1886 ret = intel_gvt_init_irq(gvt); 1887 if (ret) 1888 goto out_free_firmware; 1889 1890 ret = intel_gvt_init_gtt(gvt); 1891 if (ret) 1892 goto out_free_firmware; 1893 1894 ret = intel_gvt_init_workload_scheduler(gvt); 1895 if (ret) 1896 goto out_clean_gtt; 1897 1898 ret = intel_gvt_init_sched_policy(gvt); 1899 if (ret) 1900 goto out_clean_workload_scheduler; 1901 1902 ret = intel_gvt_init_cmd_parser(gvt); 1903 if (ret) 1904 goto out_clean_sched_policy; 1905 1906 ret = init_service_thread(gvt); 1907 if (ret) 1908 goto out_clean_cmd_parser; 1909 1910 ret = intel_gvt_init_vgpu_types(gvt); 1911 if (ret) 1912 goto out_clean_thread; 1913 1914 vgpu = intel_gvt_create_idle_vgpu(gvt); 1915 if (IS_ERR(vgpu)) { 1916 ret = PTR_ERR(vgpu); 1917 gvt_err("failed to create idle vgpu\n"); 1918 goto out_clean_types; 1919 } 1920 gvt->idle_vgpu = vgpu; 1921 1922 intel_gvt_debugfs_init(gvt); 1923 1924 ret = mdev_register_parent(&gvt->parent, i915->drm.dev, 1925 &intel_vgpu_mdev_driver, 1926 gvt->mdev_types, gvt->num_types); 1927 if (ret) 1928 goto out_destroy_idle_vgpu; 1929 1930 gvt_dbg_core("gvt device initialization is done\n"); 1931 return 0; 1932 1933 out_destroy_idle_vgpu: 1934 intel_gvt_destroy_idle_vgpu(gvt->idle_vgpu); 1935 intel_gvt_debugfs_clean(gvt); 1936 out_clean_types: 1937 intel_gvt_clean_vgpu_types(gvt); 1938 out_clean_thread: 1939 clean_service_thread(gvt); 1940 out_clean_cmd_parser: 1941 intel_gvt_clean_cmd_parser(gvt); 1942 out_clean_sched_policy: 1943 intel_gvt_clean_sched_policy(gvt); 1944 out_clean_workload_scheduler: 1945 intel_gvt_clean_workload_scheduler(gvt); 1946 out_clean_gtt: 1947 intel_gvt_clean_gtt(gvt); 1948 out_free_firmware: 1949 intel_gvt_free_firmware(gvt); 1950 out_clean_mmio_info: 1951 intel_gvt_clean_mmio_info(gvt); 1952 out_clean_idr: 1953 idr_destroy(&gvt->vgpu_idr); 1954 kfree(gvt); 1955 i915->gvt = NULL; 1956 return ret; 1957 } 1958 1959 static void intel_gvt_pm_resume(struct drm_i915_private *i915) 1960 { 1961 struct intel_gvt *gvt = i915->gvt; 1962 1963 intel_gvt_restore_fence(gvt); 1964 intel_gvt_restore_mmio(gvt); 1965 intel_gvt_restore_ggtt(gvt); 1966 } 1967 1968 static const struct intel_vgpu_ops intel_gvt_vgpu_ops = { 1969 .init_device = intel_gvt_init_device, 1970 .clean_device = intel_gvt_clean_device, 1971 .pm_resume = intel_gvt_pm_resume, 1972 }; 1973 1974 static int __init kvmgt_init(void) 1975 { 1976 int ret; 1977 1978 ret = intel_gvt_set_ops(&intel_gvt_vgpu_ops); 1979 if (ret) 1980 return ret; 1981 1982 ret = mdev_register_driver(&intel_vgpu_mdev_driver); 1983 if (ret) 1984 intel_gvt_clear_ops(&intel_gvt_vgpu_ops); 1985 return ret; 1986 } 1987 1988 static void __exit kvmgt_exit(void) 1989 { 1990 mdev_unregister_driver(&intel_vgpu_mdev_driver); 1991 intel_gvt_clear_ops(&intel_gvt_vgpu_ops); 1992 } 1993 1994 module_init(kvmgt_init); 1995 module_exit(kvmgt_exit); 1996 1997 MODULE_DESCRIPTION("Intel mediated pass-through framework for KVM"); 1998 MODULE_LICENSE("GPL and additional rights"); 1999 MODULE_AUTHOR("Intel Corporation"); 2000