1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021 Intel Corporation 4 */ 5 6 #include <linux/dma-fence.h> 7 #include <linux/dma-resv.h> 8 9 #include <drm/drm_blend.h> 10 #include <drm/drm_gem.h> 11 #include <drm/drm_modeset_helper.h> 12 #include <drm/drm_print.h> 13 14 #include "i915_drv.h" 15 #include "i915_utils.h" 16 #include "intel_bo.h" 17 #include "intel_display.h" 18 #include "intel_display_core.h" 19 #include "intel_display_types.h" 20 #include "intel_dpt.h" 21 #include "intel_fb.h" 22 #include "intel_fb_bo.h" 23 #include "intel_frontbuffer.h" 24 #include "intel_panic.h" 25 #include "intel_plane.h" 26 27 #define check_array_bounds(display, a, i) drm_WARN_ON((display)->drm, (i) >= ARRAY_SIZE(a)) 28 29 /* 30 * From the Sky Lake PRM: 31 * "The Color Control Surface (CCS) contains the compression status of 32 * the cache-line pairs. The compression state of the cache-line pair 33 * is specified by 2 bits in the CCS. Each CCS cache-line represents 34 * an area on the main surface of 16 x16 sets of 128 byte Y-tiled 35 * cache-line-pairs. CCS is always Y tiled." 36 * 37 * Since cache line pairs refers to horizontally adjacent cache lines, 38 * each cache line in the CCS corresponds to an area of 32x16 cache 39 * lines on the main surface. Since each pixel is 4 bytes, this gives 40 * us a ratio of one byte in the CCS for each 8x16 pixels in the 41 * main surface. 42 */ 43 static const struct drm_format_info skl_ccs_formats[] = { 44 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, 45 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, 46 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, 47 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, 48 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, 49 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, }, 50 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, 51 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, }, 52 { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 2, 53 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, 54 { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 2, 55 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, 56 { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 2, 57 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, }, 58 { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 2, 59 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, }, 60 }; 61 62 /* 63 * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the 64 * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles 65 * in the main surface. With 4 byte pixels and each Y-tile having dimensions of 66 * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in 67 * the main surface. 68 */ 69 static const struct drm_format_info gen12_ccs_formats[] = { 70 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, 71 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 72 .hsub = 1, .vsub = 1, }, 73 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, 74 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 75 .hsub = 1, .vsub = 1, }, 76 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, 77 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 78 .hsub = 1, .vsub = 1, .has_alpha = true }, 79 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, 80 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 81 .hsub = 1, .vsub = 1, .has_alpha = true }, 82 { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 2, 83 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 84 .hsub = 1, .vsub = 1, }, 85 { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 2, 86 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 87 .hsub = 1, .vsub = 1, }, 88 { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 2, 89 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 90 .hsub = 1, .vsub = 1, .has_alpha = true }, 91 { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 2, 92 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 93 .hsub = 1, .vsub = 1, .has_alpha = true }, 94 { .format = DRM_FORMAT_XRGB16161616F, .depth = 0, .num_planes = 2, 95 .char_per_block = { 8, 1 }, .block_w = { 1, 1 }, .block_h = { 1, 1 }, 96 .hsub = 1, .vsub = 1, }, 97 { .format = DRM_FORMAT_XBGR16161616F, .depth = 0, .num_planes = 2, 98 .char_per_block = { 8, 1 }, .block_w = { 1, 1 }, .block_h = { 1, 1 }, 99 .hsub = 1, .vsub = 1, }, 100 { .format = DRM_FORMAT_ARGB16161616F, .depth = 0, .num_planes = 2, 101 .char_per_block = { 8, 1 }, .block_w = { 1, 1 }, .block_h = { 1, 1 }, 102 .hsub = 1, .vsub = 1, .has_alpha = true }, 103 { .format = DRM_FORMAT_ABGR16161616F, .depth = 0, .num_planes = 2, 104 .char_per_block = { 8, 1 }, .block_w = { 1, 1 }, .block_h = { 1, 1 }, 105 .hsub = 1, .vsub = 1, .has_alpha = true }, 106 { .format = DRM_FORMAT_YUYV, .num_planes = 2, 107 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 108 .hsub = 2, .vsub = 1, .is_yuv = true }, 109 { .format = DRM_FORMAT_YVYU, .num_planes = 2, 110 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 111 .hsub = 2, .vsub = 1, .is_yuv = true }, 112 { .format = DRM_FORMAT_UYVY, .num_planes = 2, 113 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 114 .hsub = 2, .vsub = 1, .is_yuv = true }, 115 { .format = DRM_FORMAT_VYUY, .num_planes = 2, 116 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 117 .hsub = 2, .vsub = 1, .is_yuv = true }, 118 { .format = DRM_FORMAT_XYUV8888, .num_planes = 2, 119 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 120 .hsub = 1, .vsub = 1, .is_yuv = true }, 121 { .format = DRM_FORMAT_NV12, .num_planes = 4, 122 .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h = { 1, 1, 1, 1 }, 123 .hsub = 2, .vsub = 2, .is_yuv = true }, 124 { .format = DRM_FORMAT_P010, .num_planes = 4, 125 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 }, 126 .hsub = 2, .vsub = 2, .is_yuv = true }, 127 { .format = DRM_FORMAT_P012, .num_planes = 4, 128 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 }, 129 .hsub = 2, .vsub = 2, .is_yuv = true }, 130 { .format = DRM_FORMAT_P016, .num_planes = 4, 131 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 }, 132 .hsub = 2, .vsub = 2, .is_yuv = true }, 133 }; 134 135 /* 136 * Same as gen12_ccs_formats[] above, but with additional surface used 137 * to pass Clear Color information in plane 2 with 64 bits of data. 138 */ 139 static const struct drm_format_info gen12_ccs_cc_formats[] = { 140 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3, 141 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 0 }, .block_h = { 1, 1, 0 }, 142 .hsub = 1, .vsub = 1, }, 143 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3, 144 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 0 }, .block_h = { 1, 1, 0 }, 145 .hsub = 1, .vsub = 1, }, 146 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3, 147 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 0 }, .block_h = { 1, 1, 0 }, 148 .hsub = 1, .vsub = 1, .has_alpha = true }, 149 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3, 150 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 0 }, .block_h = { 1, 1, 0 }, 151 .hsub = 1, .vsub = 1, .has_alpha = true }, 152 { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 3, 153 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 0 }, .block_h = { 1, 1, 0 }, 154 .hsub = 1, .vsub = 1, }, 155 { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 3, 156 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 0 }, .block_h = { 1, 1, 0 }, 157 .hsub = 1, .vsub = 1, }, 158 { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 3, 159 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 0 }, .block_h = { 1, 1, 0 }, 160 .hsub = 1, .vsub = 1, .has_alpha = true }, 161 { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 3, 162 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 0 }, .block_h = { 1, 1, 0 }, 163 .hsub = 1, .vsub = 1, .has_alpha = true }, 164 { .format = DRM_FORMAT_XRGB16161616F, .depth = 0, .num_planes = 3, 165 .char_per_block = { 8, 1, 0 }, .block_w = { 1, 1, 0 }, .block_h = { 1, 1, 0 }, 166 .hsub = 1, .vsub = 1, }, 167 { .format = DRM_FORMAT_XBGR16161616F, .depth = 0, .num_planes = 3, 168 .char_per_block = { 8, 1, 0 }, .block_w = { 1, 1, 0 }, .block_h = { 1, 1, 0 }, 169 .hsub = 1, .vsub = 1, }, 170 { .format = DRM_FORMAT_ARGB16161616F, .depth = 0, .num_planes = 3, 171 .char_per_block = { 8, 1, 0 }, .block_w = { 1, 1, 0 }, .block_h = { 1, 1, 0 }, 172 .hsub = 1, .vsub = 1, .has_alpha = true }, 173 { .format = DRM_FORMAT_ABGR16161616F, .depth = 0, .num_planes = 3, 174 .char_per_block = { 8, 1, 0 }, .block_w = { 1, 1, 0 }, .block_h = { 1, 1, 0 }, 175 .hsub = 1, .vsub = 1, .has_alpha = true }, 176 }; 177 178 static const struct drm_format_info gen12_flat_ccs_cc_formats[] = { 179 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, 180 .char_per_block = { 4, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 }, 181 .hsub = 1, .vsub = 1, }, 182 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, 183 .char_per_block = { 4, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 }, 184 .hsub = 1, .vsub = 1, }, 185 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, 186 .char_per_block = { 4, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 }, 187 .hsub = 1, .vsub = 1, .has_alpha = true }, 188 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, 189 .char_per_block = { 4, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 }, 190 .hsub = 1, .vsub = 1, .has_alpha = true }, 191 { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 2, 192 .char_per_block = { 4, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 }, 193 .hsub = 1, .vsub = 1, }, 194 { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 2, 195 .char_per_block = { 4, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 }, 196 .hsub = 1, .vsub = 1, }, 197 { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 2, 198 .char_per_block = { 4, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 }, 199 .hsub = 1, .vsub = 1, .has_alpha = true }, 200 { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 2, 201 .char_per_block = { 4, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 }, 202 .hsub = 1, .vsub = 1, .has_alpha = true }, 203 { .format = DRM_FORMAT_XRGB16161616F, .depth = 0, .num_planes = 2, 204 .char_per_block = { 8, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 }, 205 .hsub = 1, .vsub = 1, }, 206 { .format = DRM_FORMAT_XBGR16161616F, .depth = 0, .num_planes = 2, 207 .char_per_block = { 8, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 }, 208 .hsub = 1, .vsub = 1, }, 209 { .format = DRM_FORMAT_ARGB16161616F, .depth = 0, .num_planes = 2, 210 .char_per_block = { 8, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 }, 211 .hsub = 1, .vsub = 1, .has_alpha = true }, 212 { .format = DRM_FORMAT_ABGR16161616F, .depth = 0, .num_planes = 2, 213 .char_per_block = { 8, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 }, 214 .hsub = 1, .vsub = 1, .has_alpha = true }, 215 }; 216 217 struct intel_modifier_desc { 218 u64 modifier; 219 struct { 220 u8 from; 221 u8 until; 222 } display_ver; 223 #define DISPLAY_VER_ALL { 0, -1 } 224 225 const struct drm_format_info *formats; 226 int format_count; 227 #define FORMAT_OVERRIDE(format_list) \ 228 .formats = format_list, \ 229 .format_count = ARRAY_SIZE(format_list) 230 231 u8 plane_caps; 232 233 struct { 234 u8 cc_planes:3; 235 u8 packed_aux_planes:4; 236 u8 planar_aux_planes:4; 237 } ccs; 238 }; 239 240 #define INTEL_PLANE_CAP_CCS_MASK (INTEL_PLANE_CAP_CCS_RC | \ 241 INTEL_PLANE_CAP_CCS_RC_CC | \ 242 INTEL_PLANE_CAP_CCS_MC) 243 #define INTEL_PLANE_CAP_TILING_MASK (INTEL_PLANE_CAP_TILING_X | \ 244 INTEL_PLANE_CAP_TILING_Y | \ 245 INTEL_PLANE_CAP_TILING_Yf | \ 246 INTEL_PLANE_CAP_TILING_4) 247 #define INTEL_PLANE_CAP_TILING_NONE 0 248 249 static const struct intel_modifier_desc intel_modifiers[] = { 250 { 251 .modifier = I915_FORMAT_MOD_4_TILED_LNL_CCS, 252 .display_ver = { 20, -1 }, 253 .plane_caps = INTEL_PLANE_CAP_TILING_4, 254 }, { 255 .modifier = I915_FORMAT_MOD_4_TILED_BMG_CCS, 256 .display_ver = { 14, -1 }, 257 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_NEED64K_PHYS, 258 }, { 259 .modifier = I915_FORMAT_MOD_4_TILED_MTL_MC_CCS, 260 .display_ver = { 14, 14 }, 261 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_MC, 262 263 .ccs.packed_aux_planes = BIT(1), 264 .ccs.planar_aux_planes = BIT(2) | BIT(3), 265 266 FORMAT_OVERRIDE(gen12_ccs_formats), 267 }, { 268 .modifier = I915_FORMAT_MOD_4_TILED_MTL_RC_CCS, 269 .display_ver = { 14, 14 }, 270 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC, 271 272 .ccs.packed_aux_planes = BIT(1), 273 274 FORMAT_OVERRIDE(gen12_ccs_formats), 275 }, { 276 .modifier = I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC, 277 .display_ver = { 14, 14 }, 278 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC_CC, 279 280 .ccs.cc_planes = BIT(2), 281 .ccs.packed_aux_planes = BIT(1), 282 283 FORMAT_OVERRIDE(gen12_ccs_cc_formats), 284 }, { 285 .modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS, 286 .display_ver = { 13, 13 }, 287 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_MC, 288 }, { 289 .modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC, 290 .display_ver = { 13, 13 }, 291 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC_CC, 292 293 .ccs.cc_planes = BIT(1), 294 295 FORMAT_OVERRIDE(gen12_flat_ccs_cc_formats), 296 }, { 297 .modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS, 298 .display_ver = { 13, 13 }, 299 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC, 300 }, { 301 .modifier = I915_FORMAT_MOD_4_TILED, 302 .display_ver = { 13, -1 }, 303 .plane_caps = INTEL_PLANE_CAP_TILING_4, 304 }, { 305 .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, 306 .display_ver = { 12, 13 }, 307 .plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_MC, 308 309 .ccs.packed_aux_planes = BIT(1), 310 .ccs.planar_aux_planes = BIT(2) | BIT(3), 311 312 FORMAT_OVERRIDE(gen12_ccs_formats), 313 }, { 314 .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, 315 .display_ver = { 12, 13 }, 316 .plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_RC, 317 318 .ccs.packed_aux_planes = BIT(1), 319 320 FORMAT_OVERRIDE(gen12_ccs_formats), 321 }, { 322 .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC, 323 .display_ver = { 12, 13 }, 324 .plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_RC_CC, 325 326 .ccs.cc_planes = BIT(2), 327 .ccs.packed_aux_planes = BIT(1), 328 329 FORMAT_OVERRIDE(gen12_ccs_cc_formats), 330 }, { 331 .modifier = I915_FORMAT_MOD_Yf_TILED_CCS, 332 .display_ver = { 9, 11 }, 333 .plane_caps = INTEL_PLANE_CAP_TILING_Yf | INTEL_PLANE_CAP_CCS_RC, 334 335 .ccs.packed_aux_planes = BIT(1), 336 337 FORMAT_OVERRIDE(skl_ccs_formats), 338 }, { 339 .modifier = I915_FORMAT_MOD_Y_TILED_CCS, 340 .display_ver = { 9, 11 }, 341 .plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_RC, 342 343 .ccs.packed_aux_planes = BIT(1), 344 345 FORMAT_OVERRIDE(skl_ccs_formats), 346 }, { 347 .modifier = I915_FORMAT_MOD_Yf_TILED, 348 .display_ver = { 9, 11 }, 349 .plane_caps = INTEL_PLANE_CAP_TILING_Yf, 350 }, { 351 .modifier = I915_FORMAT_MOD_Y_TILED, 352 .display_ver = { 9, 13 }, 353 .plane_caps = INTEL_PLANE_CAP_TILING_Y, 354 }, { 355 .modifier = I915_FORMAT_MOD_X_TILED, 356 .display_ver = { 0, 29 }, 357 .plane_caps = INTEL_PLANE_CAP_TILING_X, 358 }, { 359 .modifier = DRM_FORMAT_MOD_LINEAR, 360 .display_ver = DISPLAY_VER_ALL, 361 }, 362 }; 363 364 static const struct intel_modifier_desc *lookup_modifier_or_null(u64 modifier) 365 { 366 int i; 367 368 for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) 369 if (intel_modifiers[i].modifier == modifier) 370 return &intel_modifiers[i]; 371 372 return NULL; 373 } 374 375 static const struct intel_modifier_desc *lookup_modifier(u64 modifier) 376 { 377 const struct intel_modifier_desc *md = lookup_modifier_or_null(modifier); 378 379 if (WARN_ON(!md)) 380 return &intel_modifiers[0]; 381 382 return md; 383 } 384 385 static const struct drm_format_info * 386 lookup_format_info(const struct drm_format_info formats[], 387 int num_formats, u32 format) 388 { 389 int i; 390 391 for (i = 0; i < num_formats; i++) { 392 if (formats[i].format == format) 393 return &formats[i]; 394 } 395 396 return NULL; 397 } 398 399 unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier) 400 { 401 const struct intel_modifier_desc *md; 402 u8 tiling_caps; 403 404 md = lookup_modifier_or_null(fb_modifier); 405 if (!md) 406 return I915_TILING_NONE; 407 408 tiling_caps = lookup_modifier_or_null(fb_modifier)->plane_caps & 409 INTEL_PLANE_CAP_TILING_MASK; 410 411 switch (tiling_caps) { 412 case INTEL_PLANE_CAP_TILING_Y: 413 return I915_TILING_Y; 414 case INTEL_PLANE_CAP_TILING_X: 415 return I915_TILING_X; 416 case INTEL_PLANE_CAP_TILING_4: 417 case INTEL_PLANE_CAP_TILING_Yf: 418 case INTEL_PLANE_CAP_TILING_NONE: 419 return I915_TILING_NONE; 420 default: 421 MISSING_CASE(tiling_caps); 422 return I915_TILING_NONE; 423 } 424 } 425 426 /** 427 * intel_fb_get_format_info: Get a modifier specific format information 428 * @pixel_format: pixel format 429 * @modifier: modifier 430 * 431 * Returns: 432 * Returns the format information for @pixel_format specific to @modifier, 433 * or %NULL if the modifier doesn't override the format. 434 */ 435 const struct drm_format_info * 436 intel_fb_get_format_info(u32 pixel_format, u64 modifier) 437 { 438 const struct intel_modifier_desc *md = lookup_modifier_or_null(modifier); 439 440 if (!md || !md->formats) 441 return NULL; 442 443 return lookup_format_info(md->formats, md->format_count, pixel_format); 444 } 445 446 static bool plane_caps_contain_any(u8 caps, u8 mask) 447 { 448 return caps & mask; 449 } 450 451 static bool plane_caps_contain_all(u8 caps, u8 mask) 452 { 453 return (caps & mask) == mask; 454 } 455 456 /** 457 * intel_fb_is_tiled_modifier: Check if a modifier is a tiled modifier type 458 * @modifier: Modifier to check 459 * 460 * Returns: 461 * Returns %true if @modifier is a tiled modifier. 462 */ 463 bool intel_fb_is_tiled_modifier(u64 modifier) 464 { 465 return plane_caps_contain_any(lookup_modifier(modifier)->plane_caps, 466 INTEL_PLANE_CAP_TILING_MASK); 467 } 468 469 /** 470 * intel_fb_is_ccs_modifier: Check if a modifier is a CCS modifier type 471 * @modifier: Modifier to check 472 * 473 * Returns: 474 * Returns %true if @modifier is a render, render with color clear or 475 * media compression modifier. 476 */ 477 bool intel_fb_is_ccs_modifier(u64 modifier) 478 { 479 return plane_caps_contain_any(lookup_modifier(modifier)->plane_caps, 480 INTEL_PLANE_CAP_CCS_MASK); 481 } 482 483 /** 484 * intel_fb_is_rc_ccs_cc_modifier: Check if a modifier is an RC CCS CC modifier type 485 * @modifier: Modifier to check 486 * 487 * Returns: 488 * Returns %true if @modifier is a render with color clear modifier. 489 */ 490 bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier) 491 { 492 return plane_caps_contain_any(lookup_modifier(modifier)->plane_caps, 493 INTEL_PLANE_CAP_CCS_RC_CC); 494 } 495 496 /** 497 * intel_fb_is_mc_ccs_modifier: Check if a modifier is an MC CCS modifier type 498 * @modifier: Modifier to check 499 * 500 * Returns: 501 * Returns %true if @modifier is a media compression modifier. 502 */ 503 bool intel_fb_is_mc_ccs_modifier(u64 modifier) 504 { 505 return plane_caps_contain_any(lookup_modifier(modifier)->plane_caps, 506 INTEL_PLANE_CAP_CCS_MC); 507 } 508 509 /** 510 * intel_fb_needs_64k_phys: Check if modifier requires 64k physical placement. 511 * @modifier: Modifier to check 512 * 513 * Returns: 514 * Returns %true if @modifier requires 64k aligned physical pages. 515 */ 516 bool intel_fb_needs_64k_phys(u64 modifier) 517 { 518 const struct intel_modifier_desc *md = lookup_modifier_or_null(modifier); 519 520 if (!md) 521 return false; 522 523 return plane_caps_contain_any(md->plane_caps, 524 INTEL_PLANE_CAP_NEED64K_PHYS); 525 } 526 527 /** 528 * intel_fb_is_tile4_modifier: Check if a modifier is a tile4 modifier type 529 * @modifier: Modifier to check 530 * 531 * Returns: 532 * Returns %true if @modifier is a tile4 modifier. 533 */ 534 bool intel_fb_is_tile4_modifier(u64 modifier) 535 { 536 return plane_caps_contain_any(lookup_modifier(modifier)->plane_caps, 537 INTEL_PLANE_CAP_TILING_4); 538 } 539 540 static bool check_modifier_display_ver_range(const struct intel_modifier_desc *md, 541 u8 display_ver_from, u8 display_ver_until) 542 { 543 return md->display_ver.from <= display_ver_until && 544 display_ver_from <= md->display_ver.until; 545 } 546 547 static bool plane_has_modifier(struct intel_display *display, 548 u8 plane_caps, 549 const struct intel_modifier_desc *md) 550 { 551 struct drm_i915_private *i915 = to_i915(display->drm); 552 553 if (!IS_DISPLAY_VER(display, md->display_ver.from, md->display_ver.until)) 554 return false; 555 556 if (!plane_caps_contain_all(plane_caps, md->plane_caps)) 557 return false; 558 559 /* 560 * Separate AuxCCS and Flat CCS modifiers to be run only on platforms 561 * where supported. 562 */ 563 if (intel_fb_is_ccs_modifier(md->modifier) && 564 HAS_FLAT_CCS(i915) != !md->ccs.packed_aux_planes) 565 return false; 566 567 if (md->modifier == I915_FORMAT_MOD_4_TILED_BMG_CCS && 568 (GRAPHICS_VER(i915) < 20 || !display->platform.dgfx)) 569 return false; 570 571 if (md->modifier == I915_FORMAT_MOD_4_TILED_LNL_CCS && 572 (GRAPHICS_VER(i915) < 20 || display->platform.dgfx)) 573 return false; 574 575 return true; 576 } 577 578 /** 579 * intel_fb_plane_get_modifiers: Get the modifiers for the given platform and plane capabilities 580 * @display: display instance 581 * @plane_caps: capabilities for the plane the modifiers are queried for 582 * 583 * Returns: 584 * Returns the list of modifiers allowed by the @display platform and @plane_caps. 585 * The caller must free the returned buffer. 586 */ 587 u64 *intel_fb_plane_get_modifiers(struct intel_display *display, 588 u8 plane_caps) 589 { 590 u64 *list, *p; 591 int count = 1; /* +1 for invalid modifier terminator */ 592 int i; 593 594 for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) { 595 if (plane_has_modifier(display, plane_caps, &intel_modifiers[i])) 596 count++; 597 } 598 599 list = kmalloc_array(count, sizeof(*list), GFP_KERNEL); 600 if (drm_WARN_ON(display->drm, !list)) 601 return NULL; 602 603 p = list; 604 for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) { 605 if (plane_has_modifier(display, plane_caps, &intel_modifiers[i])) 606 *p++ = intel_modifiers[i].modifier; 607 } 608 *p++ = DRM_FORMAT_MOD_INVALID; 609 610 return list; 611 } 612 613 /** 614 * intel_fb_plane_supports_modifier: Determine if a modifier is supported by the given plane 615 * @plane: Plane to check the modifier support for 616 * @modifier: The modifier to check the support for 617 * 618 * Returns: 619 * %true if the @modifier is supported on @plane. 620 */ 621 bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier) 622 { 623 int i; 624 625 for (i = 0; i < plane->base.modifier_count; i++) 626 if (plane->base.modifiers[i] == modifier) 627 return true; 628 629 return false; 630 } 631 632 static bool format_is_yuv_semiplanar(const struct intel_modifier_desc *md, 633 const struct drm_format_info *info) 634 { 635 if (!info->is_yuv) 636 return false; 637 638 if (hweight8(md->ccs.planar_aux_planes) == 2) 639 return info->num_planes == 4; 640 else 641 return info->num_planes == 2; 642 } 643 644 /** 645 * intel_format_info_is_yuv_semiplanar: Check if the given format is YUV semiplanar 646 * @info: format to check 647 * @modifier: modifier used with the format 648 * 649 * Returns: 650 * %true if @info / @modifier is YUV semiplanar. 651 */ 652 bool intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info, 653 u64 modifier) 654 { 655 return format_is_yuv_semiplanar(lookup_modifier(modifier), info); 656 } 657 658 static u8 ccs_aux_plane_mask(const struct intel_modifier_desc *md, 659 const struct drm_format_info *format) 660 { 661 if (format_is_yuv_semiplanar(md, format)) 662 return md->ccs.planar_aux_planes; 663 else 664 return md->ccs.packed_aux_planes; 665 } 666 667 /** 668 * intel_fb_is_ccs_aux_plane: Check if a framebuffer color plane is a CCS AUX plane 669 * @fb: Framebuffer 670 * @color_plane: color plane index to check 671 * 672 * Returns: 673 * Returns %true if @fb's color plane at index @color_plane is a CCS AUX plane. 674 */ 675 bool intel_fb_is_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane) 676 { 677 const struct intel_modifier_desc *md = lookup_modifier(fb->modifier); 678 679 return ccs_aux_plane_mask(md, fb->format) & BIT(color_plane); 680 } 681 682 /** 683 * intel_fb_is_gen12_ccs_aux_plane: Check if a framebuffer color plane is a GEN12 CCS AUX plane 684 * @fb: Framebuffer 685 * @color_plane: color plane index to check 686 * 687 * Returns: 688 * Returns %true if @fb's color plane at index @color_plane is a GEN12 CCS AUX plane. 689 */ 690 static bool intel_fb_is_gen12_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane) 691 { 692 const struct intel_modifier_desc *md = lookup_modifier(fb->modifier); 693 694 return check_modifier_display_ver_range(md, 12, 14) && 695 ccs_aux_plane_mask(md, fb->format) & BIT(color_plane); 696 } 697 698 /** 699 * intel_fb_rc_ccs_cc_plane: Get the CCS CC color plane index for a framebuffer 700 * @fb: Framebuffer 701 * 702 * Returns: 703 * Returns the index of the color clear plane for @fb, or -1 if @fb is not a 704 * framebuffer using a render compression/color clear modifier. 705 */ 706 int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb) 707 { 708 const struct intel_modifier_desc *md = lookup_modifier(fb->modifier); 709 710 if (!md->ccs.cc_planes) 711 return -1; 712 713 drm_WARN_ON_ONCE(fb->dev, hweight8(md->ccs.cc_planes) > 1); 714 715 return ilog2((int)md->ccs.cc_planes); 716 } 717 718 static bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int color_plane) 719 { 720 return intel_fb_rc_ccs_cc_plane(fb) == color_plane; 721 } 722 723 bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane) 724 { 725 return fb->modifier == DRM_FORMAT_MOD_LINEAR || 726 intel_fb_is_gen12_ccs_aux_plane(fb, color_plane) || 727 is_gen12_ccs_cc_plane(fb, color_plane); 728 } 729 730 int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane) 731 { 732 drm_WARN_ON(fb->dev, !intel_fb_is_ccs_modifier(fb->modifier) || 733 (main_plane && main_plane >= fb->format->num_planes / 2)); 734 735 return fb->format->num_planes / 2 + main_plane; 736 } 737 738 int skl_ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane) 739 { 740 drm_WARN_ON(fb->dev, !intel_fb_is_ccs_modifier(fb->modifier) || 741 ccs_plane < fb->format->num_planes / 2); 742 743 if (is_gen12_ccs_cc_plane(fb, ccs_plane)) 744 return 0; 745 746 return ccs_plane - fb->format->num_planes / 2; 747 } 748 749 static unsigned int gen12_ccs_aux_stride(struct intel_framebuffer *fb, int ccs_plane) 750 { 751 int main_plane = skl_ccs_to_main_plane(&fb->base, ccs_plane); 752 unsigned int main_stride = fb->base.pitches[main_plane]; 753 unsigned int main_tile_width = intel_tile_width_bytes(&fb->base, main_plane); 754 755 return DIV_ROUND_UP(main_stride, 4 * main_tile_width) * 64; 756 } 757 758 int skl_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane) 759 { 760 const struct intel_modifier_desc *md = lookup_modifier(fb->modifier); 761 struct intel_display *display = to_intel_display(fb->dev); 762 763 if (md->ccs.packed_aux_planes | md->ccs.planar_aux_planes) 764 return main_to_ccs_plane(fb, main_plane); 765 else if (DISPLAY_VER(display) < 11 && 766 format_is_yuv_semiplanar(md, fb->format)) 767 return 1; 768 else 769 return 0; 770 } 771 772 unsigned int intel_tile_size(struct intel_display *display) 773 { 774 return DISPLAY_VER(display) == 2 ? 2048 : 4096; 775 } 776 777 unsigned int 778 intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane) 779 { 780 struct intel_display *display = to_intel_display(fb->dev); 781 struct drm_i915_private *i915 = to_i915(display->drm); 782 unsigned int cpp = fb->format->cpp[color_plane]; 783 784 switch (fb->modifier) { 785 case DRM_FORMAT_MOD_LINEAR: 786 return intel_tile_size(display); 787 case I915_FORMAT_MOD_X_TILED: 788 if (DISPLAY_VER(display) == 2) 789 return 128; 790 else 791 return 512; 792 case I915_FORMAT_MOD_4_TILED_BMG_CCS: 793 case I915_FORMAT_MOD_4_TILED_LNL_CCS: 794 case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS: 795 case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC: 796 case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS: 797 case I915_FORMAT_MOD_4_TILED: 798 /* 799 * Each 4K tile consists of 64B(8*8) subtiles, with 800 * same shape as Y Tile(i.e 4*16B OWords) 801 */ 802 return 128; 803 case I915_FORMAT_MOD_Y_TILED_CCS: 804 if (intel_fb_is_ccs_aux_plane(fb, color_plane)) 805 return 128; 806 fallthrough; 807 case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS: 808 case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC: 809 case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS: 810 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: 811 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: 812 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: 813 if (intel_fb_is_ccs_aux_plane(fb, color_plane) || 814 is_gen12_ccs_cc_plane(fb, color_plane)) 815 return 64; 816 fallthrough; 817 case I915_FORMAT_MOD_Y_TILED: 818 if (DISPLAY_VER(display) == 2 || HAS_128_BYTE_Y_TILING(i915)) 819 return 128; 820 else 821 return 512; 822 case I915_FORMAT_MOD_Yf_TILED_CCS: 823 if (intel_fb_is_ccs_aux_plane(fb, color_plane)) 824 return 128; 825 fallthrough; 826 case I915_FORMAT_MOD_Yf_TILED: 827 switch (cpp) { 828 case 1: 829 return 64; 830 case 2: 831 case 4: 832 return 128; 833 case 8: 834 case 16: 835 return 256; 836 default: 837 MISSING_CASE(cpp); 838 return cpp; 839 } 840 break; 841 default: 842 MISSING_CASE(fb->modifier); 843 return cpp; 844 } 845 } 846 847 unsigned int intel_tile_height(const struct drm_framebuffer *fb, int color_plane) 848 { 849 struct intel_display *display = to_intel_display(fb->dev); 850 851 return intel_tile_size(display) / 852 intel_tile_width_bytes(fb, color_plane); 853 } 854 855 /* 856 * Return the tile dimensions in pixel units, based on the (2 or 4 kbyte) GTT 857 * page tile size. 858 */ 859 static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane, 860 unsigned int *tile_width, 861 unsigned int *tile_height) 862 { 863 unsigned int tile_width_bytes = intel_tile_width_bytes(fb, color_plane); 864 unsigned int cpp = fb->format->cpp[color_plane]; 865 866 *tile_width = tile_width_bytes / cpp; 867 *tile_height = intel_tile_height(fb, color_plane); 868 } 869 870 /* 871 * Return the tile dimensions in pixel units, based on the tile block size. 872 * The block covers the full GTT page sized tile on all tiled surfaces and 873 * it's a 64 byte portion of the tile on TGL+ CCS surfaces. 874 */ 875 static void intel_tile_block_dims(const struct drm_framebuffer *fb, int color_plane, 876 unsigned int *tile_width, 877 unsigned int *tile_height) 878 { 879 intel_tile_dims(fb, color_plane, tile_width, tile_height); 880 881 if (intel_fb_is_gen12_ccs_aux_plane(fb, color_plane)) 882 *tile_height = 1; 883 } 884 885 unsigned int intel_tile_row_size(const struct drm_framebuffer *fb, int color_plane) 886 { 887 unsigned int tile_width, tile_height; 888 889 intel_tile_dims(fb, color_plane, &tile_width, &tile_height); 890 891 return fb->pitches[color_plane] * tile_height; 892 } 893 894 unsigned int 895 intel_fb_align_height(const struct drm_framebuffer *fb, 896 int color_plane, unsigned int height) 897 { 898 unsigned int tile_height = intel_tile_height(fb, color_plane); 899 900 return ALIGN(height, tile_height); 901 } 902 903 bool intel_fb_modifier_uses_dpt(struct intel_display *display, u64 modifier) 904 { 905 return HAS_DPT(display) && modifier != DRM_FORMAT_MOD_LINEAR; 906 } 907 908 bool intel_fb_uses_dpt(const struct drm_framebuffer *fb) 909 { 910 struct intel_display *display = to_intel_display(fb->dev); 911 912 return display->params.enable_dpt && 913 intel_fb_modifier_uses_dpt(display, fb->modifier); 914 } 915 916 void intel_fb_plane_get_subsampling(int *hsub, int *vsub, 917 const struct drm_framebuffer *fb, 918 int color_plane) 919 { 920 int main_plane; 921 922 if (color_plane == 0) { 923 *hsub = 1; 924 *vsub = 1; 925 926 return; 927 } 928 929 /* 930 * TODO: Deduct the subsampling from the char block for all CCS 931 * formats and planes. 932 */ 933 if (!intel_fb_is_gen12_ccs_aux_plane(fb, color_plane)) { 934 *hsub = fb->format->hsub; 935 *vsub = fb->format->vsub; 936 937 return; 938 } 939 940 main_plane = skl_ccs_to_main_plane(fb, color_plane); 941 *hsub = drm_format_info_block_width(fb->format, color_plane) / 942 drm_format_info_block_width(fb->format, main_plane); 943 944 /* 945 * The min stride check in the core framebuffer_check() function 946 * assumes that format->hsub applies to every plane except for the 947 * first plane. That's incorrect for the CCS AUX plane of the first 948 * plane, but for the above check to pass we must define the block 949 * width with that subsampling applied to it. Adjust the width here 950 * accordingly, so we can calculate the actual subsampling factor. 951 */ 952 if (main_plane == 0) 953 *hsub *= fb->format->hsub; 954 955 *vsub = 32; 956 } 957 958 static void intel_fb_plane_dims(const struct intel_framebuffer *fb, int color_plane, int *w, int *h) 959 { 960 int main_plane = intel_fb_is_ccs_aux_plane(&fb->base, color_plane) ? 961 skl_ccs_to_main_plane(&fb->base, color_plane) : 0; 962 unsigned int main_width = fb->base.width; 963 unsigned int main_height = fb->base.height; 964 int main_hsub, main_vsub; 965 int hsub, vsub; 966 967 intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, &fb->base, main_plane); 968 intel_fb_plane_get_subsampling(&hsub, &vsub, &fb->base, color_plane); 969 970 *w = DIV_ROUND_UP(main_width, main_hsub * hsub); 971 *h = DIV_ROUND_UP(main_height, main_vsub * vsub); 972 } 973 974 static u32 intel_adjust_tile_offset(int *x, int *y, 975 unsigned int tile_width, 976 unsigned int tile_height, 977 unsigned int tile_size, 978 unsigned int pitch_tiles, 979 u32 old_offset, 980 u32 new_offset) 981 { 982 unsigned int pitch_pixels = pitch_tiles * tile_width; 983 unsigned int tiles; 984 985 WARN_ON(old_offset & (tile_size - 1)); 986 WARN_ON(new_offset & (tile_size - 1)); 987 WARN_ON(new_offset > old_offset); 988 989 tiles = (old_offset - new_offset) / tile_size; 990 991 *y += tiles / pitch_tiles * tile_height; 992 *x += tiles % pitch_tiles * tile_width; 993 994 /* minimize x in case it got needlessly big */ 995 *y += *x / pitch_pixels * tile_height; 996 *x %= pitch_pixels; 997 998 return new_offset; 999 } 1000 1001 static u32 intel_adjust_linear_offset(int *x, int *y, 1002 unsigned int cpp, 1003 unsigned int pitch, 1004 u32 old_offset, 1005 u32 new_offset) 1006 { 1007 old_offset += *y * pitch + *x * cpp; 1008 1009 *y = (old_offset - new_offset) / pitch; 1010 *x = ((old_offset - new_offset) - *y * pitch) / cpp; 1011 1012 return new_offset; 1013 } 1014 1015 static u32 intel_adjust_aligned_offset(int *x, int *y, 1016 const struct drm_framebuffer *fb, 1017 int color_plane, 1018 unsigned int rotation, 1019 unsigned int pitch, 1020 u32 old_offset, u32 new_offset) 1021 { 1022 struct intel_display *display = to_intel_display(fb->dev); 1023 unsigned int cpp = fb->format->cpp[color_plane]; 1024 1025 drm_WARN_ON(display->drm, new_offset > old_offset); 1026 1027 if (!is_surface_linear(fb, color_plane)) { 1028 unsigned int tile_size, tile_width, tile_height; 1029 unsigned int pitch_tiles; 1030 1031 tile_size = intel_tile_size(display); 1032 intel_tile_dims(fb, color_plane, &tile_width, &tile_height); 1033 1034 if (drm_rotation_90_or_270(rotation)) { 1035 pitch_tiles = pitch / tile_height; 1036 swap(tile_width, tile_height); 1037 } else { 1038 pitch_tiles = pitch / (tile_width * cpp); 1039 } 1040 1041 intel_adjust_tile_offset(x, y, tile_width, tile_height, 1042 tile_size, pitch_tiles, 1043 old_offset, new_offset); 1044 } else { 1045 intel_adjust_linear_offset(x, y, cpp, pitch, 1046 old_offset, new_offset); 1047 } 1048 1049 return new_offset; 1050 } 1051 1052 /* 1053 * Adjust the tile offset by moving the difference into 1054 * the x/y offsets. 1055 */ 1056 u32 intel_plane_adjust_aligned_offset(int *x, int *y, 1057 const struct intel_plane_state *plane_state, 1058 int color_plane, 1059 u32 old_offset, u32 new_offset) 1060 { 1061 return intel_adjust_aligned_offset(x, y, plane_state->hw.fb, color_plane, 1062 plane_state->hw.rotation, 1063 plane_state->view.color_plane[color_plane].mapping_stride, 1064 old_offset, new_offset); 1065 } 1066 1067 /* 1068 * Computes the aligned offset to the base tile and adjusts 1069 * x, y. bytes per pixel is assumed to be a power-of-two. 1070 * 1071 * In the 90/270 rotated case, x and y are assumed 1072 * to be already rotated to match the rotated GTT view, and 1073 * pitch is the tile_height aligned framebuffer height. 1074 * 1075 * This function is used when computing the derived information 1076 * under intel_framebuffer, so using any of that information 1077 * here is not allowed. Anything under drm_framebuffer can be 1078 * used. This is why the user has to pass in the pitch since it 1079 * is specified in the rotated orientation. 1080 */ 1081 static u32 intel_compute_aligned_offset(struct intel_display *display, 1082 int *x, int *y, 1083 const struct drm_framebuffer *fb, 1084 int color_plane, 1085 unsigned int pitch, 1086 unsigned int rotation, 1087 unsigned int alignment) 1088 { 1089 unsigned int cpp = fb->format->cpp[color_plane]; 1090 u32 offset, offset_aligned; 1091 1092 if (!is_surface_linear(fb, color_plane)) { 1093 unsigned int tile_size, tile_width, tile_height; 1094 unsigned int tile_rows, tiles, pitch_tiles; 1095 1096 tile_size = intel_tile_size(display); 1097 intel_tile_dims(fb, color_plane, &tile_width, &tile_height); 1098 1099 if (drm_rotation_90_or_270(rotation)) { 1100 pitch_tiles = pitch / tile_height; 1101 swap(tile_width, tile_height); 1102 } else { 1103 pitch_tiles = pitch / (tile_width * cpp); 1104 } 1105 1106 tile_rows = *y / tile_height; 1107 *y %= tile_height; 1108 1109 tiles = *x / tile_width; 1110 *x %= tile_width; 1111 1112 offset = (tile_rows * pitch_tiles + tiles) * tile_size; 1113 1114 offset_aligned = offset; 1115 if (alignment) 1116 offset_aligned = rounddown(offset_aligned, alignment); 1117 1118 intel_adjust_tile_offset(x, y, tile_width, tile_height, 1119 tile_size, pitch_tiles, 1120 offset, offset_aligned); 1121 } else { 1122 offset = *y * pitch + *x * cpp; 1123 offset_aligned = offset; 1124 if (alignment) { 1125 offset_aligned = rounddown(offset_aligned, alignment); 1126 *y = (offset % alignment) / pitch; 1127 *x = ((offset % alignment) - *y * pitch) / cpp; 1128 } else { 1129 *y = *x = 0; 1130 } 1131 } 1132 1133 return offset_aligned; 1134 } 1135 1136 u32 intel_plane_compute_aligned_offset(int *x, int *y, 1137 const struct intel_plane_state *plane_state, 1138 int color_plane) 1139 { 1140 struct intel_display *display = to_intel_display(plane_state); 1141 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1142 const struct drm_framebuffer *fb = plane_state->hw.fb; 1143 unsigned int rotation = plane_state->hw.rotation; 1144 unsigned int pitch = plane_state->view.color_plane[color_plane].mapping_stride; 1145 unsigned int alignment = plane->min_alignment(plane, fb, color_plane); 1146 1147 return intel_compute_aligned_offset(display, x, y, fb, color_plane, 1148 pitch, rotation, alignment); 1149 } 1150 1151 /* Convert the fb->offset[] into x/y offsets */ 1152 static int intel_fb_offset_to_xy(int *x, int *y, 1153 const struct drm_framebuffer *fb, 1154 int color_plane) 1155 { 1156 struct intel_display *display = to_intel_display(fb->dev); 1157 unsigned int height, alignment, unused; 1158 1159 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) 1160 alignment = intel_tile_size(display); 1161 else 1162 alignment = 0; 1163 1164 if (alignment != 0 && fb->offsets[color_plane] % alignment) { 1165 drm_dbg_kms(display->drm, 1166 "Misaligned offset 0x%08x for color plane %d\n", 1167 fb->offsets[color_plane], color_plane); 1168 return -EINVAL; 1169 } 1170 1171 height = drm_format_info_plane_height(fb->format, fb->height, color_plane); 1172 height = ALIGN(height, intel_tile_height(fb, color_plane)); 1173 1174 /* Catch potential overflows early */ 1175 if (check_add_overflow(mul_u32_u32(height, fb->pitches[color_plane]), 1176 fb->offsets[color_plane], &unused)) { 1177 drm_dbg_kms(display->drm, 1178 "Bad offset 0x%08x or pitch %d for color plane %d\n", 1179 fb->offsets[color_plane], fb->pitches[color_plane], 1180 color_plane); 1181 return -ERANGE; 1182 } 1183 1184 *x = 0; 1185 *y = 0; 1186 1187 intel_adjust_aligned_offset(x, y, 1188 fb, color_plane, DRM_MODE_ROTATE_0, 1189 fb->pitches[color_plane], 1190 fb->offsets[color_plane], 0); 1191 1192 return 0; 1193 } 1194 1195 static int intel_fb_check_ccs_xy(const struct drm_framebuffer *fb, int ccs_plane, int x, int y) 1196 { 1197 struct intel_display *display = to_intel_display(fb->dev); 1198 const struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 1199 int main_plane; 1200 int hsub, vsub; 1201 int tile_width, tile_height; 1202 int ccs_x, ccs_y; 1203 int main_x, main_y; 1204 1205 if (!intel_fb_is_ccs_aux_plane(fb, ccs_plane)) 1206 return 0; 1207 1208 /* 1209 * While all the tile dimensions are based on a 2k or 4k GTT page size 1210 * here the main and CCS coordinates must match only within a (64 byte 1211 * on TGL+) block inside the tile. 1212 */ 1213 intel_tile_block_dims(fb, ccs_plane, &tile_width, &tile_height); 1214 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane); 1215 1216 tile_width *= hsub; 1217 tile_height *= vsub; 1218 1219 ccs_x = (x * hsub) % tile_width; 1220 ccs_y = (y * vsub) % tile_height; 1221 1222 main_plane = skl_ccs_to_main_plane(fb, ccs_plane); 1223 main_x = intel_fb->normal_view.color_plane[main_plane].x % tile_width; 1224 main_y = intel_fb->normal_view.color_plane[main_plane].y % tile_height; 1225 1226 /* 1227 * CCS doesn't have its own x/y offset register, so the intra CCS tile 1228 * x/y offsets must match between CCS and the main surface. 1229 */ 1230 if (main_x != ccs_x || main_y != ccs_y) { 1231 drm_dbg_kms(display->drm, 1232 "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n", 1233 main_x, main_y, ccs_x, ccs_y, 1234 intel_fb->normal_view.color_plane[main_plane].x, 1235 intel_fb->normal_view.color_plane[main_plane].y, 1236 x, y); 1237 return -EINVAL; 1238 } 1239 1240 return 0; 1241 } 1242 1243 static bool intel_plane_can_remap(const struct intel_plane_state *plane_state) 1244 { 1245 struct intel_display *display = to_intel_display(plane_state); 1246 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1247 const struct drm_framebuffer *fb = plane_state->hw.fb; 1248 int i; 1249 1250 /* We don't want to deal with remapping with cursors */ 1251 if (plane->id == PLANE_CURSOR) 1252 return false; 1253 1254 /* 1255 * The display engine limits already match/exceed the 1256 * render engine limits, so not much point in remapping. 1257 * Would also need to deal with the fence POT alignment 1258 * and gen2 2KiB GTT tile size. 1259 */ 1260 if (DISPLAY_VER(display) < 4) 1261 return false; 1262 1263 /* 1264 * The new CCS hash mode isn't compatible with remapping as 1265 * the virtual address of the pages affects the compressed data. 1266 */ 1267 if (intel_fb_is_ccs_modifier(fb->modifier)) 1268 return false; 1269 1270 /* Linear needs a page aligned stride for remapping */ 1271 if (fb->modifier == DRM_FORMAT_MOD_LINEAR) { 1272 unsigned int alignment = intel_tile_size(display) - 1; 1273 1274 for (i = 0; i < fb->format->num_planes; i++) { 1275 if (fb->pitches[i] & alignment) 1276 return false; 1277 } 1278 } 1279 1280 return true; 1281 } 1282 1283 bool intel_fb_needs_pot_stride_remap(const struct intel_framebuffer *fb) 1284 { 1285 struct intel_display *display = to_intel_display(fb->base.dev); 1286 1287 return (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) && 1288 intel_fb_uses_dpt(&fb->base); 1289 } 1290 1291 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state) 1292 { 1293 struct intel_display *display = to_intel_display(plane_state); 1294 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1295 1296 return DISPLAY_VER(display) < 4 || 1297 (plane->fbc && !plane_state->no_fbc_reason && 1298 plane_state->view.gtt.type == I915_GTT_VIEW_NORMAL); 1299 } 1300 1301 static int intel_fb_pitch(const struct intel_framebuffer *fb, int color_plane, unsigned int rotation) 1302 { 1303 if (drm_rotation_90_or_270(rotation)) 1304 return fb->rotated_view.color_plane[color_plane].mapping_stride; 1305 else if (intel_fb_needs_pot_stride_remap(fb)) 1306 return fb->remapped_view.color_plane[color_plane].mapping_stride; 1307 else 1308 return fb->normal_view.color_plane[color_plane].mapping_stride; 1309 } 1310 1311 static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state) 1312 { 1313 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1314 const struct intel_framebuffer *fb = to_intel_framebuffer(plane_state->hw.fb); 1315 unsigned int rotation = plane_state->hw.rotation; 1316 u32 stride, max_stride; 1317 1318 /* 1319 * No remapping for invisible planes since we don't have 1320 * an actual source viewport to remap. 1321 */ 1322 if (!plane_state->uapi.visible) 1323 return false; 1324 1325 if (!intel_plane_can_remap(plane_state)) 1326 return false; 1327 1328 /* 1329 * FIXME: aux plane limits on gen9+ are 1330 * unclear in Bspec, for now no checking. 1331 */ 1332 stride = intel_fb_pitch(fb, 0, rotation); 1333 max_stride = plane->max_stride(plane, fb->base.format->format, 1334 fb->base.modifier, rotation); 1335 1336 return stride > max_stride; 1337 } 1338 1339 static int convert_plane_offset_to_xy(const struct intel_framebuffer *fb, int color_plane, 1340 int plane_width, int *x, int *y) 1341 { 1342 struct intel_display *display = to_intel_display(fb->base.dev); 1343 struct drm_gem_object *obj = intel_fb_bo(&fb->base); 1344 int ret; 1345 1346 ret = intel_fb_offset_to_xy(x, y, &fb->base, color_plane); 1347 if (ret) { 1348 drm_dbg_kms(display->drm, 1349 "bad fb plane %d offset: 0x%x\n", 1350 color_plane, fb->base.offsets[color_plane]); 1351 return ret; 1352 } 1353 1354 ret = intel_fb_check_ccs_xy(&fb->base, color_plane, *x, *y); 1355 if (ret) 1356 return ret; 1357 1358 /* 1359 * The fence (if used) is aligned to the start of the object 1360 * so having the framebuffer wrap around across the edge of the 1361 * fenced region doesn't really work. We have no API to configure 1362 * the fence start offset within the object (nor could we probably 1363 * on gen2/3). So it's just easier if we just require that the 1364 * fb layout agrees with the fence layout. We already check that the 1365 * fb stride matches the fence stride elsewhere. 1366 */ 1367 if (color_plane == 0 && intel_bo_is_tiled(obj) && 1368 (*x + plane_width) * fb->base.format->cpp[color_plane] > fb->base.pitches[color_plane]) { 1369 drm_dbg_kms(display->drm, 1370 "bad fb plane %d offset: 0x%x\n", 1371 color_plane, fb->base.offsets[color_plane]); 1372 return -EINVAL; 1373 } 1374 1375 return 0; 1376 } 1377 1378 static u32 calc_plane_aligned_offset(const struct intel_framebuffer *fb, int color_plane, int *x, int *y) 1379 { 1380 struct intel_display *display = to_intel_display(fb->base.dev); 1381 unsigned int tile_size = intel_tile_size(display); 1382 u32 offset; 1383 1384 offset = intel_compute_aligned_offset(display, x, y, &fb->base, color_plane, 1385 fb->base.pitches[color_plane], 1386 DRM_MODE_ROTATE_0, 1387 tile_size); 1388 1389 return offset / tile_size; 1390 } 1391 1392 struct fb_plane_view_dims { 1393 unsigned int width, height; 1394 unsigned int tile_width, tile_height; 1395 }; 1396 1397 static void init_plane_view_dims(const struct intel_framebuffer *fb, int color_plane, 1398 unsigned int width, unsigned int height, 1399 struct fb_plane_view_dims *dims) 1400 { 1401 dims->width = width; 1402 dims->height = height; 1403 1404 intel_tile_dims(&fb->base, color_plane, &dims->tile_width, &dims->tile_height); 1405 } 1406 1407 static unsigned int 1408 plane_view_src_stride_tiles(const struct intel_framebuffer *fb, int color_plane, 1409 const struct fb_plane_view_dims *dims) 1410 { 1411 return DIV_ROUND_UP(fb->base.pitches[color_plane], 1412 dims->tile_width * fb->base.format->cpp[color_plane]); 1413 } 1414 1415 static unsigned int 1416 plane_view_dst_stride_tiles(const struct intel_framebuffer *fb, int color_plane, 1417 unsigned int pitch_tiles) 1418 { 1419 if (intel_fb_needs_pot_stride_remap(fb)) { 1420 /* 1421 * ADL_P, the only platform needing a POT stride has a minimum 1422 * of 8 main surface tiles. 1423 */ 1424 return roundup_pow_of_two(max(pitch_tiles, 8u)); 1425 } else { 1426 return pitch_tiles; 1427 } 1428 } 1429 1430 static unsigned int 1431 plane_view_scanout_stride(const struct intel_framebuffer *fb, int color_plane, 1432 unsigned int tile_width, 1433 unsigned int src_stride_tiles, unsigned int dst_stride_tiles) 1434 { 1435 struct intel_display *display = to_intel_display(fb->base.dev); 1436 unsigned int stride_tiles; 1437 1438 if ((display->platform.alderlake_p || DISPLAY_VER(display) >= 14) && 1439 src_stride_tiles < dst_stride_tiles) 1440 stride_tiles = src_stride_tiles; 1441 else 1442 stride_tiles = dst_stride_tiles; 1443 1444 return stride_tiles * tile_width * fb->base.format->cpp[color_plane]; 1445 } 1446 1447 static unsigned int 1448 plane_view_width_tiles(const struct intel_framebuffer *fb, int color_plane, 1449 const struct fb_plane_view_dims *dims, 1450 int x) 1451 { 1452 return DIV_ROUND_UP(x + dims->width, dims->tile_width); 1453 } 1454 1455 static unsigned int 1456 plane_view_height_tiles(const struct intel_framebuffer *fb, int color_plane, 1457 const struct fb_plane_view_dims *dims, 1458 int y) 1459 { 1460 return DIV_ROUND_UP(y + dims->height, dims->tile_height); 1461 } 1462 1463 static unsigned int 1464 plane_view_linear_tiles(const struct intel_framebuffer *fb, int color_plane, 1465 const struct fb_plane_view_dims *dims, 1466 int x, int y) 1467 { 1468 struct intel_display *display = to_intel_display(fb->base.dev); 1469 unsigned int size; 1470 1471 size = (y + dims->height) * fb->base.pitches[color_plane] + 1472 x * fb->base.format->cpp[color_plane]; 1473 1474 return DIV_ROUND_UP(size, intel_tile_size(display)); 1475 } 1476 1477 #define assign_chk_ovf(display, var, val) ({ \ 1478 drm_WARN_ON((display)->drm, overflows_type(val, var)); \ 1479 (var) = (val); \ 1480 }) 1481 1482 #define assign_bfld_chk_ovf(display, var, val) ({ \ 1483 (var) = (val); \ 1484 drm_WARN_ON((display)->drm, (var) != (val)); \ 1485 (var); \ 1486 }) 1487 1488 static u32 calc_plane_remap_info(const struct intel_framebuffer *fb, int color_plane, 1489 const struct fb_plane_view_dims *dims, 1490 u32 obj_offset, u32 gtt_offset, int x, int y, 1491 struct intel_fb_view *view) 1492 { 1493 struct intel_display *display = to_intel_display(fb->base.dev); 1494 struct intel_remapped_plane_info *remap_info = &view->gtt.remapped.plane[color_plane]; 1495 struct i915_color_plane_view *color_plane_info = &view->color_plane[color_plane]; 1496 unsigned int tile_width = dims->tile_width; 1497 unsigned int tile_height = dims->tile_height; 1498 unsigned int tile_size = intel_tile_size(display); 1499 struct drm_rect r; 1500 u32 size = 0; 1501 1502 assign_bfld_chk_ovf(display, remap_info->offset, obj_offset); 1503 1504 if (intel_fb_is_gen12_ccs_aux_plane(&fb->base, color_plane)) { 1505 remap_info->linear = 1; 1506 1507 assign_chk_ovf(display, remap_info->size, 1508 plane_view_linear_tiles(fb, color_plane, dims, x, y)); 1509 } else { 1510 remap_info->linear = 0; 1511 1512 assign_chk_ovf(display, remap_info->src_stride, 1513 plane_view_src_stride_tiles(fb, color_plane, dims)); 1514 assign_chk_ovf(display, remap_info->width, 1515 plane_view_width_tiles(fb, color_plane, dims, x)); 1516 assign_chk_ovf(display, remap_info->height, 1517 plane_view_height_tiles(fb, color_plane, dims, y)); 1518 } 1519 1520 if (view->gtt.type == I915_GTT_VIEW_ROTATED) { 1521 drm_WARN_ON(display->drm, remap_info->linear); 1522 check_array_bounds(display, view->gtt.rotated.plane, color_plane); 1523 1524 assign_chk_ovf(display, remap_info->dst_stride, 1525 plane_view_dst_stride_tiles(fb, color_plane, remap_info->height)); 1526 1527 /* rotate the x/y offsets to match the GTT view */ 1528 drm_rect_init(&r, x, y, dims->width, dims->height); 1529 drm_rect_rotate(&r, 1530 remap_info->width * tile_width, 1531 remap_info->height * tile_height, 1532 DRM_MODE_ROTATE_270); 1533 1534 color_plane_info->x = r.x1; 1535 color_plane_info->y = r.y1; 1536 1537 color_plane_info->mapping_stride = remap_info->dst_stride * tile_height; 1538 color_plane_info->scanout_stride = color_plane_info->mapping_stride; 1539 1540 size += remap_info->dst_stride * remap_info->width; 1541 1542 /* rotate the tile dimensions to match the GTT view */ 1543 swap(tile_width, tile_height); 1544 } else { 1545 drm_WARN_ON(display->drm, view->gtt.type != I915_GTT_VIEW_REMAPPED); 1546 1547 check_array_bounds(display, view->gtt.remapped.plane, color_plane); 1548 1549 if (view->gtt.remapped.plane_alignment) { 1550 u32 aligned_offset = ALIGN(gtt_offset, 1551 view->gtt.remapped.plane_alignment); 1552 1553 size += aligned_offset - gtt_offset; 1554 gtt_offset = aligned_offset; 1555 } 1556 1557 color_plane_info->x = x; 1558 color_plane_info->y = y; 1559 1560 if (remap_info->linear) { 1561 color_plane_info->mapping_stride = fb->base.pitches[color_plane]; 1562 color_plane_info->scanout_stride = color_plane_info->mapping_stride; 1563 1564 size += remap_info->size; 1565 } else { 1566 unsigned int dst_stride; 1567 1568 /* 1569 * The hardware automagically calculates the CCS AUX surface 1570 * stride from the main surface stride so can't really remap a 1571 * smaller subset (unless we'd remap in whole AUX page units). 1572 */ 1573 if (intel_fb_needs_pot_stride_remap(fb) && 1574 intel_fb_is_ccs_modifier(fb->base.modifier)) 1575 dst_stride = remap_info->src_stride; 1576 else 1577 dst_stride = remap_info->width; 1578 1579 dst_stride = plane_view_dst_stride_tiles(fb, color_plane, dst_stride); 1580 1581 assign_chk_ovf(display, remap_info->dst_stride, dst_stride); 1582 color_plane_info->mapping_stride = dst_stride * 1583 tile_width * 1584 fb->base.format->cpp[color_plane]; 1585 color_plane_info->scanout_stride = 1586 plane_view_scanout_stride(fb, color_plane, tile_width, 1587 remap_info->src_stride, 1588 dst_stride); 1589 1590 size += dst_stride * remap_info->height; 1591 } 1592 } 1593 1594 /* 1595 * We only keep the x/y offsets, so push all of the gtt offset into 1596 * the x/y offsets. x,y will hold the first pixel of the framebuffer 1597 * plane from the start of the remapped/rotated gtt mapping. 1598 */ 1599 if (remap_info->linear) 1600 intel_adjust_linear_offset(&color_plane_info->x, &color_plane_info->y, 1601 fb->base.format->cpp[color_plane], 1602 color_plane_info->mapping_stride, 1603 gtt_offset * tile_size, 0); 1604 else 1605 intel_adjust_tile_offset(&color_plane_info->x, &color_plane_info->y, 1606 tile_width, tile_height, 1607 tile_size, remap_info->dst_stride, 1608 gtt_offset * tile_size, 0); 1609 1610 return size; 1611 } 1612 1613 #undef assign_chk_ovf 1614 1615 /* Return number of tiles @color_plane needs. */ 1616 static unsigned int 1617 calc_plane_normal_size(const struct intel_framebuffer *fb, int color_plane, 1618 const struct fb_plane_view_dims *dims, 1619 int x, int y) 1620 { 1621 unsigned int tiles; 1622 1623 if (is_surface_linear(&fb->base, color_plane)) { 1624 tiles = plane_view_linear_tiles(fb, color_plane, dims, x, y); 1625 } else { 1626 tiles = plane_view_src_stride_tiles(fb, color_plane, dims) * 1627 plane_view_height_tiles(fb, color_plane, dims, y); 1628 /* 1629 * If the plane isn't horizontally tile aligned, 1630 * we need one more tile. 1631 */ 1632 if (x != 0) 1633 tiles++; 1634 } 1635 1636 return tiles; 1637 } 1638 1639 static void intel_fb_view_init(struct intel_display *display, 1640 struct intel_fb_view *view, 1641 enum i915_gtt_view_type view_type) 1642 { 1643 memset(view, 0, sizeof(*view)); 1644 view->gtt.type = view_type; 1645 1646 if (view_type == I915_GTT_VIEW_REMAPPED && 1647 (display->platform.alderlake_p || DISPLAY_VER(display) >= 14)) 1648 view->gtt.remapped.plane_alignment = SZ_2M / PAGE_SIZE; 1649 } 1650 1651 bool intel_fb_supports_90_270_rotation(const struct intel_framebuffer *fb) 1652 { 1653 struct intel_display *display = to_intel_display(fb->base.dev); 1654 1655 if (DISPLAY_VER(display) >= 13) 1656 return false; 1657 1658 return fb->base.modifier == I915_FORMAT_MOD_Y_TILED || 1659 fb->base.modifier == I915_FORMAT_MOD_Yf_TILED; 1660 } 1661 1662 static unsigned int intel_fb_min_alignment(const struct drm_framebuffer *fb) 1663 { 1664 struct intel_display *display = to_intel_display(fb->dev); 1665 struct intel_plane *plane; 1666 unsigned int min_alignment = 0; 1667 1668 for_each_intel_plane(display->drm, plane) { 1669 unsigned int plane_min_alignment; 1670 1671 if (!drm_plane_has_format(&plane->base, fb->format->format, fb->modifier)) 1672 continue; 1673 1674 plane_min_alignment = plane->min_alignment(plane, fb, 0); 1675 1676 drm_WARN_ON(display->drm, plane_min_alignment && 1677 !is_power_of_2(plane_min_alignment)); 1678 1679 if (intel_plane_needs_physical(plane)) 1680 continue; 1681 1682 min_alignment = max(min_alignment, plane_min_alignment); 1683 } 1684 1685 return min_alignment; 1686 } 1687 1688 static unsigned int intel_fb_vtd_guard(const struct drm_framebuffer *fb) 1689 { 1690 struct intel_display *display = to_intel_display(fb->dev); 1691 struct intel_plane *plane; 1692 unsigned int vtd_guard = 0; 1693 1694 for_each_intel_plane(display->drm, plane) { 1695 if (!drm_plane_has_format(&plane->base, fb->format->format, fb->modifier)) 1696 continue; 1697 1698 vtd_guard = max_t(unsigned int, vtd_guard, plane->vtd_guard); 1699 } 1700 1701 return vtd_guard; 1702 } 1703 1704 int intel_fill_fb_info(struct intel_display *display, struct intel_framebuffer *fb) 1705 { 1706 struct drm_gem_object *obj = intel_fb_bo(&fb->base); 1707 u32 gtt_offset_rotated = 0; 1708 u32 gtt_offset_remapped = 0; 1709 unsigned int max_size = 0; 1710 int i, num_planes = fb->base.format->num_planes; 1711 unsigned int tile_size = intel_tile_size(display); 1712 1713 intel_fb_view_init(display, &fb->normal_view, I915_GTT_VIEW_NORMAL); 1714 1715 drm_WARN_ON(display->drm, 1716 intel_fb_supports_90_270_rotation(fb) && 1717 intel_fb_needs_pot_stride_remap(fb)); 1718 1719 if (intel_fb_supports_90_270_rotation(fb)) 1720 intel_fb_view_init(display, &fb->rotated_view, I915_GTT_VIEW_ROTATED); 1721 if (intel_fb_needs_pot_stride_remap(fb)) 1722 intel_fb_view_init(display, &fb->remapped_view, I915_GTT_VIEW_REMAPPED); 1723 1724 for (i = 0; i < num_planes; i++) { 1725 struct fb_plane_view_dims view_dims; 1726 unsigned int width, height; 1727 unsigned int size; 1728 u32 offset; 1729 int x, y; 1730 int ret; 1731 1732 /* 1733 * Plane 2 of Render Compression with Clear Color fb modifier 1734 * is consumed by the driver and not passed to DE. Skip the 1735 * arithmetic related to alignment and offset calculation. 1736 */ 1737 if (is_gen12_ccs_cc_plane(&fb->base, i)) { 1738 unsigned int end; 1739 1740 if (!IS_ALIGNED(fb->base.offsets[i], 64)) { 1741 drm_dbg_kms(display->drm, 1742 "fb misaligned clear color plane %d offset (0x%x)\n", 1743 i, fb->base.offsets[i]); 1744 return -EINVAL; 1745 } 1746 1747 if (check_add_overflow(fb->base.offsets[i], 64, &end)) { 1748 drm_dbg_kms(display->drm, 1749 "fb bad clear color plane %d offset (0x%x)\n", 1750 i, fb->base.offsets[i]); 1751 return -EINVAL; 1752 } 1753 1754 max_size = max(max_size, DIV_ROUND_UP(end, tile_size)); 1755 continue; 1756 } 1757 1758 intel_fb_plane_dims(fb, i, &width, &height); 1759 1760 ret = convert_plane_offset_to_xy(fb, i, width, &x, &y); 1761 if (ret) 1762 return ret; 1763 1764 init_plane_view_dims(fb, i, width, height, &view_dims); 1765 1766 /* 1767 * First pixel of the framebuffer from 1768 * the start of the normal gtt mapping. 1769 */ 1770 fb->normal_view.color_plane[i].x = x; 1771 fb->normal_view.color_plane[i].y = y; 1772 fb->normal_view.color_plane[i].mapping_stride = fb->base.pitches[i]; 1773 fb->normal_view.color_plane[i].scanout_stride = 1774 fb->normal_view.color_plane[i].mapping_stride; 1775 1776 offset = calc_plane_aligned_offset(fb, i, &x, &y); 1777 1778 if (intel_fb_supports_90_270_rotation(fb)) 1779 gtt_offset_rotated += calc_plane_remap_info(fb, i, &view_dims, 1780 offset, gtt_offset_rotated, x, y, 1781 &fb->rotated_view); 1782 1783 if (intel_fb_needs_pot_stride_remap(fb)) 1784 gtt_offset_remapped += calc_plane_remap_info(fb, i, &view_dims, 1785 offset, gtt_offset_remapped, x, y, 1786 &fb->remapped_view); 1787 1788 size = calc_plane_normal_size(fb, i, &view_dims, x, y); 1789 /* how many tiles in total needed in the bo */ 1790 max_size = max(max_size, offset + size); 1791 } 1792 1793 if (mul_u32_u32(max_size, tile_size) > obj->size) { 1794 drm_dbg_kms(display->drm, 1795 "fb too big for bo (need %llu bytes, have %zu bytes)\n", 1796 mul_u32_u32(max_size, tile_size), obj->size); 1797 return -EINVAL; 1798 } 1799 1800 fb->min_alignment = intel_fb_min_alignment(&fb->base); 1801 fb->vtd_guard = intel_fb_vtd_guard(&fb->base); 1802 1803 return 0; 1804 } 1805 1806 unsigned int intel_fb_view_vtd_guard(const struct drm_framebuffer *fb, 1807 const struct intel_fb_view *view, 1808 unsigned int rotation) 1809 { 1810 unsigned int vtd_guard; 1811 int color_plane; 1812 1813 vtd_guard = to_intel_framebuffer(fb)->vtd_guard; 1814 if (!vtd_guard) 1815 return 0; 1816 1817 for (color_plane = 0; color_plane < fb->format->num_planes; color_plane++) { 1818 unsigned int stride, tile; 1819 1820 if (intel_fb_is_ccs_aux_plane(fb, color_plane) || 1821 is_gen12_ccs_cc_plane(fb, color_plane)) 1822 continue; 1823 1824 stride = view->color_plane[color_plane].mapping_stride; 1825 1826 if (drm_rotation_90_or_270(rotation)) 1827 tile = intel_tile_height(fb, color_plane); 1828 else 1829 tile = intel_tile_width_bytes(fb, color_plane); 1830 1831 vtd_guard = max(vtd_guard, DIV_ROUND_UP(stride, tile)); 1832 } 1833 1834 return vtd_guard; 1835 } 1836 1837 static void intel_plane_remap_gtt(struct intel_plane_state *plane_state) 1838 { 1839 struct intel_display *display = to_intel_display(plane_state); 1840 struct drm_framebuffer *fb = plane_state->hw.fb; 1841 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 1842 unsigned int rotation = plane_state->hw.rotation; 1843 int i, num_planes = fb->format->num_planes; 1844 unsigned int src_x, src_y; 1845 unsigned int src_w, src_h; 1846 u32 gtt_offset = 0; 1847 1848 intel_fb_view_init(display, &plane_state->view, 1849 drm_rotation_90_or_270(rotation) ? I915_GTT_VIEW_ROTATED : 1850 I915_GTT_VIEW_REMAPPED); 1851 1852 src_x = plane_state->uapi.src.x1 >> 16; 1853 src_y = plane_state->uapi.src.y1 >> 16; 1854 src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 1855 src_h = drm_rect_height(&plane_state->uapi.src) >> 16; 1856 1857 drm_WARN_ON(display->drm, intel_fb_is_ccs_modifier(fb->modifier)); 1858 1859 /* Make src coordinates relative to the viewport */ 1860 drm_rect_translate(&plane_state->uapi.src, 1861 -(src_x << 16), -(src_y << 16)); 1862 1863 /* Rotate src coordinates to match rotated GTT view */ 1864 if (drm_rotation_90_or_270(rotation)) 1865 drm_rect_rotate(&plane_state->uapi.src, 1866 src_w << 16, src_h << 16, 1867 DRM_MODE_ROTATE_270); 1868 1869 for (i = 0; i < num_planes; i++) { 1870 unsigned int hsub = i ? fb->format->hsub : 1; 1871 unsigned int vsub = i ? fb->format->vsub : 1; 1872 struct fb_plane_view_dims view_dims; 1873 unsigned int width, height; 1874 unsigned int x, y; 1875 u32 offset; 1876 1877 x = src_x / hsub; 1878 y = src_y / vsub; 1879 width = src_w / hsub; 1880 height = src_h / vsub; 1881 1882 init_plane_view_dims(intel_fb, i, width, height, &view_dims); 1883 1884 /* 1885 * First pixel of the src viewport from the 1886 * start of the normal gtt mapping. 1887 */ 1888 x += intel_fb->normal_view.color_plane[i].x; 1889 y += intel_fb->normal_view.color_plane[i].y; 1890 1891 offset = calc_plane_aligned_offset(intel_fb, i, &x, &y); 1892 1893 gtt_offset += calc_plane_remap_info(intel_fb, i, &view_dims, 1894 offset, gtt_offset, x, y, 1895 &plane_state->view); 1896 } 1897 } 1898 1899 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) 1900 { 1901 unsigned int size = 0; 1902 int i; 1903 1904 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) 1905 size += rot_info->plane[i].dst_stride * rot_info->plane[i].width; 1906 1907 return size; 1908 } 1909 1910 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info) 1911 { 1912 unsigned int size = 0; 1913 int i; 1914 1915 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) { 1916 unsigned int plane_size; 1917 1918 if (rem_info->plane[i].linear) 1919 plane_size = rem_info->plane[i].size; 1920 else 1921 plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height; 1922 1923 if (plane_size == 0) 1924 continue; 1925 1926 if (rem_info->plane_alignment) 1927 size = ALIGN(size, rem_info->plane_alignment); 1928 1929 size += plane_size; 1930 } 1931 1932 return size; 1933 } 1934 1935 void intel_fb_fill_view(const struct intel_framebuffer *fb, unsigned int rotation, 1936 struct intel_fb_view *view) 1937 { 1938 if (drm_rotation_90_or_270(rotation)) 1939 *view = fb->rotated_view; 1940 else if (intel_fb_needs_pot_stride_remap(fb)) 1941 *view = fb->remapped_view; 1942 else 1943 *view = fb->normal_view; 1944 } 1945 1946 /* 1947 * Convert the x/y offsets into a linear offset. 1948 * Only valid with 0/180 degree rotation, which is fine since linear 1949 * offset is only used with linear buffers on pre-hsw and tiled buffers 1950 * with gen2/3, and 90/270 degree rotations isn't supported on any of them. 1951 */ 1952 u32 intel_fb_xy_to_linear(int x, int y, 1953 const struct intel_plane_state *plane_state, 1954 int color_plane) 1955 { 1956 const struct drm_framebuffer *fb = plane_state->hw.fb; 1957 unsigned int cpp = fb->format->cpp[color_plane]; 1958 unsigned int pitch = plane_state->view.color_plane[color_plane].mapping_stride; 1959 1960 return y * pitch + x * cpp; 1961 } 1962 1963 /* 1964 * Add the x/y offsets derived from fb->offsets[] to the user 1965 * specified plane src x/y offsets. The resulting x/y offsets 1966 * specify the start of scanout from the beginning of the gtt mapping. 1967 */ 1968 void intel_add_fb_offsets(int *x, int *y, 1969 const struct intel_plane_state *plane_state, 1970 int color_plane) 1971 1972 { 1973 *x += plane_state->view.color_plane[color_plane].x; 1974 *y += plane_state->view.color_plane[color_plane].y; 1975 } 1976 1977 static 1978 u32 intel_fb_max_stride(struct intel_display *display, 1979 u32 pixel_format, u64 modifier) 1980 { 1981 /* 1982 * Arbitrary limit for gen4+ chosen to match the 1983 * render engine max stride. 1984 * 1985 * The new CCS hash mode makes remapping impossible 1986 */ 1987 if (DISPLAY_VER(display) < 4 || intel_fb_is_ccs_modifier(modifier) || 1988 intel_fb_modifier_uses_dpt(display, modifier)) 1989 return intel_plane_fb_max_stride(display->drm, pixel_format, modifier); 1990 else if (DISPLAY_VER(display) >= 7) 1991 return 256 * 1024; 1992 else 1993 return 128 * 1024; 1994 } 1995 1996 static unsigned int 1997 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane) 1998 { 1999 struct intel_display *display = to_intel_display(fb->dev); 2000 unsigned int tile_width; 2001 2002 if (is_surface_linear(fb, color_plane)) { 2003 unsigned int max_stride = intel_plane_fb_max_stride(display->drm, 2004 fb->format->format, 2005 fb->modifier); 2006 2007 /* 2008 * To make remapping with linear generally feasible 2009 * we need the stride to be page aligned. 2010 */ 2011 if (fb->pitches[color_plane] > max_stride && 2012 !intel_fb_is_ccs_modifier(fb->modifier)) 2013 return intel_tile_size(display); 2014 else 2015 return 64; 2016 } 2017 2018 tile_width = intel_tile_width_bytes(fb, color_plane); 2019 if (intel_fb_is_ccs_modifier(fb->modifier)) { 2020 /* 2021 * On TGL the surface stride must be 4 tile aligned, mapped by 2022 * one 64 byte cacheline on the CCS AUX surface. 2023 */ 2024 if (DISPLAY_VER(display) >= 12) 2025 tile_width *= 4; 2026 /* 2027 * Display WA #0531: skl,bxt,kbl,glk 2028 * 2029 * Render decompression and plane width > 3840 2030 * combined with horizontal panning requires the 2031 * plane stride to be a multiple of 4. We'll just 2032 * require the entire fb to accommodate that to avoid 2033 * potential runtime errors at plane configuration time. 2034 */ 2035 else if ((DISPLAY_VER(display) == 9 || display->platform.geminilake) && 2036 color_plane == 0 && fb->width > 3840) 2037 tile_width *= 4; 2038 } 2039 return tile_width; 2040 } 2041 2042 static int intel_plane_check_stride(const struct intel_plane_state *plane_state) 2043 { 2044 struct intel_display *display = to_intel_display(plane_state); 2045 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 2046 const struct drm_framebuffer *fb = plane_state->hw.fb; 2047 unsigned int rotation = plane_state->hw.rotation; 2048 u32 stride, max_stride; 2049 2050 /* 2051 * We ignore stride for all invisible planes that 2052 * can be remapped. Otherwise we could end up 2053 * with a false positive when the remapping didn't 2054 * kick in due the plane being invisible. 2055 */ 2056 if (intel_plane_can_remap(plane_state) && 2057 !plane_state->uapi.visible) 2058 return 0; 2059 2060 /* FIXME other color planes? */ 2061 stride = plane_state->view.color_plane[0].mapping_stride; 2062 max_stride = plane->max_stride(plane, fb->format->format, 2063 fb->modifier, rotation); 2064 2065 if (stride > max_stride) { 2066 drm_dbg_kms(display->drm, 2067 "[FB:%d] stride (%d) exceeds [PLANE:%d:%s] max stride (%d)\n", 2068 fb->base.id, stride, 2069 plane->base.base.id, plane->base.name, max_stride); 2070 return -EINVAL; 2071 } 2072 2073 return 0; 2074 } 2075 2076 int intel_plane_compute_gtt(struct intel_plane_state *plane_state) 2077 { 2078 const struct intel_framebuffer *fb = 2079 to_intel_framebuffer(plane_state->hw.fb); 2080 unsigned int rotation = plane_state->hw.rotation; 2081 2082 if (!fb) 2083 return 0; 2084 2085 if (intel_plane_needs_remap(plane_state)) { 2086 intel_plane_remap_gtt(plane_state); 2087 2088 /* 2089 * Sometimes even remapping can't overcome 2090 * the stride limitations :( Can happen with 2091 * big plane sizes and suitably misaligned 2092 * offsets. 2093 */ 2094 return intel_plane_check_stride(plane_state); 2095 } 2096 2097 intel_fb_fill_view(fb, rotation, &plane_state->view); 2098 2099 /* Rotate src coordinates to match rotated GTT view */ 2100 if (drm_rotation_90_or_270(rotation)) 2101 drm_rect_rotate(&plane_state->uapi.src, 2102 fb->base.width << 16, fb->base.height << 16, 2103 DRM_MODE_ROTATE_270); 2104 2105 return intel_plane_check_stride(plane_state); 2106 } 2107 2108 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) 2109 { 2110 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 2111 2112 drm_framebuffer_cleanup(fb); 2113 2114 if (intel_fb_uses_dpt(fb)) 2115 intel_dpt_destroy(intel_fb->dpt_vm); 2116 2117 intel_fb_bo_framebuffer_fini(intel_fb_bo(fb)); 2118 2119 intel_frontbuffer_put(intel_fb->frontbuffer); 2120 2121 kfree(intel_fb); 2122 } 2123 2124 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, 2125 struct drm_file *file, 2126 unsigned int *handle) 2127 { 2128 struct drm_gem_object *obj = intel_fb_bo(fb); 2129 struct intel_display *display = to_intel_display(obj->dev); 2130 2131 if (intel_bo_is_userptr(obj)) { 2132 drm_dbg(display->drm, 2133 "attempting to use a userptr for a framebuffer, denied\n"); 2134 return -EINVAL; 2135 } 2136 2137 return drm_gem_handle_create(file, obj, handle); 2138 } 2139 2140 struct frontbuffer_fence_cb { 2141 struct dma_fence_cb base; 2142 struct intel_frontbuffer *front; 2143 }; 2144 2145 static void intel_user_framebuffer_fence_wake(struct dma_fence *dma, 2146 struct dma_fence_cb *data) 2147 { 2148 struct frontbuffer_fence_cb *cb = container_of(data, typeof(*cb), base); 2149 2150 intel_frontbuffer_queue_flush(cb->front); 2151 kfree(cb); 2152 dma_fence_put(dma); 2153 } 2154 2155 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, 2156 struct drm_file *file, 2157 unsigned int flags, unsigned int color, 2158 struct drm_clip_rect *clips, 2159 unsigned int num_clips) 2160 { 2161 struct drm_gem_object *obj = intel_fb_bo(fb); 2162 struct intel_frontbuffer *front = to_intel_frontbuffer(fb); 2163 struct dma_fence *fence; 2164 struct frontbuffer_fence_cb *cb; 2165 int ret = 0; 2166 2167 if (!atomic_read(&front->bits)) 2168 return 0; 2169 2170 if (dma_resv_test_signaled(obj->resv, dma_resv_usage_rw(false))) 2171 goto flush; 2172 2173 ret = dma_resv_get_singleton(obj->resv, dma_resv_usage_rw(false), 2174 &fence); 2175 if (ret || !fence) 2176 goto flush; 2177 2178 cb = kmalloc(sizeof(*cb), GFP_KERNEL); 2179 if (!cb) { 2180 dma_fence_put(fence); 2181 ret = -ENOMEM; 2182 goto flush; 2183 } 2184 2185 cb->front = front; 2186 2187 intel_frontbuffer_invalidate(front, ORIGIN_DIRTYFB); 2188 2189 ret = dma_fence_add_callback(fence, &cb->base, 2190 intel_user_framebuffer_fence_wake); 2191 if (ret) { 2192 intel_user_framebuffer_fence_wake(fence, &cb->base); 2193 if (ret == -ENOENT) 2194 ret = 0; 2195 } 2196 2197 return ret; 2198 2199 flush: 2200 intel_bo_flush_if_display(obj); 2201 intel_frontbuffer_flush(front, ORIGIN_DIRTYFB); 2202 return ret; 2203 } 2204 2205 static const struct drm_framebuffer_funcs intel_fb_funcs = { 2206 .destroy = intel_user_framebuffer_destroy, 2207 .create_handle = intel_user_framebuffer_create_handle, 2208 .dirty = intel_user_framebuffer_dirty, 2209 }; 2210 2211 int intel_framebuffer_init(struct intel_framebuffer *intel_fb, 2212 struct drm_gem_object *obj, 2213 const struct drm_format_info *info, 2214 struct drm_mode_fb_cmd2 *mode_cmd) 2215 { 2216 struct intel_display *display = to_intel_display(obj->dev); 2217 struct drm_framebuffer *fb = &intel_fb->base; 2218 u32 max_stride; 2219 int ret = -EINVAL; 2220 int i; 2221 2222 /* 2223 * intel_frontbuffer_get() must be done before 2224 * intel_fb_bo_framebuffer_init() to avoid set_tiling vs. addfb race. 2225 */ 2226 intel_fb->frontbuffer = intel_frontbuffer_get(obj); 2227 if (!intel_fb->frontbuffer) 2228 return -ENOMEM; 2229 2230 ret = intel_fb_bo_framebuffer_init(fb, obj, mode_cmd); 2231 if (ret) 2232 goto err_frontbuffer_put; 2233 2234 ret = -EINVAL; 2235 if (!drm_any_plane_has_format(display->drm, 2236 mode_cmd->pixel_format, 2237 mode_cmd->modifier[0])) { 2238 drm_dbg_kms(display->drm, 2239 "unsupported pixel format %p4cc / modifier 0x%llx\n", 2240 &mode_cmd->pixel_format, mode_cmd->modifier[0]); 2241 goto err_bo_framebuffer_fini; 2242 } 2243 2244 max_stride = intel_fb_max_stride(display, mode_cmd->pixel_format, 2245 mode_cmd->modifier[0]); 2246 if (mode_cmd->pitches[0] > max_stride) { 2247 drm_dbg_kms(display->drm, 2248 "%s pitch (%u) must be at most %d\n", 2249 mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ? 2250 "tiled" : "linear", 2251 mode_cmd->pitches[0], max_stride); 2252 goto err_bo_framebuffer_fini; 2253 } 2254 2255 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ 2256 if (mode_cmd->offsets[0] != 0) { 2257 drm_dbg_kms(display->drm, 2258 "plane 0 offset (0x%08x) must be 0\n", 2259 mode_cmd->offsets[0]); 2260 goto err_bo_framebuffer_fini; 2261 } 2262 2263 drm_helper_mode_fill_fb_struct(display->drm, fb, info, mode_cmd); 2264 2265 for (i = 0; i < fb->format->num_planes; i++) { 2266 unsigned int stride_alignment; 2267 2268 if (mode_cmd->handles[i] != mode_cmd->handles[0]) { 2269 drm_dbg_kms(display->drm, "bad plane %d handle\n", i); 2270 goto err_bo_framebuffer_fini; 2271 } 2272 2273 stride_alignment = intel_fb_stride_alignment(fb, i); 2274 if (fb->pitches[i] & (stride_alignment - 1)) { 2275 drm_dbg_kms(display->drm, 2276 "plane %d pitch (%d) must be at least %u byte aligned\n", 2277 i, fb->pitches[i], stride_alignment); 2278 goto err_bo_framebuffer_fini; 2279 } 2280 2281 if (intel_fb_is_gen12_ccs_aux_plane(fb, i)) { 2282 unsigned int ccs_aux_stride = gen12_ccs_aux_stride(intel_fb, i); 2283 2284 if (fb->pitches[i] != ccs_aux_stride) { 2285 drm_dbg_kms(display->drm, 2286 "ccs aux plane %d pitch (%d) must be %d\n", 2287 i, fb->pitches[i], ccs_aux_stride); 2288 goto err_bo_framebuffer_fini; 2289 } 2290 } 2291 2292 fb->obj[i] = obj; 2293 } 2294 2295 ret = intel_fill_fb_info(display, intel_fb); 2296 if (ret) 2297 goto err_bo_framebuffer_fini; 2298 2299 if (intel_fb_uses_dpt(fb)) { 2300 struct i915_address_space *vm; 2301 2302 vm = intel_dpt_create(intel_fb); 2303 if (IS_ERR(vm)) { 2304 drm_dbg_kms(display->drm, "failed to create DPT\n"); 2305 ret = PTR_ERR(vm); 2306 goto err_frontbuffer_put; 2307 } 2308 2309 intel_fb->dpt_vm = vm; 2310 } 2311 2312 ret = drm_framebuffer_init(display->drm, fb, &intel_fb_funcs); 2313 if (ret) { 2314 drm_err(display->drm, "framebuffer init failed %d\n", ret); 2315 goto err_free_dpt; 2316 } 2317 2318 return 0; 2319 2320 err_free_dpt: 2321 if (intel_fb_uses_dpt(fb)) 2322 intel_dpt_destroy(intel_fb->dpt_vm); 2323 err_bo_framebuffer_fini: 2324 intel_fb_bo_framebuffer_fini(obj); 2325 err_frontbuffer_put: 2326 intel_frontbuffer_put(intel_fb->frontbuffer); 2327 return ret; 2328 } 2329 2330 struct drm_framebuffer * 2331 intel_user_framebuffer_create(struct drm_device *dev, 2332 struct drm_file *filp, 2333 const struct drm_format_info *info, 2334 const struct drm_mode_fb_cmd2 *user_mode_cmd) 2335 { 2336 struct drm_framebuffer *fb; 2337 struct drm_gem_object *obj; 2338 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; 2339 2340 obj = intel_fb_bo_lookup_valid_bo(dev, filp, &mode_cmd); 2341 if (IS_ERR(obj)) 2342 return ERR_CAST(obj); 2343 2344 fb = intel_framebuffer_create(obj, info, &mode_cmd); 2345 drm_gem_object_put(obj); 2346 2347 return fb; 2348 } 2349 2350 struct intel_framebuffer *intel_framebuffer_alloc(void) 2351 { 2352 struct intel_framebuffer *intel_fb; 2353 struct intel_panic *panic; 2354 2355 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); 2356 if (!intel_fb) 2357 return NULL; 2358 2359 panic = intel_panic_alloc(); 2360 if (!panic) { 2361 kfree(intel_fb); 2362 return NULL; 2363 } 2364 2365 intel_fb->panic = panic; 2366 2367 return intel_fb; 2368 } 2369 2370 struct drm_framebuffer * 2371 intel_framebuffer_create(struct drm_gem_object *obj, 2372 const struct drm_format_info *info, 2373 struct drm_mode_fb_cmd2 *mode_cmd) 2374 { 2375 struct intel_framebuffer *intel_fb; 2376 int ret; 2377 2378 intel_fb = intel_framebuffer_alloc(); 2379 if (!intel_fb) 2380 return ERR_PTR(-ENOMEM); 2381 2382 ret = intel_framebuffer_init(intel_fb, obj, info, mode_cmd); 2383 if (ret) 2384 goto err; 2385 2386 return &intel_fb->base; 2387 2388 err: 2389 kfree(intel_fb); 2390 return ERR_PTR(ret); 2391 } 2392 2393 struct drm_gem_object *intel_fb_bo(const struct drm_framebuffer *fb) 2394 { 2395 return fb ? fb->obj[0] : NULL; 2396 } 2397