1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/string_helpers.h> 8 9 #include "i915_reg.h" 10 #include "intel_atomic.h" 11 #include "intel_crtc.h" 12 #include "intel_cx0_phy.h" 13 #include "intel_de.h" 14 #include "intel_display.h" 15 #include "intel_display_types.h" 16 #include "intel_dpio_phy.h" 17 #include "intel_dpll.h" 18 #include "intel_lvds.h" 19 #include "intel_lvds_regs.h" 20 #include "intel_panel.h" 21 #include "intel_pps.h" 22 #include "intel_snps_phy.h" 23 #include "vlv_sideband.h" 24 25 struct intel_dpll_funcs { 26 int (*crtc_compute_clock)(struct intel_atomic_state *state, 27 struct intel_crtc *crtc); 28 int (*crtc_get_shared_dpll)(struct intel_atomic_state *state, 29 struct intel_crtc *crtc); 30 }; 31 32 struct intel_limit { 33 struct { 34 int min, max; 35 } dot, vco, n, m, m1, m2, p, p1; 36 37 struct { 38 int dot_limit; 39 int p2_slow, p2_fast; 40 } p2; 41 }; 42 static const struct intel_limit intel_limits_i8xx_dac = { 43 .dot = { .min = 25000, .max = 350000 }, 44 .vco = { .min = 908000, .max = 1512000 }, 45 .n = { .min = 2, .max = 16 }, 46 .m = { .min = 96, .max = 140 }, 47 .m1 = { .min = 18, .max = 26 }, 48 .m2 = { .min = 6, .max = 16 }, 49 .p = { .min = 4, .max = 128 }, 50 .p1 = { .min = 2, .max = 33 }, 51 .p2 = { .dot_limit = 165000, 52 .p2_slow = 4, .p2_fast = 2 }, 53 }; 54 55 static const struct intel_limit intel_limits_i8xx_dvo = { 56 .dot = { .min = 25000, .max = 350000 }, 57 .vco = { .min = 908000, .max = 1512000 }, 58 .n = { .min = 2, .max = 16 }, 59 .m = { .min = 96, .max = 140 }, 60 .m1 = { .min = 18, .max = 26 }, 61 .m2 = { .min = 6, .max = 16 }, 62 .p = { .min = 4, .max = 128 }, 63 .p1 = { .min = 2, .max = 33 }, 64 .p2 = { .dot_limit = 165000, 65 .p2_slow = 4, .p2_fast = 4 }, 66 }; 67 68 static const struct intel_limit intel_limits_i8xx_lvds = { 69 .dot = { .min = 25000, .max = 350000 }, 70 .vco = { .min = 908000, .max = 1512000 }, 71 .n = { .min = 2, .max = 16 }, 72 .m = { .min = 96, .max = 140 }, 73 .m1 = { .min = 18, .max = 26 }, 74 .m2 = { .min = 6, .max = 16 }, 75 .p = { .min = 4, .max = 128 }, 76 .p1 = { .min = 1, .max = 6 }, 77 .p2 = { .dot_limit = 165000, 78 .p2_slow = 14, .p2_fast = 7 }, 79 }; 80 81 static const struct intel_limit intel_limits_i9xx_sdvo = { 82 .dot = { .min = 20000, .max = 400000 }, 83 .vco = { .min = 1400000, .max = 2800000 }, 84 .n = { .min = 1, .max = 6 }, 85 .m = { .min = 70, .max = 120 }, 86 .m1 = { .min = 8, .max = 18 }, 87 .m2 = { .min = 3, .max = 7 }, 88 .p = { .min = 5, .max = 80 }, 89 .p1 = { .min = 1, .max = 8 }, 90 .p2 = { .dot_limit = 200000, 91 .p2_slow = 10, .p2_fast = 5 }, 92 }; 93 94 static const struct intel_limit intel_limits_i9xx_lvds = { 95 .dot = { .min = 20000, .max = 400000 }, 96 .vco = { .min = 1400000, .max = 2800000 }, 97 .n = { .min = 1, .max = 6 }, 98 .m = { .min = 70, .max = 120 }, 99 .m1 = { .min = 8, .max = 18 }, 100 .m2 = { .min = 3, .max = 7 }, 101 .p = { .min = 7, .max = 98 }, 102 .p1 = { .min = 1, .max = 8 }, 103 .p2 = { .dot_limit = 112000, 104 .p2_slow = 14, .p2_fast = 7 }, 105 }; 106 107 108 static const struct intel_limit intel_limits_g4x_sdvo = { 109 .dot = { .min = 25000, .max = 270000 }, 110 .vco = { .min = 1750000, .max = 3500000}, 111 .n = { .min = 1, .max = 4 }, 112 .m = { .min = 104, .max = 138 }, 113 .m1 = { .min = 17, .max = 23 }, 114 .m2 = { .min = 5, .max = 11 }, 115 .p = { .min = 10, .max = 30 }, 116 .p1 = { .min = 1, .max = 3}, 117 .p2 = { .dot_limit = 270000, 118 .p2_slow = 10, 119 .p2_fast = 10 120 }, 121 }; 122 123 static const struct intel_limit intel_limits_g4x_hdmi = { 124 .dot = { .min = 22000, .max = 400000 }, 125 .vco = { .min = 1750000, .max = 3500000}, 126 .n = { .min = 1, .max = 4 }, 127 .m = { .min = 104, .max = 138 }, 128 .m1 = { .min = 16, .max = 23 }, 129 .m2 = { .min = 5, .max = 11 }, 130 .p = { .min = 5, .max = 80 }, 131 .p1 = { .min = 1, .max = 8}, 132 .p2 = { .dot_limit = 165000, 133 .p2_slow = 10, .p2_fast = 5 }, 134 }; 135 136 static const struct intel_limit intel_limits_g4x_single_channel_lvds = { 137 .dot = { .min = 20000, .max = 115000 }, 138 .vco = { .min = 1750000, .max = 3500000 }, 139 .n = { .min = 1, .max = 3 }, 140 .m = { .min = 104, .max = 138 }, 141 .m1 = { .min = 17, .max = 23 }, 142 .m2 = { .min = 5, .max = 11 }, 143 .p = { .min = 28, .max = 112 }, 144 .p1 = { .min = 2, .max = 8 }, 145 .p2 = { .dot_limit = 0, 146 .p2_slow = 14, .p2_fast = 14 147 }, 148 }; 149 150 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = { 151 .dot = { .min = 80000, .max = 224000 }, 152 .vco = { .min = 1750000, .max = 3500000 }, 153 .n = { .min = 1, .max = 3 }, 154 .m = { .min = 104, .max = 138 }, 155 .m1 = { .min = 17, .max = 23 }, 156 .m2 = { .min = 5, .max = 11 }, 157 .p = { .min = 14, .max = 42 }, 158 .p1 = { .min = 2, .max = 6 }, 159 .p2 = { .dot_limit = 0, 160 .p2_slow = 7, .p2_fast = 7 161 }, 162 }; 163 164 static const struct intel_limit pnv_limits_sdvo = { 165 .dot = { .min = 20000, .max = 400000}, 166 .vco = { .min = 1700000, .max = 3500000 }, 167 /* Pineview's Ncounter is a ring counter */ 168 .n = { .min = 3, .max = 6 }, 169 .m = { .min = 2, .max = 256 }, 170 /* Pineview only has one combined m divider, which we treat as m2. */ 171 .m1 = { .min = 0, .max = 0 }, 172 .m2 = { .min = 0, .max = 254 }, 173 .p = { .min = 5, .max = 80 }, 174 .p1 = { .min = 1, .max = 8 }, 175 .p2 = { .dot_limit = 200000, 176 .p2_slow = 10, .p2_fast = 5 }, 177 }; 178 179 static const struct intel_limit pnv_limits_lvds = { 180 .dot = { .min = 20000, .max = 400000 }, 181 .vco = { .min = 1700000, .max = 3500000 }, 182 .n = { .min = 3, .max = 6 }, 183 .m = { .min = 2, .max = 256 }, 184 .m1 = { .min = 0, .max = 0 }, 185 .m2 = { .min = 0, .max = 254 }, 186 .p = { .min = 7, .max = 112 }, 187 .p1 = { .min = 1, .max = 8 }, 188 .p2 = { .dot_limit = 112000, 189 .p2_slow = 14, .p2_fast = 14 }, 190 }; 191 192 /* Ironlake / Sandybridge 193 * 194 * We calculate clock using (register_value + 2) for N/M1/M2, so here 195 * the range value for them is (actual_value - 2). 196 */ 197 static const struct intel_limit ilk_limits_dac = { 198 .dot = { .min = 25000, .max = 350000 }, 199 .vco = { .min = 1760000, .max = 3510000 }, 200 .n = { .min = 1, .max = 5 }, 201 .m = { .min = 79, .max = 127 }, 202 .m1 = { .min = 12, .max = 22 }, 203 .m2 = { .min = 5, .max = 9 }, 204 .p = { .min = 5, .max = 80 }, 205 .p1 = { .min = 1, .max = 8 }, 206 .p2 = { .dot_limit = 225000, 207 .p2_slow = 10, .p2_fast = 5 }, 208 }; 209 210 static const struct intel_limit ilk_limits_single_lvds = { 211 .dot = { .min = 25000, .max = 350000 }, 212 .vco = { .min = 1760000, .max = 3510000 }, 213 .n = { .min = 1, .max = 3 }, 214 .m = { .min = 79, .max = 118 }, 215 .m1 = { .min = 12, .max = 22 }, 216 .m2 = { .min = 5, .max = 9 }, 217 .p = { .min = 28, .max = 112 }, 218 .p1 = { .min = 2, .max = 8 }, 219 .p2 = { .dot_limit = 225000, 220 .p2_slow = 14, .p2_fast = 14 }, 221 }; 222 223 static const struct intel_limit ilk_limits_dual_lvds = { 224 .dot = { .min = 25000, .max = 350000 }, 225 .vco = { .min = 1760000, .max = 3510000 }, 226 .n = { .min = 1, .max = 3 }, 227 .m = { .min = 79, .max = 127 }, 228 .m1 = { .min = 12, .max = 22 }, 229 .m2 = { .min = 5, .max = 9 }, 230 .p = { .min = 14, .max = 56 }, 231 .p1 = { .min = 2, .max = 8 }, 232 .p2 = { .dot_limit = 225000, 233 .p2_slow = 7, .p2_fast = 7 }, 234 }; 235 236 /* LVDS 100mhz refclk limits. */ 237 static const struct intel_limit ilk_limits_single_lvds_100m = { 238 .dot = { .min = 25000, .max = 350000 }, 239 .vco = { .min = 1760000, .max = 3510000 }, 240 .n = { .min = 1, .max = 2 }, 241 .m = { .min = 79, .max = 126 }, 242 .m1 = { .min = 12, .max = 22 }, 243 .m2 = { .min = 5, .max = 9 }, 244 .p = { .min = 28, .max = 112 }, 245 .p1 = { .min = 2, .max = 8 }, 246 .p2 = { .dot_limit = 225000, 247 .p2_slow = 14, .p2_fast = 14 }, 248 }; 249 250 static const struct intel_limit ilk_limits_dual_lvds_100m = { 251 .dot = { .min = 25000, .max = 350000 }, 252 .vco = { .min = 1760000, .max = 3510000 }, 253 .n = { .min = 1, .max = 3 }, 254 .m = { .min = 79, .max = 126 }, 255 .m1 = { .min = 12, .max = 22 }, 256 .m2 = { .min = 5, .max = 9 }, 257 .p = { .min = 14, .max = 42 }, 258 .p1 = { .min = 2, .max = 6 }, 259 .p2 = { .dot_limit = 225000, 260 .p2_slow = 7, .p2_fast = 7 }, 261 }; 262 263 static const struct intel_limit intel_limits_vlv = { 264 /* 265 * These are based on the data rate limits (measured in fast clocks) 266 * since those are the strictest limits we have. The fast 267 * clock and actual rate limits are more relaxed, so checking 268 * them would make no difference. 269 */ 270 .dot = { .min = 25000, .max = 270000 }, 271 .vco = { .min = 4000000, .max = 6000000 }, 272 .n = { .min = 1, .max = 7 }, 273 .m1 = { .min = 2, .max = 3 }, 274 .m2 = { .min = 11, .max = 156 }, 275 .p1 = { .min = 2, .max = 3 }, 276 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ 277 }; 278 279 static const struct intel_limit intel_limits_chv = { 280 /* 281 * These are based on the data rate limits (measured in fast clocks) 282 * since those are the strictest limits we have. The fast 283 * clock and actual rate limits are more relaxed, so checking 284 * them would make no difference. 285 */ 286 .dot = { .min = 25000, .max = 540000 }, 287 .vco = { .min = 4800000, .max = 6480000 }, 288 .n = { .min = 1, .max = 1 }, 289 .m1 = { .min = 2, .max = 2 }, 290 .m2 = { .min = 24 << 22, .max = 175 << 22 }, 291 .p1 = { .min = 2, .max = 4 }, 292 .p2 = { .p2_slow = 1, .p2_fast = 14 }, 293 }; 294 295 static const struct intel_limit intel_limits_bxt = { 296 .dot = { .min = 25000, .max = 594000 }, 297 .vco = { .min = 4800000, .max = 6700000 }, 298 .n = { .min = 1, .max = 1 }, 299 .m1 = { .min = 2, .max = 2 }, 300 /* FIXME: find real m2 limits */ 301 .m2 = { .min = 2 << 22, .max = 255 << 22 }, 302 .p1 = { .min = 2, .max = 4 }, 303 .p2 = { .p2_slow = 1, .p2_fast = 20 }, 304 }; 305 306 /* 307 * Platform specific helpers to calculate the port PLL loopback- (clock.m), 308 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast 309 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. 310 * The helpers' return value is the rate of the clock that is fed to the 311 * display engine's pipe which can be the above fast dot clock rate or a 312 * divided-down version of it. 313 */ 314 /* m1 is reserved as 0 in Pineview, n is a ring counter */ 315 static int pnv_calc_dpll_params(int refclk, struct dpll *clock) 316 { 317 clock->m = clock->m2 + 2; 318 clock->p = clock->p1 * clock->p2; 319 320 clock->vco = clock->n == 0 ? 0 : 321 DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); 322 clock->dot = clock->p == 0 ? 0 : 323 DIV_ROUND_CLOSEST(clock->vco, clock->p); 324 325 return clock->dot; 326 } 327 328 static u32 i9xx_dpll_compute_m(const struct dpll *dpll) 329 { 330 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); 331 } 332 333 int i9xx_calc_dpll_params(int refclk, struct dpll *clock) 334 { 335 clock->m = i9xx_dpll_compute_m(clock); 336 clock->p = clock->p1 * clock->p2; 337 338 clock->vco = clock->n + 2 == 0 ? 0 : 339 DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); 340 clock->dot = clock->p == 0 ? 0 : 341 DIV_ROUND_CLOSEST(clock->vco, clock->p); 342 343 return clock->dot; 344 } 345 346 static int vlv_calc_dpll_params(int refclk, struct dpll *clock) 347 { 348 clock->m = clock->m1 * clock->m2; 349 clock->p = clock->p1 * clock->p2 * 5; 350 351 clock->vco = clock->n == 0 ? 0 : 352 DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); 353 clock->dot = clock->p == 0 ? 0 : 354 DIV_ROUND_CLOSEST(clock->vco, clock->p); 355 356 return clock->dot; 357 } 358 359 int chv_calc_dpll_params(int refclk, struct dpll *clock) 360 { 361 clock->m = clock->m1 * clock->m2; 362 clock->p = clock->p1 * clock->p2 * 5; 363 364 clock->vco = clock->n == 0 ? 0 : 365 DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m), clock->n << 22); 366 clock->dot = clock->p == 0 ? 0 : 367 DIV_ROUND_CLOSEST(clock->vco, clock->p); 368 369 return clock->dot; 370 } 371 372 static int i9xx_pll_refclk(const struct intel_crtc_state *crtc_state) 373 { 374 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 375 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; 376 377 if ((hw_state->dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) 378 return i915->display.vbt.lvds_ssc_freq; 379 else if (HAS_PCH_SPLIT(i915)) 380 return 120000; 381 else if (DISPLAY_VER(i915) != 2) 382 return 96000; 383 else 384 return 48000; 385 } 386 387 void i9xx_dpll_get_hw_state(struct intel_crtc *crtc, 388 struct intel_dpll_hw_state *dpll_hw_state) 389 { 390 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 391 struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx; 392 393 if (DISPLAY_VER(dev_priv) >= 4) { 394 u32 tmp; 395 396 /* No way to read it out on pipes B and C */ 397 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) 398 tmp = dev_priv->display.state.chv_dpll_md[crtc->pipe]; 399 else 400 tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe)); 401 402 hw_state->dpll_md = tmp; 403 } 404 405 hw_state->dpll = intel_de_read(dev_priv, DPLL(crtc->pipe)); 406 407 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { 408 hw_state->fp0 = intel_de_read(dev_priv, FP0(crtc->pipe)); 409 hw_state->fp1 = intel_de_read(dev_priv, FP1(crtc->pipe)); 410 } else { 411 /* Mask out read-only status bits. */ 412 hw_state->dpll &= ~(DPLL_LOCK_VLV | 413 DPLL_PORTC_READY_MASK | 414 DPLL_PORTB_READY_MASK); 415 } 416 } 417 418 /* Returns the clock of the currently programmed mode of the given pipe. */ 419 void i9xx_crtc_clock_get(struct intel_crtc_state *crtc_state) 420 { 421 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 422 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 423 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; 424 u32 dpll = hw_state->dpll; 425 u32 fp; 426 struct dpll clock; 427 int port_clock; 428 int refclk = i9xx_pll_refclk(crtc_state); 429 430 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 431 fp = hw_state->fp0; 432 else 433 fp = hw_state->fp1; 434 435 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 436 if (IS_PINEVIEW(dev_priv)) { 437 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; 438 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; 439 } else { 440 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; 441 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; 442 } 443 444 if (DISPLAY_VER(dev_priv) != 2) { 445 if (IS_PINEVIEW(dev_priv)) 446 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> 447 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); 448 else 449 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> 450 DPLL_FPA01_P1_POST_DIV_SHIFT); 451 452 switch (dpll & DPLL_MODE_MASK) { 453 case DPLLB_MODE_DAC_SERIAL: 454 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? 455 5 : 10; 456 break; 457 case DPLLB_MODE_LVDS: 458 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? 459 7 : 14; 460 break; 461 default: 462 drm_dbg_kms(&dev_priv->drm, 463 "Unknown DPLL mode %08x in programmed " 464 "mode\n", (int)(dpll & DPLL_MODE_MASK)); 465 return; 466 } 467 468 if (IS_PINEVIEW(dev_priv)) 469 port_clock = pnv_calc_dpll_params(refclk, &clock); 470 else 471 port_clock = i9xx_calc_dpll_params(refclk, &clock); 472 } else { 473 enum pipe lvds_pipe; 474 475 if (IS_I85X(dev_priv) && 476 intel_lvds_port_enabled(dev_priv, LVDS, &lvds_pipe) && 477 lvds_pipe == crtc->pipe) { 478 u32 lvds = intel_de_read(dev_priv, LVDS); 479 480 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> 481 DPLL_FPA01_P1_POST_DIV_SHIFT); 482 483 if (lvds & LVDS_CLKB_POWER_UP) 484 clock.p2 = 7; 485 else 486 clock.p2 = 14; 487 } else { 488 if (dpll & PLL_P1_DIVIDE_BY_TWO) 489 clock.p1 = 2; 490 else { 491 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> 492 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; 493 } 494 if (dpll & PLL_P2_DIVIDE_BY_4) 495 clock.p2 = 4; 496 else 497 clock.p2 = 2; 498 } 499 500 port_clock = i9xx_calc_dpll_params(refclk, &clock); 501 } 502 503 /* 504 * This value includes pixel_multiplier. We will use 505 * port_clock to compute adjusted_mode.crtc_clock in the 506 * encoder's get_config() function. 507 */ 508 crtc_state->port_clock = port_clock; 509 } 510 511 void vlv_crtc_clock_get(struct intel_crtc_state *crtc_state) 512 { 513 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 514 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 515 enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); 516 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; 517 struct dpll clock; 518 u32 mdiv; 519 int refclk = 100000; 520 521 /* In case of DSI, DPLL will not be used */ 522 if ((hw_state->dpll & DPLL_VCO_ENABLE) == 0) 523 return; 524 525 vlv_dpio_get(dev_priv); 526 mdiv = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW3(crtc->pipe)); 527 vlv_dpio_put(dev_priv); 528 529 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; 530 clock.m2 = mdiv & DPIO_M2DIV_MASK; 531 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; 532 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; 533 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; 534 535 crtc_state->port_clock = vlv_calc_dpll_params(refclk, &clock); 536 } 537 538 void chv_crtc_clock_get(struct intel_crtc_state *crtc_state) 539 { 540 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 541 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 542 enum dpio_channel port = vlv_pipe_to_channel(crtc->pipe); 543 enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); 544 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; 545 struct dpll clock; 546 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; 547 int refclk = 100000; 548 549 /* In case of DSI, DPLL will not be used */ 550 if ((hw_state->dpll & DPLL_VCO_ENABLE) == 0) 551 return; 552 553 vlv_dpio_get(dev_priv); 554 cmn_dw13 = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW13(port)); 555 pll_dw0 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW0(port)); 556 pll_dw1 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW1(port)); 557 pll_dw2 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW2(port)); 558 pll_dw3 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW3(port)); 559 vlv_dpio_put(dev_priv); 560 561 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; 562 clock.m2 = (pll_dw0 & 0xff) << 22; 563 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) 564 clock.m2 |= pll_dw2 & 0x3fffff; 565 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; 566 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; 567 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; 568 569 crtc_state->port_clock = chv_calc_dpll_params(refclk, &clock); 570 } 571 572 /* 573 * Returns whether the given set of divisors are valid for a given refclk with 574 * the given connectors. 575 */ 576 static bool intel_pll_is_valid(struct drm_i915_private *dev_priv, 577 const struct intel_limit *limit, 578 const struct dpll *clock) 579 { 580 if (clock->n < limit->n.min || limit->n.max < clock->n) 581 return false; 582 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) 583 return false; 584 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) 585 return false; 586 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) 587 return false; 588 589 if (!IS_PINEVIEW(dev_priv) && !IS_LP(dev_priv)) 590 if (clock->m1 <= clock->m2) 591 return false; 592 593 if (!IS_LP(dev_priv)) { 594 if (clock->p < limit->p.min || limit->p.max < clock->p) 595 return false; 596 if (clock->m < limit->m.min || limit->m.max < clock->m) 597 return false; 598 } 599 600 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) 601 return false; 602 /* XXX: We may need to be checking "Dot clock" depending on the multiplier, 603 * connector, etc., rather than just a single range. 604 */ 605 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) 606 return false; 607 608 return true; 609 } 610 611 static int 612 i9xx_select_p2_div(const struct intel_limit *limit, 613 const struct intel_crtc_state *crtc_state, 614 int target) 615 { 616 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 617 618 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 619 /* 620 * For LVDS just rely on its current settings for dual-channel. 621 * We haven't figured out how to reliably set up different 622 * single/dual channel state, if we even can. 623 */ 624 if (intel_is_dual_link_lvds(dev_priv)) 625 return limit->p2.p2_fast; 626 else 627 return limit->p2.p2_slow; 628 } else { 629 if (target < limit->p2.dot_limit) 630 return limit->p2.p2_slow; 631 else 632 return limit->p2.p2_fast; 633 } 634 } 635 636 /* 637 * Returns a set of divisors for the desired target clock with the given 638 * refclk, or FALSE. 639 * 640 * Target and reference clocks are specified in kHz. 641 * 642 * If match_clock is provided, then best_clock P divider must match the P 643 * divider from @match_clock used for LVDS downclocking. 644 */ 645 static bool 646 i9xx_find_best_dpll(const struct intel_limit *limit, 647 struct intel_crtc_state *crtc_state, 648 int target, int refclk, 649 const struct dpll *match_clock, 650 struct dpll *best_clock) 651 { 652 struct drm_device *dev = crtc_state->uapi.crtc->dev; 653 struct dpll clock; 654 int err = target; 655 656 memset(best_clock, 0, sizeof(*best_clock)); 657 658 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); 659 660 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; 661 clock.m1++) { 662 for (clock.m2 = limit->m2.min; 663 clock.m2 <= limit->m2.max; clock.m2++) { 664 if (clock.m2 >= clock.m1) 665 break; 666 for (clock.n = limit->n.min; 667 clock.n <= limit->n.max; clock.n++) { 668 for (clock.p1 = limit->p1.min; 669 clock.p1 <= limit->p1.max; clock.p1++) { 670 int this_err; 671 672 i9xx_calc_dpll_params(refclk, &clock); 673 if (!intel_pll_is_valid(to_i915(dev), 674 limit, 675 &clock)) 676 continue; 677 if (match_clock && 678 clock.p != match_clock->p) 679 continue; 680 681 this_err = abs(clock.dot - target); 682 if (this_err < err) { 683 *best_clock = clock; 684 err = this_err; 685 } 686 } 687 } 688 } 689 } 690 691 return (err != target); 692 } 693 694 /* 695 * Returns a set of divisors for the desired target clock with the given 696 * refclk, or FALSE. 697 * 698 * Target and reference clocks are specified in kHz. 699 * 700 * If match_clock is provided, then best_clock P divider must match the P 701 * divider from @match_clock used for LVDS downclocking. 702 */ 703 static bool 704 pnv_find_best_dpll(const struct intel_limit *limit, 705 struct intel_crtc_state *crtc_state, 706 int target, int refclk, 707 const struct dpll *match_clock, 708 struct dpll *best_clock) 709 { 710 struct drm_device *dev = crtc_state->uapi.crtc->dev; 711 struct dpll clock; 712 int err = target; 713 714 memset(best_clock, 0, sizeof(*best_clock)); 715 716 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); 717 718 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; 719 clock.m1++) { 720 for (clock.m2 = limit->m2.min; 721 clock.m2 <= limit->m2.max; clock.m2++) { 722 for (clock.n = limit->n.min; 723 clock.n <= limit->n.max; clock.n++) { 724 for (clock.p1 = limit->p1.min; 725 clock.p1 <= limit->p1.max; clock.p1++) { 726 int this_err; 727 728 pnv_calc_dpll_params(refclk, &clock); 729 if (!intel_pll_is_valid(to_i915(dev), 730 limit, 731 &clock)) 732 continue; 733 if (match_clock && 734 clock.p != match_clock->p) 735 continue; 736 737 this_err = abs(clock.dot - target); 738 if (this_err < err) { 739 *best_clock = clock; 740 err = this_err; 741 } 742 } 743 } 744 } 745 } 746 747 return (err != target); 748 } 749 750 /* 751 * Returns a set of divisors for the desired target clock with the given 752 * refclk, or FALSE. 753 * 754 * Target and reference clocks are specified in kHz. 755 * 756 * If match_clock is provided, then best_clock P divider must match the P 757 * divider from @match_clock used for LVDS downclocking. 758 */ 759 static bool 760 g4x_find_best_dpll(const struct intel_limit *limit, 761 struct intel_crtc_state *crtc_state, 762 int target, int refclk, 763 const struct dpll *match_clock, 764 struct dpll *best_clock) 765 { 766 struct drm_device *dev = crtc_state->uapi.crtc->dev; 767 struct dpll clock; 768 int max_n; 769 bool found = false; 770 /* approximately equals target * 0.00585 */ 771 int err_most = (target >> 8) + (target >> 9); 772 773 memset(best_clock, 0, sizeof(*best_clock)); 774 775 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); 776 777 max_n = limit->n.max; 778 /* based on hardware requirement, prefer smaller n to precision */ 779 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { 780 /* based on hardware requirement, prefere larger m1,m2 */ 781 for (clock.m1 = limit->m1.max; 782 clock.m1 >= limit->m1.min; clock.m1--) { 783 for (clock.m2 = limit->m2.max; 784 clock.m2 >= limit->m2.min; clock.m2--) { 785 for (clock.p1 = limit->p1.max; 786 clock.p1 >= limit->p1.min; clock.p1--) { 787 int this_err; 788 789 i9xx_calc_dpll_params(refclk, &clock); 790 if (!intel_pll_is_valid(to_i915(dev), 791 limit, 792 &clock)) 793 continue; 794 795 this_err = abs(clock.dot - target); 796 if (this_err < err_most) { 797 *best_clock = clock; 798 err_most = this_err; 799 max_n = clock.n; 800 found = true; 801 } 802 } 803 } 804 } 805 } 806 return found; 807 } 808 809 /* 810 * Check if the calculated PLL configuration is more optimal compared to the 811 * best configuration and error found so far. Return the calculated error. 812 */ 813 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, 814 const struct dpll *calculated_clock, 815 const struct dpll *best_clock, 816 unsigned int best_error_ppm, 817 unsigned int *error_ppm) 818 { 819 /* 820 * For CHV ignore the error and consider only the P value. 821 * Prefer a bigger P value based on HW requirements. 822 */ 823 if (IS_CHERRYVIEW(to_i915(dev))) { 824 *error_ppm = 0; 825 826 return calculated_clock->p > best_clock->p; 827 } 828 829 if (drm_WARN_ON_ONCE(dev, !target_freq)) 830 return false; 831 832 *error_ppm = div_u64(1000000ULL * 833 abs(target_freq - calculated_clock->dot), 834 target_freq); 835 /* 836 * Prefer a better P value over a better (smaller) error if the error 837 * is small. Ensure this preference for future configurations too by 838 * setting the error to 0. 839 */ 840 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { 841 *error_ppm = 0; 842 843 return true; 844 } 845 846 return *error_ppm + 10 < best_error_ppm; 847 } 848 849 /* 850 * Returns a set of divisors for the desired target clock with the given 851 * refclk, or FALSE. 852 */ 853 static bool 854 vlv_find_best_dpll(const struct intel_limit *limit, 855 struct intel_crtc_state *crtc_state, 856 int target, int refclk, 857 const struct dpll *match_clock, 858 struct dpll *best_clock) 859 { 860 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 861 struct drm_device *dev = crtc->base.dev; 862 struct dpll clock; 863 unsigned int bestppm = 1000000; 864 /* min update 19.2 MHz */ 865 int max_n = min(limit->n.max, refclk / 19200); 866 bool found = false; 867 868 memset(best_clock, 0, sizeof(*best_clock)); 869 870 /* based on hardware requirement, prefer smaller n to precision */ 871 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { 872 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { 873 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; 874 clock.p2 -= clock.p2 > 10 ? 2 : 1) { 875 clock.p = clock.p1 * clock.p2 * 5; 876 /* based on hardware requirement, prefer bigger m1,m2 values */ 877 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { 878 unsigned int ppm; 879 880 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, 881 refclk * clock.m1); 882 883 vlv_calc_dpll_params(refclk, &clock); 884 885 if (!intel_pll_is_valid(to_i915(dev), 886 limit, 887 &clock)) 888 continue; 889 890 if (!vlv_PLL_is_optimal(dev, target, 891 &clock, 892 best_clock, 893 bestppm, &ppm)) 894 continue; 895 896 *best_clock = clock; 897 bestppm = ppm; 898 found = true; 899 } 900 } 901 } 902 } 903 904 return found; 905 } 906 907 /* 908 * Returns a set of divisors for the desired target clock with the given 909 * refclk, or FALSE. 910 */ 911 static bool 912 chv_find_best_dpll(const struct intel_limit *limit, 913 struct intel_crtc_state *crtc_state, 914 int target, int refclk, 915 const struct dpll *match_clock, 916 struct dpll *best_clock) 917 { 918 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 919 struct drm_device *dev = crtc->base.dev; 920 unsigned int best_error_ppm; 921 struct dpll clock; 922 u64 m2; 923 int found = false; 924 925 memset(best_clock, 0, sizeof(*best_clock)); 926 best_error_ppm = 1000000; 927 928 /* 929 * Based on hardware doc, the n always set to 1, and m1 always 930 * set to 2. If requires to support 200Mhz refclk, we need to 931 * revisit this because n may not 1 anymore. 932 */ 933 clock.n = 1; 934 clock.m1 = 2; 935 936 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { 937 for (clock.p2 = limit->p2.p2_fast; 938 clock.p2 >= limit->p2.p2_slow; 939 clock.p2 -= clock.p2 > 10 ? 2 : 1) { 940 unsigned int error_ppm; 941 942 clock.p = clock.p1 * clock.p2 * 5; 943 944 m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22, 945 refclk * clock.m1); 946 947 if (m2 > INT_MAX/clock.m1) 948 continue; 949 950 clock.m2 = m2; 951 952 chv_calc_dpll_params(refclk, &clock); 953 954 if (!intel_pll_is_valid(to_i915(dev), limit, &clock)) 955 continue; 956 957 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, 958 best_error_ppm, &error_ppm)) 959 continue; 960 961 *best_clock = clock; 962 best_error_ppm = error_ppm; 963 found = true; 964 } 965 } 966 967 return found; 968 } 969 970 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, 971 struct dpll *best_clock) 972 { 973 const struct intel_limit *limit = &intel_limits_bxt; 974 int refclk = 100000; 975 976 return chv_find_best_dpll(limit, crtc_state, 977 crtc_state->port_clock, refclk, 978 NULL, best_clock); 979 } 980 981 u32 i9xx_dpll_compute_fp(const struct dpll *dpll) 982 { 983 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; 984 } 985 986 static u32 pnv_dpll_compute_fp(const struct dpll *dpll) 987 { 988 return (1 << dpll->n) << 16 | dpll->m2; 989 } 990 991 static u32 i965_dpll_md(const struct intel_crtc_state *crtc_state) 992 { 993 return (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; 994 } 995 996 static u32 i9xx_dpll(const struct intel_crtc_state *crtc_state, 997 const struct dpll *clock, 998 const struct dpll *reduced_clock) 999 { 1000 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1001 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1002 u32 dpll; 1003 1004 dpll = DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS; 1005 1006 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) 1007 dpll |= DPLLB_MODE_LVDS; 1008 else 1009 dpll |= DPLLB_MODE_DAC_SERIAL; 1010 1011 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || 1012 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { 1013 dpll |= (crtc_state->pixel_multiplier - 1) 1014 << SDVO_MULTIPLIER_SHIFT_HIRES; 1015 } 1016 1017 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || 1018 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1019 dpll |= DPLL_SDVO_HIGH_SPEED; 1020 1021 if (intel_crtc_has_dp_encoder(crtc_state)) 1022 dpll |= DPLL_SDVO_HIGH_SPEED; 1023 1024 /* compute bitmask from p1 value */ 1025 if (IS_G4X(dev_priv)) { 1026 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 1027 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; 1028 } else if (IS_PINEVIEW(dev_priv)) { 1029 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; 1030 WARN_ON(reduced_clock->p1 != clock->p1); 1031 } else { 1032 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 1033 WARN_ON(reduced_clock->p1 != clock->p1); 1034 } 1035 1036 switch (clock->p2) { 1037 case 5: 1038 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; 1039 break; 1040 case 7: 1041 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; 1042 break; 1043 case 10: 1044 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; 1045 break; 1046 case 14: 1047 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; 1048 break; 1049 } 1050 WARN_ON(reduced_clock->p2 != clock->p2); 1051 1052 if (DISPLAY_VER(dev_priv) >= 4) 1053 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); 1054 1055 if (crtc_state->sdvo_tv_clock) 1056 dpll |= PLL_REF_INPUT_TVCLKINBC; 1057 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 1058 intel_panel_use_ssc(dev_priv)) 1059 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 1060 else 1061 dpll |= PLL_REF_INPUT_DREFCLK; 1062 1063 return dpll; 1064 } 1065 1066 static void i9xx_compute_dpll(struct intel_crtc_state *crtc_state, 1067 const struct dpll *clock, 1068 const struct dpll *reduced_clock) 1069 { 1070 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1071 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1072 struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; 1073 1074 if (IS_PINEVIEW(dev_priv)) { 1075 hw_state->fp0 = pnv_dpll_compute_fp(clock); 1076 hw_state->fp1 = pnv_dpll_compute_fp(reduced_clock); 1077 } else { 1078 hw_state->fp0 = i9xx_dpll_compute_fp(clock); 1079 hw_state->fp1 = i9xx_dpll_compute_fp(reduced_clock); 1080 } 1081 1082 hw_state->dpll = i9xx_dpll(crtc_state, clock, reduced_clock); 1083 1084 if (DISPLAY_VER(dev_priv) >= 4) 1085 hw_state->dpll_md = i965_dpll_md(crtc_state); 1086 } 1087 1088 static u32 i8xx_dpll(const struct intel_crtc_state *crtc_state, 1089 const struct dpll *clock, 1090 const struct dpll *reduced_clock) 1091 { 1092 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1093 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1094 u32 dpll; 1095 1096 dpll = DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS; 1097 1098 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 1099 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 1100 } else { 1101 if (clock->p1 == 2) 1102 dpll |= PLL_P1_DIVIDE_BY_TWO; 1103 else 1104 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; 1105 if (clock->p2 == 4) 1106 dpll |= PLL_P2_DIVIDE_BY_4; 1107 } 1108 WARN_ON(reduced_clock->p1 != clock->p1); 1109 WARN_ON(reduced_clock->p2 != clock->p2); 1110 1111 /* 1112 * Bspec: 1113 * "[Almador Errata}: For the correct operation of the muxed DVO pins 1114 * (GDEVSELB/I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data, 1115 * GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock 1116 * Enable) must be set to “1” in both the DPLL A Control Register 1117 * (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)." 1118 * 1119 * For simplicity We simply keep both bits always enabled in 1120 * both DPLLS. The spec says we should disable the DVO 2X clock 1121 * when not needed, but this seems to work fine in practice. 1122 */ 1123 if (IS_I830(dev_priv) || 1124 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) 1125 dpll |= DPLL_DVO_2X_MODE; 1126 1127 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 1128 intel_panel_use_ssc(dev_priv)) 1129 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 1130 else 1131 dpll |= PLL_REF_INPUT_DREFCLK; 1132 1133 return dpll; 1134 } 1135 1136 static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state, 1137 const struct dpll *clock, 1138 const struct dpll *reduced_clock) 1139 { 1140 struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; 1141 1142 hw_state->fp0 = i9xx_dpll_compute_fp(clock); 1143 hw_state->fp1 = i9xx_dpll_compute_fp(reduced_clock); 1144 1145 hw_state->dpll = i8xx_dpll(crtc_state, clock, reduced_clock); 1146 } 1147 1148 static int hsw_crtc_compute_clock(struct intel_atomic_state *state, 1149 struct intel_crtc *crtc) 1150 { 1151 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1152 struct intel_crtc_state *crtc_state = 1153 intel_atomic_get_new_crtc_state(state, crtc); 1154 struct intel_encoder *encoder = 1155 intel_get_crtc_new_encoder(state, crtc_state); 1156 int ret; 1157 1158 if (DISPLAY_VER(dev_priv) < 11 && 1159 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) 1160 return 0; 1161 1162 ret = intel_compute_shared_dplls(state, crtc, encoder); 1163 if (ret) 1164 return ret; 1165 1166 /* FIXME this is a mess */ 1167 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) 1168 return 0; 1169 1170 /* CRT dotclock is determined via other means */ 1171 if (!crtc_state->has_pch_encoder) 1172 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); 1173 1174 return 0; 1175 } 1176 1177 static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state, 1178 struct intel_crtc *crtc) 1179 { 1180 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1181 struct intel_crtc_state *crtc_state = 1182 intel_atomic_get_new_crtc_state(state, crtc); 1183 struct intel_encoder *encoder = 1184 intel_get_crtc_new_encoder(state, crtc_state); 1185 1186 if (DISPLAY_VER(dev_priv) < 11 && 1187 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) 1188 return 0; 1189 1190 return intel_reserve_shared_dplls(state, crtc, encoder); 1191 } 1192 1193 static int dg2_crtc_compute_clock(struct intel_atomic_state *state, 1194 struct intel_crtc *crtc) 1195 { 1196 struct intel_crtc_state *crtc_state = 1197 intel_atomic_get_new_crtc_state(state, crtc); 1198 struct intel_encoder *encoder = 1199 intel_get_crtc_new_encoder(state, crtc_state); 1200 int ret; 1201 1202 ret = intel_mpllb_calc_state(crtc_state, encoder); 1203 if (ret) 1204 return ret; 1205 1206 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); 1207 1208 return 0; 1209 } 1210 1211 static int mtl_crtc_compute_clock(struct intel_atomic_state *state, 1212 struct intel_crtc *crtc) 1213 { 1214 struct intel_crtc_state *crtc_state = 1215 intel_atomic_get_new_crtc_state(state, crtc); 1216 struct intel_encoder *encoder = 1217 intel_get_crtc_new_encoder(state, crtc_state); 1218 int ret; 1219 1220 ret = intel_cx0pll_calc_state(crtc_state, encoder); 1221 if (ret) 1222 return ret; 1223 1224 /* TODO: Do the readback via intel_compute_shared_dplls() */ 1225 crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll); 1226 1227 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); 1228 1229 return 0; 1230 } 1231 1232 static int ilk_fb_cb_factor(const struct intel_crtc_state *crtc_state) 1233 { 1234 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1235 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 1236 1237 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 1238 ((intel_panel_use_ssc(i915) && i915->display.vbt.lvds_ssc_freq == 100000) || 1239 (HAS_PCH_IBX(i915) && intel_is_dual_link_lvds(i915)))) 1240 return 25; 1241 1242 if (crtc_state->sdvo_tv_clock) 1243 return 20; 1244 1245 return 21; 1246 } 1247 1248 static bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor) 1249 { 1250 return dpll->m < factor * dpll->n; 1251 } 1252 1253 static u32 ilk_dpll_compute_fp(const struct dpll *clock, int factor) 1254 { 1255 u32 fp; 1256 1257 fp = i9xx_dpll_compute_fp(clock); 1258 if (ilk_needs_fb_cb_tune(clock, factor)) 1259 fp |= FP_CB_TUNE; 1260 1261 return fp; 1262 } 1263 1264 static u32 ilk_dpll(const struct intel_crtc_state *crtc_state, 1265 const struct dpll *clock, 1266 const struct dpll *reduced_clock) 1267 { 1268 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1269 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1270 u32 dpll; 1271 1272 dpll = DPLL_VCO_ENABLE; 1273 1274 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) 1275 dpll |= DPLLB_MODE_LVDS; 1276 else 1277 dpll |= DPLLB_MODE_DAC_SERIAL; 1278 1279 dpll |= (crtc_state->pixel_multiplier - 1) 1280 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; 1281 1282 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || 1283 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1284 dpll |= DPLL_SDVO_HIGH_SPEED; 1285 1286 if (intel_crtc_has_dp_encoder(crtc_state)) 1287 dpll |= DPLL_SDVO_HIGH_SPEED; 1288 1289 /* 1290 * The high speed IO clock is only really required for 1291 * SDVO/HDMI/DP, but we also enable it for CRT to make it 1292 * possible to share the DPLL between CRT and HDMI. Enabling 1293 * the clock needlessly does no real harm, except use up a 1294 * bit of power potentially. 1295 * 1296 * We'll limit this to IVB with 3 pipes, since it has only two 1297 * DPLLs and so DPLL sharing is the only way to get three pipes 1298 * driving PCH ports at the same time. On SNB we could do this, 1299 * and potentially avoid enabling the second DPLL, but it's not 1300 * clear if it''s a win or loss power wise. No point in doing 1301 * this on ILK at all since it has a fixed DPLL<->pipe mapping. 1302 */ 1303 if (INTEL_NUM_PIPES(dev_priv) == 3 && 1304 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) 1305 dpll |= DPLL_SDVO_HIGH_SPEED; 1306 1307 /* compute bitmask from p1 value */ 1308 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 1309 /* also FPA1 */ 1310 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; 1311 1312 switch (clock->p2) { 1313 case 5: 1314 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; 1315 break; 1316 case 7: 1317 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; 1318 break; 1319 case 10: 1320 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; 1321 break; 1322 case 14: 1323 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; 1324 break; 1325 } 1326 WARN_ON(reduced_clock->p2 != clock->p2); 1327 1328 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 1329 intel_panel_use_ssc(dev_priv)) 1330 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 1331 else 1332 dpll |= PLL_REF_INPUT_DREFCLK; 1333 1334 return dpll; 1335 } 1336 1337 static void ilk_compute_dpll(struct intel_crtc_state *crtc_state, 1338 const struct dpll *clock, 1339 const struct dpll *reduced_clock) 1340 { 1341 struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; 1342 int factor = ilk_fb_cb_factor(crtc_state); 1343 1344 hw_state->fp0 = ilk_dpll_compute_fp(clock, factor); 1345 hw_state->fp1 = ilk_dpll_compute_fp(reduced_clock, factor); 1346 1347 hw_state->dpll = ilk_dpll(crtc_state, clock, reduced_clock); 1348 } 1349 1350 static int ilk_crtc_compute_clock(struct intel_atomic_state *state, 1351 struct intel_crtc *crtc) 1352 { 1353 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1354 struct intel_crtc_state *crtc_state = 1355 intel_atomic_get_new_crtc_state(state, crtc); 1356 const struct intel_limit *limit; 1357 int refclk = 120000; 1358 int ret; 1359 1360 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ 1361 if (!crtc_state->has_pch_encoder) 1362 return 0; 1363 1364 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 1365 if (intel_panel_use_ssc(dev_priv)) { 1366 drm_dbg_kms(&dev_priv->drm, 1367 "using SSC reference clock of %d kHz\n", 1368 dev_priv->display.vbt.lvds_ssc_freq); 1369 refclk = dev_priv->display.vbt.lvds_ssc_freq; 1370 } 1371 1372 if (intel_is_dual_link_lvds(dev_priv)) { 1373 if (refclk == 100000) 1374 limit = &ilk_limits_dual_lvds_100m; 1375 else 1376 limit = &ilk_limits_dual_lvds; 1377 } else { 1378 if (refclk == 100000) 1379 limit = &ilk_limits_single_lvds_100m; 1380 else 1381 limit = &ilk_limits_single_lvds; 1382 } 1383 } else { 1384 limit = &ilk_limits_dac; 1385 } 1386 1387 if (!crtc_state->clock_set && 1388 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1389 refclk, NULL, &crtc_state->dpll)) 1390 return -EINVAL; 1391 1392 i9xx_calc_dpll_params(refclk, &crtc_state->dpll); 1393 1394 ilk_compute_dpll(crtc_state, &crtc_state->dpll, 1395 &crtc_state->dpll); 1396 1397 ret = intel_compute_shared_dplls(state, crtc, NULL); 1398 if (ret) 1399 return ret; 1400 1401 crtc_state->port_clock = crtc_state->dpll.dot; 1402 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); 1403 1404 return ret; 1405 } 1406 1407 static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state, 1408 struct intel_crtc *crtc) 1409 { 1410 struct intel_crtc_state *crtc_state = 1411 intel_atomic_get_new_crtc_state(state, crtc); 1412 1413 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ 1414 if (!crtc_state->has_pch_encoder) 1415 return 0; 1416 1417 return intel_reserve_shared_dplls(state, crtc, NULL); 1418 } 1419 1420 static u32 vlv_dpll(const struct intel_crtc_state *crtc_state) 1421 { 1422 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1423 u32 dpll; 1424 1425 dpll = DPLL_INTEGRATED_REF_CLK_VLV | 1426 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 1427 1428 if (crtc->pipe != PIPE_A) 1429 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; 1430 1431 /* DPLL not used with DSI, but still need the rest set up */ 1432 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) 1433 dpll |= DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV; 1434 1435 return dpll; 1436 } 1437 1438 void vlv_compute_dpll(struct intel_crtc_state *crtc_state) 1439 { 1440 struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; 1441 1442 hw_state->dpll = vlv_dpll(crtc_state); 1443 hw_state->dpll_md = i965_dpll_md(crtc_state); 1444 } 1445 1446 static u32 chv_dpll(const struct intel_crtc_state *crtc_state) 1447 { 1448 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1449 u32 dpll; 1450 1451 dpll = DPLL_SSC_REF_CLK_CHV | 1452 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 1453 1454 if (crtc->pipe != PIPE_A) 1455 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; 1456 1457 /* DPLL not used with DSI, but still need the rest set up */ 1458 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) 1459 dpll |= DPLL_VCO_ENABLE; 1460 1461 return dpll; 1462 } 1463 1464 void chv_compute_dpll(struct intel_crtc_state *crtc_state) 1465 { 1466 struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; 1467 1468 hw_state->dpll = chv_dpll(crtc_state); 1469 hw_state->dpll_md = i965_dpll_md(crtc_state); 1470 } 1471 1472 static int chv_crtc_compute_clock(struct intel_atomic_state *state, 1473 struct intel_crtc *crtc) 1474 { 1475 struct intel_crtc_state *crtc_state = 1476 intel_atomic_get_new_crtc_state(state, crtc); 1477 const struct intel_limit *limit = &intel_limits_chv; 1478 int refclk = 100000; 1479 1480 if (!crtc_state->clock_set && 1481 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1482 refclk, NULL, &crtc_state->dpll)) 1483 return -EINVAL; 1484 1485 chv_calc_dpll_params(refclk, &crtc_state->dpll); 1486 1487 chv_compute_dpll(crtc_state); 1488 1489 /* FIXME this is a mess */ 1490 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) 1491 return 0; 1492 1493 crtc_state->port_clock = crtc_state->dpll.dot; 1494 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); 1495 1496 return 0; 1497 } 1498 1499 static int vlv_crtc_compute_clock(struct intel_atomic_state *state, 1500 struct intel_crtc *crtc) 1501 { 1502 struct intel_crtc_state *crtc_state = 1503 intel_atomic_get_new_crtc_state(state, crtc); 1504 const struct intel_limit *limit = &intel_limits_vlv; 1505 int refclk = 100000; 1506 1507 if (!crtc_state->clock_set && 1508 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1509 refclk, NULL, &crtc_state->dpll)) 1510 return -EINVAL; 1511 1512 vlv_calc_dpll_params(refclk, &crtc_state->dpll); 1513 1514 vlv_compute_dpll(crtc_state); 1515 1516 /* FIXME this is a mess */ 1517 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) 1518 return 0; 1519 1520 crtc_state->port_clock = crtc_state->dpll.dot; 1521 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); 1522 1523 return 0; 1524 } 1525 1526 static int g4x_crtc_compute_clock(struct intel_atomic_state *state, 1527 struct intel_crtc *crtc) 1528 { 1529 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1530 struct intel_crtc_state *crtc_state = 1531 intel_atomic_get_new_crtc_state(state, crtc); 1532 const struct intel_limit *limit; 1533 int refclk = 96000; 1534 1535 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 1536 if (intel_panel_use_ssc(dev_priv)) { 1537 refclk = dev_priv->display.vbt.lvds_ssc_freq; 1538 drm_dbg_kms(&dev_priv->drm, 1539 "using SSC reference clock of %d kHz\n", 1540 refclk); 1541 } 1542 1543 if (intel_is_dual_link_lvds(dev_priv)) 1544 limit = &intel_limits_g4x_dual_channel_lvds; 1545 else 1546 limit = &intel_limits_g4x_single_channel_lvds; 1547 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) || 1548 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 1549 limit = &intel_limits_g4x_hdmi; 1550 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) { 1551 limit = &intel_limits_g4x_sdvo; 1552 } else { 1553 /* The option is for other outputs */ 1554 limit = &intel_limits_i9xx_sdvo; 1555 } 1556 1557 if (!crtc_state->clock_set && 1558 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1559 refclk, NULL, &crtc_state->dpll)) 1560 return -EINVAL; 1561 1562 i9xx_calc_dpll_params(refclk, &crtc_state->dpll); 1563 1564 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, 1565 &crtc_state->dpll); 1566 1567 crtc_state->port_clock = crtc_state->dpll.dot; 1568 /* FIXME this is a mess */ 1569 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_TVOUT)) 1570 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); 1571 1572 return 0; 1573 } 1574 1575 static int pnv_crtc_compute_clock(struct intel_atomic_state *state, 1576 struct intel_crtc *crtc) 1577 { 1578 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1579 struct intel_crtc_state *crtc_state = 1580 intel_atomic_get_new_crtc_state(state, crtc); 1581 const struct intel_limit *limit; 1582 int refclk = 96000; 1583 1584 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 1585 if (intel_panel_use_ssc(dev_priv)) { 1586 refclk = dev_priv->display.vbt.lvds_ssc_freq; 1587 drm_dbg_kms(&dev_priv->drm, 1588 "using SSC reference clock of %d kHz\n", 1589 refclk); 1590 } 1591 1592 limit = &pnv_limits_lvds; 1593 } else { 1594 limit = &pnv_limits_sdvo; 1595 } 1596 1597 if (!crtc_state->clock_set && 1598 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1599 refclk, NULL, &crtc_state->dpll)) 1600 return -EINVAL; 1601 1602 pnv_calc_dpll_params(refclk, &crtc_state->dpll); 1603 1604 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, 1605 &crtc_state->dpll); 1606 1607 crtc_state->port_clock = crtc_state->dpll.dot; 1608 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); 1609 1610 return 0; 1611 } 1612 1613 static int i9xx_crtc_compute_clock(struct intel_atomic_state *state, 1614 struct intel_crtc *crtc) 1615 { 1616 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1617 struct intel_crtc_state *crtc_state = 1618 intel_atomic_get_new_crtc_state(state, crtc); 1619 const struct intel_limit *limit; 1620 int refclk = 96000; 1621 1622 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 1623 if (intel_panel_use_ssc(dev_priv)) { 1624 refclk = dev_priv->display.vbt.lvds_ssc_freq; 1625 drm_dbg_kms(&dev_priv->drm, 1626 "using SSC reference clock of %d kHz\n", 1627 refclk); 1628 } 1629 1630 limit = &intel_limits_i9xx_lvds; 1631 } else { 1632 limit = &intel_limits_i9xx_sdvo; 1633 } 1634 1635 if (!crtc_state->clock_set && 1636 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1637 refclk, NULL, &crtc_state->dpll)) 1638 return -EINVAL; 1639 1640 i9xx_calc_dpll_params(refclk, &crtc_state->dpll); 1641 1642 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, 1643 &crtc_state->dpll); 1644 1645 crtc_state->port_clock = crtc_state->dpll.dot; 1646 /* FIXME this is a mess */ 1647 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_TVOUT)) 1648 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); 1649 1650 return 0; 1651 } 1652 1653 static int i8xx_crtc_compute_clock(struct intel_atomic_state *state, 1654 struct intel_crtc *crtc) 1655 { 1656 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1657 struct intel_crtc_state *crtc_state = 1658 intel_atomic_get_new_crtc_state(state, crtc); 1659 const struct intel_limit *limit; 1660 int refclk = 48000; 1661 1662 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 1663 if (intel_panel_use_ssc(dev_priv)) { 1664 refclk = dev_priv->display.vbt.lvds_ssc_freq; 1665 drm_dbg_kms(&dev_priv->drm, 1666 "using SSC reference clock of %d kHz\n", 1667 refclk); 1668 } 1669 1670 limit = &intel_limits_i8xx_lvds; 1671 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) { 1672 limit = &intel_limits_i8xx_dvo; 1673 } else { 1674 limit = &intel_limits_i8xx_dac; 1675 } 1676 1677 if (!crtc_state->clock_set && 1678 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1679 refclk, NULL, &crtc_state->dpll)) 1680 return -EINVAL; 1681 1682 i9xx_calc_dpll_params(refclk, &crtc_state->dpll); 1683 1684 i8xx_compute_dpll(crtc_state, &crtc_state->dpll, 1685 &crtc_state->dpll); 1686 1687 crtc_state->port_clock = crtc_state->dpll.dot; 1688 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); 1689 1690 return 0; 1691 } 1692 1693 static const struct intel_dpll_funcs mtl_dpll_funcs = { 1694 .crtc_compute_clock = mtl_crtc_compute_clock, 1695 }; 1696 1697 static const struct intel_dpll_funcs dg2_dpll_funcs = { 1698 .crtc_compute_clock = dg2_crtc_compute_clock, 1699 }; 1700 1701 static const struct intel_dpll_funcs hsw_dpll_funcs = { 1702 .crtc_compute_clock = hsw_crtc_compute_clock, 1703 .crtc_get_shared_dpll = hsw_crtc_get_shared_dpll, 1704 }; 1705 1706 static const struct intel_dpll_funcs ilk_dpll_funcs = { 1707 .crtc_compute_clock = ilk_crtc_compute_clock, 1708 .crtc_get_shared_dpll = ilk_crtc_get_shared_dpll, 1709 }; 1710 1711 static const struct intel_dpll_funcs chv_dpll_funcs = { 1712 .crtc_compute_clock = chv_crtc_compute_clock, 1713 }; 1714 1715 static const struct intel_dpll_funcs vlv_dpll_funcs = { 1716 .crtc_compute_clock = vlv_crtc_compute_clock, 1717 }; 1718 1719 static const struct intel_dpll_funcs g4x_dpll_funcs = { 1720 .crtc_compute_clock = g4x_crtc_compute_clock, 1721 }; 1722 1723 static const struct intel_dpll_funcs pnv_dpll_funcs = { 1724 .crtc_compute_clock = pnv_crtc_compute_clock, 1725 }; 1726 1727 static const struct intel_dpll_funcs i9xx_dpll_funcs = { 1728 .crtc_compute_clock = i9xx_crtc_compute_clock, 1729 }; 1730 1731 static const struct intel_dpll_funcs i8xx_dpll_funcs = { 1732 .crtc_compute_clock = i8xx_crtc_compute_clock, 1733 }; 1734 1735 int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state, 1736 struct intel_crtc *crtc) 1737 { 1738 struct drm_i915_private *i915 = to_i915(state->base.dev); 1739 struct intel_crtc_state *crtc_state = 1740 intel_atomic_get_new_crtc_state(state, crtc); 1741 int ret; 1742 1743 drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state)); 1744 1745 memset(&crtc_state->dpll_hw_state, 0, 1746 sizeof(crtc_state->dpll_hw_state)); 1747 1748 if (!crtc_state->hw.enable) 1749 return 0; 1750 1751 ret = i915->display.funcs.dpll->crtc_compute_clock(state, crtc); 1752 if (ret) { 1753 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't calculate DPLL settings\n", 1754 crtc->base.base.id, crtc->base.name); 1755 return ret; 1756 } 1757 1758 return 0; 1759 } 1760 1761 int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state, 1762 struct intel_crtc *crtc) 1763 { 1764 struct drm_i915_private *i915 = to_i915(state->base.dev); 1765 struct intel_crtc_state *crtc_state = 1766 intel_atomic_get_new_crtc_state(state, crtc); 1767 int ret; 1768 1769 drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state)); 1770 drm_WARN_ON(&i915->drm, !crtc_state->hw.enable && crtc_state->shared_dpll); 1771 1772 if (!crtc_state->hw.enable || crtc_state->shared_dpll) 1773 return 0; 1774 1775 if (!i915->display.funcs.dpll->crtc_get_shared_dpll) 1776 return 0; 1777 1778 ret = i915->display.funcs.dpll->crtc_get_shared_dpll(state, crtc); 1779 if (ret) { 1780 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't get a shared DPLL\n", 1781 crtc->base.base.id, crtc->base.name); 1782 return ret; 1783 } 1784 1785 return 0; 1786 } 1787 1788 void 1789 intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv) 1790 { 1791 if (DISPLAY_VER(dev_priv) >= 14) 1792 dev_priv->display.funcs.dpll = &mtl_dpll_funcs; 1793 else if (IS_DG2(dev_priv)) 1794 dev_priv->display.funcs.dpll = &dg2_dpll_funcs; 1795 else if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv)) 1796 dev_priv->display.funcs.dpll = &hsw_dpll_funcs; 1797 else if (HAS_PCH_SPLIT(dev_priv)) 1798 dev_priv->display.funcs.dpll = &ilk_dpll_funcs; 1799 else if (IS_CHERRYVIEW(dev_priv)) 1800 dev_priv->display.funcs.dpll = &chv_dpll_funcs; 1801 else if (IS_VALLEYVIEW(dev_priv)) 1802 dev_priv->display.funcs.dpll = &vlv_dpll_funcs; 1803 else if (IS_G4X(dev_priv)) 1804 dev_priv->display.funcs.dpll = &g4x_dpll_funcs; 1805 else if (IS_PINEVIEW(dev_priv)) 1806 dev_priv->display.funcs.dpll = &pnv_dpll_funcs; 1807 else if (DISPLAY_VER(dev_priv) != 2) 1808 dev_priv->display.funcs.dpll = &i9xx_dpll_funcs; 1809 else 1810 dev_priv->display.funcs.dpll = &i8xx_dpll_funcs; 1811 } 1812 1813 static bool i9xx_has_pps(struct drm_i915_private *dev_priv) 1814 { 1815 if (IS_I830(dev_priv)) 1816 return false; 1817 1818 return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); 1819 } 1820 1821 void i9xx_enable_pll(const struct intel_crtc_state *crtc_state) 1822 { 1823 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1824 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1825 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; 1826 enum pipe pipe = crtc->pipe; 1827 int i; 1828 1829 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); 1830 1831 /* PLL is protected by panel, make sure we can write it */ 1832 if (i9xx_has_pps(dev_priv)) 1833 assert_pps_unlocked(dev_priv, pipe); 1834 1835 intel_de_write(dev_priv, FP0(pipe), hw_state->fp0); 1836 intel_de_write(dev_priv, FP1(pipe), hw_state->fp1); 1837 1838 /* 1839 * Apparently we need to have VGA mode enabled prior to changing 1840 * the P1/P2 dividers. Otherwise the DPLL will keep using the old 1841 * dividers, even though the register value does change. 1842 */ 1843 intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll & ~DPLL_VGA_MODE_DIS); 1844 intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll); 1845 1846 /* Wait for the clocks to stabilize. */ 1847 intel_de_posting_read(dev_priv, DPLL(pipe)); 1848 udelay(150); 1849 1850 if (DISPLAY_VER(dev_priv) >= 4) { 1851 intel_de_write(dev_priv, DPLL_MD(pipe), hw_state->dpll_md); 1852 } else { 1853 /* The pixel multiplier can only be updated once the 1854 * DPLL is enabled and the clocks are stable. 1855 * 1856 * So write it again. 1857 */ 1858 intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll); 1859 } 1860 1861 /* We do this three times for luck */ 1862 for (i = 0; i < 3; i++) { 1863 intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll); 1864 intel_de_posting_read(dev_priv, DPLL(pipe)); 1865 udelay(150); /* wait for warmup */ 1866 } 1867 } 1868 1869 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, 1870 enum dpio_phy phy) 1871 { 1872 u32 reg_val; 1873 1874 /* 1875 * PLLB opamp always calibrates to max value of 0x3f, force enable it 1876 * and set it to a reasonable value instead. 1877 */ 1878 reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW9(1)); 1879 reg_val &= 0xffffff00; 1880 reg_val |= 0x00000030; 1881 vlv_dpio_write(dev_priv, phy, VLV_PLL_DW9(1), reg_val); 1882 1883 reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW13); 1884 reg_val &= 0x00ffffff; 1885 reg_val |= 0x8c000000; 1886 vlv_dpio_write(dev_priv, phy, VLV_REF_DW13, reg_val); 1887 1888 reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW9(1)); 1889 reg_val &= 0xffffff00; 1890 vlv_dpio_write(dev_priv, phy, VLV_PLL_DW9(1), reg_val); 1891 1892 reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW13); 1893 reg_val &= 0x00ffffff; 1894 reg_val |= 0xb0000000; 1895 vlv_dpio_write(dev_priv, phy, VLV_REF_DW13, reg_val); 1896 } 1897 1898 static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state) 1899 { 1900 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1901 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1902 enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); 1903 enum pipe pipe = crtc->pipe; 1904 u32 mdiv; 1905 u32 bestn, bestm1, bestm2, bestp1, bestp2; 1906 u32 coreclk, reg_val; 1907 1908 vlv_dpio_get(dev_priv); 1909 1910 bestn = crtc_state->dpll.n; 1911 bestm1 = crtc_state->dpll.m1; 1912 bestm2 = crtc_state->dpll.m2; 1913 bestp1 = crtc_state->dpll.p1; 1914 bestp2 = crtc_state->dpll.p2; 1915 1916 /* See eDP HDMI DPIO driver vbios notes doc */ 1917 1918 /* PLL B needs special handling */ 1919 if (pipe == PIPE_B) 1920 vlv_pllb_recal_opamp(dev_priv, phy); 1921 1922 /* Set up Tx target for periodic Rcomp update */ 1923 vlv_dpio_write(dev_priv, phy, VLV_PLL_DW9_BCAST, 0x0100000f); 1924 1925 /* Disable target IRef on PLL */ 1926 reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW8(pipe)); 1927 reg_val &= 0x00ffffff; 1928 vlv_dpio_write(dev_priv, phy, VLV_PLL_DW8(pipe), reg_val); 1929 1930 /* Disable fast lock */ 1931 vlv_dpio_write(dev_priv, phy, VLV_CMN_DW0, 0x610); 1932 1933 /* Set idtafcrecal before PLL is enabled */ 1934 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); 1935 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); 1936 mdiv |= ((bestn << DPIO_N_SHIFT)); 1937 mdiv |= (1 << DPIO_K_SHIFT); 1938 1939 /* 1940 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, 1941 * but we don't support that). 1942 * Note: don't use the DAC post divider as it seems unstable. 1943 */ 1944 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); 1945 vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(pipe), mdiv); 1946 1947 mdiv |= DPIO_ENABLE_CALIBRATION; 1948 vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(pipe), mdiv); 1949 1950 /* Set HBR and RBR LPF coefficients */ 1951 if (crtc_state->port_clock == 162000 || 1952 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG) || 1953 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1954 vlv_dpio_write(dev_priv, phy, VLV_PLL_DW10(pipe), 1955 0x009f0003); 1956 else 1957 vlv_dpio_write(dev_priv, phy, VLV_PLL_DW10(pipe), 1958 0x00d0000f); 1959 1960 if (intel_crtc_has_dp_encoder(crtc_state)) { 1961 /* Use SSC source */ 1962 if (pipe == PIPE_A) 1963 vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(pipe), 1964 0x0df40000); 1965 else 1966 vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(pipe), 1967 0x0df70000); 1968 } else { /* HDMI or VGA */ 1969 /* Use bend source */ 1970 if (pipe == PIPE_A) 1971 vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(pipe), 1972 0x0df70000); 1973 else 1974 vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(pipe), 1975 0x0df40000); 1976 } 1977 1978 coreclk = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW7(pipe)); 1979 coreclk = (coreclk & 0x0000ff00) | 0x01c00000; 1980 if (intel_crtc_has_dp_encoder(crtc_state)) 1981 coreclk |= 0x01000000; 1982 vlv_dpio_write(dev_priv, phy, VLV_PLL_DW7(pipe), coreclk); 1983 1984 vlv_dpio_write(dev_priv, phy, VLV_PLL_DW11(pipe), 0x87871000); 1985 1986 vlv_dpio_put(dev_priv); 1987 } 1988 1989 static void _vlv_enable_pll(const struct intel_crtc_state *crtc_state) 1990 { 1991 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1992 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1993 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; 1994 enum pipe pipe = crtc->pipe; 1995 1996 intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll); 1997 intel_de_posting_read(dev_priv, DPLL(pipe)); 1998 udelay(150); 1999 2000 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) 2001 drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe); 2002 } 2003 2004 void vlv_enable_pll(const struct intel_crtc_state *crtc_state) 2005 { 2006 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2007 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2008 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; 2009 enum pipe pipe = crtc->pipe; 2010 2011 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); 2012 2013 /* PLL is protected by panel, make sure we can write it */ 2014 assert_pps_unlocked(dev_priv, pipe); 2015 2016 /* Enable Refclk */ 2017 intel_de_write(dev_priv, DPLL(pipe), 2018 hw_state->dpll & ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); 2019 2020 if (hw_state->dpll & DPLL_VCO_ENABLE) { 2021 vlv_prepare_pll(crtc_state); 2022 _vlv_enable_pll(crtc_state); 2023 } 2024 2025 intel_de_write(dev_priv, DPLL_MD(pipe), hw_state->dpll_md); 2026 intel_de_posting_read(dev_priv, DPLL_MD(pipe)); 2027 } 2028 2029 static void chv_prepare_pll(const struct intel_crtc_state *crtc_state) 2030 { 2031 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2032 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2033 enum pipe pipe = crtc->pipe; 2034 enum dpio_channel port = vlv_pipe_to_channel(pipe); 2035 enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); 2036 u32 loopfilter, tribuf_calcntr; 2037 u32 bestm2, bestp1, bestp2, bestm2_frac; 2038 u32 dpio_val; 2039 int vco; 2040 2041 bestm2_frac = crtc_state->dpll.m2 & 0x3fffff; 2042 bestm2 = crtc_state->dpll.m2 >> 22; 2043 bestp1 = crtc_state->dpll.p1; 2044 bestp2 = crtc_state->dpll.p2; 2045 vco = crtc_state->dpll.vco; 2046 dpio_val = 0; 2047 loopfilter = 0; 2048 2049 vlv_dpio_get(dev_priv); 2050 2051 /* p1 and p2 divider */ 2052 vlv_dpio_write(dev_priv, phy, CHV_CMN_DW13(port), 2053 5 << DPIO_CHV_S1_DIV_SHIFT | 2054 bestp1 << DPIO_CHV_P1_DIV_SHIFT | 2055 bestp2 << DPIO_CHV_P2_DIV_SHIFT | 2056 1 << DPIO_CHV_K_DIV_SHIFT); 2057 2058 /* Feedback post-divider - m2 */ 2059 vlv_dpio_write(dev_priv, phy, CHV_PLL_DW0(port), bestm2); 2060 2061 /* Feedback refclk divider - n and m1 */ 2062 vlv_dpio_write(dev_priv, phy, CHV_PLL_DW1(port), 2063 DPIO_CHV_M1_DIV_BY_2 | 2064 1 << DPIO_CHV_N_DIV_SHIFT); 2065 2066 /* M2 fraction division */ 2067 vlv_dpio_write(dev_priv, phy, CHV_PLL_DW2(port), bestm2_frac); 2068 2069 /* M2 fraction division enable */ 2070 dpio_val = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW3(port)); 2071 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); 2072 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); 2073 if (bestm2_frac) 2074 dpio_val |= DPIO_CHV_FRAC_DIV_EN; 2075 vlv_dpio_write(dev_priv, phy, CHV_PLL_DW3(port), dpio_val); 2076 2077 /* Program digital lock detect threshold */ 2078 dpio_val = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW9(port)); 2079 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | 2080 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); 2081 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); 2082 if (!bestm2_frac) 2083 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; 2084 vlv_dpio_write(dev_priv, phy, CHV_PLL_DW9(port), dpio_val); 2085 2086 /* Loop filter */ 2087 if (vco == 5400000) { 2088 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); 2089 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); 2090 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); 2091 tribuf_calcntr = 0x9; 2092 } else if (vco <= 6200000) { 2093 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); 2094 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); 2095 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); 2096 tribuf_calcntr = 0x9; 2097 } else if (vco <= 6480000) { 2098 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); 2099 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); 2100 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); 2101 tribuf_calcntr = 0x8; 2102 } else { 2103 /* Not supported. Apply the same limits as in the max case */ 2104 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); 2105 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); 2106 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); 2107 tribuf_calcntr = 0; 2108 } 2109 vlv_dpio_write(dev_priv, phy, CHV_PLL_DW6(port), loopfilter); 2110 2111 dpio_val = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW8(port)); 2112 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; 2113 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); 2114 vlv_dpio_write(dev_priv, phy, CHV_PLL_DW8(port), dpio_val); 2115 2116 /* AFC Recal */ 2117 vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(port), 2118 vlv_dpio_read(dev_priv, phy, CHV_CMN_DW14(port)) | 2119 DPIO_AFC_RECAL); 2120 2121 vlv_dpio_put(dev_priv); 2122 } 2123 2124 static void _chv_enable_pll(const struct intel_crtc_state *crtc_state) 2125 { 2126 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2127 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2128 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; 2129 enum pipe pipe = crtc->pipe; 2130 enum dpio_channel port = vlv_pipe_to_channel(pipe); 2131 enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); 2132 u32 tmp; 2133 2134 vlv_dpio_get(dev_priv); 2135 2136 /* Enable back the 10bit clock to display controller */ 2137 tmp = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW14(port)); 2138 tmp |= DPIO_DCLKP_EN; 2139 vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(port), tmp); 2140 2141 vlv_dpio_put(dev_priv); 2142 2143 /* 2144 * Need to wait > 100ns between dclkp clock enable bit and PLL enable. 2145 */ 2146 udelay(1); 2147 2148 /* Enable PLL */ 2149 intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll); 2150 2151 /* Check PLL is locked */ 2152 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) 2153 drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe); 2154 } 2155 2156 void chv_enable_pll(const struct intel_crtc_state *crtc_state) 2157 { 2158 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2159 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2160 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; 2161 enum pipe pipe = crtc->pipe; 2162 2163 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); 2164 2165 /* PLL is protected by panel, make sure we can write it */ 2166 assert_pps_unlocked(dev_priv, pipe); 2167 2168 /* Enable Refclk and SSC */ 2169 intel_de_write(dev_priv, DPLL(pipe), 2170 hw_state->dpll & ~DPLL_VCO_ENABLE); 2171 2172 if (hw_state->dpll & DPLL_VCO_ENABLE) { 2173 chv_prepare_pll(crtc_state); 2174 _chv_enable_pll(crtc_state); 2175 } 2176 2177 if (pipe != PIPE_A) { 2178 /* 2179 * WaPixelRepeatModeFixForC0:chv 2180 * 2181 * DPLLCMD is AWOL. Use chicken bits to propagate 2182 * the value from DPLLBMD to either pipe B or C. 2183 */ 2184 intel_de_write(dev_priv, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe)); 2185 intel_de_write(dev_priv, DPLL_MD(PIPE_B), hw_state->dpll_md); 2186 intel_de_write(dev_priv, CBR4_VLV, 0); 2187 dev_priv->display.state.chv_dpll_md[pipe] = hw_state->dpll_md; 2188 2189 /* 2190 * DPLLB VGA mode also seems to cause problems. 2191 * We should always have it disabled. 2192 */ 2193 drm_WARN_ON(&dev_priv->drm, 2194 (intel_de_read(dev_priv, DPLL(PIPE_B)) & 2195 DPLL_VGA_MODE_DIS) == 0); 2196 } else { 2197 intel_de_write(dev_priv, DPLL_MD(pipe), hw_state->dpll_md); 2198 intel_de_posting_read(dev_priv, DPLL_MD(pipe)); 2199 } 2200 } 2201 2202 /** 2203 * vlv_force_pll_on - forcibly enable just the PLL 2204 * @dev_priv: i915 private structure 2205 * @pipe: pipe PLL to enable 2206 * @dpll: PLL configuration 2207 * 2208 * Enable the PLL for @pipe using the supplied @dpll config. To be used 2209 * in cases where we need the PLL enabled even when @pipe is not going to 2210 * be enabled. 2211 */ 2212 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, 2213 const struct dpll *dpll) 2214 { 2215 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 2216 struct intel_crtc_state *crtc_state; 2217 2218 crtc_state = intel_crtc_state_alloc(crtc); 2219 if (!crtc_state) 2220 return -ENOMEM; 2221 2222 crtc_state->cpu_transcoder = (enum transcoder)pipe; 2223 crtc_state->pixel_multiplier = 1; 2224 crtc_state->dpll = *dpll; 2225 crtc_state->output_types = BIT(INTEL_OUTPUT_EDP); 2226 2227 if (IS_CHERRYVIEW(dev_priv)) { 2228 chv_compute_dpll(crtc_state); 2229 chv_enable_pll(crtc_state); 2230 } else { 2231 vlv_compute_dpll(crtc_state); 2232 vlv_enable_pll(crtc_state); 2233 } 2234 2235 intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi); 2236 2237 return 0; 2238 } 2239 2240 void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) 2241 { 2242 u32 val; 2243 2244 /* Make sure the pipe isn't still relying on us */ 2245 assert_transcoder_disabled(dev_priv, (enum transcoder)pipe); 2246 2247 val = DPLL_INTEGRATED_REF_CLK_VLV | 2248 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 2249 if (pipe != PIPE_A) 2250 val |= DPLL_INTEGRATED_CRI_CLK_VLV; 2251 2252 intel_de_write(dev_priv, DPLL(pipe), val); 2253 intel_de_posting_read(dev_priv, DPLL(pipe)); 2254 } 2255 2256 void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) 2257 { 2258 enum dpio_channel port = vlv_pipe_to_channel(pipe); 2259 enum dpio_phy phy = vlv_pipe_to_phy(pipe); 2260 u32 val; 2261 2262 /* Make sure the pipe isn't still relying on us */ 2263 assert_transcoder_disabled(dev_priv, (enum transcoder)pipe); 2264 2265 val = DPLL_SSC_REF_CLK_CHV | 2266 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 2267 if (pipe != PIPE_A) 2268 val |= DPLL_INTEGRATED_CRI_CLK_VLV; 2269 2270 intel_de_write(dev_priv, DPLL(pipe), val); 2271 intel_de_posting_read(dev_priv, DPLL(pipe)); 2272 2273 vlv_dpio_get(dev_priv); 2274 2275 /* Disable 10bit clock to display controller */ 2276 val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW14(port)); 2277 val &= ~DPIO_DCLKP_EN; 2278 vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(port), val); 2279 2280 vlv_dpio_put(dev_priv); 2281 } 2282 2283 void i9xx_disable_pll(const struct intel_crtc_state *crtc_state) 2284 { 2285 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2286 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2287 enum pipe pipe = crtc->pipe; 2288 2289 /* Don't disable pipe or pipe PLLs if needed */ 2290 if (IS_I830(dev_priv)) 2291 return; 2292 2293 /* Make sure the pipe isn't still relying on us */ 2294 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); 2295 2296 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); 2297 intel_de_posting_read(dev_priv, DPLL(pipe)); 2298 } 2299 2300 2301 /** 2302 * vlv_force_pll_off - forcibly disable just the PLL 2303 * @dev_priv: i915 private structure 2304 * @pipe: pipe PLL to disable 2305 * 2306 * Disable the PLL for @pipe. To be used in cases where we need 2307 * the PLL enabled even when @pipe is not going to be enabled. 2308 */ 2309 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe) 2310 { 2311 if (IS_CHERRYVIEW(dev_priv)) 2312 chv_disable_pll(dev_priv, pipe); 2313 else 2314 vlv_disable_pll(dev_priv, pipe); 2315 } 2316 2317 /* Only for pre-ILK configs */ 2318 static void assert_pll(struct drm_i915_private *dev_priv, 2319 enum pipe pipe, bool state) 2320 { 2321 bool cur_state; 2322 2323 cur_state = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE; 2324 I915_STATE_WARN(dev_priv, cur_state != state, 2325 "PLL state assertion failure (expected %s, current %s)\n", 2326 str_on_off(state), str_on_off(cur_state)); 2327 } 2328 2329 void assert_pll_enabled(struct drm_i915_private *i915, enum pipe pipe) 2330 { 2331 assert_pll(i915, pipe, true); 2332 } 2333 2334 void assert_pll_disabled(struct drm_i915_private *i915, enum pipe pipe) 2335 { 2336 assert_pll(i915, pipe, false); 2337 } 2338