1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/debugfs.h> 26 #include <linux/firmware.h> 27 28 #include "i915_drv.h" 29 #include "i915_reg.h" 30 #include "intel_de.h" 31 #include "intel_display_rpm.h" 32 #include "intel_display_power_well.h" 33 #include "intel_dmc.h" 34 #include "intel_dmc_regs.h" 35 #include "intel_step.h" 36 37 /** 38 * DOC: DMC Firmware Support 39 * 40 * From gen9 onwards we have newly added DMC (Display microcontroller) in display 41 * engine to save and restore the state of display engine when it enter into 42 * low-power state and comes back to normal. 43 */ 44 45 #define INTEL_DMC_FIRMWARE_URL "https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git" 46 47 enum intel_dmc_id { 48 DMC_FW_MAIN = 0, 49 DMC_FW_PIPEA, 50 DMC_FW_PIPEB, 51 DMC_FW_PIPEC, 52 DMC_FW_PIPED, 53 DMC_FW_MAX 54 }; 55 56 struct intel_dmc { 57 struct intel_display *display; 58 struct work_struct work; 59 const char *fw_path; 60 u32 max_fw_size; /* bytes */ 61 u32 version; 62 struct { 63 u32 dc5_start; 64 u32 count; 65 } dc6_allowed; 66 struct dmc_fw_info { 67 u32 mmio_count; 68 i915_reg_t mmioaddr[20]; 69 u32 mmiodata[20]; 70 u32 dmc_offset; 71 u32 start_mmioaddr; 72 u32 dmc_fw_size; /*dwords */ 73 u32 *payload; 74 bool present; 75 } dmc_info[DMC_FW_MAX]; 76 }; 77 78 /* Note: This may be NULL. */ 79 static struct intel_dmc *display_to_dmc(struct intel_display *display) 80 { 81 return display->dmc.dmc; 82 } 83 84 static const char *dmc_firmware_param(struct intel_display *display) 85 { 86 const char *p = display->params.dmc_firmware_path; 87 88 return p && *p ? p : NULL; 89 } 90 91 static bool dmc_firmware_param_disabled(struct intel_display *display) 92 { 93 const char *p = dmc_firmware_param(display); 94 95 /* Magic path to indicate disabled */ 96 return p && !strcmp(p, "/dev/null"); 97 } 98 99 #define DMC_VERSION(major, minor) ((major) << 16 | (minor)) 100 #define DMC_VERSION_MAJOR(version) ((version) >> 16) 101 #define DMC_VERSION_MINOR(version) ((version) & 0xffff) 102 103 #define DMC_PATH(platform) \ 104 "i915/" __stringify(platform) "_dmc.bin" 105 106 /* 107 * New DMC additions should not use this. This is used solely to remain 108 * compatible with systems that have not yet updated DMC blobs to use 109 * unversioned file names. 110 */ 111 #define DMC_LEGACY_PATH(platform, major, minor) \ 112 "i915/" \ 113 __stringify(platform) "_dmc_ver" \ 114 __stringify(major) "_" \ 115 __stringify(minor) ".bin" 116 117 #define XE2LPD_DMC_MAX_FW_SIZE 0x8000 118 #define XELPDP_DMC_MAX_FW_SIZE 0x7000 119 #define DISPLAY_VER13_DMC_MAX_FW_SIZE 0x20000 120 #define DISPLAY_VER12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE 121 122 #define XE3LPD_DMC_PATH DMC_PATH(xe3lpd) 123 MODULE_FIRMWARE(XE3LPD_DMC_PATH); 124 125 #define XE2LPD_DMC_PATH DMC_PATH(xe2lpd) 126 MODULE_FIRMWARE(XE2LPD_DMC_PATH); 127 128 #define BMG_DMC_PATH DMC_PATH(bmg) 129 MODULE_FIRMWARE(BMG_DMC_PATH); 130 131 #define MTL_DMC_PATH DMC_PATH(mtl) 132 MODULE_FIRMWARE(MTL_DMC_PATH); 133 134 #define DG2_DMC_PATH DMC_LEGACY_PATH(dg2, 2, 08) 135 MODULE_FIRMWARE(DG2_DMC_PATH); 136 137 #define ADLP_DMC_PATH DMC_PATH(adlp) 138 #define ADLP_DMC_FALLBACK_PATH DMC_LEGACY_PATH(adlp, 2, 16) 139 MODULE_FIRMWARE(ADLP_DMC_PATH); 140 MODULE_FIRMWARE(ADLP_DMC_FALLBACK_PATH); 141 142 #define ADLS_DMC_PATH DMC_LEGACY_PATH(adls, 2, 01) 143 MODULE_FIRMWARE(ADLS_DMC_PATH); 144 145 #define DG1_DMC_PATH DMC_LEGACY_PATH(dg1, 2, 02) 146 MODULE_FIRMWARE(DG1_DMC_PATH); 147 148 #define RKL_DMC_PATH DMC_LEGACY_PATH(rkl, 2, 03) 149 MODULE_FIRMWARE(RKL_DMC_PATH); 150 151 #define TGL_DMC_PATH DMC_LEGACY_PATH(tgl, 2, 12) 152 MODULE_FIRMWARE(TGL_DMC_PATH); 153 154 #define ICL_DMC_PATH DMC_LEGACY_PATH(icl, 1, 09) 155 #define ICL_DMC_MAX_FW_SIZE 0x6000 156 MODULE_FIRMWARE(ICL_DMC_PATH); 157 158 #define GLK_DMC_PATH DMC_LEGACY_PATH(glk, 1, 04) 159 #define GLK_DMC_MAX_FW_SIZE 0x4000 160 MODULE_FIRMWARE(GLK_DMC_PATH); 161 162 #define KBL_DMC_PATH DMC_LEGACY_PATH(kbl, 1, 04) 163 #define KBL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE 164 MODULE_FIRMWARE(KBL_DMC_PATH); 165 166 #define SKL_DMC_PATH DMC_LEGACY_PATH(skl, 1, 27) 167 #define SKL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE 168 MODULE_FIRMWARE(SKL_DMC_PATH); 169 170 #define BXT_DMC_PATH DMC_LEGACY_PATH(bxt, 1, 07) 171 #define BXT_DMC_MAX_FW_SIZE 0x3000 172 MODULE_FIRMWARE(BXT_DMC_PATH); 173 174 static const char *dmc_firmware_default(struct intel_display *display, u32 *size) 175 { 176 struct drm_i915_private *i915 = to_i915(display->drm); 177 const char *fw_path = NULL; 178 u32 max_fw_size = 0; 179 180 if (DISPLAY_VERx100(display) == 3000) { 181 fw_path = XE3LPD_DMC_PATH; 182 max_fw_size = XE2LPD_DMC_MAX_FW_SIZE; 183 } else if (DISPLAY_VERx100(display) == 2000) { 184 fw_path = XE2LPD_DMC_PATH; 185 max_fw_size = XE2LPD_DMC_MAX_FW_SIZE; 186 } else if (DISPLAY_VERx100(display) == 1401) { 187 fw_path = BMG_DMC_PATH; 188 max_fw_size = XELPDP_DMC_MAX_FW_SIZE; 189 } else if (DISPLAY_VERx100(display) == 1400) { 190 fw_path = MTL_DMC_PATH; 191 max_fw_size = XELPDP_DMC_MAX_FW_SIZE; 192 } else if (IS_DG2(i915)) { 193 fw_path = DG2_DMC_PATH; 194 max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE; 195 } else if (IS_ALDERLAKE_P(i915)) { 196 fw_path = ADLP_DMC_PATH; 197 max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE; 198 } else if (IS_ALDERLAKE_S(i915)) { 199 fw_path = ADLS_DMC_PATH; 200 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 201 } else if (IS_DG1(i915)) { 202 fw_path = DG1_DMC_PATH; 203 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 204 } else if (IS_ROCKETLAKE(i915)) { 205 fw_path = RKL_DMC_PATH; 206 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 207 } else if (IS_TIGERLAKE(i915)) { 208 fw_path = TGL_DMC_PATH; 209 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 210 } else if (DISPLAY_VER(display) == 11) { 211 fw_path = ICL_DMC_PATH; 212 max_fw_size = ICL_DMC_MAX_FW_SIZE; 213 } else if (IS_GEMINILAKE(i915)) { 214 fw_path = GLK_DMC_PATH; 215 max_fw_size = GLK_DMC_MAX_FW_SIZE; 216 } else if (IS_KABYLAKE(i915) || 217 IS_COFFEELAKE(i915) || 218 IS_COMETLAKE(i915)) { 219 fw_path = KBL_DMC_PATH; 220 max_fw_size = KBL_DMC_MAX_FW_SIZE; 221 } else if (IS_SKYLAKE(i915)) { 222 fw_path = SKL_DMC_PATH; 223 max_fw_size = SKL_DMC_MAX_FW_SIZE; 224 } else if (IS_BROXTON(i915)) { 225 fw_path = BXT_DMC_PATH; 226 max_fw_size = BXT_DMC_MAX_FW_SIZE; 227 } 228 229 *size = max_fw_size; 230 231 return fw_path; 232 } 233 234 #define DMC_DEFAULT_FW_OFFSET 0xFFFFFFFF 235 #define PACKAGE_MAX_FW_INFO_ENTRIES 20 236 #define PACKAGE_V2_MAX_FW_INFO_ENTRIES 32 237 #define DMC_V1_MAX_MMIO_COUNT 8 238 #define DMC_V3_MAX_MMIO_COUNT 20 239 #define DMC_V1_MMIO_START_RANGE 0x80000 240 241 #define PIPE_TO_DMC_ID(pipe) (DMC_FW_PIPEA + ((pipe) - PIPE_A)) 242 243 struct intel_css_header { 244 /* 0x09 for DMC */ 245 u32 module_type; 246 247 /* Includes the DMC specific header in dwords */ 248 u32 header_len; 249 250 /* always value would be 0x10000 */ 251 u32 header_ver; 252 253 /* Not used */ 254 u32 module_id; 255 256 /* Not used */ 257 u32 module_vendor; 258 259 /* in YYYYMMDD format */ 260 u32 date; 261 262 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */ 263 u32 size; 264 265 /* Not used */ 266 u32 key_size; 267 268 /* Not used */ 269 u32 modulus_size; 270 271 /* Not used */ 272 u32 exponent_size; 273 274 /* Not used */ 275 u32 reserved1[12]; 276 277 /* Major Minor */ 278 u32 version; 279 280 /* Not used */ 281 u32 reserved2[8]; 282 283 /* Not used */ 284 u32 kernel_header_info; 285 } __packed; 286 287 struct intel_fw_info { 288 u8 reserved1; 289 290 /* reserved on package_header version 1, must be 0 on version 2 */ 291 u8 dmc_id; 292 293 /* Stepping (A, B, C, ..., *). * is a wildcard */ 294 char stepping; 295 296 /* Sub-stepping (0, 1, ..., *). * is a wildcard */ 297 char substepping; 298 299 u32 offset; 300 u32 reserved2; 301 } __packed; 302 303 struct intel_package_header { 304 /* DMC container header length in dwords */ 305 u8 header_len; 306 307 /* 0x01, 0x02 */ 308 u8 header_ver; 309 310 u8 reserved[10]; 311 312 /* Number of valid entries in the FWInfo array below */ 313 u32 num_entries; 314 } __packed; 315 316 struct intel_dmc_header_base { 317 /* always value would be 0x40403E3E */ 318 u32 signature; 319 320 /* DMC binary header length */ 321 u8 header_len; 322 323 /* 0x01 */ 324 u8 header_ver; 325 326 /* Reserved */ 327 u16 dmcc_ver; 328 329 /* Major, Minor */ 330 u32 project; 331 332 /* Firmware program size (excluding header) in dwords */ 333 u32 fw_size; 334 335 /* Major Minor version */ 336 u32 fw_version; 337 } __packed; 338 339 struct intel_dmc_header_v1 { 340 struct intel_dmc_header_base base; 341 342 /* Number of valid MMIO cycles present. */ 343 u32 mmio_count; 344 345 /* MMIO address */ 346 u32 mmioaddr[DMC_V1_MAX_MMIO_COUNT]; 347 348 /* MMIO data */ 349 u32 mmiodata[DMC_V1_MAX_MMIO_COUNT]; 350 351 /* FW filename */ 352 char dfile[32]; 353 354 u32 reserved1[2]; 355 } __packed; 356 357 struct intel_dmc_header_v3 { 358 struct intel_dmc_header_base base; 359 360 /* DMC RAM start MMIO address */ 361 u32 start_mmioaddr; 362 363 u32 reserved[9]; 364 365 /* FW filename */ 366 char dfile[32]; 367 368 /* Number of valid MMIO cycles present. */ 369 u32 mmio_count; 370 371 /* MMIO address */ 372 u32 mmioaddr[DMC_V3_MAX_MMIO_COUNT]; 373 374 /* MMIO data */ 375 u32 mmiodata[DMC_V3_MAX_MMIO_COUNT]; 376 } __packed; 377 378 struct stepping_info { 379 char stepping; 380 char substepping; 381 }; 382 383 #define for_each_dmc_id(__dmc_id) \ 384 for ((__dmc_id) = DMC_FW_MAIN; (__dmc_id) < DMC_FW_MAX; (__dmc_id)++) 385 386 static bool is_valid_dmc_id(enum intel_dmc_id dmc_id) 387 { 388 return dmc_id >= DMC_FW_MAIN && dmc_id < DMC_FW_MAX; 389 } 390 391 static bool has_dmc_id_fw(struct intel_display *display, enum intel_dmc_id dmc_id) 392 { 393 struct intel_dmc *dmc = display_to_dmc(display); 394 395 return dmc && dmc->dmc_info[dmc_id].payload; 396 } 397 398 bool intel_dmc_has_payload(struct intel_display *display) 399 { 400 return has_dmc_id_fw(display, DMC_FW_MAIN); 401 } 402 403 static const struct stepping_info * 404 intel_get_stepping_info(struct intel_display *display, 405 struct stepping_info *si) 406 { 407 const char *step_name = intel_step_name(INTEL_DISPLAY_STEP(display)); 408 409 si->stepping = step_name[0]; 410 si->substepping = step_name[1]; 411 return si; 412 } 413 414 static void gen9_set_dc_state_debugmask(struct intel_display *display) 415 { 416 /* The below bit doesn't need to be cleared ever afterwards */ 417 intel_de_rmw(display, DC_STATE_DEBUG, 0, 418 DC_STATE_DEBUG_MASK_CORES | DC_STATE_DEBUG_MASK_MEMORY_UP); 419 intel_de_posting_read(display, DC_STATE_DEBUG); 420 } 421 422 static void disable_event_handler(struct intel_display *display, 423 i915_reg_t ctl_reg, i915_reg_t htp_reg) 424 { 425 intel_de_write(display, ctl_reg, 426 REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, 427 DMC_EVT_CTL_TYPE_EDGE_0_1) | 428 REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, 429 DMC_EVT_CTL_EVENT_ID_FALSE)); 430 intel_de_write(display, htp_reg, 0); 431 } 432 433 static void disable_all_event_handlers(struct intel_display *display) 434 { 435 enum intel_dmc_id dmc_id; 436 437 /* TODO: disable the event handlers on pre-GEN12 platforms as well */ 438 if (DISPLAY_VER(display) < 12) 439 return; 440 441 for_each_dmc_id(dmc_id) { 442 int handler; 443 444 if (!has_dmc_id_fw(display, dmc_id)) 445 continue; 446 447 for (handler = 0; handler < DMC_EVENT_HANDLER_COUNT_GEN12; handler++) 448 disable_event_handler(display, 449 DMC_EVT_CTL(display, dmc_id, handler), 450 DMC_EVT_HTP(display, dmc_id, handler)); 451 } 452 } 453 454 static void adlp_pipedmc_clock_gating_wa(struct intel_display *display, bool enable) 455 { 456 enum pipe pipe; 457 458 /* 459 * Wa_16015201720:adl-p,dg2 460 * The WA requires clock gating to be disabled all the time 461 * for pipe A and B. 462 * For pipe C and D clock gating needs to be disabled only 463 * during initializing the firmware. 464 */ 465 if (enable) 466 for (pipe = PIPE_A; pipe <= PIPE_D; pipe++) 467 intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe), 468 0, PIPEDMC_GATING_DIS); 469 else 470 for (pipe = PIPE_C; pipe <= PIPE_D; pipe++) 471 intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe), 472 PIPEDMC_GATING_DIS, 0); 473 } 474 475 static void mtl_pipedmc_clock_gating_wa(struct intel_display *display) 476 { 477 /* 478 * Wa_16015201720 479 * The WA requires clock gating to be disabled all the time 480 * for pipe A and B. 481 */ 482 intel_de_rmw(display, GEN9_CLKGATE_DIS_0, 0, 483 MTL_PIPEDMC_GATING_DIS_A | MTL_PIPEDMC_GATING_DIS_B); 484 } 485 486 static void pipedmc_clock_gating_wa(struct intel_display *display, bool enable) 487 { 488 if (DISPLAY_VER(display) >= 14 && enable) 489 mtl_pipedmc_clock_gating_wa(display); 490 else if (DISPLAY_VER(display) == 13) 491 adlp_pipedmc_clock_gating_wa(display, enable); 492 } 493 494 void intel_dmc_enable_pipe(struct intel_display *display, enum pipe pipe) 495 { 496 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); 497 498 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id)) 499 return; 500 501 if (DISPLAY_VER(display) >= 14) 502 intel_de_rmw(display, MTL_PIPEDMC_CONTROL, 0, PIPEDMC_ENABLE_MTL(pipe)); 503 else 504 intel_de_rmw(display, PIPEDMC_CONTROL(pipe), 0, PIPEDMC_ENABLE); 505 } 506 507 void intel_dmc_disable_pipe(struct intel_display *display, enum pipe pipe) 508 { 509 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); 510 511 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id)) 512 return; 513 514 if (DISPLAY_VER(display) >= 14) 515 intel_de_rmw(display, MTL_PIPEDMC_CONTROL, PIPEDMC_ENABLE_MTL(pipe), 0); 516 else 517 intel_de_rmw(display, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0); 518 } 519 520 static bool is_dmc_evt_ctl_reg(struct intel_display *display, 521 enum intel_dmc_id dmc_id, i915_reg_t reg) 522 { 523 u32 offset = i915_mmio_reg_offset(reg); 524 u32 start = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, 0)); 525 u32 end = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); 526 527 return offset >= start && offset < end; 528 } 529 530 static bool is_dmc_evt_htp_reg(struct intel_display *display, 531 enum intel_dmc_id dmc_id, i915_reg_t reg) 532 { 533 u32 offset = i915_mmio_reg_offset(reg); 534 u32 start = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, 0)); 535 u32 end = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); 536 537 return offset >= start && offset < end; 538 } 539 540 static bool disable_dmc_evt(struct intel_display *display, 541 enum intel_dmc_id dmc_id, 542 i915_reg_t reg, u32 data) 543 { 544 struct drm_i915_private *i915 = to_i915(display->drm); 545 546 if (!is_dmc_evt_ctl_reg(display, dmc_id, reg)) 547 return false; 548 549 /* keep all pipe DMC events disabled by default */ 550 if (dmc_id != DMC_FW_MAIN) 551 return true; 552 553 /* also disable the flip queue event on the main DMC on TGL */ 554 if (IS_TIGERLAKE(i915) && 555 REG_FIELD_GET(DMC_EVT_CTL_EVENT_ID_MASK, data) == DMC_EVT_CTL_EVENT_ID_CLK_MSEC) 556 return true; 557 558 /* also disable the HRR event on the main DMC on TGL/ADLS */ 559 if ((IS_TIGERLAKE(i915) || IS_ALDERLAKE_S(i915)) && 560 REG_FIELD_GET(DMC_EVT_CTL_EVENT_ID_MASK, data) == DMC_EVT_CTL_EVENT_ID_VBLANK_A) 561 return true; 562 563 return false; 564 } 565 566 static u32 dmc_mmiodata(struct intel_display *display, 567 struct intel_dmc *dmc, 568 enum intel_dmc_id dmc_id, int i) 569 { 570 if (disable_dmc_evt(display, dmc_id, 571 dmc->dmc_info[dmc_id].mmioaddr[i], 572 dmc->dmc_info[dmc_id].mmiodata[i])) 573 return REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, 574 DMC_EVT_CTL_TYPE_EDGE_0_1) | 575 REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, 576 DMC_EVT_CTL_EVENT_ID_FALSE); 577 else 578 return dmc->dmc_info[dmc_id].mmiodata[i]; 579 } 580 581 /** 582 * intel_dmc_load_program() - write the firmware from memory to register. 583 * @display: display instance 584 * 585 * DMC firmware is read from a .bin file and kept in internal memory one time. 586 * Everytime display comes back from low power state this function is called to 587 * copy the firmware from internal memory to registers. 588 */ 589 void intel_dmc_load_program(struct intel_display *display) 590 { 591 struct drm_i915_private *i915 __maybe_unused = to_i915(display->drm); 592 struct i915_power_domains *power_domains = &display->power.domains; 593 struct intel_dmc *dmc = display_to_dmc(display); 594 enum intel_dmc_id dmc_id; 595 u32 i; 596 597 if (!intel_dmc_has_payload(display)) 598 return; 599 600 pipedmc_clock_gating_wa(display, true); 601 602 disable_all_event_handlers(display); 603 604 assert_display_rpm_held(display); 605 606 preempt_disable(); 607 608 for_each_dmc_id(dmc_id) { 609 for (i = 0; i < dmc->dmc_info[dmc_id].dmc_fw_size; i++) { 610 intel_de_write_fw(display, 611 DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, i), 612 dmc->dmc_info[dmc_id].payload[i]); 613 } 614 } 615 616 preempt_enable(); 617 618 for_each_dmc_id(dmc_id) { 619 for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) { 620 intel_de_write(display, dmc->dmc_info[dmc_id].mmioaddr[i], 621 dmc_mmiodata(display, dmc, dmc_id, i)); 622 } 623 } 624 625 power_domains->dc_state = 0; 626 627 gen9_set_dc_state_debugmask(display); 628 629 pipedmc_clock_gating_wa(display, false); 630 } 631 632 /** 633 * intel_dmc_disable_program() - disable the firmware 634 * @display: display instance 635 * 636 * Disable all event handlers in the firmware, making sure the firmware is 637 * inactive after the display is uninitialized. 638 */ 639 void intel_dmc_disable_program(struct intel_display *display) 640 { 641 if (!intel_dmc_has_payload(display)) 642 return; 643 644 pipedmc_clock_gating_wa(display, true); 645 disable_all_event_handlers(display); 646 pipedmc_clock_gating_wa(display, false); 647 } 648 649 void assert_dmc_loaded(struct intel_display *display) 650 { 651 struct intel_dmc *dmc = display_to_dmc(display); 652 653 drm_WARN_ONCE(display->drm, !dmc, "DMC not initialized\n"); 654 drm_WARN_ONCE(display->drm, dmc && 655 !intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)), 656 "DMC program storage start is NULL\n"); 657 drm_WARN_ONCE(display->drm, !intel_de_read(display, DMC_SSP_BASE), 658 "DMC SSP Base Not fine\n"); 659 drm_WARN_ONCE(display->drm, !intel_de_read(display, DMC_HTP_SKL), 660 "DMC HTP Not fine\n"); 661 } 662 663 static bool fw_info_matches_stepping(const struct intel_fw_info *fw_info, 664 const struct stepping_info *si) 665 { 666 if ((fw_info->substepping == '*' && si->stepping == fw_info->stepping) || 667 (si->stepping == fw_info->stepping && si->substepping == fw_info->substepping) || 668 /* 669 * If we don't find a more specific one from above two checks, we 670 * then check for the generic one to be sure to work even with 671 * "broken firmware" 672 */ 673 (si->stepping == '*' && si->substepping == fw_info->substepping) || 674 (fw_info->stepping == '*' && fw_info->substepping == '*')) 675 return true; 676 677 return false; 678 } 679 680 /* 681 * Search fw_info table for dmc_offset to find firmware binary: num_entries is 682 * already sanitized. 683 */ 684 static void dmc_set_fw_offset(struct intel_dmc *dmc, 685 const struct intel_fw_info *fw_info, 686 unsigned int num_entries, 687 const struct stepping_info *si, 688 u8 package_ver) 689 { 690 struct intel_display *display = dmc->display; 691 enum intel_dmc_id dmc_id; 692 unsigned int i; 693 694 for (i = 0; i < num_entries; i++) { 695 dmc_id = package_ver <= 1 ? DMC_FW_MAIN : fw_info[i].dmc_id; 696 697 if (!is_valid_dmc_id(dmc_id)) { 698 drm_dbg(display->drm, "Unsupported firmware id: %u\n", dmc_id); 699 continue; 700 } 701 702 /* More specific versions come first, so we don't even have to 703 * check for the stepping since we already found a previous FW 704 * for this id. 705 */ 706 if (dmc->dmc_info[dmc_id].present) 707 continue; 708 709 if (fw_info_matches_stepping(&fw_info[i], si)) { 710 dmc->dmc_info[dmc_id].present = true; 711 dmc->dmc_info[dmc_id].dmc_offset = fw_info[i].offset; 712 } 713 } 714 } 715 716 static bool dmc_mmio_addr_sanity_check(struct intel_dmc *dmc, 717 const u32 *mmioaddr, u32 mmio_count, 718 int header_ver, enum intel_dmc_id dmc_id) 719 { 720 struct intel_display *display = dmc->display; 721 u32 start_range, end_range; 722 int i; 723 724 if (header_ver == 1) { 725 start_range = DMC_MMIO_START_RANGE; 726 end_range = DMC_MMIO_END_RANGE; 727 } else if (dmc_id == DMC_FW_MAIN) { 728 start_range = TGL_MAIN_MMIO_START; 729 end_range = TGL_MAIN_MMIO_END; 730 } else if (DISPLAY_VER(display) >= 13) { 731 start_range = ADLP_PIPE_MMIO_START; 732 end_range = ADLP_PIPE_MMIO_END; 733 } else if (DISPLAY_VER(display) >= 12) { 734 start_range = TGL_PIPE_MMIO_START(dmc_id); 735 end_range = TGL_PIPE_MMIO_END(dmc_id); 736 } else { 737 drm_warn(display->drm, "Unknown mmio range for sanity check"); 738 return false; 739 } 740 741 for (i = 0; i < mmio_count; i++) { 742 if (mmioaddr[i] < start_range || mmioaddr[i] > end_range) 743 return false; 744 } 745 746 return true; 747 } 748 749 static u32 parse_dmc_fw_header(struct intel_dmc *dmc, 750 const struct intel_dmc_header_base *dmc_header, 751 size_t rem_size, enum intel_dmc_id dmc_id) 752 { 753 struct intel_display *display = dmc->display; 754 struct dmc_fw_info *dmc_info = &dmc->dmc_info[dmc_id]; 755 unsigned int header_len_bytes, dmc_header_size, payload_size, i; 756 const u32 *mmioaddr, *mmiodata; 757 u32 mmio_count, mmio_count_max, start_mmioaddr; 758 u8 *payload; 759 760 BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT || 761 ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V1_MAX_MMIO_COUNT); 762 763 /* 764 * Check if we can access common fields, we will checkc again below 765 * after we have read the version 766 */ 767 if (rem_size < sizeof(struct intel_dmc_header_base)) 768 goto error_truncated; 769 770 /* Cope with small differences between v1 and v3 */ 771 if (dmc_header->header_ver == 3) { 772 const struct intel_dmc_header_v3 *v3 = 773 (const struct intel_dmc_header_v3 *)dmc_header; 774 775 if (rem_size < sizeof(struct intel_dmc_header_v3)) 776 goto error_truncated; 777 778 mmioaddr = v3->mmioaddr; 779 mmiodata = v3->mmiodata; 780 mmio_count = v3->mmio_count; 781 mmio_count_max = DMC_V3_MAX_MMIO_COUNT; 782 /* header_len is in dwords */ 783 header_len_bytes = dmc_header->header_len * 4; 784 start_mmioaddr = v3->start_mmioaddr; 785 dmc_header_size = sizeof(*v3); 786 } else if (dmc_header->header_ver == 1) { 787 const struct intel_dmc_header_v1 *v1 = 788 (const struct intel_dmc_header_v1 *)dmc_header; 789 790 if (rem_size < sizeof(struct intel_dmc_header_v1)) 791 goto error_truncated; 792 793 mmioaddr = v1->mmioaddr; 794 mmiodata = v1->mmiodata; 795 mmio_count = v1->mmio_count; 796 mmio_count_max = DMC_V1_MAX_MMIO_COUNT; 797 header_len_bytes = dmc_header->header_len; 798 start_mmioaddr = DMC_V1_MMIO_START_RANGE; 799 dmc_header_size = sizeof(*v1); 800 } else { 801 drm_err(display->drm, "Unknown DMC fw header version: %u\n", 802 dmc_header->header_ver); 803 return 0; 804 } 805 806 if (header_len_bytes != dmc_header_size) { 807 drm_err(display->drm, "DMC firmware has wrong dmc header length " 808 "(%u bytes)\n", header_len_bytes); 809 return 0; 810 } 811 812 /* Cache the dmc header info. */ 813 if (mmio_count > mmio_count_max) { 814 drm_err(display->drm, "DMC firmware has wrong mmio count %u\n", mmio_count); 815 return 0; 816 } 817 818 if (!dmc_mmio_addr_sanity_check(dmc, mmioaddr, mmio_count, 819 dmc_header->header_ver, dmc_id)) { 820 drm_err(display->drm, "DMC firmware has Wrong MMIO Addresses\n"); 821 return 0; 822 } 823 824 drm_dbg_kms(display->drm, "DMC %d:\n", dmc_id); 825 for (i = 0; i < mmio_count; i++) { 826 dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]); 827 dmc_info->mmiodata[i] = mmiodata[i]; 828 829 drm_dbg_kms(display->drm, " mmio[%d]: 0x%x = 0x%x%s%s\n", 830 i, mmioaddr[i], mmiodata[i], 831 is_dmc_evt_ctl_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_CTL)" : 832 is_dmc_evt_htp_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_HTP)" : "", 833 disable_dmc_evt(display, dmc_id, dmc_info->mmioaddr[i], 834 dmc_info->mmiodata[i]) ? " (disabling)" : ""); 835 } 836 dmc_info->mmio_count = mmio_count; 837 dmc_info->start_mmioaddr = start_mmioaddr; 838 839 rem_size -= header_len_bytes; 840 841 /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */ 842 payload_size = dmc_header->fw_size * 4; 843 if (rem_size < payload_size) 844 goto error_truncated; 845 846 if (payload_size > dmc->max_fw_size) { 847 drm_err(display->drm, "DMC FW too big (%u bytes)\n", payload_size); 848 return 0; 849 } 850 dmc_info->dmc_fw_size = dmc_header->fw_size; 851 852 dmc_info->payload = kmalloc(payload_size, GFP_KERNEL); 853 if (!dmc_info->payload) 854 return 0; 855 856 payload = (u8 *)(dmc_header) + header_len_bytes; 857 memcpy(dmc_info->payload, payload, payload_size); 858 859 return header_len_bytes + payload_size; 860 861 error_truncated: 862 drm_err(display->drm, "Truncated DMC firmware, refusing.\n"); 863 return 0; 864 } 865 866 static u32 867 parse_dmc_fw_package(struct intel_dmc *dmc, 868 const struct intel_package_header *package_header, 869 const struct stepping_info *si, 870 size_t rem_size) 871 { 872 struct intel_display *display = dmc->display; 873 u32 package_size = sizeof(struct intel_package_header); 874 u32 num_entries, max_entries; 875 const struct intel_fw_info *fw_info; 876 877 if (rem_size < package_size) 878 goto error_truncated; 879 880 if (package_header->header_ver == 1) { 881 max_entries = PACKAGE_MAX_FW_INFO_ENTRIES; 882 } else if (package_header->header_ver == 2) { 883 max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES; 884 } else { 885 drm_err(display->drm, "DMC firmware has unknown header version %u\n", 886 package_header->header_ver); 887 return 0; 888 } 889 890 /* 891 * We should always have space for max_entries, 892 * even if not all are used 893 */ 894 package_size += max_entries * sizeof(struct intel_fw_info); 895 if (rem_size < package_size) 896 goto error_truncated; 897 898 if (package_header->header_len * 4 != package_size) { 899 drm_err(display->drm, "DMC firmware has wrong package header length " 900 "(%u bytes)\n", package_size); 901 return 0; 902 } 903 904 num_entries = package_header->num_entries; 905 if (WARN_ON(package_header->num_entries > max_entries)) 906 num_entries = max_entries; 907 908 fw_info = (const struct intel_fw_info *) 909 ((u8 *)package_header + sizeof(*package_header)); 910 dmc_set_fw_offset(dmc, fw_info, num_entries, si, 911 package_header->header_ver); 912 913 /* dmc_offset is in dwords */ 914 return package_size; 915 916 error_truncated: 917 drm_err(display->drm, "Truncated DMC firmware, refusing.\n"); 918 return 0; 919 } 920 921 /* Return number of bytes parsed or 0 on error */ 922 static u32 parse_dmc_fw_css(struct intel_dmc *dmc, 923 struct intel_css_header *css_header, 924 size_t rem_size) 925 { 926 struct intel_display *display = dmc->display; 927 928 if (rem_size < sizeof(struct intel_css_header)) { 929 drm_err(display->drm, "Truncated DMC firmware, refusing.\n"); 930 return 0; 931 } 932 933 if (sizeof(struct intel_css_header) != 934 (css_header->header_len * 4)) { 935 drm_err(display->drm, "DMC firmware has wrong CSS header length " 936 "(%u bytes)\n", 937 (css_header->header_len * 4)); 938 return 0; 939 } 940 941 dmc->version = css_header->version; 942 943 return sizeof(struct intel_css_header); 944 } 945 946 static int parse_dmc_fw(struct intel_dmc *dmc, const struct firmware *fw) 947 { 948 struct intel_display *display = dmc->display; 949 struct intel_css_header *css_header; 950 struct intel_package_header *package_header; 951 struct intel_dmc_header_base *dmc_header; 952 struct stepping_info display_info = { '*', '*'}; 953 const struct stepping_info *si = intel_get_stepping_info(display, &display_info); 954 enum intel_dmc_id dmc_id; 955 u32 readcount = 0; 956 u32 r, offset; 957 958 if (!fw) 959 return -EINVAL; 960 961 /* Extract CSS Header information */ 962 css_header = (struct intel_css_header *)fw->data; 963 r = parse_dmc_fw_css(dmc, css_header, fw->size); 964 if (!r) 965 return -EINVAL; 966 967 readcount += r; 968 969 /* Extract Package Header information */ 970 package_header = (struct intel_package_header *)&fw->data[readcount]; 971 r = parse_dmc_fw_package(dmc, package_header, si, fw->size - readcount); 972 if (!r) 973 return -EINVAL; 974 975 readcount += r; 976 977 for_each_dmc_id(dmc_id) { 978 if (!dmc->dmc_info[dmc_id].present) 979 continue; 980 981 offset = readcount + dmc->dmc_info[dmc_id].dmc_offset * 4; 982 if (offset > fw->size) { 983 drm_err(display->drm, "Reading beyond the fw_size\n"); 984 continue; 985 } 986 987 dmc_header = (struct intel_dmc_header_base *)&fw->data[offset]; 988 parse_dmc_fw_header(dmc, dmc_header, fw->size - offset, dmc_id); 989 } 990 991 if (!intel_dmc_has_payload(display)) { 992 drm_err(display->drm, "DMC firmware main program not found\n"); 993 return -ENOENT; 994 } 995 996 return 0; 997 } 998 999 static void intel_dmc_runtime_pm_get(struct intel_display *display) 1000 { 1001 drm_WARN_ON(display->drm, display->dmc.wakeref); 1002 display->dmc.wakeref = intel_display_power_get(display, POWER_DOMAIN_INIT); 1003 } 1004 1005 static void intel_dmc_runtime_pm_put(struct intel_display *display) 1006 { 1007 intel_wakeref_t wakeref __maybe_unused = 1008 fetch_and_zero(&display->dmc.wakeref); 1009 1010 intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref); 1011 } 1012 1013 static const char *dmc_fallback_path(struct intel_display *display) 1014 { 1015 struct drm_i915_private *i915 = to_i915(display->drm); 1016 1017 if (IS_ALDERLAKE_P(i915)) 1018 return ADLP_DMC_FALLBACK_PATH; 1019 1020 return NULL; 1021 } 1022 1023 static void dmc_load_work_fn(struct work_struct *work) 1024 { 1025 struct intel_dmc *dmc = container_of(work, typeof(*dmc), work); 1026 struct intel_display *display = dmc->display; 1027 const struct firmware *fw = NULL; 1028 const char *fallback_path; 1029 int err; 1030 1031 err = request_firmware(&fw, dmc->fw_path, display->drm->dev); 1032 1033 if (err == -ENOENT && !dmc_firmware_param(display)) { 1034 fallback_path = dmc_fallback_path(display); 1035 if (fallback_path) { 1036 drm_dbg_kms(display->drm, "%s not found, falling back to %s\n", 1037 dmc->fw_path, fallback_path); 1038 err = request_firmware(&fw, fallback_path, display->drm->dev); 1039 if (err == 0) 1040 dmc->fw_path = fallback_path; 1041 } 1042 } 1043 1044 if (err) { 1045 drm_notice(display->drm, 1046 "Failed to load DMC firmware %s (%pe). Disabling runtime power management.\n", 1047 dmc->fw_path, ERR_PTR(err)); 1048 drm_notice(display->drm, "DMC firmware homepage: %s", 1049 INTEL_DMC_FIRMWARE_URL); 1050 return; 1051 } 1052 1053 err = parse_dmc_fw(dmc, fw); 1054 if (err) { 1055 drm_notice(display->drm, 1056 "Failed to parse DMC firmware %s (%pe). Disabling runtime power management.\n", 1057 dmc->fw_path, ERR_PTR(err)); 1058 goto out; 1059 } 1060 1061 intel_dmc_load_program(display); 1062 intel_dmc_runtime_pm_put(display); 1063 1064 drm_info(display->drm, "Finished loading DMC firmware %s (v%u.%u)\n", 1065 dmc->fw_path, DMC_VERSION_MAJOR(dmc->version), 1066 DMC_VERSION_MINOR(dmc->version)); 1067 1068 out: 1069 release_firmware(fw); 1070 } 1071 1072 /** 1073 * intel_dmc_init() - initialize the firmware loading. 1074 * @display: display instance 1075 * 1076 * This function is called at the time of loading the display driver to read 1077 * firmware from a .bin file and copied into a internal memory. 1078 */ 1079 void intel_dmc_init(struct intel_display *display) 1080 { 1081 struct drm_i915_private *i915 = to_i915(display->drm); 1082 struct intel_dmc *dmc; 1083 1084 if (!HAS_DMC(display)) 1085 return; 1086 1087 /* 1088 * Obtain a runtime pm reference, until DMC is loaded, to avoid entering 1089 * runtime-suspend. 1090 * 1091 * On error, we return with the rpm wakeref held to prevent runtime 1092 * suspend as runtime suspend *requires* a working DMC for whatever 1093 * reason. 1094 */ 1095 intel_dmc_runtime_pm_get(display); 1096 1097 dmc = kzalloc(sizeof(*dmc), GFP_KERNEL); 1098 if (!dmc) 1099 return; 1100 1101 dmc->display = display; 1102 1103 INIT_WORK(&dmc->work, dmc_load_work_fn); 1104 1105 dmc->fw_path = dmc_firmware_default(display, &dmc->max_fw_size); 1106 1107 if (dmc_firmware_param_disabled(display)) { 1108 drm_info(display->drm, "Disabling DMC firmware and runtime PM\n"); 1109 goto out; 1110 } 1111 1112 if (dmc_firmware_param(display)) 1113 dmc->fw_path = dmc_firmware_param(display); 1114 1115 if (!dmc->fw_path) { 1116 drm_dbg_kms(display->drm, 1117 "No known DMC firmware for platform, disabling runtime PM\n"); 1118 goto out; 1119 } 1120 1121 display->dmc.dmc = dmc; 1122 1123 drm_dbg_kms(display->drm, "Loading %s\n", dmc->fw_path); 1124 queue_work(i915->unordered_wq, &dmc->work); 1125 1126 return; 1127 1128 out: 1129 kfree(dmc); 1130 } 1131 1132 /** 1133 * intel_dmc_suspend() - prepare DMC firmware before system suspend 1134 * @display: display instance 1135 * 1136 * Prepare the DMC firmware before entering system suspend. This includes 1137 * flushing pending work items and releasing any resources acquired during 1138 * init. 1139 */ 1140 void intel_dmc_suspend(struct intel_display *display) 1141 { 1142 struct intel_dmc *dmc = display_to_dmc(display); 1143 1144 if (!HAS_DMC(display)) 1145 return; 1146 1147 if (dmc) 1148 flush_work(&dmc->work); 1149 1150 /* Drop the reference held in case DMC isn't loaded. */ 1151 if (!intel_dmc_has_payload(display)) 1152 intel_dmc_runtime_pm_put(display); 1153 } 1154 1155 /** 1156 * intel_dmc_resume() - init DMC firmware during system resume 1157 * @display: display instance 1158 * 1159 * Reinitialize the DMC firmware during system resume, reacquiring any 1160 * resources released in intel_dmc_suspend(). 1161 */ 1162 void intel_dmc_resume(struct intel_display *display) 1163 { 1164 if (!HAS_DMC(display)) 1165 return; 1166 1167 /* 1168 * Reacquire the reference to keep RPM disabled in case DMC isn't 1169 * loaded. 1170 */ 1171 if (!intel_dmc_has_payload(display)) 1172 intel_dmc_runtime_pm_get(display); 1173 } 1174 1175 /** 1176 * intel_dmc_fini() - unload the DMC firmware. 1177 * @display: display instance 1178 * 1179 * Firmmware unloading includes freeing the internal memory and reset the 1180 * firmware loading status. 1181 */ 1182 void intel_dmc_fini(struct intel_display *display) 1183 { 1184 struct intel_dmc *dmc = display_to_dmc(display); 1185 enum intel_dmc_id dmc_id; 1186 1187 if (!HAS_DMC(display)) 1188 return; 1189 1190 intel_dmc_suspend(display); 1191 drm_WARN_ON(display->drm, display->dmc.wakeref); 1192 1193 if (dmc) { 1194 for_each_dmc_id(dmc_id) 1195 kfree(dmc->dmc_info[dmc_id].payload); 1196 1197 kfree(dmc); 1198 display->dmc.dmc = NULL; 1199 } 1200 } 1201 1202 struct intel_dmc_snapshot { 1203 bool initialized; 1204 bool loaded; 1205 u32 version; 1206 }; 1207 1208 struct intel_dmc_snapshot *intel_dmc_snapshot_capture(struct intel_display *display) 1209 { 1210 struct intel_dmc *dmc = display_to_dmc(display); 1211 struct intel_dmc_snapshot *snapshot; 1212 1213 if (!HAS_DMC(display)) 1214 return NULL; 1215 1216 snapshot = kzalloc(sizeof(*snapshot), GFP_ATOMIC); 1217 if (!snapshot) 1218 return NULL; 1219 1220 snapshot->initialized = dmc; 1221 snapshot->loaded = intel_dmc_has_payload(display); 1222 if (dmc) 1223 snapshot->version = dmc->version; 1224 1225 return snapshot; 1226 } 1227 1228 void intel_dmc_snapshot_print(const struct intel_dmc_snapshot *snapshot, struct drm_printer *p) 1229 { 1230 if (!snapshot) 1231 return; 1232 1233 drm_printf(p, "DMC initialized: %s\n", str_yes_no(snapshot->initialized)); 1234 drm_printf(p, "DMC loaded: %s\n", str_yes_no(snapshot->loaded)); 1235 if (snapshot->initialized) 1236 drm_printf(p, "DMC fw version: %d.%d\n", 1237 DMC_VERSION_MAJOR(snapshot->version), 1238 DMC_VERSION_MINOR(snapshot->version)); 1239 } 1240 1241 void intel_dmc_update_dc6_allowed_count(struct intel_display *display, 1242 bool start_tracking) 1243 { 1244 struct intel_dmc *dmc = display_to_dmc(display); 1245 u32 dc5_cur_count; 1246 1247 if (DISPLAY_VER(dmc->display) < 14) 1248 return; 1249 1250 dc5_cur_count = intel_de_read(dmc->display, DG1_DMC_DEBUG_DC5_COUNT); 1251 1252 if (!start_tracking) 1253 dmc->dc6_allowed.count += dc5_cur_count - dmc->dc6_allowed.dc5_start; 1254 1255 dmc->dc6_allowed.dc5_start = dc5_cur_count; 1256 } 1257 1258 static bool intel_dmc_get_dc6_allowed_count(struct intel_display *display, u32 *count) 1259 { 1260 struct i915_power_domains *power_domains = &display->power.domains; 1261 struct intel_dmc *dmc = display_to_dmc(display); 1262 bool dc6_enabled; 1263 1264 if (DISPLAY_VER(display) < 14) 1265 return false; 1266 1267 mutex_lock(&power_domains->lock); 1268 dc6_enabled = intel_de_read(display, DC_STATE_EN) & 1269 DC_STATE_EN_UPTO_DC6; 1270 if (dc6_enabled) 1271 intel_dmc_update_dc6_allowed_count(display, false); 1272 1273 *count = dmc->dc6_allowed.count; 1274 mutex_unlock(&power_domains->lock); 1275 1276 return true; 1277 } 1278 1279 static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused) 1280 { 1281 struct intel_display *display = m->private; 1282 struct drm_i915_private *i915 = to_i915(display->drm); 1283 struct intel_dmc *dmc = display_to_dmc(display); 1284 struct ref_tracker *wakeref; 1285 i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG; 1286 u32 dc6_allowed_count; 1287 1288 if (!HAS_DMC(display)) 1289 return -ENODEV; 1290 1291 wakeref = intel_display_rpm_get(display); 1292 1293 seq_printf(m, "DMC initialized: %s\n", str_yes_no(dmc)); 1294 seq_printf(m, "fw loaded: %s\n", 1295 str_yes_no(intel_dmc_has_payload(display))); 1296 seq_printf(m, "path: %s\n", dmc ? dmc->fw_path : "N/A"); 1297 seq_printf(m, "Pipe A fw needed: %s\n", 1298 str_yes_no(DISPLAY_VER(display) >= 12)); 1299 seq_printf(m, "Pipe A fw loaded: %s\n", 1300 str_yes_no(has_dmc_id_fw(display, DMC_FW_PIPEA))); 1301 seq_printf(m, "Pipe B fw needed: %s\n", 1302 str_yes_no(IS_ALDERLAKE_P(i915) || 1303 DISPLAY_VER(display) >= 14)); 1304 seq_printf(m, "Pipe B fw loaded: %s\n", 1305 str_yes_no(has_dmc_id_fw(display, DMC_FW_PIPEB))); 1306 1307 if (!intel_dmc_has_payload(display)) 1308 goto out; 1309 1310 seq_printf(m, "version: %d.%d\n", DMC_VERSION_MAJOR(dmc->version), 1311 DMC_VERSION_MINOR(dmc->version)); 1312 1313 if (DISPLAY_VER(display) >= 12) { 1314 i915_reg_t dc3co_reg; 1315 1316 if (IS_DGFX(i915) || DISPLAY_VER(display) >= 14) { 1317 dc3co_reg = DG1_DMC_DEBUG3; 1318 dc5_reg = DG1_DMC_DEBUG_DC5_COUNT; 1319 } else { 1320 dc3co_reg = TGL_DMC_DEBUG3; 1321 dc5_reg = TGL_DMC_DEBUG_DC5_COUNT; 1322 dc6_reg = TGL_DMC_DEBUG_DC6_COUNT; 1323 } 1324 1325 seq_printf(m, "DC3CO count: %d\n", 1326 intel_de_read(display, dc3co_reg)); 1327 } else { 1328 dc5_reg = IS_BROXTON(i915) ? BXT_DMC_DC3_DC5_COUNT : 1329 SKL_DMC_DC3_DC5_COUNT; 1330 if (!IS_GEMINILAKE(i915) && !IS_BROXTON(i915)) 1331 dc6_reg = SKL_DMC_DC5_DC6_COUNT; 1332 } 1333 1334 seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(display, dc5_reg)); 1335 1336 if (intel_dmc_get_dc6_allowed_count(display, &dc6_allowed_count)) 1337 seq_printf(m, "DC5 -> DC6 allowed count: %d\n", 1338 dc6_allowed_count); 1339 else if (i915_mmio_reg_valid(dc6_reg)) 1340 seq_printf(m, "DC5 -> DC6 count: %d\n", 1341 intel_de_read(display, dc6_reg)); 1342 1343 seq_printf(m, "program base: 0x%08x\n", 1344 intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0))); 1345 1346 out: 1347 seq_printf(m, "ssp base: 0x%08x\n", 1348 intel_de_read(display, DMC_SSP_BASE)); 1349 seq_printf(m, "htp: 0x%08x\n", intel_de_read(display, DMC_HTP_SKL)); 1350 1351 intel_display_rpm_put(display, wakeref); 1352 1353 return 0; 1354 } 1355 1356 DEFINE_SHOW_ATTRIBUTE(intel_dmc_debugfs_status); 1357 1358 void intel_dmc_debugfs_register(struct intel_display *display) 1359 { 1360 struct drm_minor *minor = display->drm->primary; 1361 1362 debugfs_create_file("i915_dmc_info", 0444, minor->debugfs_root, 1363 display, &intel_dmc_debugfs_status_fops); 1364 } 1365