1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/debugfs.h> 26 #include <linux/firmware.h> 27 #include <drm/drm_vblank.h> 28 29 #include <drm/drm_file.h> 30 #include <drm/drm_print.h> 31 32 #include "intel_crtc.h" 33 #include "intel_de.h" 34 #include "intel_display_power_well.h" 35 #include "intel_display_regs.h" 36 #include "intel_display_rpm.h" 37 #include "intel_display_types.h" 38 #include "intel_display_utils.h" 39 #include "intel_dmc.h" 40 #include "intel_dmc_regs.h" 41 #include "intel_flipq.h" 42 #include "intel_step.h" 43 44 /** 45 * DOC: DMC Firmware Support 46 * 47 * From gen9 onwards we have newly added DMC (Display microcontroller) in display 48 * engine to save and restore the state of display engine when it enter into 49 * low-power state and comes back to normal. 50 */ 51 52 #define INTEL_DMC_FIRMWARE_URL "https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git" 53 54 enum intel_dmc_id { 55 DMC_FW_MAIN = 0, 56 DMC_FW_PIPEA, 57 DMC_FW_PIPEB, 58 DMC_FW_PIPEC, 59 DMC_FW_PIPED, 60 DMC_FW_MAX 61 }; 62 63 struct intel_dmc { 64 struct intel_display *display; 65 struct work_struct work; 66 const char *fw_path; 67 u32 max_fw_size; /* bytes */ 68 u32 version; 69 struct { 70 u32 dc5_start; 71 u32 count; 72 } dc6_allowed; 73 struct dmc_fw_info { 74 u32 mmio_count; 75 i915_reg_t mmioaddr[20]; 76 u32 mmiodata[20]; 77 u32 dmc_offset; 78 u32 start_mmioaddr; 79 u32 dmc_fw_size; /*dwords */ 80 u32 *payload; 81 bool present; 82 } dmc_info[DMC_FW_MAX]; 83 }; 84 85 /* Note: This may be NULL. */ 86 static struct intel_dmc *display_to_dmc(struct intel_display *display) 87 { 88 return display->dmc.dmc; 89 } 90 91 static const char *dmc_firmware_param(struct intel_display *display) 92 { 93 const char *p = display->params.dmc_firmware_path; 94 95 return p && *p ? p : NULL; 96 } 97 98 static bool dmc_firmware_param_disabled(struct intel_display *display) 99 { 100 const char *p = dmc_firmware_param(display); 101 102 /* Magic path to indicate disabled */ 103 return p && !strcmp(p, "/dev/null"); 104 } 105 106 #define DMC_VERSION(major, minor) ((major) << 16 | (minor)) 107 #define DMC_VERSION_MAJOR(version) ((version) >> 16) 108 #define DMC_VERSION_MINOR(version) ((version) & 0xffff) 109 110 #define DMC_PATH(platform) \ 111 "i915/" __stringify(platform) "_dmc.bin" 112 113 /* 114 * New DMC additions should not use this. This is used solely to remain 115 * compatible with systems that have not yet updated DMC blobs to use 116 * unversioned file names. 117 */ 118 #define DMC_LEGACY_PATH(platform, major, minor) \ 119 "i915/" \ 120 __stringify(platform) "_dmc_ver" \ 121 __stringify(major) "_" \ 122 __stringify(minor) ".bin" 123 124 #define XE2LPD_DMC_MAX_FW_SIZE 0x8000 125 #define XELPDP_DMC_MAX_FW_SIZE 0x7000 126 #define DISPLAY_VER13_DMC_MAX_FW_SIZE 0x20000 127 #define DISPLAY_VER12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE 128 129 #define XE3P_LPD_DMC_PATH DMC_PATH(xe3p_lpd) 130 MODULE_FIRMWARE(XE3P_LPD_DMC_PATH); 131 132 #define XE3LPD_3002_DMC_PATH DMC_PATH(xe3lpd_3002) 133 MODULE_FIRMWARE(XE3LPD_3002_DMC_PATH); 134 135 #define XE3LPD_DMC_PATH DMC_PATH(xe3lpd) 136 MODULE_FIRMWARE(XE3LPD_DMC_PATH); 137 138 #define XE2LPD_DMC_PATH DMC_PATH(xe2lpd) 139 MODULE_FIRMWARE(XE2LPD_DMC_PATH); 140 141 #define BMG_DMC_PATH DMC_PATH(bmg) 142 MODULE_FIRMWARE(BMG_DMC_PATH); 143 144 #define MTL_DMC_PATH DMC_PATH(mtl) 145 MODULE_FIRMWARE(MTL_DMC_PATH); 146 147 #define DG2_DMC_PATH DMC_LEGACY_PATH(dg2, 2, 08) 148 MODULE_FIRMWARE(DG2_DMC_PATH); 149 150 #define ADLP_DMC_PATH DMC_PATH(adlp) 151 #define ADLP_DMC_FALLBACK_PATH DMC_LEGACY_PATH(adlp, 2, 16) 152 MODULE_FIRMWARE(ADLP_DMC_PATH); 153 MODULE_FIRMWARE(ADLP_DMC_FALLBACK_PATH); 154 155 #define ADLS_DMC_PATH DMC_LEGACY_PATH(adls, 2, 01) 156 MODULE_FIRMWARE(ADLS_DMC_PATH); 157 158 #define DG1_DMC_PATH DMC_LEGACY_PATH(dg1, 2, 02) 159 MODULE_FIRMWARE(DG1_DMC_PATH); 160 161 #define RKL_DMC_PATH DMC_LEGACY_PATH(rkl, 2, 03) 162 MODULE_FIRMWARE(RKL_DMC_PATH); 163 164 #define TGL_DMC_PATH DMC_LEGACY_PATH(tgl, 2, 12) 165 MODULE_FIRMWARE(TGL_DMC_PATH); 166 167 #define ICL_DMC_PATH DMC_LEGACY_PATH(icl, 1, 09) 168 #define ICL_DMC_MAX_FW_SIZE 0x6000 169 MODULE_FIRMWARE(ICL_DMC_PATH); 170 171 #define GLK_DMC_PATH DMC_LEGACY_PATH(glk, 1, 04) 172 #define GLK_DMC_MAX_FW_SIZE 0x4000 173 MODULE_FIRMWARE(GLK_DMC_PATH); 174 175 #define KBL_DMC_PATH DMC_LEGACY_PATH(kbl, 1, 04) 176 #define KBL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE 177 MODULE_FIRMWARE(KBL_DMC_PATH); 178 179 #define SKL_DMC_PATH DMC_LEGACY_PATH(skl, 1, 27) 180 #define SKL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE 181 MODULE_FIRMWARE(SKL_DMC_PATH); 182 183 #define BXT_DMC_PATH DMC_LEGACY_PATH(bxt, 1, 07) 184 #define BXT_DMC_MAX_FW_SIZE 0x3000 185 MODULE_FIRMWARE(BXT_DMC_PATH); 186 187 static const char *dmc_firmware_default(struct intel_display *display, u32 *size) 188 { 189 const char *fw_path = NULL; 190 u32 max_fw_size = 0; 191 192 if (DISPLAY_VERx100(display) == 3500) { 193 fw_path = XE3P_LPD_DMC_PATH; 194 max_fw_size = XE2LPD_DMC_MAX_FW_SIZE; 195 } else if (DISPLAY_VERx100(display) == 3002) { 196 fw_path = XE3LPD_3002_DMC_PATH; 197 max_fw_size = XE2LPD_DMC_MAX_FW_SIZE; 198 } else if (DISPLAY_VERx100(display) == 3000) { 199 fw_path = XE3LPD_DMC_PATH; 200 max_fw_size = XE2LPD_DMC_MAX_FW_SIZE; 201 } else if (DISPLAY_VERx100(display) == 2000) { 202 fw_path = XE2LPD_DMC_PATH; 203 max_fw_size = XE2LPD_DMC_MAX_FW_SIZE; 204 } else if (DISPLAY_VERx100(display) == 1401) { 205 fw_path = BMG_DMC_PATH; 206 max_fw_size = XELPDP_DMC_MAX_FW_SIZE; 207 } else if (DISPLAY_VERx100(display) == 1400) { 208 fw_path = MTL_DMC_PATH; 209 max_fw_size = XELPDP_DMC_MAX_FW_SIZE; 210 } else if (display->platform.dg2) { 211 fw_path = DG2_DMC_PATH; 212 max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE; 213 } else if (display->platform.alderlake_p) { 214 fw_path = ADLP_DMC_PATH; 215 max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE; 216 } else if (display->platform.alderlake_s) { 217 fw_path = ADLS_DMC_PATH; 218 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 219 } else if (display->platform.dg1) { 220 fw_path = DG1_DMC_PATH; 221 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 222 } else if (display->platform.rocketlake) { 223 fw_path = RKL_DMC_PATH; 224 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 225 } else if (display->platform.tigerlake) { 226 fw_path = TGL_DMC_PATH; 227 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 228 } else if (DISPLAY_VER(display) == 11) { 229 fw_path = ICL_DMC_PATH; 230 max_fw_size = ICL_DMC_MAX_FW_SIZE; 231 } else if (display->platform.geminilake) { 232 fw_path = GLK_DMC_PATH; 233 max_fw_size = GLK_DMC_MAX_FW_SIZE; 234 } else if (display->platform.kabylake || 235 display->platform.coffeelake || 236 display->platform.cometlake) { 237 fw_path = KBL_DMC_PATH; 238 max_fw_size = KBL_DMC_MAX_FW_SIZE; 239 } else if (display->platform.skylake) { 240 fw_path = SKL_DMC_PATH; 241 max_fw_size = SKL_DMC_MAX_FW_SIZE; 242 } else if (display->platform.broxton) { 243 fw_path = BXT_DMC_PATH; 244 max_fw_size = BXT_DMC_MAX_FW_SIZE; 245 } 246 247 *size = max_fw_size; 248 249 return fw_path; 250 } 251 252 #define DMC_DEFAULT_FW_OFFSET 0xFFFFFFFF 253 #define PACKAGE_MAX_FW_INFO_ENTRIES 20 254 #define PACKAGE_V2_MAX_FW_INFO_ENTRIES 32 255 #define DMC_V1_MAX_MMIO_COUNT 8 256 #define DMC_V3_MAX_MMIO_COUNT 20 257 #define DMC_V1_MMIO_START_RANGE 0x80000 258 259 #define PIPE_TO_DMC_ID(pipe) (DMC_FW_PIPEA + ((pipe) - PIPE_A)) 260 261 struct intel_css_header { 262 /* 0x09 for DMC */ 263 u32 module_type; 264 265 /* Includes the DMC specific header in dwords */ 266 u32 header_len; 267 268 /* always value would be 0x10000 */ 269 u32 header_ver; 270 271 /* Not used */ 272 u32 module_id; 273 274 /* Not used */ 275 u32 module_vendor; 276 277 /* in YYYYMMDD format */ 278 u32 date; 279 280 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */ 281 u32 size; 282 283 /* Not used */ 284 u32 key_size; 285 286 /* Not used */ 287 u32 modulus_size; 288 289 /* Not used */ 290 u32 exponent_size; 291 292 /* Not used */ 293 u32 reserved1[12]; 294 295 /* Major Minor */ 296 u32 version; 297 298 /* Not used */ 299 u32 reserved2[8]; 300 301 /* Not used */ 302 u32 kernel_header_info; 303 } __packed; 304 305 struct intel_fw_info { 306 u8 reserved1; 307 308 /* reserved on package_header version 1, must be 0 on version 2 */ 309 u8 dmc_id; 310 311 /* Stepping (A, B, C, ..., *). * is a wildcard */ 312 char stepping; 313 314 /* Sub-stepping (0, 1, ..., *). * is a wildcard */ 315 char substepping; 316 317 u32 offset; 318 u32 reserved2; 319 } __packed; 320 321 struct intel_package_header { 322 /* DMC container header length in dwords */ 323 u8 header_len; 324 325 /* 0x01, 0x02 */ 326 u8 header_ver; 327 328 u8 reserved[10]; 329 330 /* Number of valid entries in the FWInfo array below */ 331 u32 num_entries; 332 } __packed; 333 334 struct intel_dmc_header_base { 335 /* always value would be 0x40403E3E */ 336 u32 signature; 337 338 /* DMC binary header length */ 339 u8 header_len; 340 341 /* 0x01 */ 342 u8 header_ver; 343 344 /* Reserved */ 345 u16 dmcc_ver; 346 347 /* Major, Minor */ 348 u32 project; 349 350 /* Firmware program size (excluding header) in dwords */ 351 u32 fw_size; 352 353 /* Major Minor version */ 354 u32 fw_version; 355 } __packed; 356 357 struct intel_dmc_header_v1 { 358 struct intel_dmc_header_base base; 359 360 /* Number of valid MMIO cycles present. */ 361 u32 mmio_count; 362 363 /* MMIO address */ 364 u32 mmioaddr[DMC_V1_MAX_MMIO_COUNT]; 365 366 /* MMIO data */ 367 u32 mmiodata[DMC_V1_MAX_MMIO_COUNT]; 368 369 /* FW filename */ 370 char dfile[32]; 371 372 u32 reserved1[2]; 373 } __packed; 374 375 struct intel_dmc_header_v3 { 376 struct intel_dmc_header_base base; 377 378 /* DMC RAM start MMIO address */ 379 u32 start_mmioaddr; 380 381 u32 reserved[9]; 382 383 /* FW filename */ 384 char dfile[32]; 385 386 /* Number of valid MMIO cycles present. */ 387 u32 mmio_count; 388 389 /* MMIO address */ 390 u32 mmioaddr[DMC_V3_MAX_MMIO_COUNT]; 391 392 /* MMIO data */ 393 u32 mmiodata[DMC_V3_MAX_MMIO_COUNT]; 394 } __packed; 395 396 struct stepping_info { 397 char stepping; 398 char substepping; 399 }; 400 401 #define for_each_dmc_id(__dmc_id) \ 402 for ((__dmc_id) = DMC_FW_MAIN; (__dmc_id) < DMC_FW_MAX; (__dmc_id)++) 403 404 static bool is_valid_dmc_id(enum intel_dmc_id dmc_id) 405 { 406 return dmc_id >= DMC_FW_MAIN && dmc_id < DMC_FW_MAX; 407 } 408 409 static bool has_dmc_id_fw(struct intel_display *display, enum intel_dmc_id dmc_id) 410 { 411 struct intel_dmc *dmc = display_to_dmc(display); 412 413 return dmc && dmc->dmc_info[dmc_id].payload; 414 } 415 416 bool intel_dmc_has_payload(struct intel_display *display) 417 { 418 return has_dmc_id_fw(display, DMC_FW_MAIN); 419 } 420 421 static const struct stepping_info * 422 intel_get_stepping_info(struct intel_display *display, 423 struct stepping_info *si) 424 { 425 const char *step_name = intel_step_name(INTEL_DISPLAY_STEP(display)); 426 427 si->stepping = step_name[0]; 428 si->substepping = step_name[1]; 429 return si; 430 } 431 432 static void gen9_set_dc_state_debugmask(struct intel_display *display) 433 { 434 /* The below bit doesn't need to be cleared ever afterwards */ 435 intel_de_rmw(display, DC_STATE_DEBUG, 0, 436 DC_STATE_DEBUG_MASK_CORES | DC_STATE_DEBUG_MASK_MEMORY_UP); 437 intel_de_posting_read(display, DC_STATE_DEBUG); 438 } 439 440 static void disable_event_handler(struct intel_display *display, 441 i915_reg_t ctl_reg, i915_reg_t htp_reg) 442 { 443 intel_de_write(display, ctl_reg, 444 REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, 445 DMC_EVT_CTL_TYPE_EDGE_0_1) | 446 REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, 447 DMC_EVENT_FALSE)); 448 intel_de_write(display, htp_reg, 0); 449 } 450 451 static void disable_all_event_handlers(struct intel_display *display, 452 enum intel_dmc_id dmc_id) 453 { 454 int handler; 455 456 /* TODO: disable the event handlers on pre-GEN12 platforms as well */ 457 if (DISPLAY_VER(display) < 12) 458 return; 459 460 if (!has_dmc_id_fw(display, dmc_id)) 461 return; 462 463 for (handler = 0; handler < DMC_EVENT_HANDLER_COUNT_GEN12; handler++) 464 disable_event_handler(display, 465 DMC_EVT_CTL(display, dmc_id, handler), 466 DMC_EVT_HTP(display, dmc_id, handler)); 467 } 468 469 static void adlp_pipedmc_clock_gating_wa(struct intel_display *display, bool enable) 470 { 471 enum pipe pipe; 472 473 /* 474 * Wa_16015201720:adl-p,dg2 475 * The WA requires clock gating to be disabled all the time 476 * for pipe A and B. 477 * For pipe C and D clock gating needs to be disabled only 478 * during initializing the firmware. 479 */ 480 if (enable) 481 for (pipe = PIPE_A; pipe <= PIPE_D; pipe++) 482 intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe), 483 0, PIPEDMC_GATING_DIS); 484 else 485 for (pipe = PIPE_C; pipe <= PIPE_D; pipe++) 486 intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe), 487 PIPEDMC_GATING_DIS, 0); 488 } 489 490 static void mtl_pipedmc_clock_gating_wa(struct intel_display *display) 491 { 492 /* 493 * Wa_16015201720 494 * The WA requires clock gating to be disabled all the time 495 * for pipe A and B. 496 */ 497 intel_de_rmw(display, GEN9_CLKGATE_DIS_0, 0, 498 MTL_PIPEDMC_GATING_DIS(PIPE_A) | 499 MTL_PIPEDMC_GATING_DIS(PIPE_B)); 500 } 501 502 static void pipedmc_clock_gating_wa(struct intel_display *display, bool enable) 503 { 504 if (display->platform.meteorlake && enable) 505 mtl_pipedmc_clock_gating_wa(display); 506 else if (DISPLAY_VER(display) == 13) 507 adlp_pipedmc_clock_gating_wa(display, enable); 508 } 509 510 static u32 pipedmc_interrupt_mask(struct intel_display *display) 511 { 512 /* 513 * FIXME PIPEDMC_ERROR not enabled for now due to LNL pipe B 514 * triggering it during the first DC state transition. Figure 515 * out what is going on... 516 */ 517 return PIPEDMC_FLIPQ_PROG_DONE | 518 PIPEDMC_GTT_FAULT | 519 PIPEDMC_ATS_FAULT; 520 } 521 522 static u32 dmc_evt_ctl_disable(u32 dmc_evt_ctl) 523 { 524 /* 525 * DMC_EVT_CTL_ENABLE cannot be cleared once set. Always 526 * configure it based on the original event definition to 527 * avoid mismatches in assert_dmc_loaded(). 528 */ 529 return (dmc_evt_ctl & DMC_EVT_CTL_ENABLE) | 530 REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, 531 DMC_EVT_CTL_TYPE_EDGE_0_1) | 532 REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, 533 DMC_EVENT_FALSE); 534 } 535 536 static bool is_dmc_evt_ctl_reg(struct intel_display *display, 537 enum intel_dmc_id dmc_id, i915_reg_t reg) 538 { 539 u32 offset = i915_mmio_reg_offset(reg); 540 u32 start = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, 0)); 541 u32 end = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); 542 543 return offset >= start && offset < end; 544 } 545 546 static bool is_dmc_evt_htp_reg(struct intel_display *display, 547 enum intel_dmc_id dmc_id, i915_reg_t reg) 548 { 549 u32 offset = i915_mmio_reg_offset(reg); 550 u32 start = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, 0)); 551 u32 end = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); 552 553 return offset >= start && offset < end; 554 } 555 556 static bool is_event_handler(struct intel_display *display, 557 enum intel_dmc_id dmc_id, 558 unsigned int event_id, 559 i915_reg_t reg, u32 data) 560 { 561 return is_dmc_evt_ctl_reg(display, dmc_id, reg) && 562 REG_FIELD_GET(DMC_EVT_CTL_EVENT_ID_MASK, data) == event_id; 563 } 564 565 static bool fixup_dmc_evt(struct intel_display *display, 566 enum intel_dmc_id dmc_id, 567 i915_reg_t reg_ctl, u32 *data_ctl, 568 i915_reg_t reg_htp, u32 *data_htp) 569 { 570 if (!is_dmc_evt_ctl_reg(display, dmc_id, reg_ctl)) 571 return false; 572 573 if (!is_dmc_evt_htp_reg(display, dmc_id, reg_htp)) 574 return false; 575 576 /* make sure reg_ctl and reg_htp are for the same event */ 577 if (i915_mmio_reg_offset(reg_ctl) - i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, 0)) != 578 i915_mmio_reg_offset(reg_htp) - i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, 0))) 579 return false; 580 581 /* 582 * On ADL-S the HRR event handler is not restored after DC6. 583 * Clear it to zero from the beginning to avoid mismatches later. 584 */ 585 if (display->platform.alderlake_s && dmc_id == DMC_FW_MAIN && 586 is_event_handler(display, dmc_id, MAINDMC_EVENT_VBLANK_A, reg_ctl, *data_ctl)) { 587 *data_ctl = 0; 588 *data_htp = 0; 589 return true; 590 } 591 592 /* 593 * TGL/ADL-S DMC firmware incorrectly uses the undelayed vblank 594 * event for the HRR handler, when it should be using the delayed 595 * vblank event instead. Fixed firmware was never released 596 * so the Windows driver just hacks around it by overriding 597 * the event ID. Do the same. 598 */ 599 if ((display->platform.tigerlake || display->platform.alderlake_s) && 600 is_event_handler(display, dmc_id, MAINDMC_EVENT_VBLANK_A, reg_ctl, *data_ctl)) { 601 *data_ctl &= ~DMC_EVT_CTL_EVENT_ID_MASK; 602 *data_ctl |= REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, 603 MAINDMC_EVENT_VBLANK_DELAYED_A); 604 return true; 605 } 606 607 return false; 608 } 609 610 static bool disable_dmc_evt(struct intel_display *display, 611 enum intel_dmc_id dmc_id, 612 i915_reg_t reg, u32 data) 613 { 614 if (!is_dmc_evt_ctl_reg(display, dmc_id, reg)) 615 return false; 616 617 /* keep all pipe DMC events disabled by default */ 618 if (dmc_id != DMC_FW_MAIN) 619 return true; 620 621 /* also disable the flip queue event on the main DMC on TGL */ 622 if (display->platform.tigerlake && 623 is_event_handler(display, dmc_id, MAINDMC_EVENT_CLK_MSEC, reg, data)) 624 return true; 625 626 /* also disable the HRR event on the main DMC on TGL/ADLS */ 627 if ((display->platform.tigerlake || display->platform.alderlake_s) && 628 is_event_handler(display, dmc_id, MAINDMC_EVENT_VBLANK_DELAYED_A, reg, data)) 629 return true; 630 631 return false; 632 } 633 634 static u32 dmc_mmiodata(struct intel_display *display, 635 struct intel_dmc *dmc, 636 enum intel_dmc_id dmc_id, int i) 637 { 638 if (disable_dmc_evt(display, dmc_id, 639 dmc->dmc_info[dmc_id].mmioaddr[i], 640 dmc->dmc_info[dmc_id].mmiodata[i])) 641 return dmc_evt_ctl_disable(dmc->dmc_info[dmc_id].mmiodata[i]); 642 else 643 return dmc->dmc_info[dmc_id].mmiodata[i]; 644 } 645 646 static void dmc_load_mmio(struct intel_display *display, enum intel_dmc_id dmc_id) 647 { 648 struct intel_dmc *dmc = display_to_dmc(display); 649 int i; 650 651 for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) { 652 intel_de_write(display, dmc->dmc_info[dmc_id].mmioaddr[i], 653 dmc_mmiodata(display, dmc, dmc_id, i)); 654 } 655 } 656 657 static void dmc_load_program(struct intel_display *display, enum intel_dmc_id dmc_id) 658 { 659 struct intel_dmc *dmc = display_to_dmc(display); 660 int i; 661 662 disable_all_event_handlers(display, dmc_id); 663 664 preempt_disable(); 665 666 for (i = 0; i < dmc->dmc_info[dmc_id].dmc_fw_size; i++) { 667 intel_de_write_fw(display, 668 DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, i), 669 dmc->dmc_info[dmc_id].payload[i]); 670 } 671 672 preempt_enable(); 673 674 dmc_load_mmio(display, dmc_id); 675 } 676 677 static void assert_dmc_loaded(struct intel_display *display, 678 enum intel_dmc_id dmc_id) 679 { 680 struct intel_dmc *dmc = display_to_dmc(display); 681 u32 expected, found; 682 int i; 683 684 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id)) 685 return; 686 687 found = intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, 0)); 688 expected = dmc->dmc_info[dmc_id].payload[0]; 689 690 drm_WARN(display->drm, found != expected, 691 "DMC %d program storage start incorrect (expected 0x%x, current 0x%x)\n", 692 dmc_id, expected, found); 693 694 for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) { 695 i915_reg_t reg = dmc->dmc_info[dmc_id].mmioaddr[i]; 696 697 found = intel_de_read(display, reg); 698 expected = dmc_mmiodata(display, dmc, dmc_id, i); 699 700 drm_WARN(display->drm, found != expected, 701 "DMC %d mmio[%d]/0x%x incorrect (expected 0x%x, current 0x%x)\n", 702 dmc_id, i, i915_mmio_reg_offset(reg), expected, found); 703 } 704 } 705 706 void assert_main_dmc_loaded(struct intel_display *display) 707 { 708 assert_dmc_loaded(display, DMC_FW_MAIN); 709 } 710 711 static bool need_pipedmc_load_program(struct intel_display *display) 712 { 713 /* On TGL/derivatives pipe DMC state is lost when PG1 is disabled */ 714 return DISPLAY_VER(display) == 12; 715 } 716 717 static bool need_pipedmc_load_mmio(struct intel_display *display, enum pipe pipe) 718 { 719 /* 720 * Xe3_LPD/Xe3p_LPD: 721 * - pipe A/B DMC doesn't need save/restore 722 * - pipe C/D DMC is in PG0, needs manual save/restore 723 */ 724 if (IS_DISPLAY_VER(display, 30, 35)) 725 return pipe >= PIPE_C; 726 727 /* 728 * FIXME LNL unclear, main DMC firmware has the pipe DMC A/B PG0 729 * save/restore, but so far unable to see the loss of pipe DMC state 730 * in action. Are we just failing to turn off PG0 due to some other 731 * SoC level stuff? 732 */ 733 if (DISPLAY_VER(display) == 20) 734 return false; 735 736 /* 737 * FIXME BMG untested, main DMC firmware has the 738 * pipe DMC A/B PG0 save/restore... 739 */ 740 if (display->platform.battlemage) 741 return false; 742 743 /* 744 * DG2: 745 * - Pipe DMCs presumably in PG0? 746 * - No DC6, and even DC9 doesn't seem to result 747 * in loss of DMC state for whatever reason 748 */ 749 if (display->platform.dg2) 750 return false; 751 752 /* 753 * ADL/MTL: 754 * - pipe A/B DMC is in PG0, saved/restored by the main DMC 755 * - pipe C/D DMC is in PG0, needs manual save/restore 756 */ 757 if (IS_DISPLAY_VER(display, 13, 14)) 758 return pipe >= PIPE_C; 759 760 return false; 761 } 762 763 static bool can_enable_pipedmc(const struct intel_crtc_state *crtc_state) 764 { 765 struct intel_display *display = to_intel_display(crtc_state); 766 767 /* 768 * On TGL/derivatives pipe DMC state is lost when PG1 is disabled. 769 * Do not even enable the pipe DMC when that can happen outside 770 * of driver control (PSR+DC5/6). 771 */ 772 if (DISPLAY_VER(display) == 12 && crtc_state->has_psr) 773 return false; 774 775 return true; 776 } 777 778 void intel_dmc_enable_pipe(const struct intel_crtc_state *crtc_state) 779 { 780 struct intel_display *display = to_intel_display(crtc_state); 781 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 782 enum pipe pipe = crtc->pipe; 783 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); 784 785 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id)) 786 return; 787 788 if (!can_enable_pipedmc(crtc_state)) { 789 intel_dmc_disable_pipe(crtc_state); 790 return; 791 } 792 793 if (need_pipedmc_load_program(display)) 794 dmc_load_program(display, dmc_id); 795 else if (need_pipedmc_load_mmio(display, pipe)) 796 dmc_load_mmio(display, dmc_id); 797 798 assert_dmc_loaded(display, dmc_id); 799 800 if (DISPLAY_VER(display) >= 20) { 801 intel_flipq_reset(display, pipe); 802 803 intel_de_write(display, PIPEDMC_INTERRUPT(pipe), pipedmc_interrupt_mask(display)); 804 intel_de_write(display, PIPEDMC_INTERRUPT_MASK(pipe), ~pipedmc_interrupt_mask(display)); 805 } 806 807 if (DISPLAY_VER(display) >= 14) 808 intel_de_rmw(display, MTL_PIPEDMC_CONTROL, 0, PIPEDMC_ENABLE_MTL(pipe)); 809 else 810 intel_de_rmw(display, PIPEDMC_CONTROL(pipe), 0, PIPEDMC_ENABLE); 811 } 812 813 void intel_dmc_disable_pipe(const struct intel_crtc_state *crtc_state) 814 { 815 struct intel_display *display = to_intel_display(crtc_state); 816 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 817 enum pipe pipe = crtc->pipe; 818 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); 819 820 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id)) 821 return; 822 823 if (DISPLAY_VER(display) >= 14) 824 intel_de_rmw(display, MTL_PIPEDMC_CONTROL, PIPEDMC_ENABLE_MTL(pipe), 0); 825 else 826 intel_de_rmw(display, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0); 827 828 if (DISPLAY_VER(display) >= 20) { 829 intel_de_write(display, PIPEDMC_INTERRUPT_MASK(pipe), ~0); 830 intel_de_write(display, PIPEDMC_INTERRUPT(pipe), pipedmc_interrupt_mask(display)); 831 832 intel_flipq_reset(display, pipe); 833 } 834 } 835 836 static void dmc_configure_event(struct intel_display *display, 837 enum intel_dmc_id dmc_id, 838 unsigned int event_id, 839 bool enable) 840 { 841 struct intel_dmc *dmc = display_to_dmc(display); 842 int num_handlers = 0; 843 int i; 844 845 for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) { 846 i915_reg_t reg = dmc->dmc_info[dmc_id].mmioaddr[i]; 847 u32 data = dmc->dmc_info[dmc_id].mmiodata[i]; 848 849 if (!is_event_handler(display, dmc_id, event_id, reg, data)) 850 continue; 851 852 intel_de_write(display, reg, enable ? data : dmc_evt_ctl_disable(data)); 853 num_handlers++; 854 } 855 856 drm_WARN_ONCE(display->drm, num_handlers != 1, 857 "DMC %d has %d handlers for event 0x%x\n", 858 dmc_id, num_handlers, event_id); 859 } 860 861 void intel_dmc_configure_dc_balance_event(struct intel_display *display, 862 enum pipe pipe, bool enable) 863 { 864 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); 865 866 dmc_configure_event(display, dmc_id, PIPEDMC_EVENT_ADAPTIVE_DCB_TRIGGER, enable); 867 } 868 869 /** 870 * intel_dmc_block_pkgc() - block PKG C-state 871 * @display: display instance 872 * @pipe: pipe which register use to block 873 * @block: block/unblock 874 * 875 * This interface is target for Wa_16025596647 usage. I.e. to set/clear 876 * PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS bit in PIPEDMC_BLOCK_PKGC_SW register. 877 */ 878 void intel_dmc_block_pkgc(struct intel_display *display, enum pipe pipe, 879 bool block) 880 { 881 intel_de_rmw(display, PIPEDMC_BLOCK_PKGC_SW(pipe), 882 PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS, block ? 883 PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS : 0); 884 } 885 886 /** 887 * intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank() - start of PKG 888 * C-state exit 889 * @display: display instance 890 * @pipe: pipe which register use to block 891 * @enable: enable/disable 892 * 893 * This interface is target for Wa_16025596647 usage. I.e. start the package C 894 * exit at the start of the undelayed vblank 895 */ 896 void intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(struct intel_display *display, 897 enum pipe pipe, bool enable) 898 { 899 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); 900 901 dmc_configure_event(display, dmc_id, PIPEDMC_EVENT_VBLANK, enable); 902 } 903 904 /** 905 * intel_dmc_load_program() - write the firmware from memory to register. 906 * @display: display instance 907 * 908 * DMC firmware is read from a .bin file and kept in internal memory one time. 909 * Everytime display comes back from low power state this function is called to 910 * copy the firmware from internal memory to registers. 911 */ 912 void intel_dmc_load_program(struct intel_display *display) 913 { 914 struct i915_power_domains *power_domains = &display->power.domains; 915 enum intel_dmc_id dmc_id; 916 917 if (!intel_dmc_has_payload(display)) 918 return; 919 920 assert_display_rpm_held(display); 921 922 pipedmc_clock_gating_wa(display, true); 923 924 for_each_dmc_id(dmc_id) { 925 dmc_load_program(display, dmc_id); 926 assert_dmc_loaded(display, dmc_id); 927 } 928 929 if (DISPLAY_VER(display) >= 20) 930 intel_de_write(display, DMC_FQ_W2_PTS_CFG_SEL, 931 PIPE_D_DMC_W2_PTS_CONFIG_SELECT(PIPE_D) | 932 PIPE_C_DMC_W2_PTS_CONFIG_SELECT(PIPE_C) | 933 PIPE_B_DMC_W2_PTS_CONFIG_SELECT(PIPE_B) | 934 PIPE_A_DMC_W2_PTS_CONFIG_SELECT(PIPE_A)); 935 936 power_domains->dc_state = 0; 937 938 gen9_set_dc_state_debugmask(display); 939 940 pipedmc_clock_gating_wa(display, false); 941 } 942 943 /** 944 * intel_dmc_disable_program() - disable the firmware 945 * @display: display instance 946 * 947 * Disable all event handlers in the firmware, making sure the firmware is 948 * inactive after the display is uninitialized. 949 */ 950 void intel_dmc_disable_program(struct intel_display *display) 951 { 952 enum intel_dmc_id dmc_id; 953 954 if (!intel_dmc_has_payload(display)) 955 return; 956 957 pipedmc_clock_gating_wa(display, true); 958 959 for_each_dmc_id(dmc_id) 960 disable_all_event_handlers(display, dmc_id); 961 962 pipedmc_clock_gating_wa(display, false); 963 } 964 965 static bool fw_info_matches_stepping(const struct intel_fw_info *fw_info, 966 const struct stepping_info *si) 967 { 968 if ((fw_info->substepping == '*' && si->stepping == fw_info->stepping) || 969 (si->stepping == fw_info->stepping && si->substepping == fw_info->substepping) || 970 /* 971 * If we don't find a more specific one from above two checks, we 972 * then check for the generic one to be sure to work even with 973 * "broken firmware" 974 */ 975 (si->stepping == '*' && si->substepping == fw_info->substepping) || 976 (fw_info->stepping == '*' && fw_info->substepping == '*')) 977 return true; 978 979 return false; 980 } 981 982 /* 983 * Search fw_info table for dmc_offset to find firmware binary: num_entries is 984 * already sanitized. 985 */ 986 static void dmc_set_fw_offset(struct intel_dmc *dmc, 987 const struct intel_fw_info *fw_info, 988 unsigned int num_entries, 989 const struct stepping_info *si, 990 u8 package_ver) 991 { 992 struct intel_display *display = dmc->display; 993 enum intel_dmc_id dmc_id; 994 unsigned int i; 995 996 for (i = 0; i < num_entries; i++) { 997 dmc_id = package_ver <= 1 ? DMC_FW_MAIN : fw_info[i].dmc_id; 998 999 if (!is_valid_dmc_id(dmc_id)) { 1000 drm_dbg(display->drm, "Unsupported firmware id: %u\n", dmc_id); 1001 continue; 1002 } 1003 1004 /* More specific versions come first, so we don't even have to 1005 * check for the stepping since we already found a previous FW 1006 * for this id. 1007 */ 1008 if (dmc->dmc_info[dmc_id].present) 1009 continue; 1010 1011 if (fw_info_matches_stepping(&fw_info[i], si)) { 1012 dmc->dmc_info[dmc_id].present = true; 1013 dmc->dmc_info[dmc_id].dmc_offset = fw_info[i].offset; 1014 } 1015 } 1016 } 1017 1018 static bool dmc_mmio_addr_sanity_check(struct intel_dmc *dmc, 1019 const u32 *mmioaddr, u32 mmio_count, 1020 int header_ver, enum intel_dmc_id dmc_id) 1021 { 1022 struct intel_display *display = dmc->display; 1023 u32 start_range, end_range; 1024 int i; 1025 1026 if (header_ver == 1) { 1027 start_range = DMC_MMIO_START_RANGE; 1028 end_range = DMC_MMIO_END_RANGE; 1029 } else if (dmc_id == DMC_FW_MAIN) { 1030 start_range = TGL_MAIN_MMIO_START; 1031 end_range = TGL_MAIN_MMIO_END; 1032 } else if (DISPLAY_VER(display) >= 13) { 1033 start_range = ADLP_PIPE_MMIO_START; 1034 end_range = ADLP_PIPE_MMIO_END; 1035 } else if (DISPLAY_VER(display) >= 12) { 1036 start_range = TGL_PIPE_MMIO_START(dmc_id); 1037 end_range = TGL_PIPE_MMIO_END(dmc_id); 1038 } else { 1039 drm_warn(display->drm, "Unknown mmio range for sanity check"); 1040 return false; 1041 } 1042 1043 for (i = 0; i < mmio_count; i++) { 1044 if (mmioaddr[i] < start_range || mmioaddr[i] > end_range) 1045 return false; 1046 } 1047 1048 return true; 1049 } 1050 1051 static u32 parse_dmc_fw_header(struct intel_dmc *dmc, 1052 const struct intel_dmc_header_base *dmc_header, 1053 size_t rem_size, enum intel_dmc_id dmc_id) 1054 { 1055 struct intel_display *display = dmc->display; 1056 struct dmc_fw_info *dmc_info = &dmc->dmc_info[dmc_id]; 1057 unsigned int header_len_bytes, dmc_header_size, payload_size, i; 1058 const u32 *mmioaddr, *mmiodata; 1059 u32 mmio_count, mmio_count_max, start_mmioaddr; 1060 u8 *payload; 1061 1062 BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT || 1063 ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V1_MAX_MMIO_COUNT); 1064 1065 /* 1066 * Check if we can access common fields, we will checkc again below 1067 * after we have read the version 1068 */ 1069 if (rem_size < sizeof(struct intel_dmc_header_base)) 1070 goto error_truncated; 1071 1072 /* Cope with small differences between v1 and v3 */ 1073 if (dmc_header->header_ver == 3) { 1074 const struct intel_dmc_header_v3 *v3 = 1075 (const struct intel_dmc_header_v3 *)dmc_header; 1076 1077 if (rem_size < sizeof(struct intel_dmc_header_v3)) 1078 goto error_truncated; 1079 1080 mmioaddr = v3->mmioaddr; 1081 mmiodata = v3->mmiodata; 1082 mmio_count = v3->mmio_count; 1083 mmio_count_max = DMC_V3_MAX_MMIO_COUNT; 1084 /* header_len is in dwords */ 1085 header_len_bytes = dmc_header->header_len * 4; 1086 start_mmioaddr = v3->start_mmioaddr; 1087 dmc_header_size = sizeof(*v3); 1088 } else if (dmc_header->header_ver == 1) { 1089 const struct intel_dmc_header_v1 *v1 = 1090 (const struct intel_dmc_header_v1 *)dmc_header; 1091 1092 if (rem_size < sizeof(struct intel_dmc_header_v1)) 1093 goto error_truncated; 1094 1095 mmioaddr = v1->mmioaddr; 1096 mmiodata = v1->mmiodata; 1097 mmio_count = v1->mmio_count; 1098 mmio_count_max = DMC_V1_MAX_MMIO_COUNT; 1099 header_len_bytes = dmc_header->header_len; 1100 start_mmioaddr = DMC_V1_MMIO_START_RANGE; 1101 dmc_header_size = sizeof(*v1); 1102 } else { 1103 drm_err(display->drm, "Unknown DMC fw header version: %u\n", 1104 dmc_header->header_ver); 1105 return 0; 1106 } 1107 1108 if (header_len_bytes != dmc_header_size) { 1109 drm_err(display->drm, "DMC firmware has wrong dmc header length " 1110 "(%u bytes)\n", header_len_bytes); 1111 return 0; 1112 } 1113 1114 /* Cache the dmc header info. */ 1115 if (mmio_count > mmio_count_max) { 1116 drm_err(display->drm, "DMC firmware has wrong mmio count %u\n", mmio_count); 1117 return 0; 1118 } 1119 1120 if (!dmc_mmio_addr_sanity_check(dmc, mmioaddr, mmio_count, 1121 dmc_header->header_ver, dmc_id)) { 1122 drm_err(display->drm, "DMC firmware has Wrong MMIO Addresses\n"); 1123 return 0; 1124 } 1125 1126 drm_dbg_kms(display->drm, "DMC %d:\n", dmc_id); 1127 for (i = 0; i < mmio_count; i++) { 1128 dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]); 1129 dmc_info->mmiodata[i] = mmiodata[i]; 1130 } 1131 1132 for (i = 0; i < mmio_count - 1; i++) { 1133 u32 orig_mmiodata[2] = { 1134 dmc_info->mmiodata[i], 1135 dmc_info->mmiodata[i+1], 1136 }; 1137 1138 if (!fixup_dmc_evt(display, dmc_id, 1139 dmc_info->mmioaddr[i], &dmc_info->mmiodata[i], 1140 dmc_info->mmioaddr[i+1], &dmc_info->mmiodata[i+1])) 1141 continue; 1142 1143 drm_dbg_kms(display->drm, 1144 " mmio[%d]: 0x%x = 0x%x->0x%x (EVT_CTL)\n", 1145 i, i915_mmio_reg_offset(dmc_info->mmioaddr[i]), 1146 orig_mmiodata[0], dmc_info->mmiodata[i]); 1147 drm_dbg_kms(display->drm, 1148 " mmio[%d]: 0x%x = 0x%x->0x%x (EVT_HTP)\n", 1149 i+1, i915_mmio_reg_offset(dmc_info->mmioaddr[i+1]), 1150 orig_mmiodata[1], dmc_info->mmiodata[i+1]); 1151 } 1152 1153 for (i = 0; i < mmio_count; i++) { 1154 drm_dbg_kms(display->drm, " mmio[%d]: 0x%x = 0x%x%s%s\n", 1155 i, i915_mmio_reg_offset(dmc_info->mmioaddr[i]), dmc_info->mmiodata[i], 1156 is_dmc_evt_ctl_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_CTL)" : 1157 is_dmc_evt_htp_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_HTP)" : "", 1158 disable_dmc_evt(display, dmc_id, dmc_info->mmioaddr[i], 1159 dmc_info->mmiodata[i]) ? " (disabling)" : ""); 1160 } 1161 dmc_info->mmio_count = mmio_count; 1162 dmc_info->start_mmioaddr = start_mmioaddr; 1163 1164 rem_size -= header_len_bytes; 1165 1166 /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */ 1167 payload_size = dmc_header->fw_size * 4; 1168 if (rem_size < payload_size) 1169 goto error_truncated; 1170 1171 if (payload_size > dmc->max_fw_size) { 1172 drm_err(display->drm, "DMC FW too big (%u bytes)\n", payload_size); 1173 return 0; 1174 } 1175 dmc_info->dmc_fw_size = dmc_header->fw_size; 1176 1177 dmc_info->payload = kmalloc(payload_size, GFP_KERNEL); 1178 if (!dmc_info->payload) 1179 return 0; 1180 1181 payload = (u8 *)(dmc_header) + header_len_bytes; 1182 memcpy(dmc_info->payload, payload, payload_size); 1183 1184 return header_len_bytes + payload_size; 1185 1186 error_truncated: 1187 drm_err(display->drm, "Truncated DMC firmware, refusing.\n"); 1188 return 0; 1189 } 1190 1191 static u32 1192 parse_dmc_fw_package(struct intel_dmc *dmc, 1193 const struct intel_package_header *package_header, 1194 const struct stepping_info *si, 1195 size_t rem_size) 1196 { 1197 struct intel_display *display = dmc->display; 1198 u32 package_size = sizeof(struct intel_package_header); 1199 u32 num_entries, max_entries; 1200 const struct intel_fw_info *fw_info; 1201 1202 if (rem_size < package_size) 1203 goto error_truncated; 1204 1205 if (package_header->header_ver == 1) { 1206 max_entries = PACKAGE_MAX_FW_INFO_ENTRIES; 1207 } else if (package_header->header_ver == 2) { 1208 max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES; 1209 } else { 1210 drm_err(display->drm, "DMC firmware has unknown header version %u\n", 1211 package_header->header_ver); 1212 return 0; 1213 } 1214 1215 /* 1216 * We should always have space for max_entries, 1217 * even if not all are used 1218 */ 1219 package_size += max_entries * sizeof(struct intel_fw_info); 1220 if (rem_size < package_size) 1221 goto error_truncated; 1222 1223 if (package_header->header_len * 4 != package_size) { 1224 drm_err(display->drm, "DMC firmware has wrong package header length " 1225 "(%u bytes)\n", package_size); 1226 return 0; 1227 } 1228 1229 num_entries = package_header->num_entries; 1230 if (WARN_ON(num_entries > max_entries)) 1231 num_entries = max_entries; 1232 1233 fw_info = (const struct intel_fw_info *) 1234 ((u8 *)package_header + sizeof(*package_header)); 1235 dmc_set_fw_offset(dmc, fw_info, num_entries, si, 1236 package_header->header_ver); 1237 1238 /* dmc_offset is in dwords */ 1239 return package_size; 1240 1241 error_truncated: 1242 drm_err(display->drm, "Truncated DMC firmware, refusing.\n"); 1243 return 0; 1244 } 1245 1246 /* Return number of bytes parsed or 0 on error */ 1247 static u32 parse_dmc_fw_css(struct intel_dmc *dmc, 1248 struct intel_css_header *css_header, 1249 size_t rem_size) 1250 { 1251 struct intel_display *display = dmc->display; 1252 1253 if (rem_size < sizeof(struct intel_css_header)) { 1254 drm_err(display->drm, "Truncated DMC firmware, refusing.\n"); 1255 return 0; 1256 } 1257 1258 if (sizeof(struct intel_css_header) != 1259 (css_header->header_len * 4)) { 1260 drm_err(display->drm, "DMC firmware has wrong CSS header length " 1261 "(%u bytes)\n", 1262 (css_header->header_len * 4)); 1263 return 0; 1264 } 1265 1266 dmc->version = css_header->version; 1267 1268 return sizeof(struct intel_css_header); 1269 } 1270 1271 static int parse_dmc_fw(struct intel_dmc *dmc, const struct firmware *fw) 1272 { 1273 struct intel_display *display = dmc->display; 1274 struct intel_css_header *css_header; 1275 struct intel_package_header *package_header; 1276 struct intel_dmc_header_base *dmc_header; 1277 struct stepping_info display_info = { '*', '*'}; 1278 const struct stepping_info *si = intel_get_stepping_info(display, &display_info); 1279 enum intel_dmc_id dmc_id; 1280 u32 readcount = 0; 1281 u32 r, offset; 1282 1283 if (!fw) 1284 return -EINVAL; 1285 1286 /* Extract CSS Header information */ 1287 css_header = (struct intel_css_header *)fw->data; 1288 r = parse_dmc_fw_css(dmc, css_header, fw->size); 1289 if (!r) 1290 return -EINVAL; 1291 1292 readcount += r; 1293 1294 /* Extract Package Header information */ 1295 package_header = (struct intel_package_header *)&fw->data[readcount]; 1296 r = parse_dmc_fw_package(dmc, package_header, si, fw->size - readcount); 1297 if (!r) 1298 return -EINVAL; 1299 1300 readcount += r; 1301 1302 for_each_dmc_id(dmc_id) { 1303 if (!dmc->dmc_info[dmc_id].present) 1304 continue; 1305 1306 offset = readcount + dmc->dmc_info[dmc_id].dmc_offset * 4; 1307 if (offset > fw->size) { 1308 drm_err(display->drm, "Reading beyond the fw_size\n"); 1309 continue; 1310 } 1311 1312 dmc_header = (struct intel_dmc_header_base *)&fw->data[offset]; 1313 parse_dmc_fw_header(dmc, dmc_header, fw->size - offset, dmc_id); 1314 } 1315 1316 if (!intel_dmc_has_payload(display)) { 1317 drm_err(display->drm, "DMC firmware main program not found\n"); 1318 return -ENOENT; 1319 } 1320 1321 return 0; 1322 } 1323 1324 static void intel_dmc_runtime_pm_get(struct intel_display *display) 1325 { 1326 drm_WARN_ON(display->drm, display->dmc.wakeref); 1327 display->dmc.wakeref = intel_display_power_get(display, POWER_DOMAIN_INIT); 1328 } 1329 1330 static void intel_dmc_runtime_pm_put(struct intel_display *display) 1331 { 1332 struct ref_tracker *wakeref __maybe_unused = 1333 fetch_and_zero(&display->dmc.wakeref); 1334 1335 intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref); 1336 } 1337 1338 static const char *dmc_fallback_path(struct intel_display *display) 1339 { 1340 if (display->platform.alderlake_p) 1341 return ADLP_DMC_FALLBACK_PATH; 1342 1343 return NULL; 1344 } 1345 1346 static void dmc_load_work_fn(struct work_struct *work) 1347 { 1348 struct intel_dmc *dmc = container_of(work, typeof(*dmc), work); 1349 struct intel_display *display = dmc->display; 1350 const struct firmware *fw = NULL; 1351 const char *fallback_path; 1352 int err; 1353 1354 err = request_firmware(&fw, dmc->fw_path, display->drm->dev); 1355 1356 if (err == -ENOENT && !dmc_firmware_param(display)) { 1357 fallback_path = dmc_fallback_path(display); 1358 if (fallback_path) { 1359 drm_dbg_kms(display->drm, "%s not found, falling back to %s\n", 1360 dmc->fw_path, fallback_path); 1361 err = request_firmware(&fw, fallback_path, display->drm->dev); 1362 if (err == 0) 1363 dmc->fw_path = fallback_path; 1364 } 1365 } 1366 1367 if (err) { 1368 drm_notice(display->drm, 1369 "Failed to load DMC firmware %s (%pe). Disabling runtime power management.\n", 1370 dmc->fw_path, ERR_PTR(err)); 1371 drm_notice(display->drm, "DMC firmware homepage: %s", 1372 INTEL_DMC_FIRMWARE_URL); 1373 return; 1374 } 1375 1376 err = parse_dmc_fw(dmc, fw); 1377 if (err) { 1378 drm_notice(display->drm, 1379 "Failed to parse DMC firmware %s (%pe). Disabling runtime power management.\n", 1380 dmc->fw_path, ERR_PTR(err)); 1381 goto out; 1382 } 1383 1384 intel_dmc_load_program(display); 1385 intel_dmc_runtime_pm_put(display); 1386 1387 drm_info(display->drm, "Finished loading DMC firmware %s (v%u.%u)\n", 1388 dmc->fw_path, DMC_VERSION_MAJOR(dmc->version), 1389 DMC_VERSION_MINOR(dmc->version)); 1390 1391 out: 1392 release_firmware(fw); 1393 } 1394 1395 /** 1396 * intel_dmc_init() - initialize the firmware loading. 1397 * @display: display instance 1398 * 1399 * This function is called at the time of loading the display driver to read 1400 * firmware from a .bin file and copied into a internal memory. 1401 */ 1402 void intel_dmc_init(struct intel_display *display) 1403 { 1404 struct intel_dmc *dmc; 1405 1406 if (!HAS_DMC(display)) 1407 return; 1408 1409 /* 1410 * Obtain a runtime pm reference, until DMC is loaded, to avoid entering 1411 * runtime-suspend. 1412 * 1413 * On error, we return with the rpm wakeref held to prevent runtime 1414 * suspend as runtime suspend *requires* a working DMC for whatever 1415 * reason. 1416 */ 1417 intel_dmc_runtime_pm_get(display); 1418 1419 dmc = kzalloc_obj(*dmc); 1420 if (!dmc) 1421 return; 1422 1423 dmc->display = display; 1424 1425 INIT_WORK(&dmc->work, dmc_load_work_fn); 1426 1427 dmc->fw_path = dmc_firmware_default(display, &dmc->max_fw_size); 1428 1429 if (dmc_firmware_param_disabled(display)) { 1430 drm_info(display->drm, "Disabling DMC firmware and runtime PM\n"); 1431 goto out; 1432 } 1433 1434 if (dmc_firmware_param(display)) 1435 dmc->fw_path = dmc_firmware_param(display); 1436 1437 if (!dmc->fw_path) { 1438 drm_dbg_kms(display->drm, 1439 "No known DMC firmware for platform, disabling runtime PM\n"); 1440 goto out; 1441 } 1442 1443 display->dmc.dmc = dmc; 1444 1445 drm_dbg_kms(display->drm, "Loading %s\n", dmc->fw_path); 1446 queue_work(display->wq.unordered, &dmc->work); 1447 1448 return; 1449 1450 out: 1451 kfree(dmc); 1452 } 1453 1454 /** 1455 * intel_dmc_suspend() - prepare DMC firmware before system suspend 1456 * @display: display instance 1457 * 1458 * Prepare the DMC firmware before entering system suspend. This includes 1459 * flushing pending work items and releasing any resources acquired during 1460 * init. 1461 */ 1462 void intel_dmc_suspend(struct intel_display *display) 1463 { 1464 struct intel_dmc *dmc = display_to_dmc(display); 1465 1466 if (!HAS_DMC(display)) 1467 return; 1468 1469 if (dmc) 1470 flush_work(&dmc->work); 1471 1472 /* Drop the reference held in case DMC isn't loaded. */ 1473 if (!intel_dmc_has_payload(display)) 1474 intel_dmc_runtime_pm_put(display); 1475 } 1476 1477 void intel_dmc_wait_fw_load(struct intel_display *display) 1478 { 1479 struct intel_dmc *dmc = display_to_dmc(display); 1480 1481 if (!HAS_DMC(display)) 1482 return; 1483 1484 if (dmc) 1485 flush_work(&dmc->work); 1486 } 1487 1488 /** 1489 * intel_dmc_resume() - init DMC firmware during system resume 1490 * @display: display instance 1491 * 1492 * Reinitialize the DMC firmware during system resume, reacquiring any 1493 * resources released in intel_dmc_suspend(). 1494 */ 1495 void intel_dmc_resume(struct intel_display *display) 1496 { 1497 if (!HAS_DMC(display)) 1498 return; 1499 1500 /* 1501 * Reacquire the reference to keep RPM disabled in case DMC isn't 1502 * loaded. 1503 */ 1504 if (!intel_dmc_has_payload(display)) 1505 intel_dmc_runtime_pm_get(display); 1506 } 1507 1508 /** 1509 * intel_dmc_fini() - unload the DMC firmware. 1510 * @display: display instance 1511 * 1512 * Firmmware unloading includes freeing the internal memory and reset the 1513 * firmware loading status. 1514 */ 1515 void intel_dmc_fini(struct intel_display *display) 1516 { 1517 struct intel_dmc *dmc = display_to_dmc(display); 1518 enum intel_dmc_id dmc_id; 1519 1520 if (!HAS_DMC(display)) 1521 return; 1522 1523 intel_dmc_suspend(display); 1524 drm_WARN_ON(display->drm, display->dmc.wakeref); 1525 1526 if (dmc) { 1527 for_each_dmc_id(dmc_id) 1528 kfree(dmc->dmc_info[dmc_id].payload); 1529 1530 kfree(dmc); 1531 display->dmc.dmc = NULL; 1532 } 1533 } 1534 1535 struct intel_dmc_snapshot { 1536 bool initialized; 1537 bool loaded; 1538 u32 version; 1539 }; 1540 1541 struct intel_dmc_snapshot *intel_dmc_snapshot_capture(struct intel_display *display) 1542 { 1543 struct intel_dmc *dmc = display_to_dmc(display); 1544 struct intel_dmc_snapshot *snapshot; 1545 1546 if (!HAS_DMC(display)) 1547 return NULL; 1548 1549 snapshot = kzalloc_obj(*snapshot, GFP_ATOMIC); 1550 if (!snapshot) 1551 return NULL; 1552 1553 snapshot->initialized = dmc; 1554 snapshot->loaded = intel_dmc_has_payload(display); 1555 if (dmc) 1556 snapshot->version = dmc->version; 1557 1558 return snapshot; 1559 } 1560 1561 void intel_dmc_snapshot_print(const struct intel_dmc_snapshot *snapshot, struct drm_printer *p) 1562 { 1563 if (!snapshot) 1564 return; 1565 1566 drm_printf(p, "DMC initialized: %s\n", str_yes_no(snapshot->initialized)); 1567 drm_printf(p, "DMC loaded: %s\n", str_yes_no(snapshot->loaded)); 1568 if (snapshot->initialized) 1569 drm_printf(p, "DMC fw version: %d.%d\n", 1570 DMC_VERSION_MAJOR(snapshot->version), 1571 DMC_VERSION_MINOR(snapshot->version)); 1572 } 1573 1574 void intel_dmc_update_dc6_allowed_count(struct intel_display *display, 1575 bool start_tracking) 1576 { 1577 struct intel_dmc *dmc = display_to_dmc(display); 1578 u32 dc5_cur_count; 1579 1580 if (DISPLAY_VER(dmc->display) < 14) 1581 return; 1582 1583 dc5_cur_count = intel_de_read(dmc->display, DG1_DMC_DEBUG_DC5_COUNT); 1584 1585 if (!start_tracking) 1586 dmc->dc6_allowed.count += dc5_cur_count - dmc->dc6_allowed.dc5_start; 1587 1588 dmc->dc6_allowed.dc5_start = dc5_cur_count; 1589 } 1590 1591 static bool intel_dmc_get_dc6_allowed_count(struct intel_display *display, u32 *count) 1592 { 1593 struct i915_power_domains *power_domains = &display->power.domains; 1594 struct intel_dmc *dmc = display_to_dmc(display); 1595 bool dc6_enabled; 1596 1597 if (DISPLAY_VER(display) < 14) 1598 return false; 1599 1600 mutex_lock(&power_domains->lock); 1601 dc6_enabled = power_domains->dc_state & DC_STATE_EN_UPTO_DC6; 1602 if (dc6_enabled) 1603 intel_dmc_update_dc6_allowed_count(display, false); 1604 1605 *count = dmc->dc6_allowed.count; 1606 mutex_unlock(&power_domains->lock); 1607 1608 return true; 1609 } 1610 1611 static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused) 1612 { 1613 struct intel_display *display = m->private; 1614 struct intel_dmc *dmc = display_to_dmc(display); 1615 struct ref_tracker *wakeref; 1616 i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG; 1617 u32 dc6_allowed_count; 1618 1619 if (!HAS_DMC(display)) 1620 return -ENODEV; 1621 1622 wakeref = intel_display_rpm_get(display); 1623 1624 seq_printf(m, "DMC initialized: %s\n", str_yes_no(dmc)); 1625 seq_printf(m, "fw loaded: %s\n", 1626 str_yes_no(intel_dmc_has_payload(display))); 1627 seq_printf(m, "path: %s\n", dmc ? dmc->fw_path : "N/A"); 1628 seq_printf(m, "Pipe A fw needed: %s\n", 1629 str_yes_no(DISPLAY_VER(display) >= 12)); 1630 seq_printf(m, "Pipe A fw loaded: %s\n", 1631 str_yes_no(has_dmc_id_fw(display, DMC_FW_PIPEA))); 1632 seq_printf(m, "Pipe B fw needed: %s\n", 1633 str_yes_no(display->platform.alderlake_p || 1634 DISPLAY_VER(display) >= 14)); 1635 seq_printf(m, "Pipe B fw loaded: %s\n", 1636 str_yes_no(has_dmc_id_fw(display, DMC_FW_PIPEB))); 1637 1638 if (!intel_dmc_has_payload(display)) 1639 goto out; 1640 1641 seq_printf(m, "version: %d.%d\n", DMC_VERSION_MAJOR(dmc->version), 1642 DMC_VERSION_MINOR(dmc->version)); 1643 1644 if (DISPLAY_VER(display) >= 12) { 1645 i915_reg_t dc3co_reg; 1646 1647 if (display->platform.dgfx || DISPLAY_VER(display) >= 14) { 1648 dc3co_reg = DG1_DMC_DEBUG3; 1649 dc5_reg = DG1_DMC_DEBUG_DC5_COUNT; 1650 } else { 1651 dc3co_reg = TGL_DMC_DEBUG3; 1652 dc5_reg = TGL_DMC_DEBUG_DC5_COUNT; 1653 dc6_reg = TGL_DMC_DEBUG_DC6_COUNT; 1654 } 1655 1656 seq_printf(m, "DC3CO count: %d\n", 1657 intel_de_read(display, dc3co_reg)); 1658 } else { 1659 dc5_reg = display->platform.broxton ? BXT_DMC_DC3_DC5_COUNT : 1660 SKL_DMC_DC3_DC5_COUNT; 1661 if (!display->platform.geminilake && !display->platform.broxton) 1662 dc6_reg = SKL_DMC_DC5_DC6_COUNT; 1663 } 1664 1665 seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(display, dc5_reg)); 1666 1667 if (intel_dmc_get_dc6_allowed_count(display, &dc6_allowed_count)) 1668 seq_printf(m, "DC5 -> DC6 allowed count: %d\n", 1669 dc6_allowed_count); 1670 else if (i915_mmio_reg_valid(dc6_reg)) 1671 seq_printf(m, "DC5 -> DC6 count: %d\n", 1672 intel_de_read(display, dc6_reg)); 1673 1674 seq_printf(m, "program base: 0x%08x\n", 1675 intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0))); 1676 1677 out: 1678 seq_printf(m, "ssp base: 0x%08x\n", 1679 intel_de_read(display, DMC_SSP_BASE)); 1680 seq_printf(m, "htp: 0x%08x\n", intel_de_read(display, DMC_HTP_SKL)); 1681 1682 intel_display_rpm_put(display, wakeref); 1683 1684 return 0; 1685 } 1686 1687 DEFINE_SHOW_ATTRIBUTE(intel_dmc_debugfs_status); 1688 1689 void intel_dmc_debugfs_register(struct intel_display *display) 1690 { 1691 debugfs_create_file("i915_dmc_info", 0444, display->drm->debugfs_root, 1692 display, &intel_dmc_debugfs_status_fops); 1693 } 1694 1695 void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe) 1696 { 1697 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); 1698 u32 tmp = 0, int_vector; 1699 1700 if (DISPLAY_VER(display) >= 20) { 1701 tmp = intel_de_read(display, PIPEDMC_INTERRUPT(pipe)); 1702 intel_de_write(display, PIPEDMC_INTERRUPT(pipe), tmp); 1703 1704 if (tmp & PIPEDMC_FLIPQ_PROG_DONE) { 1705 spin_lock(&display->drm->event_lock); 1706 1707 if (crtc->flipq_event) { 1708 /* 1709 * Update vblank counter/timestamp in case it 1710 * hasn't been done yet for this frame. 1711 */ 1712 drm_crtc_accurate_vblank_count(&crtc->base); 1713 1714 drm_crtc_send_vblank_event(&crtc->base, crtc->flipq_event); 1715 crtc->flipq_event = NULL; 1716 } 1717 1718 spin_unlock(&display->drm->event_lock); 1719 } 1720 1721 if (tmp & PIPEDMC_ATS_FAULT) 1722 drm_err_ratelimited(display->drm, "[CRTC:%d:%s] PIPEDMC ATS fault\n", 1723 crtc->base.base.id, crtc->base.name); 1724 if (tmp & PIPEDMC_GTT_FAULT) 1725 drm_err_ratelimited(display->drm, "[CRTC:%d:%s] PIPEDMC GTT fault\n", 1726 crtc->base.base.id, crtc->base.name); 1727 if (tmp & PIPEDMC_ERROR) 1728 drm_err(display->drm, "[CRTC:%d:%s] PIPEDMC error\n", 1729 crtc->base.base.id, crtc->base.name); 1730 } 1731 1732 int_vector = intel_de_read(display, PIPEDMC_STATUS(pipe)) & PIPEDMC_INT_VECTOR_MASK; 1733 if (tmp == 0 && int_vector != 0) 1734 drm_err(display->drm, "[CRTC:%d:%s] PIPEDMC interrupt vector 0x%x\n", 1735 crtc->base.base.id, crtc->base.name, int_vector); 1736 } 1737 1738 void intel_pipedmc_enable_event(struct intel_crtc *crtc, 1739 enum pipedmc_event_id event) 1740 { 1741 struct intel_display *display = to_intel_display(crtc); 1742 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(crtc->pipe); 1743 1744 dmc_configure_event(display, dmc_id, event, true); 1745 } 1746 1747 void intel_pipedmc_disable_event(struct intel_crtc *crtc, 1748 enum pipedmc_event_id event) 1749 { 1750 struct intel_display *display = to_intel_display(crtc); 1751 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(crtc->pipe); 1752 1753 dmc_configure_event(display, dmc_id, event, false); 1754 } 1755 1756 u32 intel_pipedmc_start_mmioaddr(struct intel_crtc *crtc) 1757 { 1758 struct intel_display *display = to_intel_display(crtc); 1759 struct intel_dmc *dmc = display_to_dmc(display); 1760 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(crtc->pipe); 1761 1762 return dmc ? dmc->dmc_info[dmc_id].start_mmioaddr : 0; 1763 } 1764 1765 void intel_pipedmc_dcb_enable(struct intel_dsb *dsb, struct intel_crtc *crtc) 1766 { 1767 struct intel_display *display = to_intel_display(crtc); 1768 enum pipe pipe = crtc->pipe; 1769 1770 intel_de_write_dsb(display, dsb, PIPEDMC_DCB_CTL(pipe), 1771 PIPEDMC_ADAPTIVE_DCB_ENABLE); 1772 } 1773 1774 void intel_pipedmc_dcb_disable(struct intel_dsb *dsb, struct intel_crtc *crtc) 1775 { 1776 struct intel_display *display = to_intel_display(crtc); 1777 enum pipe pipe = crtc->pipe; 1778 1779 intel_de_write_dsb(display, dsb, PIPEDMC_DCB_CTL(pipe), 0); 1780 } 1781