1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 #include "i915_irq.h" 8 #include "i915_reg.h" 9 #include "intel_backlight_regs.h" 10 #include "intel_combo_phy.h" 11 #include "intel_combo_phy_regs.h" 12 #include "intel_crt.h" 13 #include "intel_de.h" 14 #include "intel_display_irq.h" 15 #include "intel_display_power_well.h" 16 #include "intel_display_regs.h" 17 #include "intel_display_rpm.h" 18 #include "intel_display_types.h" 19 #include "intel_dkl_phy.h" 20 #include "intel_dkl_phy_regs.h" 21 #include "intel_dmc.h" 22 #include "intel_dmc_wl.h" 23 #include "intel_dp_aux_regs.h" 24 #include "intel_dpio_phy.h" 25 #include "intel_dpll.h" 26 #include "intel_hotplug.h" 27 #include "intel_pcode.h" 28 #include "intel_pps.h" 29 #include "intel_psr.h" 30 #include "intel_tc.h" 31 #include "intel_vga.h" 32 #include "skl_watermark.h" 33 #include "vlv_dpio_phy_regs.h" 34 #include "vlv_iosf_sb_reg.h" 35 #include "vlv_sideband.h" 36 37 struct i915_power_well_regs { 38 i915_reg_t bios; 39 i915_reg_t driver; 40 i915_reg_t kvmr; 41 i915_reg_t debug; 42 }; 43 44 struct i915_power_well_ops { 45 const struct i915_power_well_regs *regs; 46 /* 47 * Synchronize the well's hw state to match the current sw state, for 48 * example enable/disable it based on the current refcount. Called 49 * during driver init and resume time, possibly after first calling 50 * the enable/disable handlers. 51 */ 52 void (*sync_hw)(struct intel_display *display, 53 struct i915_power_well *power_well); 54 /* 55 * Enable the well and resources that depend on it (for example 56 * interrupts located on the well). Called after the 0->1 refcount 57 * transition. 58 */ 59 void (*enable)(struct intel_display *display, 60 struct i915_power_well *power_well); 61 /* 62 * Disable the well and resources that depend on it. Called after 63 * the 1->0 refcount transition. 64 */ 65 void (*disable)(struct intel_display *display, 66 struct i915_power_well *power_well); 67 /* Returns the hw enabled state. */ 68 bool (*is_enabled)(struct intel_display *display, 69 struct i915_power_well *power_well); 70 }; 71 72 static const struct i915_power_well_instance * 73 i915_power_well_instance(const struct i915_power_well *power_well) 74 { 75 return &power_well->desc->instances->list[power_well->instance_idx]; 76 } 77 78 struct i915_power_well * 79 lookup_power_well(struct intel_display *display, 80 enum i915_power_well_id power_well_id) 81 { 82 struct i915_power_well *power_well; 83 84 for_each_power_well(display, power_well) 85 if (i915_power_well_instance(power_well)->id == power_well_id) 86 return power_well; 87 88 /* 89 * It's not feasible to add error checking code to the callers since 90 * this condition really shouldn't happen and it doesn't even make sense 91 * to abort things like display initialization sequences. Just return 92 * the first power well and hope the WARN gets reported so we can fix 93 * our driver. 94 */ 95 drm_WARN(display->drm, 1, 96 "Power well %d not defined for this platform\n", 97 power_well_id); 98 return &display->power.domains.power_wells[0]; 99 } 100 101 void intel_power_well_enable(struct intel_display *display, 102 struct i915_power_well *power_well) 103 { 104 drm_dbg_kms(display->drm, "enabling %s\n", intel_power_well_name(power_well)); 105 power_well->desc->ops->enable(display, power_well); 106 power_well->hw_enabled = true; 107 } 108 109 void intel_power_well_disable(struct intel_display *display, 110 struct i915_power_well *power_well) 111 { 112 drm_dbg_kms(display->drm, "disabling %s\n", intel_power_well_name(power_well)); 113 power_well->hw_enabled = false; 114 power_well->desc->ops->disable(display, power_well); 115 } 116 117 void intel_power_well_sync_hw(struct intel_display *display, 118 struct i915_power_well *power_well) 119 { 120 power_well->desc->ops->sync_hw(display, power_well); 121 power_well->hw_enabled = power_well->desc->ops->is_enabled(display, power_well); 122 } 123 124 void intel_power_well_get(struct intel_display *display, 125 struct i915_power_well *power_well) 126 { 127 if (!power_well->count++) 128 intel_power_well_enable(display, power_well); 129 } 130 131 void intel_power_well_put(struct intel_display *display, 132 struct i915_power_well *power_well) 133 { 134 drm_WARN(display->drm, !power_well->count, 135 "Use count on power well %s is already zero", 136 i915_power_well_instance(power_well)->name); 137 138 if (!--power_well->count) 139 intel_power_well_disable(display, power_well); 140 } 141 142 bool intel_power_well_is_enabled(struct intel_display *display, 143 struct i915_power_well *power_well) 144 { 145 return power_well->desc->ops->is_enabled(display, power_well); 146 } 147 148 bool intel_power_well_is_enabled_cached(struct i915_power_well *power_well) 149 { 150 return power_well->hw_enabled; 151 } 152 153 bool intel_display_power_well_is_enabled(struct intel_display *display, 154 enum i915_power_well_id power_well_id) 155 { 156 struct i915_power_well *power_well; 157 158 power_well = lookup_power_well(display, power_well_id); 159 160 return intel_power_well_is_enabled(display, power_well); 161 } 162 163 bool intel_power_well_is_always_on(struct i915_power_well *power_well) 164 { 165 return power_well->desc->always_on; 166 } 167 168 const char *intel_power_well_name(struct i915_power_well *power_well) 169 { 170 return i915_power_well_instance(power_well)->name; 171 } 172 173 struct intel_power_domain_mask *intel_power_well_domains(struct i915_power_well *power_well) 174 { 175 return &power_well->domains; 176 } 177 178 int intel_power_well_refcount(struct i915_power_well *power_well) 179 { 180 return power_well->count; 181 } 182 183 /* 184 * Starting with Haswell, we have a "Power Down Well" that can be turned off 185 * when not needed anymore. We have 4 registers that can request the power well 186 * to be enabled, and it will only be disabled if none of the registers is 187 * requesting it to be enabled. 188 */ 189 static void hsw_power_well_post_enable(struct intel_display *display, 190 u8 irq_pipe_mask, bool has_vga) 191 { 192 if (has_vga) 193 intel_vga_reset_io_mem(display); 194 195 if (irq_pipe_mask) 196 gen8_irq_power_well_post_enable(display, irq_pipe_mask); 197 } 198 199 static void hsw_power_well_pre_disable(struct intel_display *display, 200 u8 irq_pipe_mask) 201 { 202 if (irq_pipe_mask) 203 gen8_irq_power_well_pre_disable(display, irq_pipe_mask); 204 } 205 206 #define ICL_AUX_PW_TO_PHY(pw_idx) \ 207 ((pw_idx) - ICL_PW_CTL_IDX_AUX_A + PHY_A) 208 209 #define ICL_AUX_PW_TO_CH(pw_idx) \ 210 ((pw_idx) - ICL_PW_CTL_IDX_AUX_A + AUX_CH_A) 211 212 #define ICL_TBT_AUX_PW_TO_CH(pw_idx) \ 213 ((pw_idx) - ICL_PW_CTL_IDX_AUX_TBT1 + AUX_CH_C) 214 215 static enum aux_ch icl_aux_pw_to_ch(const struct i915_power_well *power_well) 216 { 217 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 218 219 return power_well->desc->is_tc_tbt ? ICL_TBT_AUX_PW_TO_CH(pw_idx) : 220 ICL_AUX_PW_TO_CH(pw_idx); 221 } 222 223 static struct intel_digital_port * 224 aux_ch_to_digital_port(struct intel_display *display, 225 enum aux_ch aux_ch) 226 { 227 struct intel_encoder *encoder; 228 229 for_each_intel_encoder(display->drm, encoder) { 230 struct intel_digital_port *dig_port; 231 232 /* We'll check the MST primary port */ 233 if (encoder->type == INTEL_OUTPUT_DP_MST) 234 continue; 235 236 dig_port = enc_to_dig_port(encoder); 237 238 if (dig_port && dig_port->aux_ch == aux_ch) 239 return dig_port; 240 } 241 242 return NULL; 243 } 244 245 static enum phy icl_aux_pw_to_phy(struct intel_display *display, 246 const struct i915_power_well *power_well) 247 { 248 enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well); 249 struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch); 250 251 /* 252 * FIXME should we care about the (VBT defined) dig_port->aux_ch 253 * relationship or should this be purely defined by the hardware layout? 254 * Currently if the port doesn't appear in the VBT, or if it's declared 255 * as HDMI-only and routed to a combo PHY, the encoder either won't be 256 * present at all or it will not have an aux_ch assigned. 257 */ 258 return dig_port ? intel_encoder_to_phy(&dig_port->base) : PHY_NONE; 259 } 260 261 static void hsw_wait_for_power_well_enable(struct intel_display *display, 262 struct i915_power_well *power_well, 263 bool timeout_expected) 264 { 265 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 266 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 267 int timeout = power_well->desc->enable_timeout ? : 1; 268 269 /* 270 * For some power wells we're not supposed to watch the status bit for 271 * an ack, but rather just wait a fixed amount of time and then 272 * proceed. This is only used on DG2. 273 */ 274 if (display->platform.dg2 && power_well->desc->fixed_enable_delay) { 275 usleep_range(600, 1200); 276 return; 277 } 278 279 /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */ 280 if (intel_de_wait_for_set(display, regs->driver, 281 HSW_PWR_WELL_CTL_STATE(pw_idx), timeout)) { 282 drm_dbg_kms(display->drm, "%s power well enable timeout\n", 283 intel_power_well_name(power_well)); 284 285 drm_WARN_ON(display->drm, !timeout_expected); 286 287 } 288 } 289 290 static u32 hsw_power_well_requesters(struct intel_display *display, 291 const struct i915_power_well_regs *regs, 292 int pw_idx) 293 { 294 u32 req_mask = HSW_PWR_WELL_CTL_REQ(pw_idx); 295 u32 ret; 296 297 ret = intel_de_read(display, regs->bios) & req_mask ? 1 : 0; 298 ret |= intel_de_read(display, regs->driver) & req_mask ? 2 : 0; 299 if (regs->kvmr.reg) 300 ret |= intel_de_read(display, regs->kvmr) & req_mask ? 4 : 0; 301 ret |= intel_de_read(display, regs->debug) & req_mask ? 8 : 0; 302 303 return ret; 304 } 305 306 static void hsw_wait_for_power_well_disable(struct intel_display *display, 307 struct i915_power_well *power_well) 308 { 309 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 310 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 311 bool disabled; 312 u32 reqs; 313 314 /* 315 * Bspec doesn't require waiting for PWs to get disabled, but still do 316 * this for paranoia. The known cases where a PW will be forced on: 317 * - a KVMR request on any power well via the KVMR request register 318 * - a DMC request on PW1 and MISC_IO power wells via the BIOS and 319 * DEBUG request registers 320 * Skip the wait in case any of the request bits are set and print a 321 * diagnostic message. 322 */ 323 wait_for((disabled = !(intel_de_read(display, regs->driver) & 324 HSW_PWR_WELL_CTL_STATE(pw_idx))) || 325 (reqs = hsw_power_well_requesters(display, regs, pw_idx)), 1); 326 if (disabled) 327 return; 328 329 drm_dbg_kms(display->drm, 330 "%s forced on (bios:%d driver:%d kvmr:%d debug:%d)\n", 331 intel_power_well_name(power_well), 332 !!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8)); 333 } 334 335 static void gen9_wait_for_power_well_fuses(struct intel_display *display, 336 enum skl_power_gate pg) 337 { 338 /* Timeout 5us for PG#0, for other PGs 1us */ 339 drm_WARN_ON(display->drm, 340 intel_de_wait_for_set(display, SKL_FUSE_STATUS, 341 SKL_FUSE_PG_DIST_STATUS(pg), 1)); 342 } 343 344 static void hsw_power_well_enable(struct intel_display *display, 345 struct i915_power_well *power_well) 346 { 347 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 348 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 349 350 if (power_well->desc->has_fuses) { 351 enum skl_power_gate pg; 352 353 pg = DISPLAY_VER(display) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) : 354 SKL_PW_CTL_IDX_TO_PG(pw_idx); 355 356 /* Wa_16013190616:adlp */ 357 if (display->platform.alderlake_p && pg == SKL_PG1) 358 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 0, DISABLE_FLR_SRC); 359 360 /* 361 * For PW1 we have to wait both for the PW0/PG0 fuse state 362 * before enabling the power well and PW1/PG1's own fuse 363 * state after the enabling. For all other power wells with 364 * fuses we only have to wait for that PW/PG's fuse state 365 * after the enabling. 366 */ 367 if (pg == SKL_PG1) 368 gen9_wait_for_power_well_fuses(display, SKL_PG0); 369 } 370 371 intel_de_rmw(display, regs->driver, 0, HSW_PWR_WELL_CTL_REQ(pw_idx)); 372 373 hsw_wait_for_power_well_enable(display, power_well, false); 374 375 if (power_well->desc->has_fuses) { 376 enum skl_power_gate pg; 377 378 pg = DISPLAY_VER(display) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) : 379 SKL_PW_CTL_IDX_TO_PG(pw_idx); 380 gen9_wait_for_power_well_fuses(display, pg); 381 } 382 383 hsw_power_well_post_enable(display, 384 power_well->desc->irq_pipe_mask, 385 power_well->desc->has_vga); 386 } 387 388 static void hsw_power_well_disable(struct intel_display *display, 389 struct i915_power_well *power_well) 390 { 391 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 392 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 393 394 hsw_power_well_pre_disable(display, 395 power_well->desc->irq_pipe_mask); 396 397 intel_de_rmw(display, regs->driver, HSW_PWR_WELL_CTL_REQ(pw_idx), 0); 398 hsw_wait_for_power_well_disable(display, power_well); 399 } 400 401 static bool intel_aux_ch_is_edp(struct intel_display *display, enum aux_ch aux_ch) 402 { 403 struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch); 404 405 return dig_port && dig_port->base.type == INTEL_OUTPUT_EDP; 406 } 407 408 static void 409 icl_combo_phy_aux_power_well_enable(struct intel_display *display, 410 struct i915_power_well *power_well) 411 { 412 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 413 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 414 415 drm_WARN_ON(display->drm, !display->platform.icelake); 416 417 intel_de_rmw(display, regs->driver, 0, HSW_PWR_WELL_CTL_REQ(pw_idx)); 418 419 /* 420 * FIXME not sure if we should derive the PHY from the pw_idx, or 421 * from the VBT defined AUX_CH->DDI->PHY mapping. 422 */ 423 intel_de_rmw(display, ICL_PORT_CL_DW12(ICL_AUX_PW_TO_PHY(pw_idx)), 424 0, ICL_LANE_ENABLE_AUX); 425 426 hsw_wait_for_power_well_enable(display, power_well, false); 427 428 /* Display WA #1178: icl */ 429 if (pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B && 430 !intel_aux_ch_is_edp(display, ICL_AUX_PW_TO_CH(pw_idx))) 431 intel_de_rmw(display, ICL_PORT_TX_DW6_AUX(ICL_AUX_PW_TO_PHY(pw_idx)), 432 0, O_FUNC_OVRD_EN | O_LDO_BYPASS_CRI); 433 } 434 435 static void 436 icl_combo_phy_aux_power_well_disable(struct intel_display *display, 437 struct i915_power_well *power_well) 438 { 439 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 440 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 441 442 drm_WARN_ON(display->drm, !display->platform.icelake); 443 444 /* 445 * FIXME not sure if we should derive the PHY from the pw_idx, or 446 * from the VBT defined AUX_CH->DDI->PHY mapping. 447 */ 448 intel_de_rmw(display, ICL_PORT_CL_DW12(ICL_AUX_PW_TO_PHY(pw_idx)), 449 ICL_LANE_ENABLE_AUX, 0); 450 451 intel_de_rmw(display, regs->driver, HSW_PWR_WELL_CTL_REQ(pw_idx), 0); 452 453 hsw_wait_for_power_well_disable(display, power_well); 454 } 455 456 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 457 458 static void icl_tc_port_assert_ref_held(struct intel_display *display, 459 struct i915_power_well *power_well, 460 struct intel_digital_port *dig_port) 461 { 462 if (drm_WARN_ON(display->drm, !dig_port)) 463 return; 464 465 if (DISPLAY_VER(display) == 11 && intel_tc_cold_requires_aux_pw(dig_port)) 466 return; 467 468 drm_WARN_ON(display->drm, !intel_tc_port_ref_held(dig_port)); 469 } 470 471 #else 472 473 static void icl_tc_port_assert_ref_held(struct intel_display *display, 474 struct i915_power_well *power_well, 475 struct intel_digital_port *dig_port) 476 { 477 } 478 479 #endif 480 481 #define TGL_AUX_PW_TO_TC_PORT(pw_idx) ((pw_idx) - TGL_PW_CTL_IDX_AUX_TC1) 482 483 static void icl_tc_cold_exit(struct intel_display *display) 484 { 485 struct drm_i915_private *i915 = to_i915(display->drm); 486 int ret, tries = 0; 487 488 while (1) { 489 ret = snb_pcode_write_timeout(&i915->uncore, ICL_PCODE_EXIT_TCCOLD, 0, 490 250, 1); 491 if (ret != -EAGAIN || ++tries == 3) 492 break; 493 msleep(1); 494 } 495 496 /* Spec states that TC cold exit can take up to 1ms to complete */ 497 if (!ret) 498 msleep(1); 499 500 /* TODO: turn failure into a error as soon i915 CI updates ICL IFWI */ 501 drm_dbg_kms(&i915->drm, "TC cold block %s\n", ret ? "failed" : 502 "succeeded"); 503 } 504 505 static void 506 icl_tc_phy_aux_power_well_enable(struct intel_display *display, 507 struct i915_power_well *power_well) 508 { 509 enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well); 510 struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch); 511 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 512 bool is_tbt = power_well->desc->is_tc_tbt; 513 bool timeout_expected; 514 515 icl_tc_port_assert_ref_held(display, power_well, dig_port); 516 517 intel_de_rmw(display, DP_AUX_CH_CTL(aux_ch), 518 DP_AUX_CH_CTL_TBT_IO, is_tbt ? DP_AUX_CH_CTL_TBT_IO : 0); 519 520 intel_de_rmw(display, regs->driver, 521 0, 522 HSW_PWR_WELL_CTL_REQ(i915_power_well_instance(power_well)->hsw.idx)); 523 524 /* 525 * An AUX timeout is expected if the TBT DP tunnel is down, 526 * or need to enable AUX on a legacy TypeC port as part of the TC-cold 527 * exit sequence. 528 */ 529 timeout_expected = is_tbt || intel_tc_cold_requires_aux_pw(dig_port); 530 if (DISPLAY_VER(display) == 11 && intel_tc_cold_requires_aux_pw(dig_port)) 531 icl_tc_cold_exit(display); 532 533 hsw_wait_for_power_well_enable(display, power_well, timeout_expected); 534 535 if (DISPLAY_VER(display) >= 12 && !is_tbt) { 536 enum tc_port tc_port; 537 538 tc_port = TGL_AUX_PW_TO_TC_PORT(i915_power_well_instance(power_well)->hsw.idx); 539 540 if (wait_for(intel_dkl_phy_read(display, DKL_CMN_UC_DW_27(tc_port)) & 541 DKL_CMN_UC_DW27_UC_HEALTH, 1)) 542 drm_warn(display->drm, 543 "Timeout waiting TC uC health\n"); 544 } 545 } 546 547 static void 548 icl_aux_power_well_enable(struct intel_display *display, 549 struct i915_power_well *power_well) 550 { 551 enum phy phy = icl_aux_pw_to_phy(display, power_well); 552 553 if (intel_phy_is_tc(display, phy)) 554 return icl_tc_phy_aux_power_well_enable(display, power_well); 555 else if (display->platform.icelake) 556 return icl_combo_phy_aux_power_well_enable(display, 557 power_well); 558 else 559 return hsw_power_well_enable(display, power_well); 560 } 561 562 static void 563 icl_aux_power_well_disable(struct intel_display *display, 564 struct i915_power_well *power_well) 565 { 566 enum phy phy = icl_aux_pw_to_phy(display, power_well); 567 568 if (intel_phy_is_tc(display, phy)) 569 return hsw_power_well_disable(display, power_well); 570 else if (display->platform.icelake) 571 return icl_combo_phy_aux_power_well_disable(display, 572 power_well); 573 else 574 return hsw_power_well_disable(display, power_well); 575 } 576 577 /* 578 * We should only use the power well if we explicitly asked the hardware to 579 * enable it, so check if it's enabled and also check if we've requested it to 580 * be enabled. 581 */ 582 static bool hsw_power_well_enabled(struct intel_display *display, 583 struct i915_power_well *power_well) 584 { 585 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 586 enum i915_power_well_id id = i915_power_well_instance(power_well)->id; 587 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 588 u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx) | 589 HSW_PWR_WELL_CTL_STATE(pw_idx); 590 u32 val; 591 592 val = intel_de_read(display, regs->driver); 593 594 /* 595 * On GEN9 big core due to a DMC bug the driver's request bits for PW1 596 * and the MISC_IO PW will be not restored, so check instead for the 597 * BIOS's own request bits, which are forced-on for these power wells 598 * when exiting DC5/6. 599 */ 600 if (DISPLAY_VER(display) == 9 && !display->platform.broxton && 601 (id == SKL_DISP_PW_1 || id == SKL_DISP_PW_MISC_IO)) 602 val |= intel_de_read(display, regs->bios); 603 604 return (val & mask) == mask; 605 } 606 607 static void assert_can_enable_dc9(struct intel_display *display) 608 { 609 struct drm_i915_private *dev_priv = to_i915(display->drm); 610 611 drm_WARN_ONCE(display->drm, 612 (intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC9), 613 "DC9 already programmed to be enabled.\n"); 614 drm_WARN_ONCE(display->drm, 615 intel_de_read(display, DC_STATE_EN) & 616 DC_STATE_EN_UPTO_DC5, 617 "DC5 still not disabled to enable DC9.\n"); 618 drm_WARN_ONCE(display->drm, 619 intel_de_read(display, HSW_PWR_WELL_CTL2) & 620 HSW_PWR_WELL_CTL_REQ(SKL_PW_CTL_IDX_PW_2), 621 "Power well 2 on.\n"); 622 drm_WARN_ONCE(display->drm, intel_irqs_enabled(dev_priv), 623 "Interrupts not disabled yet.\n"); 624 625 /* 626 * TODO: check for the following to verify the conditions to enter DC9 627 * state are satisfied: 628 * 1] Check relevant display engine registers to verify if mode set 629 * disable sequence was followed. 630 * 2] Check if display uninitialize sequence is initialized. 631 */ 632 } 633 634 static void assert_can_disable_dc9(struct intel_display *display) 635 { 636 struct drm_i915_private *dev_priv = to_i915(display->drm); 637 638 drm_WARN_ONCE(display->drm, intel_irqs_enabled(dev_priv), 639 "Interrupts not disabled yet.\n"); 640 drm_WARN_ONCE(display->drm, 641 intel_de_read(display, DC_STATE_EN) & 642 DC_STATE_EN_UPTO_DC5, 643 "DC5 still not disabled.\n"); 644 645 /* 646 * TODO: check for the following to verify DC9 state was indeed 647 * entered before programming to disable it: 648 * 1] Check relevant display engine registers to verify if mode 649 * set disable sequence was followed. 650 * 2] Check if display uninitialize sequence is initialized. 651 */ 652 } 653 654 static void gen9_write_dc_state(struct intel_display *display, 655 u32 state) 656 { 657 int rewrites = 0; 658 int rereads = 0; 659 u32 v; 660 661 intel_de_write(display, DC_STATE_EN, state); 662 663 /* It has been observed that disabling the dc6 state sometimes 664 * doesn't stick and dmc keeps returning old value. Make sure 665 * the write really sticks enough times and also force rewrite until 666 * we are confident that state is exactly what we want. 667 */ 668 do { 669 v = intel_de_read(display, DC_STATE_EN); 670 671 if (v != state) { 672 intel_de_write(display, DC_STATE_EN, state); 673 rewrites++; 674 rereads = 0; 675 } else if (rereads++ > 5) { 676 break; 677 } 678 679 } while (rewrites < 100); 680 681 if (v != state) 682 drm_err(display->drm, 683 "Writing dc state to 0x%x failed, now 0x%x\n", 684 state, v); 685 686 /* Most of the times we need one retry, avoid spam */ 687 if (rewrites > 1) 688 drm_dbg_kms(display->drm, 689 "Rewrote dc state to 0x%x %d times\n", 690 state, rewrites); 691 } 692 693 static u32 gen9_dc_mask(struct intel_display *display) 694 { 695 u32 mask; 696 697 mask = DC_STATE_EN_UPTO_DC5; 698 699 if (DISPLAY_VER(display) >= 12) 700 mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6 701 | DC_STATE_EN_DC9; 702 else if (DISPLAY_VER(display) == 11) 703 mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9; 704 else if (display->platform.geminilake || display->platform.broxton) 705 mask |= DC_STATE_EN_DC9; 706 else 707 mask |= DC_STATE_EN_UPTO_DC6; 708 709 return mask; 710 } 711 712 void gen9_sanitize_dc_state(struct intel_display *display) 713 { 714 struct i915_power_domains *power_domains = &display->power.domains; 715 u32 val; 716 717 if (!HAS_DISPLAY(display)) 718 return; 719 720 val = intel_de_read(display, DC_STATE_EN) & gen9_dc_mask(display); 721 722 drm_dbg_kms(display->drm, 723 "Resetting DC state tracking from %02x to %02x\n", 724 power_domains->dc_state, val); 725 power_domains->dc_state = val; 726 } 727 728 /** 729 * gen9_set_dc_state - set target display C power state 730 * @display: display instance 731 * @state: target DC power state 732 * - DC_STATE_DISABLE 733 * - DC_STATE_EN_UPTO_DC5 734 * - DC_STATE_EN_UPTO_DC6 735 * - DC_STATE_EN_DC9 736 * 737 * Signal to DMC firmware/HW the target DC power state passed in @state. 738 * DMC/HW can turn off individual display clocks and power rails when entering 739 * a deeper DC power state (higher in number) and turns these back when exiting 740 * that state to a shallower power state (lower in number). The HW will decide 741 * when to actually enter a given state on an on-demand basis, for instance 742 * depending on the active state of display pipes. The state of display 743 * registers backed by affected power rails are saved/restored as needed. 744 * 745 * Based on the above enabling a deeper DC power state is asynchronous wrt. 746 * enabling it. Disabling a deeper power state is synchronous: for instance 747 * setting %DC_STATE_DISABLE won't complete until all HW resources are turned 748 * back on and register state is restored. This is guaranteed by the MMIO write 749 * to DC_STATE_EN blocking until the state is restored. 750 */ 751 void gen9_set_dc_state(struct intel_display *display, u32 state) 752 { 753 struct i915_power_domains *power_domains = &display->power.domains; 754 bool dc6_was_enabled, enable_dc6; 755 u32 mask; 756 u32 val; 757 758 if (!HAS_DISPLAY(display)) 759 return; 760 761 if (drm_WARN_ON_ONCE(display->drm, 762 state & ~power_domains->allowed_dc_mask)) 763 state &= power_domains->allowed_dc_mask; 764 765 if (!power_domains->initializing) 766 intel_psr_notify_dc5_dc6(display); 767 768 val = intel_de_read(display, DC_STATE_EN); 769 mask = gen9_dc_mask(display); 770 drm_dbg_kms(display->drm, "Setting DC state from %02x to %02x\n", 771 val & mask, state); 772 773 /* Check if DMC is ignoring our DC state requests */ 774 if ((val & mask) != power_domains->dc_state) 775 drm_err(display->drm, "DC state mismatch (0x%x -> 0x%x)\n", 776 power_domains->dc_state, val & mask); 777 778 enable_dc6 = state & DC_STATE_EN_UPTO_DC6; 779 dc6_was_enabled = val & DC_STATE_EN_UPTO_DC6; 780 if (!dc6_was_enabled && enable_dc6) 781 intel_dmc_update_dc6_allowed_count(display, true); 782 783 val &= ~mask; 784 val |= state; 785 786 gen9_write_dc_state(display, val); 787 788 if (!enable_dc6 && dc6_was_enabled) 789 intel_dmc_update_dc6_allowed_count(display, false); 790 791 power_domains->dc_state = val & mask; 792 } 793 794 static void tgl_enable_dc3co(struct intel_display *display) 795 { 796 drm_dbg_kms(display->drm, "Enabling DC3CO\n"); 797 gen9_set_dc_state(display, DC_STATE_EN_DC3CO); 798 } 799 800 static void tgl_disable_dc3co(struct intel_display *display) 801 { 802 drm_dbg_kms(display->drm, "Disabling DC3CO\n"); 803 intel_de_rmw(display, DC_STATE_EN, DC_STATE_DC3CO_STATUS, 0); 804 gen9_set_dc_state(display, DC_STATE_DISABLE); 805 /* 806 * Delay of 200us DC3CO Exit time B.Spec 49196 807 */ 808 usleep_range(200, 210); 809 } 810 811 static void assert_can_enable_dc5(struct intel_display *display) 812 { 813 enum i915_power_well_id high_pg; 814 815 /* Power wells at this level and above must be disabled for DC5 entry */ 816 if (DISPLAY_VER(display) == 12) 817 high_pg = ICL_DISP_PW_3; 818 else 819 high_pg = SKL_DISP_PW_2; 820 821 drm_WARN_ONCE(display->drm, 822 intel_display_power_well_is_enabled(display, high_pg), 823 "Power wells above platform's DC5 limit still enabled.\n"); 824 825 drm_WARN_ONCE(display->drm, 826 (intel_de_read(display, DC_STATE_EN) & 827 DC_STATE_EN_UPTO_DC5), 828 "DC5 already programmed to be enabled.\n"); 829 830 assert_display_rpm_held(display); 831 832 assert_dmc_loaded(display); 833 } 834 835 void gen9_enable_dc5(struct intel_display *display) 836 { 837 assert_can_enable_dc5(display); 838 839 drm_dbg_kms(display->drm, "Enabling DC5\n"); 840 841 /* Wa Display #1183: skl,kbl,cfl */ 842 if (DISPLAY_VER(display) == 9 && !display->platform.broxton) 843 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 844 0, SKL_SELECT_ALTERNATE_DC_EXIT); 845 846 intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC5); 847 848 gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC5); 849 } 850 851 static void assert_can_enable_dc6(struct intel_display *display) 852 { 853 drm_WARN_ONCE(display->drm, 854 (intel_de_read(display, UTIL_PIN_CTL) & 855 (UTIL_PIN_ENABLE | UTIL_PIN_MODE_MASK)) == 856 (UTIL_PIN_ENABLE | UTIL_PIN_MODE_PWM), 857 "Utility pin enabled in PWM mode\n"); 858 drm_WARN_ONCE(display->drm, 859 (intel_de_read(display, DC_STATE_EN) & 860 DC_STATE_EN_UPTO_DC6), 861 "DC6 already programmed to be enabled.\n"); 862 863 assert_dmc_loaded(display); 864 } 865 866 void skl_enable_dc6(struct intel_display *display) 867 { 868 assert_can_enable_dc6(display); 869 870 drm_dbg_kms(display->drm, "Enabling DC6\n"); 871 872 /* Wa Display #1183: skl,kbl,cfl */ 873 if (DISPLAY_VER(display) == 9 && !display->platform.broxton) 874 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 875 0, SKL_SELECT_ALTERNATE_DC_EXIT); 876 877 intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC6); 878 879 gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC6); 880 } 881 882 void bxt_enable_dc9(struct intel_display *display) 883 { 884 assert_can_enable_dc9(display); 885 886 drm_dbg_kms(display->drm, "Enabling DC9\n"); 887 /* 888 * Power sequencer reset is needed on BXT/GLK, because the PPS registers 889 * aren't always on, unlike with South Display Engine on PCH. 890 */ 891 if (display->platform.broxton || display->platform.geminilake) 892 bxt_pps_reset_all(display); 893 gen9_set_dc_state(display, DC_STATE_EN_DC9); 894 } 895 896 void bxt_disable_dc9(struct intel_display *display) 897 { 898 assert_can_disable_dc9(display); 899 900 drm_dbg_kms(display->drm, "Disabling DC9\n"); 901 902 gen9_set_dc_state(display, DC_STATE_DISABLE); 903 904 intel_pps_unlock_regs_wa(display); 905 } 906 907 static void hsw_power_well_sync_hw(struct intel_display *display, 908 struct i915_power_well *power_well) 909 { 910 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 911 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 912 u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx); 913 u32 bios_req = intel_de_read(display, regs->bios); 914 915 /* Take over the request bit if set by BIOS. */ 916 if (bios_req & mask) { 917 u32 drv_req = intel_de_read(display, regs->driver); 918 919 if (!(drv_req & mask)) 920 intel_de_write(display, regs->driver, drv_req | mask); 921 intel_de_write(display, regs->bios, bios_req & ~mask); 922 } 923 } 924 925 static void bxt_dpio_cmn_power_well_enable(struct intel_display *display, 926 struct i915_power_well *power_well) 927 { 928 bxt_dpio_phy_init(display, i915_power_well_instance(power_well)->bxt.phy); 929 } 930 931 static void bxt_dpio_cmn_power_well_disable(struct intel_display *display, 932 struct i915_power_well *power_well) 933 { 934 bxt_dpio_phy_uninit(display, i915_power_well_instance(power_well)->bxt.phy); 935 } 936 937 static bool bxt_dpio_cmn_power_well_enabled(struct intel_display *display, 938 struct i915_power_well *power_well) 939 { 940 return bxt_dpio_phy_is_enabled(display, i915_power_well_instance(power_well)->bxt.phy); 941 } 942 943 static void bxt_verify_dpio_phy_power_wells(struct intel_display *display) 944 { 945 struct i915_power_well *power_well; 946 947 power_well = lookup_power_well(display, BXT_DISP_PW_DPIO_CMN_A); 948 if (intel_power_well_refcount(power_well) > 0) 949 bxt_dpio_phy_verify_state(display, i915_power_well_instance(power_well)->bxt.phy); 950 951 power_well = lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC); 952 if (intel_power_well_refcount(power_well) > 0) 953 bxt_dpio_phy_verify_state(display, i915_power_well_instance(power_well)->bxt.phy); 954 955 if (display->platform.geminilake) { 956 power_well = lookup_power_well(display, 957 GLK_DISP_PW_DPIO_CMN_C); 958 if (intel_power_well_refcount(power_well) > 0) 959 bxt_dpio_phy_verify_state(display, 960 i915_power_well_instance(power_well)->bxt.phy); 961 } 962 } 963 964 static bool gen9_dc_off_power_well_enabled(struct intel_display *display, 965 struct i915_power_well *power_well) 966 { 967 return ((intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 && 968 (intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0); 969 } 970 971 static void gen9_assert_dbuf_enabled(struct intel_display *display) 972 { 973 u8 hw_enabled_dbuf_slices = intel_enabled_dbuf_slices_mask(display); 974 u8 enabled_dbuf_slices = display->dbuf.enabled_slices; 975 976 drm_WARN(display->drm, 977 hw_enabled_dbuf_slices != enabled_dbuf_slices, 978 "Unexpected DBuf power power state (0x%08x, expected 0x%08x)\n", 979 hw_enabled_dbuf_slices, 980 enabled_dbuf_slices); 981 } 982 983 void gen9_disable_dc_states(struct intel_display *display) 984 { 985 struct i915_power_domains *power_domains = &display->power.domains; 986 struct intel_cdclk_config cdclk_config = {}; 987 u32 old_state = power_domains->dc_state; 988 989 if (power_domains->target_dc_state == DC_STATE_EN_DC3CO) { 990 tgl_disable_dc3co(display); 991 return; 992 } 993 994 if (HAS_DISPLAY(display)) { 995 intel_dmc_wl_get_noreg(display); 996 gen9_set_dc_state(display, DC_STATE_DISABLE); 997 intel_dmc_wl_put_noreg(display); 998 } else { 999 gen9_set_dc_state(display, DC_STATE_DISABLE); 1000 return; 1001 } 1002 1003 if (old_state == DC_STATE_EN_UPTO_DC5 || 1004 old_state == DC_STATE_EN_UPTO_DC6) 1005 intel_dmc_wl_disable(display); 1006 1007 intel_cdclk_get_cdclk(display, &cdclk_config); 1008 /* Can't read out voltage_level so can't use intel_cdclk_changed() */ 1009 drm_WARN_ON(display->drm, 1010 intel_cdclk_clock_changed(&display->cdclk.hw, 1011 &cdclk_config)); 1012 1013 gen9_assert_dbuf_enabled(display); 1014 1015 if (display->platform.geminilake || display->platform.broxton) 1016 bxt_verify_dpio_phy_power_wells(display); 1017 1018 if (DISPLAY_VER(display) >= 11) 1019 /* 1020 * DMC retains HW context only for port A, the other combo 1021 * PHY's HW context for port B is lost after DC transitions, 1022 * so we need to restore it manually. 1023 */ 1024 intel_combo_phy_init(display); 1025 } 1026 1027 static void gen9_dc_off_power_well_enable(struct intel_display *display, 1028 struct i915_power_well *power_well) 1029 { 1030 gen9_disable_dc_states(display); 1031 } 1032 1033 static void gen9_dc_off_power_well_disable(struct intel_display *display, 1034 struct i915_power_well *power_well) 1035 { 1036 struct i915_power_domains *power_domains = &display->power.domains; 1037 1038 if (!intel_dmc_has_payload(display)) 1039 return; 1040 1041 switch (power_domains->target_dc_state) { 1042 case DC_STATE_EN_DC3CO: 1043 tgl_enable_dc3co(display); 1044 break; 1045 case DC_STATE_EN_UPTO_DC6: 1046 skl_enable_dc6(display); 1047 break; 1048 case DC_STATE_EN_UPTO_DC5: 1049 gen9_enable_dc5(display); 1050 break; 1051 } 1052 } 1053 1054 static void i9xx_power_well_sync_hw_noop(struct intel_display *display, 1055 struct i915_power_well *power_well) 1056 { 1057 } 1058 1059 static void i9xx_always_on_power_well_noop(struct intel_display *display, 1060 struct i915_power_well *power_well) 1061 { 1062 } 1063 1064 static bool i9xx_always_on_power_well_enabled(struct intel_display *display, 1065 struct i915_power_well *power_well) 1066 { 1067 return true; 1068 } 1069 1070 static void i830_pipes_power_well_enable(struct intel_display *display, 1071 struct i915_power_well *power_well) 1072 { 1073 if ((intel_de_read(display, TRANSCONF(display, PIPE_A)) & TRANSCONF_ENABLE) == 0) 1074 i830_enable_pipe(display, PIPE_A); 1075 if ((intel_de_read(display, TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE) == 0) 1076 i830_enable_pipe(display, PIPE_B); 1077 } 1078 1079 static void i830_pipes_power_well_disable(struct intel_display *display, 1080 struct i915_power_well *power_well) 1081 { 1082 i830_disable_pipe(display, PIPE_B); 1083 i830_disable_pipe(display, PIPE_A); 1084 } 1085 1086 static bool i830_pipes_power_well_enabled(struct intel_display *display, 1087 struct i915_power_well *power_well) 1088 { 1089 return intel_de_read(display, TRANSCONF(display, PIPE_A)) & TRANSCONF_ENABLE && 1090 intel_de_read(display, TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE; 1091 } 1092 1093 static void i830_pipes_power_well_sync_hw(struct intel_display *display, 1094 struct i915_power_well *power_well) 1095 { 1096 if (intel_power_well_refcount(power_well) > 0) 1097 i830_pipes_power_well_enable(display, power_well); 1098 else 1099 i830_pipes_power_well_disable(display, power_well); 1100 } 1101 1102 static void vlv_set_power_well(struct intel_display *display, 1103 struct i915_power_well *power_well, bool enable) 1104 { 1105 int pw_idx = i915_power_well_instance(power_well)->vlv.idx; 1106 u32 mask; 1107 u32 state; 1108 u32 ctrl; 1109 1110 mask = PUNIT_PWRGT_MASK(pw_idx); 1111 state = enable ? PUNIT_PWRGT_PWR_ON(pw_idx) : 1112 PUNIT_PWRGT_PWR_GATE(pw_idx); 1113 1114 vlv_punit_get(display->drm); 1115 1116 #define COND \ 1117 ((vlv_punit_read(display->drm, PUNIT_REG_PWRGT_STATUS) & mask) == state) 1118 1119 if (COND) 1120 goto out; 1121 1122 ctrl = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_CTRL); 1123 ctrl &= ~mask; 1124 ctrl |= state; 1125 vlv_punit_write(display->drm, PUNIT_REG_PWRGT_CTRL, ctrl); 1126 1127 if (wait_for(COND, 100)) 1128 drm_err(display->drm, 1129 "timeout setting power well state %08x (%08x)\n", 1130 state, 1131 vlv_punit_read(display->drm, PUNIT_REG_PWRGT_CTRL)); 1132 1133 #undef COND 1134 1135 out: 1136 vlv_punit_put(display->drm); 1137 } 1138 1139 static void vlv_power_well_enable(struct intel_display *display, 1140 struct i915_power_well *power_well) 1141 { 1142 vlv_set_power_well(display, power_well, true); 1143 } 1144 1145 static void vlv_power_well_disable(struct intel_display *display, 1146 struct i915_power_well *power_well) 1147 { 1148 vlv_set_power_well(display, power_well, false); 1149 } 1150 1151 static bool vlv_power_well_enabled(struct intel_display *display, 1152 struct i915_power_well *power_well) 1153 { 1154 int pw_idx = i915_power_well_instance(power_well)->vlv.idx; 1155 bool enabled = false; 1156 u32 mask; 1157 u32 state; 1158 u32 ctrl; 1159 1160 mask = PUNIT_PWRGT_MASK(pw_idx); 1161 ctrl = PUNIT_PWRGT_PWR_ON(pw_idx); 1162 1163 vlv_punit_get(display->drm); 1164 1165 state = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_STATUS) & mask; 1166 /* 1167 * We only ever set the power-on and power-gate states, anything 1168 * else is unexpected. 1169 */ 1170 drm_WARN_ON(display->drm, state != PUNIT_PWRGT_PWR_ON(pw_idx) && 1171 state != PUNIT_PWRGT_PWR_GATE(pw_idx)); 1172 if (state == ctrl) 1173 enabled = true; 1174 1175 /* 1176 * A transient state at this point would mean some unexpected party 1177 * is poking at the power controls too. 1178 */ 1179 ctrl = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_CTRL) & mask; 1180 drm_WARN_ON(display->drm, ctrl != state); 1181 1182 vlv_punit_put(display->drm); 1183 1184 return enabled; 1185 } 1186 1187 static void vlv_init_display_clock_gating(struct intel_display *display) 1188 { 1189 /* 1190 * On driver load, a pipe may be active and driving a DSI display. 1191 * Preserve DPOUNIT_CLOCK_GATE_DISABLE to avoid the pipe getting stuck 1192 * (and never recovering) in this case. intel_dsi_post_disable() will 1193 * clear it when we turn off the display. 1194 */ 1195 intel_de_rmw(display, DSPCLK_GATE_D(display), 1196 ~DPOUNIT_CLOCK_GATE_DISABLE, VRHUNIT_CLOCK_GATE_DISABLE); 1197 1198 /* 1199 * Disable trickle feed and enable pnd deadline calculation 1200 */ 1201 intel_de_write(display, MI_ARB_VLV, 1202 MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); 1203 intel_de_write(display, CBR1_VLV, 0); 1204 1205 drm_WARN_ON(display->drm, DISPLAY_RUNTIME_INFO(display)->rawclk_freq == 0); 1206 intel_de_write(display, RAWCLK_FREQ_VLV, 1207 DIV_ROUND_CLOSEST(DISPLAY_RUNTIME_INFO(display)->rawclk_freq, 1208 1000)); 1209 } 1210 1211 static void vlv_display_power_well_init(struct intel_display *display) 1212 { 1213 struct intel_encoder *encoder; 1214 enum pipe pipe; 1215 1216 /* 1217 * Enable the CRI clock source so we can get at the 1218 * display and the reference clock for VGA 1219 * hotplug / manual detection. Supposedly DSI also 1220 * needs the ref clock up and running. 1221 * 1222 * CHV DPLL B/C have some issues if VGA mode is enabled. 1223 */ 1224 for_each_pipe(display, pipe) { 1225 u32 val = intel_de_read(display, DPLL(display, pipe)); 1226 1227 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 1228 if (pipe != PIPE_A) 1229 val |= DPLL_INTEGRATED_CRI_CLK_VLV; 1230 1231 intel_de_write(display, DPLL(display, pipe), val); 1232 } 1233 1234 vlv_init_display_clock_gating(display); 1235 1236 valleyview_enable_display_irqs(display); 1237 1238 /* 1239 * During driver initialization/resume we can avoid restoring the 1240 * part of the HW/SW state that will be inited anyway explicitly. 1241 */ 1242 if (display->power.domains.initializing) 1243 return; 1244 1245 intel_hpd_init(display); 1246 intel_hpd_poll_disable(display); 1247 1248 /* Re-enable the ADPA, if we have one */ 1249 for_each_intel_encoder(display->drm, encoder) { 1250 if (encoder->type == INTEL_OUTPUT_ANALOG) 1251 intel_crt_reset(&encoder->base); 1252 } 1253 1254 intel_vga_disable(display); 1255 1256 intel_pps_unlock_regs_wa(display); 1257 } 1258 1259 static void vlv_display_power_well_deinit(struct intel_display *display) 1260 { 1261 struct drm_i915_private *dev_priv = to_i915(display->drm); 1262 1263 valleyview_disable_display_irqs(display); 1264 1265 /* make sure we're done processing display irqs */ 1266 intel_synchronize_irq(dev_priv); 1267 1268 vlv_pps_reset_all(display); 1269 1270 /* Prevent us from re-enabling polling on accident in late suspend */ 1271 if (!display->drm->dev->power.is_suspended) 1272 intel_hpd_poll_enable(display); 1273 } 1274 1275 static void vlv_display_power_well_enable(struct intel_display *display, 1276 struct i915_power_well *power_well) 1277 { 1278 vlv_set_power_well(display, power_well, true); 1279 1280 vlv_display_power_well_init(display); 1281 } 1282 1283 static void vlv_display_power_well_disable(struct intel_display *display, 1284 struct i915_power_well *power_well) 1285 { 1286 vlv_display_power_well_deinit(display); 1287 1288 vlv_set_power_well(display, power_well, false); 1289 } 1290 1291 static void vlv_dpio_cmn_power_well_enable(struct intel_display *display, 1292 struct i915_power_well *power_well) 1293 { 1294 /* since ref/cri clock was enabled */ 1295 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 1296 1297 vlv_set_power_well(display, power_well, true); 1298 1299 /* 1300 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - 1301 * 6. De-assert cmn_reset/side_reset. Same as VLV X0. 1302 * a. GUnit 0x2110 bit[0] set to 1 (def 0) 1303 * b. The other bits such as sfr settings / modesel may all 1304 * be set to 0. 1305 * 1306 * This should only be done on init and resume from S3 with 1307 * both PLLs disabled, or we risk losing DPIO and PLL 1308 * synchronization. 1309 */ 1310 intel_de_rmw(display, DPIO_CTL, 0, DPIO_CMNRST); 1311 } 1312 1313 static void vlv_dpio_cmn_power_well_disable(struct intel_display *display, 1314 struct i915_power_well *power_well) 1315 { 1316 enum pipe pipe; 1317 1318 for_each_pipe(display, pipe) 1319 assert_pll_disabled(display, pipe); 1320 1321 /* Assert common reset */ 1322 intel_de_rmw(display, DPIO_CTL, DPIO_CMNRST, 0); 1323 1324 vlv_set_power_well(display, power_well, false); 1325 } 1326 1327 #define BITS_SET(val, bits) (((val) & (bits)) == (bits)) 1328 1329 static void assert_chv_phy_status(struct intel_display *display) 1330 { 1331 struct i915_power_well *cmn_bc = 1332 lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC); 1333 struct i915_power_well *cmn_d = 1334 lookup_power_well(display, CHV_DISP_PW_DPIO_CMN_D); 1335 u32 phy_control = display->power.chv_phy_control; 1336 u32 phy_status = 0; 1337 u32 phy_status_mask = 0xffffffff; 1338 1339 /* 1340 * The BIOS can leave the PHY is some weird state 1341 * where it doesn't fully power down some parts. 1342 * Disable the asserts until the PHY has been fully 1343 * reset (ie. the power well has been disabled at 1344 * least once). 1345 */ 1346 if (!display->power.chv_phy_assert[DPIO_PHY0]) 1347 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) | 1348 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) | 1349 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) | 1350 PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) | 1351 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) | 1352 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1)); 1353 1354 if (!display->power.chv_phy_assert[DPIO_PHY1]) 1355 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) | 1356 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) | 1357 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1)); 1358 1359 if (intel_power_well_is_enabled(display, cmn_bc)) { 1360 phy_status |= PHY_POWERGOOD(DPIO_PHY0); 1361 1362 /* this assumes override is only used to enable lanes */ 1363 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0) 1364 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0); 1365 1366 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0) 1367 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1); 1368 1369 /* CL1 is on whenever anything is on in either channel */ 1370 if (BITS_SET(phy_control, 1371 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) | 1372 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1))) 1373 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0); 1374 1375 /* 1376 * The DPLLB check accounts for the pipe B + port A usage 1377 * with CL2 powered up but all the lanes in the second channel 1378 * powered down. 1379 */ 1380 if (BITS_SET(phy_control, 1381 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) && 1382 (intel_de_read(display, DPLL(display, PIPE_B)) & DPLL_VCO_ENABLE) == 0) 1383 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1); 1384 1385 if (BITS_SET(phy_control, 1386 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0))) 1387 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0); 1388 if (BITS_SET(phy_control, 1389 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0))) 1390 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1); 1391 1392 if (BITS_SET(phy_control, 1393 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1))) 1394 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0); 1395 if (BITS_SET(phy_control, 1396 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1))) 1397 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1); 1398 } 1399 1400 if (intel_power_well_is_enabled(display, cmn_d)) { 1401 phy_status |= PHY_POWERGOOD(DPIO_PHY1); 1402 1403 /* this assumes override is only used to enable lanes */ 1404 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0) 1405 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0); 1406 1407 if (BITS_SET(phy_control, 1408 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0))) 1409 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0); 1410 1411 if (BITS_SET(phy_control, 1412 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0))) 1413 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0); 1414 if (BITS_SET(phy_control, 1415 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0))) 1416 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1); 1417 } 1418 1419 phy_status &= phy_status_mask; 1420 1421 /* 1422 * The PHY may be busy with some initial calibration and whatnot, 1423 * so the power state can take a while to actually change. 1424 */ 1425 if (intel_de_wait(display, DISPLAY_PHY_STATUS, 1426 phy_status_mask, phy_status, 10)) 1427 drm_err(display->drm, 1428 "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n", 1429 intel_de_read(display, DISPLAY_PHY_STATUS) & phy_status_mask, 1430 phy_status, display->power.chv_phy_control); 1431 } 1432 1433 #undef BITS_SET 1434 1435 static void chv_dpio_cmn_power_well_enable(struct intel_display *display, 1436 struct i915_power_well *power_well) 1437 { 1438 enum i915_power_well_id id = i915_power_well_instance(power_well)->id; 1439 enum dpio_phy phy; 1440 u32 tmp; 1441 1442 drm_WARN_ON_ONCE(display->drm, 1443 id != VLV_DISP_PW_DPIO_CMN_BC && 1444 id != CHV_DISP_PW_DPIO_CMN_D); 1445 1446 if (id == VLV_DISP_PW_DPIO_CMN_BC) 1447 phy = DPIO_PHY0; 1448 else 1449 phy = DPIO_PHY1; 1450 1451 /* since ref/cri clock was enabled */ 1452 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 1453 vlv_set_power_well(display, power_well, true); 1454 1455 /* Poll for phypwrgood signal */ 1456 if (intel_de_wait_for_set(display, DISPLAY_PHY_STATUS, 1457 PHY_POWERGOOD(phy), 1)) 1458 drm_err(display->drm, "Display PHY %d is not power up\n", 1459 phy); 1460 1461 vlv_dpio_get(display->drm); 1462 1463 /* Enable dynamic power down */ 1464 tmp = vlv_dpio_read(display->drm, phy, CHV_CMN_DW28); 1465 tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN | 1466 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ; 1467 vlv_dpio_write(display->drm, phy, CHV_CMN_DW28, tmp); 1468 1469 if (id == VLV_DISP_PW_DPIO_CMN_BC) { 1470 tmp = vlv_dpio_read(display->drm, phy, CHV_CMN_DW6_CH1); 1471 tmp |= DPIO_DYNPWRDOWNEN_CH1; 1472 vlv_dpio_write(display->drm, phy, CHV_CMN_DW6_CH1, tmp); 1473 } else { 1474 /* 1475 * Force the non-existing CL2 off. BXT does this 1476 * too, so maybe it saves some power even though 1477 * CL2 doesn't exist? 1478 */ 1479 tmp = vlv_dpio_read(display->drm, phy, CHV_CMN_DW30); 1480 tmp |= DPIO_CL2_LDOFUSE_PWRENB; 1481 vlv_dpio_write(display->drm, phy, CHV_CMN_DW30, tmp); 1482 } 1483 1484 vlv_dpio_put(display->drm); 1485 1486 display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy); 1487 intel_de_write(display, DISPLAY_PHY_CONTROL, 1488 display->power.chv_phy_control); 1489 1490 drm_dbg_kms(display->drm, 1491 "Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1492 phy, display->power.chv_phy_control); 1493 1494 assert_chv_phy_status(display); 1495 } 1496 1497 static void chv_dpio_cmn_power_well_disable(struct intel_display *display, 1498 struct i915_power_well *power_well) 1499 { 1500 enum i915_power_well_id id = i915_power_well_instance(power_well)->id; 1501 enum dpio_phy phy; 1502 1503 drm_WARN_ON_ONCE(display->drm, 1504 id != VLV_DISP_PW_DPIO_CMN_BC && 1505 id != CHV_DISP_PW_DPIO_CMN_D); 1506 1507 if (id == VLV_DISP_PW_DPIO_CMN_BC) { 1508 phy = DPIO_PHY0; 1509 assert_pll_disabled(display, PIPE_A); 1510 assert_pll_disabled(display, PIPE_B); 1511 } else { 1512 phy = DPIO_PHY1; 1513 assert_pll_disabled(display, PIPE_C); 1514 } 1515 1516 display->power.chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy); 1517 intel_de_write(display, DISPLAY_PHY_CONTROL, 1518 display->power.chv_phy_control); 1519 1520 vlv_set_power_well(display, power_well, false); 1521 1522 drm_dbg_kms(display->drm, 1523 "Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1524 phy, display->power.chv_phy_control); 1525 1526 /* PHY is fully reset now, so we can enable the PHY state asserts */ 1527 display->power.chv_phy_assert[phy] = true; 1528 1529 assert_chv_phy_status(display); 1530 } 1531 1532 static void assert_chv_phy_powergate(struct intel_display *display, enum dpio_phy phy, 1533 enum dpio_channel ch, bool override, unsigned int mask) 1534 { 1535 u32 reg, val, expected, actual; 1536 1537 /* 1538 * The BIOS can leave the PHY is some weird state 1539 * where it doesn't fully power down some parts. 1540 * Disable the asserts until the PHY has been fully 1541 * reset (ie. the power well has been disabled at 1542 * least once). 1543 */ 1544 if (!display->power.chv_phy_assert[phy]) 1545 return; 1546 1547 if (ch == DPIO_CH0) 1548 reg = CHV_CMN_DW0_CH0; 1549 else 1550 reg = CHV_CMN_DW6_CH1; 1551 1552 vlv_dpio_get(display->drm); 1553 val = vlv_dpio_read(display->drm, phy, reg); 1554 vlv_dpio_put(display->drm); 1555 1556 /* 1557 * This assumes !override is only used when the port is disabled. 1558 * All lanes should power down even without the override when 1559 * the port is disabled. 1560 */ 1561 if (!override || mask == 0xf) { 1562 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; 1563 /* 1564 * If CH1 common lane is not active anymore 1565 * (eg. for pipe B DPLL) the entire channel will 1566 * shut down, which causes the common lane registers 1567 * to read as 0. That means we can't actually check 1568 * the lane power down status bits, but as the entire 1569 * register reads as 0 it's a good indication that the 1570 * channel is indeed entirely powered down. 1571 */ 1572 if (ch == DPIO_CH1 && val == 0) 1573 expected = 0; 1574 } else if (mask != 0x0) { 1575 expected = DPIO_ANYDL_POWERDOWN; 1576 } else { 1577 expected = 0; 1578 } 1579 1580 if (ch == DPIO_CH0) 1581 actual = REG_FIELD_GET(DPIO_ANYDL_POWERDOWN_CH0 | 1582 DPIO_ALLDL_POWERDOWN_CH0, val); 1583 else 1584 actual = REG_FIELD_GET(DPIO_ANYDL_POWERDOWN_CH1 | 1585 DPIO_ALLDL_POWERDOWN_CH1, val); 1586 1587 drm_WARN(display->drm, actual != expected, 1588 "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n", 1589 !!(actual & DPIO_ALLDL_POWERDOWN), 1590 !!(actual & DPIO_ANYDL_POWERDOWN), 1591 !!(expected & DPIO_ALLDL_POWERDOWN), 1592 !!(expected & DPIO_ANYDL_POWERDOWN), 1593 reg, val); 1594 } 1595 1596 bool chv_phy_powergate_ch(struct intel_display *display, enum dpio_phy phy, 1597 enum dpio_channel ch, bool override) 1598 { 1599 struct i915_power_domains *power_domains = &display->power.domains; 1600 bool was_override; 1601 1602 mutex_lock(&power_domains->lock); 1603 1604 was_override = display->power.chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1605 1606 if (override == was_override) 1607 goto out; 1608 1609 if (override) 1610 display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1611 else 1612 display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1613 1614 intel_de_write(display, DISPLAY_PHY_CONTROL, 1615 display->power.chv_phy_control); 1616 1617 drm_dbg_kms(display->drm, 1618 "Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n", 1619 phy, ch, display->power.chv_phy_control); 1620 1621 assert_chv_phy_status(display); 1622 1623 out: 1624 mutex_unlock(&power_domains->lock); 1625 1626 return was_override; 1627 } 1628 1629 void chv_phy_powergate_lanes(struct intel_encoder *encoder, 1630 bool override, unsigned int mask) 1631 { 1632 struct intel_display *display = to_intel_display(encoder); 1633 struct i915_power_domains *power_domains = &display->power.domains; 1634 enum dpio_phy phy = vlv_dig_port_to_phy(enc_to_dig_port(encoder)); 1635 enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder)); 1636 1637 mutex_lock(&power_domains->lock); 1638 1639 display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch); 1640 display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch); 1641 1642 if (override) 1643 display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1644 else 1645 display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1646 1647 intel_de_write(display, DISPLAY_PHY_CONTROL, 1648 display->power.chv_phy_control); 1649 1650 drm_dbg_kms(display->drm, 1651 "Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n", 1652 phy, ch, mask, display->power.chv_phy_control); 1653 1654 assert_chv_phy_status(display); 1655 1656 assert_chv_phy_powergate(display, phy, ch, override, mask); 1657 1658 mutex_unlock(&power_domains->lock); 1659 } 1660 1661 static bool chv_pipe_power_well_enabled(struct intel_display *display, 1662 struct i915_power_well *power_well) 1663 { 1664 enum pipe pipe = PIPE_A; 1665 bool enabled; 1666 u32 state, ctrl; 1667 1668 vlv_punit_get(display->drm); 1669 1670 state = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe); 1671 /* 1672 * We only ever set the power-on and power-gate states, anything 1673 * else is unexpected. 1674 */ 1675 drm_WARN_ON(display->drm, state != DP_SSS_PWR_ON(pipe) && 1676 state != DP_SSS_PWR_GATE(pipe)); 1677 enabled = state == DP_SSS_PWR_ON(pipe); 1678 1679 /* 1680 * A transient state at this point would mean some unexpected party 1681 * is poking at the power controls too. 1682 */ 1683 ctrl = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM) & DP_SSC_MASK(pipe); 1684 drm_WARN_ON(display->drm, ctrl << 16 != state); 1685 1686 vlv_punit_put(display->drm); 1687 1688 return enabled; 1689 } 1690 1691 static void chv_set_pipe_power_well(struct intel_display *display, 1692 struct i915_power_well *power_well, 1693 bool enable) 1694 { 1695 enum pipe pipe = PIPE_A; 1696 u32 state; 1697 u32 ctrl; 1698 1699 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe); 1700 1701 vlv_punit_get(display->drm); 1702 1703 #define COND \ 1704 ((vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe)) == state) 1705 1706 if (COND) 1707 goto out; 1708 1709 ctrl = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM); 1710 ctrl &= ~DP_SSC_MASK(pipe); 1711 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe); 1712 vlv_punit_write(display->drm, PUNIT_REG_DSPSSPM, ctrl); 1713 1714 if (wait_for(COND, 100)) 1715 drm_err(display->drm, 1716 "timeout setting power well state %08x (%08x)\n", 1717 state, 1718 vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM)); 1719 1720 #undef COND 1721 1722 out: 1723 vlv_punit_put(display->drm); 1724 } 1725 1726 static void chv_pipe_power_well_sync_hw(struct intel_display *display, 1727 struct i915_power_well *power_well) 1728 { 1729 intel_de_write(display, DISPLAY_PHY_CONTROL, 1730 display->power.chv_phy_control); 1731 } 1732 1733 static void chv_pipe_power_well_enable(struct intel_display *display, 1734 struct i915_power_well *power_well) 1735 { 1736 chv_set_pipe_power_well(display, power_well, true); 1737 1738 vlv_display_power_well_init(display); 1739 } 1740 1741 static void chv_pipe_power_well_disable(struct intel_display *display, 1742 struct i915_power_well *power_well) 1743 { 1744 vlv_display_power_well_deinit(display); 1745 1746 chv_set_pipe_power_well(display, power_well, false); 1747 } 1748 1749 static void 1750 tgl_tc_cold_request(struct intel_display *display, bool block) 1751 { 1752 struct drm_i915_private *i915 = to_i915(display->drm); 1753 u8 tries = 0; 1754 int ret; 1755 1756 while (1) { 1757 u32 low_val; 1758 u32 high_val = 0; 1759 1760 if (block) 1761 low_val = TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ; 1762 else 1763 low_val = TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ; 1764 1765 /* 1766 * Spec states that we should timeout the request after 200us 1767 * but the function below will timeout after 500us 1768 */ 1769 ret = snb_pcode_read(&i915->uncore, TGL_PCODE_TCCOLD, &low_val, &high_val); 1770 if (ret == 0) { 1771 if (block && 1772 (low_val & TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED)) 1773 ret = -EIO; 1774 else 1775 break; 1776 } 1777 1778 if (++tries == 3) 1779 break; 1780 1781 msleep(1); 1782 } 1783 1784 if (ret) 1785 drm_err(&i915->drm, "TC cold %sblock failed\n", 1786 block ? "" : "un"); 1787 else 1788 drm_dbg_kms(&i915->drm, "TC cold %sblock succeeded\n", 1789 block ? "" : "un"); 1790 } 1791 1792 static void 1793 tgl_tc_cold_off_power_well_enable(struct intel_display *display, 1794 struct i915_power_well *power_well) 1795 { 1796 tgl_tc_cold_request(display, true); 1797 } 1798 1799 static void 1800 tgl_tc_cold_off_power_well_disable(struct intel_display *display, 1801 struct i915_power_well *power_well) 1802 { 1803 tgl_tc_cold_request(display, false); 1804 } 1805 1806 static void 1807 tgl_tc_cold_off_power_well_sync_hw(struct intel_display *display, 1808 struct i915_power_well *power_well) 1809 { 1810 if (intel_power_well_refcount(power_well) > 0) 1811 tgl_tc_cold_off_power_well_enable(display, power_well); 1812 else 1813 tgl_tc_cold_off_power_well_disable(display, power_well); 1814 } 1815 1816 static bool 1817 tgl_tc_cold_off_power_well_is_enabled(struct intel_display *display, 1818 struct i915_power_well *power_well) 1819 { 1820 /* 1821 * Not the correctly implementation but there is no way to just read it 1822 * from PCODE, so returning count to avoid state mismatch errors 1823 */ 1824 return intel_power_well_refcount(power_well); 1825 } 1826 1827 static void xelpdp_aux_power_well_enable(struct intel_display *display, 1828 struct i915_power_well *power_well) 1829 { 1830 enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch; 1831 enum phy phy = icl_aux_pw_to_phy(display, power_well); 1832 1833 if (intel_phy_is_tc(display, phy)) 1834 icl_tc_port_assert_ref_held(display, power_well, 1835 aux_ch_to_digital_port(display, aux_ch)); 1836 1837 intel_de_rmw(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch), 1838 XELPDP_DP_AUX_CH_CTL_POWER_REQUEST, 1839 XELPDP_DP_AUX_CH_CTL_POWER_REQUEST); 1840 1841 /* 1842 * The power status flag cannot be used to determine whether aux 1843 * power wells have finished powering up. Instead we're 1844 * expected to just wait a fixed 600us after raising the request 1845 * bit. 1846 */ 1847 usleep_range(600, 1200); 1848 } 1849 1850 static void xelpdp_aux_power_well_disable(struct intel_display *display, 1851 struct i915_power_well *power_well) 1852 { 1853 enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch; 1854 1855 intel_de_rmw(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch), 1856 XELPDP_DP_AUX_CH_CTL_POWER_REQUEST, 1857 0); 1858 usleep_range(10, 30); 1859 } 1860 1861 static bool xelpdp_aux_power_well_enabled(struct intel_display *display, 1862 struct i915_power_well *power_well) 1863 { 1864 enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch; 1865 1866 return intel_de_read(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch)) & 1867 XELPDP_DP_AUX_CH_CTL_POWER_STATUS; 1868 } 1869 1870 static void xe2lpd_pica_power_well_enable(struct intel_display *display, 1871 struct i915_power_well *power_well) 1872 { 1873 intel_de_write(display, XE2LPD_PICA_PW_CTL, 1874 XE2LPD_PICA_CTL_POWER_REQUEST); 1875 1876 if (intel_de_wait_for_set(display, XE2LPD_PICA_PW_CTL, 1877 XE2LPD_PICA_CTL_POWER_STATUS, 1)) { 1878 drm_dbg_kms(display->drm, "pica power well enable timeout\n"); 1879 1880 drm_WARN(display->drm, 1, "Power well PICA timeout when enabled"); 1881 } 1882 } 1883 1884 static void xe2lpd_pica_power_well_disable(struct intel_display *display, 1885 struct i915_power_well *power_well) 1886 { 1887 intel_de_write(display, XE2LPD_PICA_PW_CTL, 0); 1888 1889 if (intel_de_wait_for_clear(display, XE2LPD_PICA_PW_CTL, 1890 XE2LPD_PICA_CTL_POWER_STATUS, 1)) { 1891 drm_dbg_kms(display->drm, "pica power well disable timeout\n"); 1892 1893 drm_WARN(display->drm, 1, "Power well PICA timeout when disabled"); 1894 } 1895 } 1896 1897 static bool xe2lpd_pica_power_well_enabled(struct intel_display *display, 1898 struct i915_power_well *power_well) 1899 { 1900 return intel_de_read(display, XE2LPD_PICA_PW_CTL) & 1901 XE2LPD_PICA_CTL_POWER_STATUS; 1902 } 1903 1904 const struct i915_power_well_ops i9xx_always_on_power_well_ops = { 1905 .sync_hw = i9xx_power_well_sync_hw_noop, 1906 .enable = i9xx_always_on_power_well_noop, 1907 .disable = i9xx_always_on_power_well_noop, 1908 .is_enabled = i9xx_always_on_power_well_enabled, 1909 }; 1910 1911 const struct i915_power_well_ops chv_pipe_power_well_ops = { 1912 .sync_hw = chv_pipe_power_well_sync_hw, 1913 .enable = chv_pipe_power_well_enable, 1914 .disable = chv_pipe_power_well_disable, 1915 .is_enabled = chv_pipe_power_well_enabled, 1916 }; 1917 1918 const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = { 1919 .sync_hw = i9xx_power_well_sync_hw_noop, 1920 .enable = chv_dpio_cmn_power_well_enable, 1921 .disable = chv_dpio_cmn_power_well_disable, 1922 .is_enabled = vlv_power_well_enabled, 1923 }; 1924 1925 const struct i915_power_well_ops i830_pipes_power_well_ops = { 1926 .sync_hw = i830_pipes_power_well_sync_hw, 1927 .enable = i830_pipes_power_well_enable, 1928 .disable = i830_pipes_power_well_disable, 1929 .is_enabled = i830_pipes_power_well_enabled, 1930 }; 1931 1932 static const struct i915_power_well_regs hsw_power_well_regs = { 1933 .bios = HSW_PWR_WELL_CTL1, 1934 .driver = HSW_PWR_WELL_CTL2, 1935 .kvmr = HSW_PWR_WELL_CTL3, 1936 .debug = HSW_PWR_WELL_CTL4, 1937 }; 1938 1939 const struct i915_power_well_ops hsw_power_well_ops = { 1940 .regs = &hsw_power_well_regs, 1941 .sync_hw = hsw_power_well_sync_hw, 1942 .enable = hsw_power_well_enable, 1943 .disable = hsw_power_well_disable, 1944 .is_enabled = hsw_power_well_enabled, 1945 }; 1946 1947 const struct i915_power_well_ops gen9_dc_off_power_well_ops = { 1948 .sync_hw = i9xx_power_well_sync_hw_noop, 1949 .enable = gen9_dc_off_power_well_enable, 1950 .disable = gen9_dc_off_power_well_disable, 1951 .is_enabled = gen9_dc_off_power_well_enabled, 1952 }; 1953 1954 const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = { 1955 .sync_hw = i9xx_power_well_sync_hw_noop, 1956 .enable = bxt_dpio_cmn_power_well_enable, 1957 .disable = bxt_dpio_cmn_power_well_disable, 1958 .is_enabled = bxt_dpio_cmn_power_well_enabled, 1959 }; 1960 1961 const struct i915_power_well_ops vlv_display_power_well_ops = { 1962 .sync_hw = i9xx_power_well_sync_hw_noop, 1963 .enable = vlv_display_power_well_enable, 1964 .disable = vlv_display_power_well_disable, 1965 .is_enabled = vlv_power_well_enabled, 1966 }; 1967 1968 const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = { 1969 .sync_hw = i9xx_power_well_sync_hw_noop, 1970 .enable = vlv_dpio_cmn_power_well_enable, 1971 .disable = vlv_dpio_cmn_power_well_disable, 1972 .is_enabled = vlv_power_well_enabled, 1973 }; 1974 1975 const struct i915_power_well_ops vlv_dpio_power_well_ops = { 1976 .sync_hw = i9xx_power_well_sync_hw_noop, 1977 .enable = vlv_power_well_enable, 1978 .disable = vlv_power_well_disable, 1979 .is_enabled = vlv_power_well_enabled, 1980 }; 1981 1982 static const struct i915_power_well_regs icl_aux_power_well_regs = { 1983 .bios = ICL_PWR_WELL_CTL_AUX1, 1984 .driver = ICL_PWR_WELL_CTL_AUX2, 1985 .debug = ICL_PWR_WELL_CTL_AUX4, 1986 }; 1987 1988 const struct i915_power_well_ops icl_aux_power_well_ops = { 1989 .regs = &icl_aux_power_well_regs, 1990 .sync_hw = hsw_power_well_sync_hw, 1991 .enable = icl_aux_power_well_enable, 1992 .disable = icl_aux_power_well_disable, 1993 .is_enabled = hsw_power_well_enabled, 1994 }; 1995 1996 static const struct i915_power_well_regs icl_ddi_power_well_regs = { 1997 .bios = ICL_PWR_WELL_CTL_DDI1, 1998 .driver = ICL_PWR_WELL_CTL_DDI2, 1999 .debug = ICL_PWR_WELL_CTL_DDI4, 2000 }; 2001 2002 const struct i915_power_well_ops icl_ddi_power_well_ops = { 2003 .regs = &icl_ddi_power_well_regs, 2004 .sync_hw = hsw_power_well_sync_hw, 2005 .enable = hsw_power_well_enable, 2006 .disable = hsw_power_well_disable, 2007 .is_enabled = hsw_power_well_enabled, 2008 }; 2009 2010 const struct i915_power_well_ops tgl_tc_cold_off_ops = { 2011 .sync_hw = tgl_tc_cold_off_power_well_sync_hw, 2012 .enable = tgl_tc_cold_off_power_well_enable, 2013 .disable = tgl_tc_cold_off_power_well_disable, 2014 .is_enabled = tgl_tc_cold_off_power_well_is_enabled, 2015 }; 2016 2017 const struct i915_power_well_ops xelpdp_aux_power_well_ops = { 2018 .sync_hw = i9xx_power_well_sync_hw_noop, 2019 .enable = xelpdp_aux_power_well_enable, 2020 .disable = xelpdp_aux_power_well_disable, 2021 .is_enabled = xelpdp_aux_power_well_enabled, 2022 }; 2023 2024 const struct i915_power_well_ops xe2lpd_pica_power_well_ops = { 2025 .sync_hw = i9xx_power_well_sync_hw_noop, 2026 .enable = xe2lpd_pica_power_well_enable, 2027 .disable = xe2lpd_pica_power_well_disable, 2028 .is_enabled = xe2lpd_pica_power_well_enabled, 2029 }; 2030