1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright © 2006-2011 Intel Corporation 4 * 5 * Authors: 6 * Eric Anholt <eric@anholt.net> 7 */ 8 9 #include <linux/delay.h> 10 #include <linux/i2c.h> 11 12 #include <drm/drm_modeset_helper.h> 13 #include <drm/drm_modeset_helper_vtables.h> 14 #include <drm/drm_print.h> 15 16 #include "framebuffer.h" 17 #include "gem.h" 18 #include "gma_display.h" 19 #include "power.h" 20 #include "psb_drv.h" 21 #include "psb_intel_drv.h" 22 #include "psb_intel_reg.h" 23 24 #define INTEL_LIMIT_I9XX_SDVO_DAC 0 25 #define INTEL_LIMIT_I9XX_LVDS 1 26 27 static const struct gma_limit_t psb_intel_limits[] = { 28 { /* INTEL_LIMIT_I9XX_SDVO_DAC */ 29 .dot = {.min = 20000, .max = 400000}, 30 .vco = {.min = 1400000, .max = 2800000}, 31 .n = {.min = 1, .max = 6}, 32 .m = {.min = 70, .max = 120}, 33 .m1 = {.min = 8, .max = 18}, 34 .m2 = {.min = 3, .max = 7}, 35 .p = {.min = 5, .max = 80}, 36 .p1 = {.min = 1, .max = 8}, 37 .p2 = {.dot_limit = 200000, .p2_slow = 10, .p2_fast = 5}, 38 .find_pll = gma_find_best_pll, 39 }, 40 { /* INTEL_LIMIT_I9XX_LVDS */ 41 .dot = {.min = 20000, .max = 400000}, 42 .vco = {.min = 1400000, .max = 2800000}, 43 .n = {.min = 1, .max = 6}, 44 .m = {.min = 70, .max = 120}, 45 .m1 = {.min = 8, .max = 18}, 46 .m2 = {.min = 3, .max = 7}, 47 .p = {.min = 7, .max = 98}, 48 .p1 = {.min = 1, .max = 8}, 49 /* The single-channel range is 25-112Mhz, and dual-channel 50 * is 80-224Mhz. Prefer single channel as much as possible. 51 */ 52 .p2 = {.dot_limit = 112000, .p2_slow = 14, .p2_fast = 7}, 53 .find_pll = gma_find_best_pll, 54 }, 55 }; 56 57 static const struct gma_limit_t *psb_intel_limit(struct drm_crtc *crtc, 58 int refclk) 59 { 60 const struct gma_limit_t *limit; 61 62 if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) 63 limit = &psb_intel_limits[INTEL_LIMIT_I9XX_LVDS]; 64 else 65 limit = &psb_intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC]; 66 return limit; 67 } 68 69 static void psb_intel_clock(int refclk, struct gma_clock_t *clock) 70 { 71 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); 72 clock->p = clock->p1 * clock->p2; 73 clock->vco = refclk * clock->m / (clock->n + 2); 74 clock->dot = clock->vco / clock->p; 75 } 76 77 /* 78 * Return the pipe currently connected to the panel fitter, 79 * or -1 if the panel fitter is not present or not in use 80 */ 81 static int psb_intel_panel_fitter_pipe(struct drm_device *dev) 82 { 83 u32 pfit_control; 84 85 pfit_control = REG_READ(PFIT_CONTROL); 86 87 /* See if the panel fitter is in use */ 88 if ((pfit_control & PFIT_ENABLE) == 0) 89 return -1; 90 /* Must be on PIPE 1 for PSB */ 91 return 1; 92 } 93 94 static int psb_intel_crtc_mode_set(struct drm_crtc *crtc, 95 struct drm_display_mode *mode, 96 struct drm_display_mode *adjusted_mode, 97 int x, int y, 98 struct drm_framebuffer *old_fb) 99 { 100 struct drm_device *dev = crtc->dev; 101 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 102 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 103 const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; 104 int pipe = gma_crtc->pipe; 105 const struct psb_offset *map = &dev_priv->regmap[pipe]; 106 int refclk; 107 struct gma_clock_t clock; 108 u32 dpll = 0, fp = 0, dspcntr, pipeconf; 109 bool ok, is_sdvo = false; 110 bool is_lvds = false, is_tv = false; 111 struct drm_connector_list_iter conn_iter; 112 struct drm_connector *connector; 113 const struct gma_limit_t *limit; 114 115 /* No scan out no play */ 116 if (crtc->primary->fb == NULL) { 117 crtc_funcs->mode_set_base(crtc, x, y, old_fb); 118 return 0; 119 } 120 121 drm_connector_list_iter_begin(dev, &conn_iter); 122 drm_for_each_connector_iter(connector, &conn_iter) { 123 struct gma_encoder *gma_encoder = gma_attached_encoder(connector); 124 125 if (!connector->encoder 126 || connector->encoder->crtc != crtc) 127 continue; 128 129 switch (gma_encoder->type) { 130 case INTEL_OUTPUT_LVDS: 131 is_lvds = true; 132 break; 133 case INTEL_OUTPUT_SDVO: 134 is_sdvo = true; 135 break; 136 case INTEL_OUTPUT_TVOUT: 137 is_tv = true; 138 break; 139 } 140 141 break; 142 } 143 drm_connector_list_iter_end(&conn_iter); 144 145 refclk = 96000; 146 147 limit = gma_crtc->clock_funcs->limit(crtc, refclk); 148 149 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, 150 &clock); 151 if (!ok) { 152 DRM_ERROR("Couldn't find PLL settings for mode! target: %d, actual: %d", 153 adjusted_mode->clock, clock.dot); 154 return 0; 155 } 156 157 fp = clock.n << 16 | clock.m1 << 8 | clock.m2; 158 159 dpll = DPLL_VGA_MODE_DIS; 160 if (is_lvds) { 161 dpll |= DPLLB_MODE_LVDS; 162 dpll |= DPLL_DVO_HIGH_SPEED; 163 } else 164 dpll |= DPLLB_MODE_DAC_SERIAL; 165 if (is_sdvo) { 166 int sdvo_pixel_multiply = 167 adjusted_mode->clock / mode->clock; 168 dpll |= DPLL_DVO_HIGH_SPEED; 169 dpll |= 170 (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; 171 } 172 173 /* compute bitmask from p1 value */ 174 dpll |= (1 << (clock.p1 - 1)) << 16; 175 switch (clock.p2) { 176 case 5: 177 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; 178 break; 179 case 7: 180 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; 181 break; 182 case 10: 183 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; 184 break; 185 case 14: 186 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; 187 break; 188 } 189 190 if (is_tv) { 191 /* XXX: just matching BIOS for now */ 192 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ 193 dpll |= 3; 194 } 195 dpll |= PLL_REF_INPUT_DREFCLK; 196 197 /* setup pipeconf */ 198 pipeconf = REG_READ(map->conf); 199 200 /* Set up the display plane register */ 201 dspcntr = DISPPLANE_GAMMA_ENABLE; 202 203 if (pipe == 0) 204 dspcntr |= DISPPLANE_SEL_PIPE_A; 205 else 206 dspcntr |= DISPPLANE_SEL_PIPE_B; 207 208 dspcntr |= DISPLAY_PLANE_ENABLE; 209 pipeconf |= PIPEACONF_ENABLE; 210 dpll |= DPLL_VCO_ENABLE; 211 212 213 /* Disable the panel fitter if it was on our pipe */ 214 if (psb_intel_panel_fitter_pipe(dev) == pipe) 215 REG_WRITE(PFIT_CONTROL, 0); 216 217 drm_mode_debug_printmodeline(mode); 218 219 if (dpll & DPLL_VCO_ENABLE) { 220 REG_WRITE(map->fp0, fp); 221 REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE); 222 REG_READ(map->dpll); 223 udelay(150); 224 } 225 226 /* The LVDS pin pair needs to be on before the DPLLs are enabled. 227 * This is an exception to the general rule that mode_set doesn't turn 228 * things on. 229 */ 230 if (is_lvds) { 231 u32 lvds = REG_READ(LVDS); 232 233 lvds &= ~LVDS_PIPEB_SELECT; 234 if (pipe == 1) 235 lvds |= LVDS_PIPEB_SELECT; 236 237 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; 238 /* Set the B0-B3 data pairs corresponding to 239 * whether we're going to 240 * set the DPLLs for dual-channel mode or not. 241 */ 242 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); 243 if (clock.p2 == 7) 244 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; 245 246 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) 247 * appropriately here, but we need to look more 248 * thoroughly into how panels behave in the two modes. 249 */ 250 251 REG_WRITE(LVDS, lvds); 252 REG_READ(LVDS); 253 } 254 255 REG_WRITE(map->fp0, fp); 256 REG_WRITE(map->dpll, dpll); 257 REG_READ(map->dpll); 258 /* Wait for the clocks to stabilize. */ 259 udelay(150); 260 261 /* write it again -- the BIOS does, after all */ 262 REG_WRITE(map->dpll, dpll); 263 264 REG_READ(map->dpll); 265 /* Wait for the clocks to stabilize. */ 266 udelay(150); 267 268 REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) | 269 ((adjusted_mode->crtc_htotal - 1) << 16)); 270 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) | 271 ((adjusted_mode->crtc_hblank_end - 1) << 16)); 272 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) | 273 ((adjusted_mode->crtc_hsync_end - 1) << 16)); 274 REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) | 275 ((adjusted_mode->crtc_vtotal - 1) << 16)); 276 REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) | 277 ((adjusted_mode->crtc_vblank_end - 1) << 16)); 278 REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) | 279 ((adjusted_mode->crtc_vsync_end - 1) << 16)); 280 /* pipesrc and dspsize control the size that is scaled from, 281 * which should always be the user's requested size. 282 */ 283 REG_WRITE(map->size, 284 ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1)); 285 REG_WRITE(map->pos, 0); 286 REG_WRITE(map->src, 287 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); 288 REG_WRITE(map->conf, pipeconf); 289 REG_READ(map->conf); 290 291 gma_wait_for_vblank(dev); 292 293 REG_WRITE(map->cntr, dspcntr); 294 295 /* Flush the plane changes */ 296 crtc_funcs->mode_set_base(crtc, x, y, old_fb); 297 298 gma_wait_for_vblank(dev); 299 300 return 0; 301 } 302 303 /* Returns the clock of the currently programmed mode of the given pipe. */ 304 static int psb_intel_crtc_clock_get(struct drm_device *dev, 305 struct drm_crtc *crtc) 306 { 307 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 308 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 309 int pipe = gma_crtc->pipe; 310 const struct psb_offset *map = &dev_priv->regmap[pipe]; 311 u32 dpll; 312 u32 fp; 313 struct gma_clock_t clock; 314 bool is_lvds; 315 struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; 316 317 if (gma_power_begin(dev, false)) { 318 dpll = REG_READ(map->dpll); 319 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 320 fp = REG_READ(map->fp0); 321 else 322 fp = REG_READ(map->fp1); 323 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN); 324 gma_power_end(dev); 325 } else { 326 dpll = p->dpll; 327 328 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 329 fp = p->fp0; 330 else 331 fp = p->fp1; 332 333 is_lvds = (pipe == 1) && (dev_priv->regs.psb.saveLVDS & 334 LVDS_PORT_EN); 335 } 336 337 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 338 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; 339 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; 340 341 if (is_lvds) { 342 clock.p1 = 343 ffs((dpll & 344 DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> 345 DPLL_FPA01_P1_POST_DIV_SHIFT); 346 clock.p2 = 14; 347 348 if ((dpll & PLL_REF_INPUT_MASK) == 349 PLLB_REF_INPUT_SPREADSPECTRUMIN) { 350 /* XXX: might not be 66MHz */ 351 psb_intel_clock(66000, &clock); 352 } else 353 psb_intel_clock(48000, &clock); 354 } else { 355 if (dpll & PLL_P1_DIVIDE_BY_TWO) 356 clock.p1 = 2; 357 else { 358 clock.p1 = 359 ((dpll & 360 DPLL_FPA01_P1_POST_DIV_MASK_I830) >> 361 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; 362 } 363 if (dpll & PLL_P2_DIVIDE_BY_4) 364 clock.p2 = 4; 365 else 366 clock.p2 = 2; 367 368 psb_intel_clock(48000, &clock); 369 } 370 371 /* XXX: It would be nice to validate the clocks, but we can't reuse 372 * i830PllIsValid() because it relies on the xf86_config connector 373 * configuration being accurate, which it isn't necessarily. 374 */ 375 376 return clock.dot; 377 } 378 379 /** Returns the currently programmed mode of the given pipe. */ 380 struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev, 381 struct drm_crtc *crtc) 382 { 383 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 384 int pipe = gma_crtc->pipe; 385 struct drm_display_mode *mode; 386 int htot; 387 int hsync; 388 int vtot; 389 int vsync; 390 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 391 struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; 392 const struct psb_offset *map = &dev_priv->regmap[pipe]; 393 394 if (gma_power_begin(dev, false)) { 395 htot = REG_READ(map->htotal); 396 hsync = REG_READ(map->hsync); 397 vtot = REG_READ(map->vtotal); 398 vsync = REG_READ(map->vsync); 399 gma_power_end(dev); 400 } else { 401 htot = p->htotal; 402 hsync = p->hsync; 403 vtot = p->vtotal; 404 vsync = p->vsync; 405 } 406 407 mode = kzalloc(sizeof(*mode), GFP_KERNEL); 408 if (!mode) 409 return NULL; 410 411 mode->clock = psb_intel_crtc_clock_get(dev, crtc); 412 mode->hdisplay = (htot & 0xffff) + 1; 413 mode->htotal = ((htot & 0xffff0000) >> 16) + 1; 414 mode->hsync_start = (hsync & 0xffff) + 1; 415 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; 416 mode->vdisplay = (vtot & 0xffff) + 1; 417 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; 418 mode->vsync_start = (vsync & 0xffff) + 1; 419 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; 420 421 drm_mode_set_name(mode); 422 drm_mode_set_crtcinfo(mode, 0); 423 424 return mode; 425 } 426 427 const struct drm_crtc_helper_funcs psb_intel_helper_funcs = { 428 .dpms = gma_crtc_dpms, 429 .mode_set = psb_intel_crtc_mode_set, 430 .mode_set_base = gma_pipe_set_base, 431 .prepare = gma_crtc_prepare, 432 .commit = gma_crtc_commit, 433 .disable = gma_crtc_disable, 434 }; 435 436 const struct gma_clock_funcs psb_clock_funcs = { 437 .clock = psb_intel_clock, 438 .limit = psb_intel_limit, 439 .pll_is_valid = gma_pll_is_valid, 440 }; 441 442 /* 443 * Set the default value of cursor control and base register 444 * to zero. This is a workaround for h/w defect on Oaktrail 445 */ 446 static void psb_intel_cursor_init(struct drm_device *dev, 447 struct gma_crtc *gma_crtc) 448 { 449 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 450 u32 control[3] = { CURACNTR, CURBCNTR, CURCCNTR }; 451 u32 base[3] = { CURABASE, CURBBASE, CURCBASE }; 452 struct psb_gem_object *cursor_pobj; 453 454 if (dev_priv->ops->cursor_needs_phys) { 455 /* Allocate 4 pages of stolen mem for a hardware cursor. That 456 * is enough for the 64 x 64 ARGB cursors we support. 457 */ 458 cursor_pobj = psb_gem_create(dev, 4 * PAGE_SIZE, "cursor", true, PAGE_SIZE); 459 if (IS_ERR(cursor_pobj)) { 460 gma_crtc->cursor_pobj = NULL; 461 goto out; 462 } 463 gma_crtc->cursor_pobj = cursor_pobj; 464 gma_crtc->cursor_addr = dev_priv->stolen_base + cursor_pobj->offset; 465 } else { 466 gma_crtc->cursor_pobj = NULL; 467 } 468 469 out: 470 REG_WRITE(control[gma_crtc->pipe], 0); 471 REG_WRITE(base[gma_crtc->pipe], 0); 472 } 473 474 void psb_intel_crtc_init(struct drm_device *dev, int pipe, 475 struct psb_intel_mode_device *mode_dev) 476 { 477 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 478 struct gma_crtc *gma_crtc; 479 int i; 480 481 /* We allocate a extra array of drm_connector pointers 482 * for fbdev after the crtc */ 483 gma_crtc = kzalloc(sizeof(struct gma_crtc) + 484 (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), 485 GFP_KERNEL); 486 if (gma_crtc == NULL) 487 return; 488 489 gma_crtc->crtc_state = 490 kzalloc(sizeof(struct psb_intel_crtc_state), GFP_KERNEL); 491 if (!gma_crtc->crtc_state) { 492 dev_err(dev->dev, "Crtc state error: No memory\n"); 493 kfree(gma_crtc); 494 return; 495 } 496 497 drm_crtc_init(dev, &gma_crtc->base, &gma_crtc_funcs); 498 499 /* Set the CRTC clock functions from chip specific data */ 500 gma_crtc->clock_funcs = dev_priv->ops->clock_funcs; 501 502 drm_mode_crtc_set_gamma_size(&gma_crtc->base, 256); 503 gma_crtc->pipe = pipe; 504 gma_crtc->plane = pipe; 505 506 for (i = 0; i < 256; i++) 507 gma_crtc->lut_adj[i] = 0; 508 509 gma_crtc->mode_dev = mode_dev; 510 gma_crtc->cursor_addr = 0; 511 512 drm_crtc_helper_add(&gma_crtc->base, 513 dev_priv->ops->crtc_helper); 514 515 /* Setup the array of drm_connector pointer array */ 516 gma_crtc->mode_set.crtc = &gma_crtc->base; 517 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || 518 dev_priv->plane_to_crtc_mapping[gma_crtc->plane] != NULL); 519 dev_priv->plane_to_crtc_mapping[gma_crtc->plane] = &gma_crtc->base; 520 dev_priv->pipe_to_crtc_mapping[gma_crtc->pipe] = &gma_crtc->base; 521 gma_crtc->mode_set.connectors = (struct drm_connector **)(gma_crtc + 1); 522 gma_crtc->mode_set.num_connectors = 0; 523 psb_intel_cursor_init(dev, gma_crtc); 524 525 /* Set to true so that the pipe is forced off on initial config. */ 526 gma_crtc->active = true; 527 } 528 529 struct drm_crtc *psb_intel_get_crtc_from_pipe(struct drm_device *dev, int pipe) 530 { 531 struct drm_crtc *crtc; 532 533 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 534 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 535 536 if (gma_crtc->pipe == pipe) 537 return crtc; 538 } 539 return NULL; 540 } 541 542 int gma_connector_clones(struct drm_device *dev, int type_mask) 543 { 544 struct drm_connector_list_iter conn_iter; 545 struct drm_connector *connector; 546 int index_mask = 0; 547 int entry = 0; 548 549 drm_connector_list_iter_begin(dev, &conn_iter); 550 drm_for_each_connector_iter(connector, &conn_iter) { 551 struct gma_encoder *gma_encoder = gma_attached_encoder(connector); 552 if (type_mask & (1 << gma_encoder->type)) 553 index_mask |= (1 << entry); 554 entry++; 555 } 556 drm_connector_list_iter_end(&conn_iter); 557 558 return index_mask; 559 } 560