1 /* drivers/gpu/drm/exynos5433_drm_decon.c 2 * 3 * Copyright (C) 2015 Samsung Electronics Co.Ltd 4 * Authors: 5 * Joonyoung Shim <jy0922.shim@samsung.com> 6 * Hyungwon Hwang <human.hwang@samsung.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundationr 11 */ 12 13 #include <linux/platform_device.h> 14 #include <linux/clk.h> 15 #include <linux/component.h> 16 #include <linux/of_device.h> 17 #include <linux/of_gpio.h> 18 #include <linux/pm_runtime.h> 19 20 #include <video/exynos5433_decon.h> 21 22 #include "exynos_drm_drv.h" 23 #include "exynos_drm_crtc.h" 24 #include "exynos_drm_fb.h" 25 #include "exynos_drm_plane.h" 26 #include "exynos_drm_iommu.h" 27 28 #define WINDOWS_NR 3 29 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128 30 31 #define IFTYPE_I80 (1 << 0) 32 #define I80_HW_TRG (1 << 1) 33 #define IFTYPE_HDMI (1 << 2) 34 35 static const char * const decon_clks_name[] = { 36 "pclk", 37 "aclk_decon", 38 "aclk_smmu_decon0x", 39 "aclk_xiu_decon0x", 40 "pclk_smmu_decon0x", 41 "sclk_decon_vclk", 42 "sclk_decon_eclk", 43 }; 44 45 enum decon_flag_bits { 46 BIT_CLKS_ENABLED, 47 BIT_IRQS_ENABLED, 48 BIT_WIN_UPDATED, 49 BIT_SUSPENDED, 50 BIT_REQUEST_UPDATE 51 }; 52 53 struct decon_context { 54 struct device *dev; 55 struct drm_device *drm_dev; 56 struct exynos_drm_crtc *crtc; 57 struct exynos_drm_plane planes[WINDOWS_NR]; 58 struct exynos_drm_plane_config configs[WINDOWS_NR]; 59 void __iomem *addr; 60 struct clk *clks[ARRAY_SIZE(decon_clks_name)]; 61 int pipe; 62 unsigned long flags; 63 unsigned long out_type; 64 int first_win; 65 }; 66 67 static const uint32_t decon_formats[] = { 68 DRM_FORMAT_XRGB1555, 69 DRM_FORMAT_RGB565, 70 DRM_FORMAT_XRGB8888, 71 DRM_FORMAT_ARGB8888, 72 }; 73 74 static const enum drm_plane_type decon_win_types[WINDOWS_NR] = { 75 DRM_PLANE_TYPE_PRIMARY, 76 DRM_PLANE_TYPE_OVERLAY, 77 DRM_PLANE_TYPE_CURSOR, 78 }; 79 80 static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask, 81 u32 val) 82 { 83 val = (val & mask) | (readl(ctx->addr + reg) & ~mask); 84 writel(val, ctx->addr + reg); 85 } 86 87 static int decon_enable_vblank(struct exynos_drm_crtc *crtc) 88 { 89 struct decon_context *ctx = crtc->ctx; 90 u32 val; 91 92 if (test_bit(BIT_SUSPENDED, &ctx->flags)) 93 return -EPERM; 94 95 if (!test_and_set_bit(BIT_IRQS_ENABLED, &ctx->flags)) { 96 val = VIDINTCON0_INTEN; 97 if (ctx->out_type & IFTYPE_I80) 98 val |= VIDINTCON0_FRAMEDONE; 99 else 100 val |= VIDINTCON0_INTFRMEN; 101 102 writel(val, ctx->addr + DECON_VIDINTCON0); 103 } 104 105 return 0; 106 } 107 108 static void decon_disable_vblank(struct exynos_drm_crtc *crtc) 109 { 110 struct decon_context *ctx = crtc->ctx; 111 112 if (test_bit(BIT_SUSPENDED, &ctx->flags)) 113 return; 114 115 if (test_and_clear_bit(BIT_IRQS_ENABLED, &ctx->flags)) 116 writel(0, ctx->addr + DECON_VIDINTCON0); 117 } 118 119 static void decon_setup_trigger(struct decon_context *ctx) 120 { 121 u32 val = !(ctx->out_type & I80_HW_TRG) 122 ? TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F | 123 TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN 124 : TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F | 125 TRIGCON_HWTRIGMASK | TRIGCON_HWTRIGEN; 126 writel(val, ctx->addr + DECON_TRIGCON); 127 } 128 129 static void decon_commit(struct exynos_drm_crtc *crtc) 130 { 131 struct decon_context *ctx = crtc->ctx; 132 struct drm_display_mode *m = &crtc->base.mode; 133 u32 val; 134 135 if (test_bit(BIT_SUSPENDED, &ctx->flags)) 136 return; 137 138 if (ctx->out_type & IFTYPE_HDMI) { 139 m->crtc_hsync_start = m->crtc_hdisplay + 10; 140 m->crtc_hsync_end = m->crtc_htotal - 92; 141 m->crtc_vsync_start = m->crtc_vdisplay + 1; 142 m->crtc_vsync_end = m->crtc_vsync_start + 1; 143 } 144 145 if (ctx->out_type & (IFTYPE_I80 | I80_HW_TRG)) 146 decon_setup_trigger(ctx); 147 148 /* lcd on and use command if */ 149 val = VIDOUT_LCD_ON; 150 if (ctx->out_type & IFTYPE_I80) { 151 val |= VIDOUT_COMMAND_IF; 152 } else { 153 val |= VIDOUT_RGB_IF; 154 } 155 156 writel(val, ctx->addr + DECON_VIDOUTCON0); 157 158 val = VIDTCON2_LINEVAL(m->vdisplay - 1) | 159 VIDTCON2_HOZVAL(m->hdisplay - 1); 160 writel(val, ctx->addr + DECON_VIDTCON2); 161 162 if (!(ctx->out_type & IFTYPE_I80)) { 163 val = VIDTCON00_VBPD_F( 164 m->crtc_vtotal - m->crtc_vsync_end - 1) | 165 VIDTCON00_VFPD_F( 166 m->crtc_vsync_start - m->crtc_vdisplay - 1); 167 writel(val, ctx->addr + DECON_VIDTCON00); 168 169 val = VIDTCON01_VSPW_F( 170 m->crtc_vsync_end - m->crtc_vsync_start - 1); 171 writel(val, ctx->addr + DECON_VIDTCON01); 172 173 val = VIDTCON10_HBPD_F( 174 m->crtc_htotal - m->crtc_hsync_end - 1) | 175 VIDTCON10_HFPD_F( 176 m->crtc_hsync_start - m->crtc_hdisplay - 1); 177 writel(val, ctx->addr + DECON_VIDTCON10); 178 179 val = VIDTCON11_HSPW_F( 180 m->crtc_hsync_end - m->crtc_hsync_start - 1); 181 writel(val, ctx->addr + DECON_VIDTCON11); 182 } 183 184 /* enable output and display signal */ 185 decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID | VIDCON0_ENVID_F, ~0); 186 187 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0); 188 } 189 190 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win, 191 struct drm_framebuffer *fb) 192 { 193 unsigned long val; 194 195 val = readl(ctx->addr + DECON_WINCONx(win)); 196 val &= ~WINCONx_BPPMODE_MASK; 197 198 switch (fb->pixel_format) { 199 case DRM_FORMAT_XRGB1555: 200 val |= WINCONx_BPPMODE_16BPP_I1555; 201 val |= WINCONx_HAWSWP_F; 202 val |= WINCONx_BURSTLEN_16WORD; 203 break; 204 case DRM_FORMAT_RGB565: 205 val |= WINCONx_BPPMODE_16BPP_565; 206 val |= WINCONx_HAWSWP_F; 207 val |= WINCONx_BURSTLEN_16WORD; 208 break; 209 case DRM_FORMAT_XRGB8888: 210 val |= WINCONx_BPPMODE_24BPP_888; 211 val |= WINCONx_WSWP_F; 212 val |= WINCONx_BURSTLEN_16WORD; 213 break; 214 case DRM_FORMAT_ARGB8888: 215 val |= WINCONx_BPPMODE_32BPP_A8888; 216 val |= WINCONx_WSWP_F | WINCONx_BLD_PIX_F | WINCONx_ALPHA_SEL_F; 217 val |= WINCONx_BURSTLEN_16WORD; 218 break; 219 default: 220 DRM_ERROR("Proper pixel format is not set\n"); 221 return; 222 } 223 224 DRM_DEBUG_KMS("bpp = %u\n", fb->bits_per_pixel); 225 226 /* 227 * In case of exynos, setting dma-burst to 16Word causes permanent 228 * tearing for very small buffers, e.g. cursor buffer. Burst Mode 229 * switching which is based on plane size is not recommended as 230 * plane size varies a lot towards the end of the screen and rapid 231 * movement causes unstable DMA which results into iommu crash/tear. 232 */ 233 234 if (fb->width < MIN_FB_WIDTH_FOR_16WORD_BURST) { 235 val &= ~WINCONx_BURSTLEN_MASK; 236 val |= WINCONx_BURSTLEN_8WORD; 237 } 238 239 writel(val, ctx->addr + DECON_WINCONx(win)); 240 } 241 242 static void decon_shadow_protect_win(struct decon_context *ctx, int win, 243 bool protect) 244 { 245 decon_set_bits(ctx, DECON_SHADOWCON, SHADOWCON_Wx_PROTECT(win), 246 protect ? ~0 : 0); 247 } 248 249 static void decon_atomic_begin(struct exynos_drm_crtc *crtc) 250 { 251 struct decon_context *ctx = crtc->ctx; 252 int i; 253 254 if (test_bit(BIT_SUSPENDED, &ctx->flags)) 255 return; 256 257 for (i = ctx->first_win; i < WINDOWS_NR; i++) 258 decon_shadow_protect_win(ctx, i, true); 259 } 260 261 #define BIT_VAL(x, e, s) (((x) & ((1 << ((e) - (s) + 1)) - 1)) << (s)) 262 #define COORDINATE_X(x) BIT_VAL((x), 23, 12) 263 #define COORDINATE_Y(x) BIT_VAL((x), 11, 0) 264 265 static void decon_update_plane(struct exynos_drm_crtc *crtc, 266 struct exynos_drm_plane *plane) 267 { 268 struct exynos_drm_plane_state *state = 269 to_exynos_plane_state(plane->base.state); 270 struct decon_context *ctx = crtc->ctx; 271 struct drm_framebuffer *fb = state->base.fb; 272 unsigned int win = plane->index; 273 unsigned int bpp = fb->bits_per_pixel >> 3; 274 unsigned int pitch = fb->pitches[0]; 275 dma_addr_t dma_addr = exynos_drm_fb_dma_addr(fb, 0); 276 u32 val; 277 278 if (test_bit(BIT_SUSPENDED, &ctx->flags)) 279 return; 280 281 val = COORDINATE_X(state->crtc.x) | COORDINATE_Y(state->crtc.y); 282 writel(val, ctx->addr + DECON_VIDOSDxA(win)); 283 284 val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) | 285 COORDINATE_Y(state->crtc.y + state->crtc.h - 1); 286 writel(val, ctx->addr + DECON_VIDOSDxB(win)); 287 288 val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) | 289 VIDOSD_Wx_ALPHA_B_F(0x0); 290 writel(val, ctx->addr + DECON_VIDOSDxC(win)); 291 292 val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) | 293 VIDOSD_Wx_ALPHA_B_F(0x0); 294 writel(val, ctx->addr + DECON_VIDOSDxD(win)); 295 296 writel(dma_addr, ctx->addr + DECON_VIDW0xADD0B0(win)); 297 298 val = dma_addr + pitch * state->src.h; 299 writel(val, ctx->addr + DECON_VIDW0xADD1B0(win)); 300 301 if (!(ctx->out_type & IFTYPE_HDMI)) 302 val = BIT_VAL(pitch - state->crtc.w * bpp, 27, 14) 303 | BIT_VAL(state->crtc.w * bpp, 13, 0); 304 else 305 val = BIT_VAL(pitch - state->crtc.w * bpp, 29, 15) 306 | BIT_VAL(state->crtc.w * bpp, 14, 0); 307 writel(val, ctx->addr + DECON_VIDW0xADD2(win)); 308 309 decon_win_set_pixfmt(ctx, win, fb); 310 311 /* window enable */ 312 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, ~0); 313 set_bit(BIT_REQUEST_UPDATE, &ctx->flags); 314 } 315 316 static void decon_disable_plane(struct exynos_drm_crtc *crtc, 317 struct exynos_drm_plane *plane) 318 { 319 struct decon_context *ctx = crtc->ctx; 320 unsigned int win = plane->index; 321 322 if (test_bit(BIT_SUSPENDED, &ctx->flags)) 323 return; 324 325 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0); 326 set_bit(BIT_REQUEST_UPDATE, &ctx->flags); 327 } 328 329 static void decon_atomic_flush(struct exynos_drm_crtc *crtc) 330 { 331 struct decon_context *ctx = crtc->ctx; 332 int i; 333 334 if (test_bit(BIT_SUSPENDED, &ctx->flags)) 335 return; 336 337 for (i = ctx->first_win; i < WINDOWS_NR; i++) 338 decon_shadow_protect_win(ctx, i, false); 339 340 if (test_and_clear_bit(BIT_REQUEST_UPDATE, &ctx->flags)) 341 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0); 342 343 if (ctx->out_type & IFTYPE_I80) 344 set_bit(BIT_WIN_UPDATED, &ctx->flags); 345 } 346 347 static void decon_swreset(struct decon_context *ctx) 348 { 349 unsigned int tries; 350 351 writel(0, ctx->addr + DECON_VIDCON0); 352 for (tries = 2000; tries; --tries) { 353 if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_STOP_STATUS) 354 break; 355 udelay(10); 356 } 357 358 WARN(tries == 0, "failed to disable DECON\n"); 359 360 writel(VIDCON0_SWRESET, ctx->addr + DECON_VIDCON0); 361 for (tries = 2000; tries; --tries) { 362 if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_SWRESET) 363 break; 364 udelay(10); 365 } 366 367 WARN(tries == 0, "failed to software reset DECON\n"); 368 369 if (!(ctx->out_type & IFTYPE_HDMI)) 370 return; 371 372 writel(VIDCON0_CLKVALUP | VIDCON0_VLCKFREE, ctx->addr + DECON_VIDCON0); 373 decon_set_bits(ctx, DECON_CMU, 374 CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F, ~0); 375 writel(VIDCON1_VCLK_RUN_VDEN_DISABLE, ctx->addr + DECON_VIDCON1); 376 writel(CRCCTRL_CRCEN | CRCCTRL_CRCSTART_F | CRCCTRL_CRCCLKEN, 377 ctx->addr + DECON_CRCCTRL); 378 } 379 380 static void decon_enable(struct exynos_drm_crtc *crtc) 381 { 382 struct decon_context *ctx = crtc->ctx; 383 384 if (!test_and_clear_bit(BIT_SUSPENDED, &ctx->flags)) 385 return; 386 387 pm_runtime_get_sync(ctx->dev); 388 389 exynos_drm_pipe_clk_enable(crtc, true); 390 391 set_bit(BIT_CLKS_ENABLED, &ctx->flags); 392 393 decon_swreset(ctx); 394 395 /* if vblank was enabled status, enable it again. */ 396 if (test_and_clear_bit(BIT_IRQS_ENABLED, &ctx->flags)) 397 decon_enable_vblank(ctx->crtc); 398 399 decon_commit(ctx->crtc); 400 } 401 402 static void decon_disable(struct exynos_drm_crtc *crtc) 403 { 404 struct decon_context *ctx = crtc->ctx; 405 int i; 406 407 if (test_bit(BIT_SUSPENDED, &ctx->flags)) 408 return; 409 410 /* 411 * We need to make sure that all windows are disabled before we 412 * suspend that connector. Otherwise we might try to scan from 413 * a destroyed buffer later. 414 */ 415 for (i = ctx->first_win; i < WINDOWS_NR; i++) 416 decon_disable_plane(crtc, &ctx->planes[i]); 417 418 decon_swreset(ctx); 419 420 clear_bit(BIT_CLKS_ENABLED, &ctx->flags); 421 422 exynos_drm_pipe_clk_enable(crtc, false); 423 424 pm_runtime_put_sync(ctx->dev); 425 426 set_bit(BIT_SUSPENDED, &ctx->flags); 427 } 428 429 static void decon_te_irq_handler(struct exynos_drm_crtc *crtc) 430 { 431 struct decon_context *ctx = crtc->ctx; 432 433 if (!test_bit(BIT_CLKS_ENABLED, &ctx->flags) || 434 (ctx->out_type & I80_HW_TRG)) 435 return; 436 437 if (test_and_clear_bit(BIT_WIN_UPDATED, &ctx->flags)) 438 decon_set_bits(ctx, DECON_TRIGCON, TRIGCON_SWTRIGCMD, ~0); 439 } 440 441 static void decon_clear_channels(struct exynos_drm_crtc *crtc) 442 { 443 struct decon_context *ctx = crtc->ctx; 444 int win, i, ret; 445 446 DRM_DEBUG_KMS("%s\n", __FILE__); 447 448 for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) { 449 ret = clk_prepare_enable(ctx->clks[i]); 450 if (ret < 0) 451 goto err; 452 } 453 454 for (win = 0; win < WINDOWS_NR; win++) { 455 decon_shadow_protect_win(ctx, win, true); 456 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0); 457 decon_shadow_protect_win(ctx, win, false); 458 } 459 460 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0); 461 462 /* TODO: wait for possible vsync */ 463 msleep(50); 464 465 err: 466 while (--i >= 0) 467 clk_disable_unprepare(ctx->clks[i]); 468 } 469 470 static struct exynos_drm_crtc_ops decon_crtc_ops = { 471 .enable = decon_enable, 472 .disable = decon_disable, 473 .enable_vblank = decon_enable_vblank, 474 .disable_vblank = decon_disable_vblank, 475 .atomic_begin = decon_atomic_begin, 476 .update_plane = decon_update_plane, 477 .disable_plane = decon_disable_plane, 478 .atomic_flush = decon_atomic_flush, 479 .te_handler = decon_te_irq_handler, 480 }; 481 482 static int decon_bind(struct device *dev, struct device *master, void *data) 483 { 484 struct decon_context *ctx = dev_get_drvdata(dev); 485 struct drm_device *drm_dev = data; 486 struct exynos_drm_private *priv = drm_dev->dev_private; 487 struct exynos_drm_plane *exynos_plane; 488 enum exynos_drm_output_type out_type; 489 unsigned int win; 490 int ret; 491 492 ctx->drm_dev = drm_dev; 493 ctx->pipe = priv->pipe++; 494 495 for (win = ctx->first_win; win < WINDOWS_NR; win++) { 496 int tmp = (win == ctx->first_win) ? 0 : win; 497 498 ctx->configs[win].pixel_formats = decon_formats; 499 ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats); 500 ctx->configs[win].zpos = win; 501 ctx->configs[win].type = decon_win_types[tmp]; 502 503 ret = exynos_plane_init(drm_dev, &ctx->planes[win], win, 504 1 << ctx->pipe, &ctx->configs[win]); 505 if (ret) 506 return ret; 507 } 508 509 exynos_plane = &ctx->planes[ctx->first_win]; 510 out_type = (ctx->out_type & IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI 511 : EXYNOS_DISPLAY_TYPE_LCD; 512 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, 513 ctx->pipe, out_type, 514 &decon_crtc_ops, ctx); 515 if (IS_ERR(ctx->crtc)) { 516 ret = PTR_ERR(ctx->crtc); 517 goto err; 518 } 519 520 decon_clear_channels(ctx->crtc); 521 522 ret = drm_iommu_attach_device(drm_dev, dev); 523 if (ret) 524 goto err; 525 526 return ret; 527 err: 528 priv->pipe--; 529 return ret; 530 } 531 532 static void decon_unbind(struct device *dev, struct device *master, void *data) 533 { 534 struct decon_context *ctx = dev_get_drvdata(dev); 535 536 decon_disable(ctx->crtc); 537 538 /* detach this sub driver from iommu mapping if supported. */ 539 drm_iommu_detach_device(ctx->drm_dev, ctx->dev); 540 } 541 542 static const struct component_ops decon_component_ops = { 543 .bind = decon_bind, 544 .unbind = decon_unbind, 545 }; 546 547 static irqreturn_t decon_irq_handler(int irq, void *dev_id) 548 { 549 struct decon_context *ctx = dev_id; 550 u32 val; 551 552 if (!test_bit(BIT_CLKS_ENABLED, &ctx->flags)) 553 goto out; 554 555 val = readl(ctx->addr + DECON_VIDINTCON1); 556 val &= VIDINTCON1_INTFRMDONEPEND | VIDINTCON1_INTFRMPEND; 557 558 if (val) { 559 writel(val, ctx->addr + DECON_VIDINTCON1); 560 drm_crtc_handle_vblank(&ctx->crtc->base); 561 } 562 563 out: 564 return IRQ_HANDLED; 565 } 566 567 #ifdef CONFIG_PM 568 static int exynos5433_decon_suspend(struct device *dev) 569 { 570 struct decon_context *ctx = dev_get_drvdata(dev); 571 int i = ARRAY_SIZE(decon_clks_name); 572 573 while (--i >= 0) 574 clk_disable_unprepare(ctx->clks[i]); 575 576 return 0; 577 } 578 579 static int exynos5433_decon_resume(struct device *dev) 580 { 581 struct decon_context *ctx = dev_get_drvdata(dev); 582 int i, ret; 583 584 for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) { 585 ret = clk_prepare_enable(ctx->clks[i]); 586 if (ret < 0) 587 goto err; 588 } 589 590 return 0; 591 592 err: 593 while (--i >= 0) 594 clk_disable_unprepare(ctx->clks[i]); 595 596 return ret; 597 } 598 #endif 599 600 static const struct dev_pm_ops exynos5433_decon_pm_ops = { 601 SET_RUNTIME_PM_OPS(exynos5433_decon_suspend, exynos5433_decon_resume, 602 NULL) 603 }; 604 605 static const struct of_device_id exynos5433_decon_driver_dt_match[] = { 606 { 607 .compatible = "samsung,exynos5433-decon", 608 .data = (void *)I80_HW_TRG 609 }, 610 { 611 .compatible = "samsung,exynos5433-decon-tv", 612 .data = (void *)(I80_HW_TRG | IFTYPE_HDMI) 613 }, 614 {}, 615 }; 616 MODULE_DEVICE_TABLE(of, exynos5433_decon_driver_dt_match); 617 618 static int exynos5433_decon_probe(struct platform_device *pdev) 619 { 620 struct device *dev = &pdev->dev; 621 struct decon_context *ctx; 622 struct resource *res; 623 int ret; 624 int i; 625 626 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 627 if (!ctx) 628 return -ENOMEM; 629 630 __set_bit(BIT_SUSPENDED, &ctx->flags); 631 ctx->dev = dev; 632 ctx->out_type = (unsigned long)of_device_get_match_data(dev); 633 634 if (ctx->out_type & IFTYPE_HDMI) { 635 ctx->first_win = 1; 636 } else if (of_get_child_by_name(dev->of_node, "i80-if-timings")) { 637 ctx->out_type |= IFTYPE_I80; 638 } 639 640 for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) { 641 struct clk *clk; 642 643 clk = devm_clk_get(ctx->dev, decon_clks_name[i]); 644 if (IS_ERR(clk)) 645 return PTR_ERR(clk); 646 647 ctx->clks[i] = clk; 648 } 649 650 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 651 if (!res) { 652 dev_err(dev, "cannot find IO resource\n"); 653 return -ENXIO; 654 } 655 656 ctx->addr = devm_ioremap_resource(dev, res); 657 if (IS_ERR(ctx->addr)) { 658 dev_err(dev, "ioremap failed\n"); 659 return PTR_ERR(ctx->addr); 660 } 661 662 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, 663 (ctx->out_type & IFTYPE_I80) ? "lcd_sys" : "vsync"); 664 if (!res) { 665 dev_err(dev, "cannot find IRQ resource\n"); 666 return -ENXIO; 667 } 668 669 ret = devm_request_irq(dev, res->start, decon_irq_handler, 0, 670 "drm_decon", ctx); 671 if (ret < 0) { 672 dev_err(dev, "lcd_sys irq request failed\n"); 673 return ret; 674 } 675 676 platform_set_drvdata(pdev, ctx); 677 678 pm_runtime_enable(dev); 679 680 ret = component_add(dev, &decon_component_ops); 681 if (ret) 682 goto err_disable_pm_runtime; 683 684 return 0; 685 686 err_disable_pm_runtime: 687 pm_runtime_disable(dev); 688 689 return ret; 690 } 691 692 static int exynos5433_decon_remove(struct platform_device *pdev) 693 { 694 pm_runtime_disable(&pdev->dev); 695 696 component_del(&pdev->dev, &decon_component_ops); 697 698 return 0; 699 } 700 701 struct platform_driver exynos5433_decon_driver = { 702 .probe = exynos5433_decon_probe, 703 .remove = exynos5433_decon_remove, 704 .driver = { 705 .name = "exynos5433-decon", 706 .pm = &exynos5433_decon_pm_ops, 707 .of_match_table = exynos5433_decon_driver_dt_match, 708 }, 709 }; 710