1 // SPDX-License-Identifier: GPL-2.0-only 2 /* drivers/gpu/drm/exynos5433_drm_decon.c 3 * 4 * Copyright (C) 2015 Samsung Electronics Co.Ltd 5 * Authors: 6 * Joonyoung Shim <jy0922.shim@samsung.com> 7 * Hyungwon Hwang <human.hwang@samsung.com> 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/component.h> 12 #include <linux/iopoll.h> 13 #include <linux/irq.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/of.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/regmap.h> 19 20 #include <drm/drm_blend.h> 21 #include <drm/drm_fourcc.h> 22 #include <drm/drm_framebuffer.h> 23 #include <drm/drm_print.h> 24 #include <drm/drm_vblank.h> 25 26 #include "exynos_drm_crtc.h" 27 #include "exynos_drm_drv.h" 28 #include "exynos_drm_fb.h" 29 #include "exynos_drm_plane.h" 30 #include "regs-decon5433.h" 31 32 #define DSD_CFG_MUX 0x1004 33 #define DSD_CFG_MUX_TE_UNMASK_GLOBAL BIT(13) 34 35 #define WINDOWS_NR 5 36 #define PRIMARY_WIN 2 37 #define CURSON_WIN 4 38 39 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128 40 41 #define I80_HW_TRG (1 << 0) 42 #define IFTYPE_HDMI (1 << 1) 43 44 static const char * const decon_clks_name[] = { 45 "pclk", 46 "aclk_decon", 47 "aclk_smmu_decon0x", 48 "aclk_xiu_decon0x", 49 "pclk_smmu_decon0x", 50 "aclk_smmu_decon1x", 51 "aclk_xiu_decon1x", 52 "pclk_smmu_decon1x", 53 "sclk_decon_vclk", 54 "sclk_decon_eclk", 55 }; 56 57 struct decon_context { 58 struct device *dev; 59 struct drm_device *drm_dev; 60 void *dma_priv; 61 struct exynos_drm_crtc *crtc; 62 struct exynos_drm_plane planes[WINDOWS_NR]; 63 struct exynos_drm_plane_config configs[WINDOWS_NR]; 64 void __iomem *addr; 65 struct regmap *sysreg; 66 struct clk *clks[ARRAY_SIZE(decon_clks_name)]; 67 unsigned int irq; 68 unsigned int irq_vsync; 69 unsigned int irq_lcd_sys; 70 unsigned int te_irq; 71 unsigned long out_type; 72 int first_win; 73 spinlock_t vblank_lock; 74 u32 frame_id; 75 }; 76 77 static const uint32_t decon_formats[] = { 78 DRM_FORMAT_XRGB1555, 79 DRM_FORMAT_RGB565, 80 DRM_FORMAT_XRGB8888, 81 DRM_FORMAT_ARGB8888, 82 }; 83 84 static const enum drm_plane_type decon_win_types[WINDOWS_NR] = { 85 [PRIMARY_WIN] = DRM_PLANE_TYPE_PRIMARY, 86 [CURSON_WIN] = DRM_PLANE_TYPE_CURSOR, 87 }; 88 89 static const unsigned int capabilities[WINDOWS_NR] = { 90 0, 91 EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND, 92 EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND, 93 EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND, 94 EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND, 95 }; 96 97 static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask, 98 u32 val) 99 { 100 val = (val & mask) | (readl(ctx->addr + reg) & ~mask); 101 writel(val, ctx->addr + reg); 102 } 103 104 static int decon_enable_vblank(struct exynos_drm_crtc *crtc) 105 { 106 struct decon_context *ctx = crtc->ctx; 107 u32 val; 108 109 val = VIDINTCON0_INTEN; 110 if (crtc->i80_mode) 111 val |= VIDINTCON0_FRAMEDONE; 112 else 113 val |= VIDINTCON0_INTFRMEN | VIDINTCON0_FRAMESEL_FP; 114 115 writel(val, ctx->addr + DECON_VIDINTCON0); 116 117 enable_irq(ctx->irq); 118 if (!(ctx->out_type & I80_HW_TRG)) 119 enable_irq(ctx->te_irq); 120 121 return 0; 122 } 123 124 static void decon_disable_vblank(struct exynos_drm_crtc *crtc) 125 { 126 struct decon_context *ctx = crtc->ctx; 127 128 if (!(ctx->out_type & I80_HW_TRG)) 129 disable_irq_nosync(ctx->te_irq); 130 disable_irq_nosync(ctx->irq); 131 132 writel(0, ctx->addr + DECON_VIDINTCON0); 133 } 134 135 /* return number of starts/ends of frame transmissions since reset */ 136 static u32 decon_get_frame_count(struct decon_context *ctx, bool end) 137 { 138 u32 frm, pfrm, status, cnt = 2; 139 140 /* To get consistent result repeat read until frame id is stable. 141 * Usually the loop will be executed once, in rare cases when the loop 142 * is executed at frame change time 2nd pass will be needed. 143 */ 144 frm = readl(ctx->addr + DECON_CRFMID); 145 do { 146 status = readl(ctx->addr + DECON_VIDCON1); 147 pfrm = frm; 148 frm = readl(ctx->addr + DECON_CRFMID); 149 } while (frm != pfrm && --cnt); 150 151 /* CRFMID is incremented on BPORCH in case of I80 and on VSYNC in case 152 * of RGB, it should be taken into account. 153 */ 154 if (!frm) 155 return 0; 156 157 switch (status & (VIDCON1_VSTATUS_MASK | VIDCON1_I80_ACTIVE)) { 158 case VIDCON1_VSTATUS_VS: 159 if (!(ctx->crtc->i80_mode)) 160 --frm; 161 break; 162 case VIDCON1_VSTATUS_BP: 163 --frm; 164 break; 165 case VIDCON1_I80_ACTIVE: 166 case VIDCON1_VSTATUS_AC: 167 if (end) 168 --frm; 169 break; 170 default: 171 break; 172 } 173 174 return frm; 175 } 176 177 static void decon_setup_trigger(struct decon_context *ctx) 178 { 179 if (!ctx->crtc->i80_mode && !(ctx->out_type & I80_HW_TRG)) 180 return; 181 182 if (!(ctx->out_type & I80_HW_TRG)) { 183 writel(TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F | 184 TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN, 185 ctx->addr + DECON_TRIGCON); 186 return; 187 } 188 189 writel(TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F | TRIGCON_HWTRIGMASK 190 | TRIGCON_HWTRIGEN, ctx->addr + DECON_TRIGCON); 191 192 if (regmap_update_bits(ctx->sysreg, DSD_CFG_MUX, 193 DSD_CFG_MUX_TE_UNMASK_GLOBAL, ~0)) 194 DRM_DEV_ERROR(ctx->dev, "Cannot update sysreg.\n"); 195 } 196 197 static void decon_commit(struct exynos_drm_crtc *crtc) 198 { 199 struct decon_context *ctx = crtc->ctx; 200 struct drm_display_mode *m = &crtc->base.mode; 201 bool interlaced = false; 202 u32 val; 203 204 if (ctx->out_type & IFTYPE_HDMI) { 205 m->crtc_hsync_start = m->crtc_hdisplay + 10; 206 m->crtc_hsync_end = m->crtc_htotal - 92; 207 m->crtc_vsync_start = m->crtc_vdisplay + 1; 208 m->crtc_vsync_end = m->crtc_vsync_start + 1; 209 if (m->flags & DRM_MODE_FLAG_INTERLACE) 210 interlaced = true; 211 } 212 213 decon_setup_trigger(ctx); 214 215 /* lcd on and use command if */ 216 val = VIDOUT_LCD_ON; 217 if (interlaced) 218 val |= VIDOUT_INTERLACE_EN_F; 219 if (crtc->i80_mode) { 220 val |= VIDOUT_COMMAND_IF; 221 } else { 222 val |= VIDOUT_RGB_IF; 223 } 224 225 writel(val, ctx->addr + DECON_VIDOUTCON0); 226 227 if (interlaced) 228 val = VIDTCON2_LINEVAL(m->vdisplay / 2 - 1) | 229 VIDTCON2_HOZVAL(m->hdisplay - 1); 230 else 231 val = VIDTCON2_LINEVAL(m->vdisplay - 1) | 232 VIDTCON2_HOZVAL(m->hdisplay - 1); 233 writel(val, ctx->addr + DECON_VIDTCON2); 234 235 if (!crtc->i80_mode) { 236 int vbp = m->crtc_vtotal - m->crtc_vsync_end; 237 int vfp = m->crtc_vsync_start - m->crtc_vdisplay; 238 239 if (interlaced) 240 vbp = vbp / 2 - 1; 241 val = VIDTCON00_VBPD_F(vbp - 1) | VIDTCON00_VFPD_F(vfp - 1); 242 writel(val, ctx->addr + DECON_VIDTCON00); 243 244 val = VIDTCON01_VSPW_F( 245 m->crtc_vsync_end - m->crtc_vsync_start - 1); 246 writel(val, ctx->addr + DECON_VIDTCON01); 247 248 val = VIDTCON10_HBPD_F( 249 m->crtc_htotal - m->crtc_hsync_end - 1) | 250 VIDTCON10_HFPD_F( 251 m->crtc_hsync_start - m->crtc_hdisplay - 1); 252 writel(val, ctx->addr + DECON_VIDTCON10); 253 254 val = VIDTCON11_HSPW_F( 255 m->crtc_hsync_end - m->crtc_hsync_start - 1); 256 writel(val, ctx->addr + DECON_VIDTCON11); 257 } 258 259 /* enable output and display signal */ 260 decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID | VIDCON0_ENVID_F, ~0); 261 262 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0); 263 } 264 265 static void decon_win_set_bldeq(struct decon_context *ctx, unsigned int win, 266 unsigned int alpha, unsigned int pixel_alpha) 267 { 268 u32 mask = BLENDERQ_A_FUNC_F(0xf) | BLENDERQ_B_FUNC_F(0xf); 269 u32 val = 0; 270 271 switch (pixel_alpha) { 272 case DRM_MODE_BLEND_PIXEL_NONE: 273 case DRM_MODE_BLEND_COVERAGE: 274 val |= BLENDERQ_A_FUNC_F(BLENDERQ_ALPHA_A); 275 val |= BLENDERQ_B_FUNC_F(BLENDERQ_ONE_MINUS_ALPHA_A); 276 break; 277 case DRM_MODE_BLEND_PREMULTI: 278 default: 279 if (alpha != DRM_BLEND_ALPHA_OPAQUE) { 280 val |= BLENDERQ_A_FUNC_F(BLENDERQ_ALPHA0); 281 val |= BLENDERQ_B_FUNC_F(BLENDERQ_ONE_MINUS_ALPHA_A); 282 } else { 283 val |= BLENDERQ_A_FUNC_F(BLENDERQ_ONE); 284 val |= BLENDERQ_B_FUNC_F(BLENDERQ_ONE_MINUS_ALPHA_A); 285 } 286 break; 287 } 288 decon_set_bits(ctx, DECON_BLENDERQx(win), mask, val); 289 } 290 291 static void decon_win_set_bldmod(struct decon_context *ctx, unsigned int win, 292 unsigned int alpha, unsigned int pixel_alpha) 293 { 294 u32 win_alpha = alpha >> 8; 295 u32 val = 0; 296 297 switch (pixel_alpha) { 298 case DRM_MODE_BLEND_PIXEL_NONE: 299 break; 300 case DRM_MODE_BLEND_COVERAGE: 301 case DRM_MODE_BLEND_PREMULTI: 302 default: 303 val |= WINCONx_ALPHA_SEL_F; 304 val |= WINCONx_BLD_PIX_F; 305 val |= WINCONx_ALPHA_MUL_F; 306 break; 307 } 308 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_BLEND_MODE_MASK, val); 309 310 if (alpha != DRM_BLEND_ALPHA_OPAQUE) { 311 val = VIDOSD_Wx_ALPHA_R_F(win_alpha) | 312 VIDOSD_Wx_ALPHA_G_F(win_alpha) | 313 VIDOSD_Wx_ALPHA_B_F(win_alpha); 314 decon_set_bits(ctx, DECON_VIDOSDxC(win), 315 VIDOSDxC_ALPHA0_RGB_MASK, val); 316 decon_set_bits(ctx, DECON_BLENDCON, BLEND_NEW, BLEND_NEW); 317 } 318 } 319 320 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win, 321 struct drm_framebuffer *fb) 322 { 323 struct exynos_drm_plane *plane = &ctx->planes[win]; 324 struct exynos_drm_plane_state *state = 325 to_exynos_plane_state(plane->base.state); 326 unsigned int alpha = state->base.alpha; 327 unsigned int pixel_alpha; 328 unsigned long val; 329 330 if (fb->format->has_alpha) 331 pixel_alpha = state->base.pixel_blend_mode; 332 else 333 pixel_alpha = DRM_MODE_BLEND_PIXEL_NONE; 334 335 val = readl(ctx->addr + DECON_WINCONx(win)); 336 val &= WINCONx_ENWIN_F; 337 338 switch (fb->format->format) { 339 case DRM_FORMAT_XRGB1555: 340 val |= WINCONx_BPPMODE_16BPP_I1555; 341 val |= WINCONx_HAWSWP_F; 342 val |= WINCONx_BURSTLEN_16WORD; 343 break; 344 case DRM_FORMAT_RGB565: 345 val |= WINCONx_BPPMODE_16BPP_565; 346 val |= WINCONx_HAWSWP_F; 347 val |= WINCONx_BURSTLEN_16WORD; 348 break; 349 case DRM_FORMAT_XRGB8888: 350 val |= WINCONx_BPPMODE_24BPP_888; 351 val |= WINCONx_WSWP_F; 352 val |= WINCONx_BURSTLEN_16WORD; 353 break; 354 case DRM_FORMAT_ARGB8888: 355 default: 356 val |= WINCONx_BPPMODE_32BPP_A8888; 357 val |= WINCONx_WSWP_F; 358 val |= WINCONx_BURSTLEN_16WORD; 359 break; 360 } 361 362 DRM_DEV_DEBUG_KMS(ctx->dev, "cpp = %u\n", fb->format->cpp[0]); 363 364 /* 365 * In case of exynos, setting dma-burst to 16Word causes permanent 366 * tearing for very small buffers, e.g. cursor buffer. Burst Mode 367 * switching which is based on plane size is not recommended as 368 * plane size varies a lot towards the end of the screen and rapid 369 * movement causes unstable DMA which results into iommu crash/tear. 370 */ 371 372 if (fb->width < MIN_FB_WIDTH_FOR_16WORD_BURST) { 373 val &= ~WINCONx_BURSTLEN_MASK; 374 val |= WINCONx_BURSTLEN_8WORD; 375 } 376 decon_set_bits(ctx, DECON_WINCONx(win), ~WINCONx_BLEND_MODE_MASK, val); 377 378 if (win > 0) { 379 decon_win_set_bldmod(ctx, win, alpha, pixel_alpha); 380 decon_win_set_bldeq(ctx, win, alpha, pixel_alpha); 381 } 382 } 383 384 static void decon_shadow_protect(struct decon_context *ctx, bool protect) 385 { 386 decon_set_bits(ctx, DECON_SHADOWCON, SHADOWCON_PROTECT_MASK, 387 protect ? ~0 : 0); 388 } 389 390 static void decon_atomic_begin(struct exynos_drm_crtc *crtc) 391 { 392 struct decon_context *ctx = crtc->ctx; 393 394 decon_shadow_protect(ctx, true); 395 } 396 397 #define BIT_VAL(x, e, s) (((x) & ((1 << ((e) - (s) + 1)) - 1)) << (s)) 398 #define COORDINATE_X(x) BIT_VAL((x), 23, 12) 399 #define COORDINATE_Y(x) BIT_VAL((x), 11, 0) 400 401 static void decon_update_plane(struct exynos_drm_crtc *crtc, 402 struct exynos_drm_plane *plane) 403 { 404 struct exynos_drm_plane_state *state = 405 to_exynos_plane_state(plane->base.state); 406 struct decon_context *ctx = crtc->ctx; 407 struct drm_framebuffer *fb = state->base.fb; 408 unsigned int win = plane->index; 409 unsigned int cpp = fb->format->cpp[0]; 410 unsigned int pitch = fb->pitches[0]; 411 dma_addr_t dma_addr = exynos_drm_fb_dma_addr(fb, 0); 412 u32 val; 413 414 if (crtc->base.mode.flags & DRM_MODE_FLAG_INTERLACE) { 415 val = COORDINATE_X(state->crtc.x) | 416 COORDINATE_Y(state->crtc.y / 2); 417 writel(val, ctx->addr + DECON_VIDOSDxA(win)); 418 419 val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) | 420 COORDINATE_Y((state->crtc.y + state->crtc.h) / 2 - 1); 421 writel(val, ctx->addr + DECON_VIDOSDxB(win)); 422 } else { 423 val = COORDINATE_X(state->crtc.x) | COORDINATE_Y(state->crtc.y); 424 writel(val, ctx->addr + DECON_VIDOSDxA(win)); 425 426 val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) | 427 COORDINATE_Y(state->crtc.y + state->crtc.h - 1); 428 writel(val, ctx->addr + DECON_VIDOSDxB(win)); 429 } 430 431 val = VIDOSD_Wx_ALPHA_R_F(0xff) | VIDOSD_Wx_ALPHA_G_F(0xff) | 432 VIDOSD_Wx_ALPHA_B_F(0xff); 433 writel(val, ctx->addr + DECON_VIDOSDxC(win)); 434 435 val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) | 436 VIDOSD_Wx_ALPHA_B_F(0x0); 437 writel(val, ctx->addr + DECON_VIDOSDxD(win)); 438 439 writel(dma_addr, ctx->addr + DECON_VIDW0xADD0B0(win)); 440 441 val = dma_addr + pitch * state->src.h; 442 writel(val, ctx->addr + DECON_VIDW0xADD1B0(win)); 443 444 if (!(ctx->out_type & IFTYPE_HDMI)) 445 val = BIT_VAL(pitch - state->crtc.w * cpp, 27, 14) 446 | BIT_VAL(state->crtc.w * cpp, 13, 0); 447 else 448 val = BIT_VAL(pitch - state->crtc.w * cpp, 29, 15) 449 | BIT_VAL(state->crtc.w * cpp, 14, 0); 450 writel(val, ctx->addr + DECON_VIDW0xADD2(win)); 451 452 decon_win_set_pixfmt(ctx, win, fb); 453 454 /* window enable */ 455 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, ~0); 456 } 457 458 static void decon_disable_plane(struct exynos_drm_crtc *crtc, 459 struct exynos_drm_plane *plane) 460 { 461 struct decon_context *ctx = crtc->ctx; 462 unsigned int win = plane->index; 463 464 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0); 465 } 466 467 static void decon_atomic_flush(struct exynos_drm_crtc *crtc) 468 { 469 struct decon_context *ctx = crtc->ctx; 470 unsigned long flags; 471 472 spin_lock_irqsave(&ctx->vblank_lock, flags); 473 474 decon_shadow_protect(ctx, false); 475 476 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0); 477 478 ctx->frame_id = decon_get_frame_count(ctx, true); 479 480 exynos_crtc_handle_event(crtc); 481 482 spin_unlock_irqrestore(&ctx->vblank_lock, flags); 483 } 484 485 static void decon_swreset(struct decon_context *ctx) 486 { 487 unsigned long flags; 488 u32 val; 489 int ret; 490 491 writel(0, ctx->addr + DECON_VIDCON0); 492 readl_poll_timeout(ctx->addr + DECON_VIDCON0, val, 493 ~val & VIDCON0_STOP_STATUS, 12, 20000); 494 495 writel(VIDCON0_SWRESET, ctx->addr + DECON_VIDCON0); 496 ret = readl_poll_timeout(ctx->addr + DECON_VIDCON0, val, 497 ~val & VIDCON0_SWRESET, 12, 20000); 498 499 WARN(ret < 0, "failed to software reset DECON\n"); 500 501 spin_lock_irqsave(&ctx->vblank_lock, flags); 502 ctx->frame_id = 0; 503 spin_unlock_irqrestore(&ctx->vblank_lock, flags); 504 505 if (!(ctx->out_type & IFTYPE_HDMI)) 506 return; 507 508 writel(VIDCON0_CLKVALUP | VIDCON0_VLCKFREE, ctx->addr + DECON_VIDCON0); 509 decon_set_bits(ctx, DECON_CMU, 510 CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F, ~0); 511 writel(VIDCON1_VCLK_RUN_VDEN_DISABLE, ctx->addr + DECON_VIDCON1); 512 writel(CRCCTRL_CRCEN | CRCCTRL_CRCSTART_F | CRCCTRL_CRCCLKEN, 513 ctx->addr + DECON_CRCCTRL); 514 } 515 516 static void decon_atomic_enable(struct exynos_drm_crtc *crtc) 517 { 518 struct decon_context *ctx = crtc->ctx; 519 int ret; 520 521 ret = pm_runtime_resume_and_get(ctx->dev); 522 if (ret < 0) { 523 DRM_DEV_ERROR(ctx->dev, "failed to enable DECON device.\n"); 524 return; 525 } 526 527 exynos_drm_pipe_clk_enable(crtc, true); 528 529 decon_swreset(ctx); 530 531 decon_commit(ctx->crtc); 532 } 533 534 static void decon_atomic_disable(struct exynos_drm_crtc *crtc) 535 { 536 struct decon_context *ctx = crtc->ctx; 537 int i; 538 539 if (!(ctx->out_type & I80_HW_TRG)) 540 synchronize_irq(ctx->te_irq); 541 synchronize_irq(ctx->irq); 542 543 /* 544 * We need to make sure that all windows are disabled before we 545 * suspend that connector. Otherwise we might try to scan from 546 * a destroyed buffer later. 547 */ 548 for (i = ctx->first_win; i < WINDOWS_NR; i++) 549 decon_disable_plane(crtc, &ctx->planes[i]); 550 551 decon_swreset(ctx); 552 553 exynos_drm_pipe_clk_enable(crtc, false); 554 555 pm_runtime_put_sync(ctx->dev); 556 } 557 558 static irqreturn_t decon_te_irq_handler(int irq, void *dev_id) 559 { 560 struct decon_context *ctx = dev_id; 561 562 decon_set_bits(ctx, DECON_TRIGCON, TRIGCON_SWTRIGCMD, ~0); 563 564 return IRQ_HANDLED; 565 } 566 567 static void decon_clear_channels(struct exynos_drm_crtc *crtc) 568 { 569 struct decon_context *ctx = crtc->ctx; 570 int win, i, ret; 571 572 for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) { 573 ret = clk_prepare_enable(ctx->clks[i]); 574 if (ret < 0) 575 goto err; 576 } 577 578 decon_shadow_protect(ctx, true); 579 for (win = 0; win < WINDOWS_NR; win++) 580 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0); 581 decon_shadow_protect(ctx, false); 582 583 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0); 584 585 /* TODO: wait for possible vsync */ 586 msleep(50); 587 588 err: 589 while (--i >= 0) 590 clk_disable_unprepare(ctx->clks[i]); 591 } 592 593 static enum drm_mode_status decon_mode_valid(struct exynos_drm_crtc *crtc, 594 const struct drm_display_mode *mode) 595 { 596 struct decon_context *ctx = crtc->ctx; 597 598 ctx->irq = crtc->i80_mode ? ctx->irq_lcd_sys : ctx->irq_vsync; 599 600 if (ctx->irq) 601 return MODE_OK; 602 603 dev_info(ctx->dev, "Sink requires %s mode, but appropriate interrupt is not provided.\n", 604 crtc->i80_mode ? "command" : "video"); 605 606 return MODE_BAD; 607 } 608 609 static const struct exynos_drm_crtc_ops decon_crtc_ops = { 610 .atomic_enable = decon_atomic_enable, 611 .atomic_disable = decon_atomic_disable, 612 .enable_vblank = decon_enable_vblank, 613 .disable_vblank = decon_disable_vblank, 614 .atomic_begin = decon_atomic_begin, 615 .update_plane = decon_update_plane, 616 .disable_plane = decon_disable_plane, 617 .mode_valid = decon_mode_valid, 618 .atomic_flush = decon_atomic_flush, 619 }; 620 621 static int decon_bind(struct device *dev, struct device *master, void *data) 622 { 623 struct decon_context *ctx = dev_get_drvdata(dev); 624 struct drm_device *drm_dev = data; 625 struct exynos_drm_plane *exynos_plane; 626 enum exynos_drm_output_type out_type; 627 unsigned int win; 628 int ret; 629 630 ctx->drm_dev = drm_dev; 631 632 for (win = ctx->first_win; win < WINDOWS_NR; win++) { 633 ctx->configs[win].pixel_formats = decon_formats; 634 ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats); 635 ctx->configs[win].zpos = win - ctx->first_win; 636 ctx->configs[win].type = decon_win_types[win]; 637 ctx->configs[win].capabilities = capabilities[win]; 638 639 ret = exynos_plane_init(drm_dev, &ctx->planes[win], win, 640 &ctx->configs[win]); 641 if (ret) 642 return ret; 643 } 644 645 exynos_plane = &ctx->planes[PRIMARY_WIN]; 646 out_type = (ctx->out_type & IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI 647 : EXYNOS_DISPLAY_TYPE_LCD; 648 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, 649 out_type, &decon_crtc_ops, ctx); 650 if (IS_ERR(ctx->crtc)) 651 return PTR_ERR(ctx->crtc); 652 653 decon_clear_channels(ctx->crtc); 654 655 return exynos_drm_register_dma(drm_dev, dev, &ctx->dma_priv); 656 } 657 658 static void decon_unbind(struct device *dev, struct device *master, void *data) 659 { 660 struct decon_context *ctx = dev_get_drvdata(dev); 661 662 decon_atomic_disable(ctx->crtc); 663 664 /* detach this sub driver from iommu mapping if supported. */ 665 exynos_drm_unregister_dma(ctx->drm_dev, ctx->dev, &ctx->dma_priv); 666 } 667 668 static const struct component_ops decon_component_ops = { 669 .bind = decon_bind, 670 .unbind = decon_unbind, 671 }; 672 673 static void decon_handle_vblank(struct decon_context *ctx) 674 { 675 u32 frm; 676 677 spin_lock(&ctx->vblank_lock); 678 679 frm = decon_get_frame_count(ctx, true); 680 681 if (frm != ctx->frame_id) { 682 /* handle only if incremented, take care of wrap-around */ 683 if ((s32)(frm - ctx->frame_id) > 0) 684 drm_crtc_handle_vblank(&ctx->crtc->base); 685 ctx->frame_id = frm; 686 } 687 688 spin_unlock(&ctx->vblank_lock); 689 } 690 691 static irqreturn_t decon_irq_handler(int irq, void *dev_id) 692 { 693 struct decon_context *ctx = dev_id; 694 u32 val; 695 696 val = readl(ctx->addr + DECON_VIDINTCON1); 697 val &= VIDINTCON1_INTFRMDONEPEND | VIDINTCON1_INTFRMPEND; 698 699 if (val) { 700 writel(val, ctx->addr + DECON_VIDINTCON1); 701 if (ctx->out_type & IFTYPE_HDMI) { 702 val = readl(ctx->addr + DECON_VIDOUTCON0); 703 val &= VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F; 704 if (val == 705 (VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F)) 706 return IRQ_HANDLED; 707 } 708 decon_handle_vblank(ctx); 709 } 710 711 return IRQ_HANDLED; 712 } 713 714 static int exynos5433_decon_suspend(struct device *dev) 715 { 716 struct decon_context *ctx = dev_get_drvdata(dev); 717 int i = ARRAY_SIZE(decon_clks_name); 718 719 while (--i >= 0) 720 clk_disable_unprepare(ctx->clks[i]); 721 722 return 0; 723 } 724 725 static int exynos5433_decon_resume(struct device *dev) 726 { 727 struct decon_context *ctx = dev_get_drvdata(dev); 728 int i, ret; 729 730 for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) { 731 ret = clk_prepare_enable(ctx->clks[i]); 732 if (ret < 0) 733 goto err; 734 } 735 736 return 0; 737 738 err: 739 while (--i >= 0) 740 clk_disable_unprepare(ctx->clks[i]); 741 742 return ret; 743 } 744 745 static DEFINE_RUNTIME_DEV_PM_OPS(exynos5433_decon_pm_ops, 746 exynos5433_decon_suspend, 747 exynos5433_decon_resume, NULL); 748 749 static const struct of_device_id exynos5433_decon_driver_dt_match[] = { 750 { 751 .compatible = "samsung,exynos5433-decon", 752 .data = (void *)I80_HW_TRG 753 }, 754 { 755 .compatible = "samsung,exynos5433-decon-tv", 756 .data = (void *)(I80_HW_TRG | IFTYPE_HDMI) 757 }, 758 {}, 759 }; 760 MODULE_DEVICE_TABLE(of, exynos5433_decon_driver_dt_match); 761 762 static int decon_conf_irq(struct decon_context *ctx, const char *name, 763 irq_handler_t handler, unsigned long int flags) 764 { 765 struct platform_device *pdev = to_platform_device(ctx->dev); 766 int ret, irq = platform_get_irq_byname(pdev, name); 767 768 if (irq < 0) { 769 switch (irq) { 770 case -EPROBE_DEFER: 771 return irq; 772 case -ENODATA: 773 case -ENXIO: 774 return 0; 775 default: 776 dev_err(ctx->dev, "IRQ %s get failed, %d\n", name, irq); 777 return irq; 778 } 779 } 780 ret = devm_request_irq(ctx->dev, irq, handler, 781 flags | IRQF_NO_AUTOEN, "drm_decon", ctx); 782 if (ret < 0) { 783 dev_err(ctx->dev, "IRQ %s request failed\n", name); 784 return ret; 785 } 786 787 return irq; 788 } 789 790 static int exynos5433_decon_probe(struct platform_device *pdev) 791 { 792 struct device *dev = &pdev->dev; 793 struct decon_context *ctx; 794 int ret; 795 int i; 796 797 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 798 if (!ctx) 799 return -ENOMEM; 800 801 ctx->dev = dev; 802 ctx->out_type = (unsigned long)of_device_get_match_data(dev); 803 spin_lock_init(&ctx->vblank_lock); 804 805 if (ctx->out_type & IFTYPE_HDMI) 806 ctx->first_win = 1; 807 808 for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) { 809 struct clk *clk; 810 811 clk = devm_clk_get(ctx->dev, decon_clks_name[i]); 812 if (IS_ERR(clk)) 813 return PTR_ERR(clk); 814 815 ctx->clks[i] = clk; 816 } 817 818 ctx->addr = devm_platform_ioremap_resource(pdev, 0); 819 if (IS_ERR(ctx->addr)) 820 return PTR_ERR(ctx->addr); 821 822 ret = decon_conf_irq(ctx, "vsync", decon_irq_handler, 0); 823 if (ret < 0) 824 return ret; 825 ctx->irq_vsync = ret; 826 827 ret = decon_conf_irq(ctx, "lcd_sys", decon_irq_handler, 0); 828 if (ret < 0) 829 return ret; 830 ctx->irq_lcd_sys = ret; 831 832 ret = decon_conf_irq(ctx, "te", decon_te_irq_handler, 833 IRQF_TRIGGER_RISING); 834 if (ret < 0) 835 return ret; 836 if (ret) { 837 ctx->te_irq = ret; 838 ctx->out_type &= ~I80_HW_TRG; 839 } 840 841 if (ctx->out_type & I80_HW_TRG) { 842 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node, 843 "samsung,disp-sysreg"); 844 if (IS_ERR(ctx->sysreg)) { 845 dev_err(dev, "failed to get system register\n"); 846 return PTR_ERR(ctx->sysreg); 847 } 848 } 849 850 platform_set_drvdata(pdev, ctx); 851 852 pm_runtime_enable(dev); 853 854 ret = component_add(dev, &decon_component_ops); 855 if (ret) 856 goto err_disable_pm_runtime; 857 858 return 0; 859 860 err_disable_pm_runtime: 861 pm_runtime_disable(dev); 862 863 return ret; 864 } 865 866 static void exynos5433_decon_remove(struct platform_device *pdev) 867 { 868 pm_runtime_disable(&pdev->dev); 869 870 component_del(&pdev->dev, &decon_component_ops); 871 } 872 873 struct platform_driver exynos5433_decon_driver = { 874 .probe = exynos5433_decon_probe, 875 .remove = exynos5433_decon_remove, 876 .driver = { 877 .name = "exynos5433-decon", 878 .pm = pm_ptr(&exynos5433_decon_pm_ops), 879 .of_match_table = exynos5433_decon_driver_dt_match, 880 }, 881 }; 882