1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #include <asm/byteorder.h> 30 #include <linux/types.h> 31 #include <linux/string.h> 32 #include <linux/delay.h> 33 34 #include "atomfirmware.h" 35 36 //<DMUB_TYPES>================================================================== 37 /* Basic type definitions. */ 38 39 #ifdef __forceinline 40 #undef __forceinline 41 #endif 42 #define __forceinline inline 43 44 /** 45 * Flag from driver to indicate that ABM should be disabled gradually 46 * by slowly reversing all backlight programming and pixel compensation. 47 */ 48 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 49 50 /** 51 * Flag from driver to indicate that ABM should be disabled immediately 52 * and undo all backlight programming and pixel compensation. 53 */ 54 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 55 56 /** 57 * Flag from driver to indicate that ABM should be disabled immediately 58 * and keep the current backlight programming and pixel compensation. 59 */ 60 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 61 62 /** 63 * Flag from driver to set the current ABM pipe index or ABM operating level. 64 */ 65 #define SET_ABM_PIPE_NORMAL 1 66 67 /** 68 * Number of ambient light levels in ABM algorithm. 69 */ 70 #define NUM_AMBI_LEVEL 5 71 72 /** 73 * Number of operating/aggression levels in ABM algorithm. 74 */ 75 #define NUM_AGGR_LEVEL 4 76 77 /** 78 * Number of segments in the gamma curve. 79 */ 80 #define NUM_POWER_FN_SEGS 8 81 82 /** 83 * Number of segments in the backlight curve. 84 */ 85 #define NUM_BL_CURVE_SEGS 16 86 87 /** 88 * Maximum number of segments in ABM ACE curve. 89 */ 90 #define ABM_MAX_NUM_OF_ACE_SEGMENTS 64 91 92 /** 93 * Maximum number of bins in ABM histogram. 94 */ 95 #define ABM_MAX_NUM_OF_HG_BINS 64 96 97 /* Maximum number of SubVP streams */ 98 #define DMUB_MAX_SUBVP_STREAMS 2 99 100 /* Define max FPO streams as 4 for now. Current implementation today 101 * only supports 1, but could be more in the future. Reduce array 102 * size to ensure the command size remains less than 64 bytes if 103 * adding new fields. 104 */ 105 #define DMUB_MAX_FPO_STREAMS 4 106 107 /* Define to ensure that the "common" members always appear in the same 108 * order in different structs for back compat purposes 109 */ 110 #define COMMON_STREAM_STATIC_SUB_STATE \ 111 struct dmub_fams2_cmd_legacy_stream_static_state legacy; \ 112 struct dmub_fams2_cmd_subvp_stream_static_state subvp; \ 113 struct dmub_fams2_cmd_drr_stream_static_state drr; 114 115 /* Maximum number of streams on any ASIC. */ 116 #define DMUB_MAX_STREAMS 6 117 118 /* Maximum number of planes on any ASIC. */ 119 #define DMUB_MAX_PLANES 6 120 121 /* Maximum number of phantom planes on any ASIC */ 122 #define DMUB_MAX_PHANTOM_PLANES ((DMUB_MAX_PLANES) / 2) 123 124 /* Trace buffer offset for entry */ 125 #define TRACE_BUFFER_ENTRY_OFFSET 16 126 127 /** 128 * Maximum number of dirty rects supported by FW. 129 */ 130 #define DMUB_MAX_DIRTY_RECTS 3 131 132 /** 133 * 134 * PSR control version legacy 135 */ 136 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 137 /** 138 * PSR control version with multi edp support 139 */ 140 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 141 142 143 /** 144 * ABM control version legacy 145 */ 146 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 147 148 /** 149 * ABM control version with multi edp support 150 */ 151 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 152 153 /** 154 * Physical framebuffer address location, 64-bit. 155 */ 156 #ifndef PHYSICAL_ADDRESS_LOC 157 #define PHYSICAL_ADDRESS_LOC union large_integer 158 #endif 159 160 /** 161 * OS/FW agnostic memcpy 162 */ 163 #ifndef dmub_memcpy 164 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 165 #endif 166 167 /** 168 * OS/FW agnostic memset 169 */ 170 #ifndef dmub_memset 171 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 172 #endif 173 174 /** 175 * OS/FW agnostic memcmp 176 */ 177 #ifndef dmub_memcmp 178 #define dmub_memcmp(lhs, rhs, bytes) memcmp((lhs), (rhs), (bytes)) 179 #endif 180 181 /** 182 * OS/FW agnostic udelay 183 */ 184 #ifndef dmub_udelay 185 #define dmub_udelay(microseconds) udelay(microseconds) 186 #endif 187 188 #pragma pack(push, 1) 189 #define ABM_NUM_OF_ACE_SEGMENTS 5 190 191 /** 192 * Debug FW state offset 193 */ 194 #define DMUB_DEBUG_FW_STATE_OFFSET 0x300 195 196 union abm_flags { 197 struct { 198 /** 199 * @abm_enabled: Indicates if ABM is enabled. 200 */ 201 unsigned int abm_enabled : 1; 202 203 /** 204 * @disable_abm_requested: Indicates if driver has requested ABM to be disabled. 205 */ 206 unsigned int disable_abm_requested : 1; 207 208 /** 209 * @disable_abm_immediately: Indicates if driver has requested ABM to be disabled immediately. 210 */ 211 unsigned int disable_abm_immediately : 1; 212 213 /** 214 * @disable_abm_immediate_keep_gain: Indicates if driver has requested ABM 215 * to be disabled immediately and keep gain. 216 */ 217 unsigned int disable_abm_immediate_keep_gain : 1; 218 219 /** 220 * @fractional_pwm: Indicates if fractional duty cycle for backlight PWM is enabled. 221 */ 222 unsigned int fractional_pwm : 1; 223 224 /** 225 * @abm_gradual_bl_change: Indicates if algorithm has completed gradual adjustment 226 * of user backlight level. 227 */ 228 unsigned int abm_gradual_bl_change : 1; 229 230 /** 231 * @abm_new_frame: Indicates if a new frame update needed for ABM to ramp up into steady 232 */ 233 unsigned int abm_new_frame : 1; 234 235 /** 236 * @vb_scaling_enabled: Indicates variBright Scaling Enable 237 */ 238 unsigned int vb_scaling_enabled : 1; 239 } bitfields; 240 241 unsigned int u32All; 242 }; 243 244 struct abm_save_restore { 245 /** 246 * @flags: Misc. ABM flags. 247 */ 248 union abm_flags flags; 249 250 /** 251 * @pause: true: pause ABM and get state 252 * false: unpause ABM after setting state 253 */ 254 uint32_t pause; 255 256 /** 257 * @next_ace_slope: Next ACE slopes to be programmed in HW (u3.13) 258 */ 259 uint32_t next_ace_slope[ABM_NUM_OF_ACE_SEGMENTS]; 260 261 /** 262 * @next_ace_thresh: Next ACE thresholds to be programmed in HW (u10.6) 263 */ 264 uint32_t next_ace_thresh[ABM_NUM_OF_ACE_SEGMENTS]; 265 266 /** 267 * @next_ace_offset: Next ACE offsets to be programmed in HW (u10.6) 268 */ 269 uint32_t next_ace_offset[ABM_NUM_OF_ACE_SEGMENTS]; 270 271 272 /** 273 * @knee_threshold: Current x-position of ACE knee (u0.16). 274 */ 275 uint32_t knee_threshold; 276 /** 277 * @current_gain: Current backlight reduction (u16.16). 278 */ 279 uint32_t current_gain; 280 /** 281 * @curr_bl_level: Current actual backlight level converging to target backlight level. 282 */ 283 uint16_t curr_bl_level; 284 285 /** 286 * @curr_user_bl_level: Current nominal backlight level converging to level requested by user. 287 */ 288 uint16_t curr_user_bl_level; 289 290 }; 291 292 /** 293 * union dmub_addr - DMUB physical/virtual 64-bit address. 294 */ 295 union dmub_addr { 296 struct { 297 uint32_t low_part; /**< Lower 32 bits */ 298 uint32_t high_part; /**< Upper 32 bits */ 299 } u; /*<< Low/high bit access */ 300 uint64_t quad_part; /*<< 64 bit address */ 301 }; 302 303 /* Flattened structure containing SOC BB parameters stored in the VBIOS 304 * It is not practical to store the entire bounding box in VBIOS since the bounding box struct can gain new parameters. 305 * This also prevents alighment issues when new parameters are added to the SoC BB. 306 * The following parameters should be added since these values can't be obtained elsewhere: 307 * -dml2_soc_power_management_parameters 308 * -dml2_soc_vmin_clock_limits 309 */ 310 struct dmub_soc_bb_params { 311 uint32_t dram_clk_change_blackout_ns; 312 uint32_t dram_clk_change_read_only_ns; 313 uint32_t dram_clk_change_write_only_ns; 314 uint32_t fclk_change_blackout_ns; 315 uint32_t g7_ppt_blackout_ns; 316 uint32_t stutter_enter_plus_exit_latency_ns; 317 uint32_t stutter_exit_latency_ns; 318 uint32_t z8_stutter_enter_plus_exit_latency_ns; 319 uint32_t z8_stutter_exit_latency_ns; 320 uint32_t z8_min_idle_time_ns; 321 uint32_t type_b_dram_clk_change_blackout_ns; 322 uint32_t type_b_ppt_blackout_ns; 323 uint32_t vmin_limit_dispclk_khz; 324 uint32_t vmin_limit_dcfclk_khz; 325 uint32_t g7_temperature_read_blackout_ns; 326 }; 327 #pragma pack(pop) 328 329 /** 330 * Dirty rect definition. 331 */ 332 struct dmub_rect { 333 /** 334 * Dirty rect x offset. 335 */ 336 uint32_t x; 337 338 /** 339 * Dirty rect y offset. 340 */ 341 uint32_t y; 342 343 /** 344 * Dirty rect width. 345 */ 346 uint32_t width; 347 348 /** 349 * Dirty rect height. 350 */ 351 uint32_t height; 352 }; 353 354 /** 355 * Flags that can be set by driver to change some PSR behaviour. 356 */ 357 union dmub_psr_debug_flags { 358 /** 359 * Debug flags. 360 */ 361 struct { 362 /** 363 * Enable visual confirm in FW. 364 */ 365 uint32_t visual_confirm : 1; 366 367 /** 368 * Force all selective updates to bw full frame updates. 369 */ 370 uint32_t force_full_frame_update : 1; 371 372 /** 373 * Use HW Lock Mgr object to do HW locking in FW. 374 */ 375 uint32_t use_hw_lock_mgr : 1; 376 377 /** 378 * Use TPS3 signal when restore main link. 379 */ 380 uint32_t force_wakeup_by_tps3 : 1; 381 382 /** 383 * Back to back flip, therefore cannot power down PHY 384 */ 385 uint32_t back_to_back_flip : 1; 386 387 /** 388 * Enable visual confirm for IPS 389 */ 390 uint32_t enable_ips_visual_confirm : 1; 391 } bitfields; 392 393 /** 394 * Union for debug flags. 395 */ 396 uint32_t u32All; 397 }; 398 399 /** 400 * Flags that can be set by driver to change some Replay behaviour. 401 */ 402 union replay_debug_flags { 403 struct { 404 /** 405 * 0x1 (bit 0) 406 * Enable visual confirm in FW. 407 */ 408 uint32_t visual_confirm : 1; 409 410 /** 411 * 0x2 (bit 1) 412 * @skip_crc: Set if need to skip CRC. 413 */ 414 uint32_t skip_crc : 1; 415 416 /** 417 * 0x4 (bit 2) 418 * @force_link_power_on: Force disable ALPM control 419 */ 420 uint32_t force_link_power_on : 1; 421 422 /** 423 * 0x8 (bit 3) 424 * @force_phy_power_on: Force phy power on 425 */ 426 uint32_t force_phy_power_on : 1; 427 428 /** 429 * 0x10 (bit 4) 430 * @timing_resync_disabled: Disabled Replay normal sleep mode timing resync 431 */ 432 uint32_t timing_resync_disabled : 1; 433 434 /** 435 * 0x20 (bit 5) 436 * @skip_crtc_disabled: CRTC disable skipped 437 */ 438 uint32_t skip_crtc_disabled : 1; 439 440 /** 441 * 0x40 (bit 6) 442 * @force_defer_one_frame_update: Force defer one frame update in ultra sleep mode 443 */ 444 uint32_t force_defer_one_frame_update : 1; 445 446 /** 447 * 0x80 (bit 7) 448 * @disable_delay_alpm_on: Force disable delay alpm on 449 */ 450 uint32_t disable_delay_alpm_on : 1; 451 452 /** 453 * 0x100 (bit 8) 454 * @disable_desync_error_check: Force disable desync error check 455 */ 456 uint32_t disable_desync_error_check : 1; 457 458 /** 459 * 0x200 (bit 9) 460 * @force_self_update_when_abm_non_steady: Force self update if abm is not steady 461 */ 462 uint32_t force_self_update_when_abm_non_steady : 1; 463 464 /** 465 * 0x400 (bit 10) 466 * @enable_ips_visual_confirm: Enable IPS visual confirm when entering IPS 467 * If we enter IPS2, the Visual confirm bar will change to yellow 468 */ 469 uint32_t enable_ips_visual_confirm : 1; 470 471 /** 472 * 0x800 (bit 11) 473 * @enable_ips_residency_profiling: Enable IPS residency profiling 474 */ 475 uint32_t enable_ips_residency_profiling : 1; 476 477 /** 478 * 0x1000 (bit 12) 479 * @enable_coasting_vtotal_check: Enable Coasting_vtotal_check 480 */ 481 uint32_t enable_coasting_vtotal_check : 1; 482 /** 483 * 0x2000 (bit 13) 484 * @enable_visual_confirm_debug: Enable Visual Confirm Debug 485 */ 486 uint32_t enable_visual_confirm_debug : 1; 487 488 /** 489 * 0x4000 (bit 14) 490 * @debug_log_enabled: Debug Log Enabled 491 */ 492 uint32_t debug_log_enabled : 1; 493 494 uint32_t reserved : 17; 495 } bitfields; 496 497 uint32_t u32All; 498 }; 499 500 /** 501 * Flags record error state. 502 */ 503 union replay_visual_confirm_error_state_flags { 504 struct { 505 /** 506 * 0x1 (bit 0) - Desync Error flag. 507 */ 508 uint32_t desync_error : 1; 509 510 /** 511 * 0x2 (bit 1) - State Transition Error flag. 512 */ 513 uint32_t state_transition_error : 1; 514 515 /** 516 * 0x4 (bit 2) - Crc Error flag 517 */ 518 uint32_t crc_error : 1; 519 520 /** 521 * 0x8 (bit 3) - Reserved 522 */ 523 uint32_t reserved_3 : 1; 524 525 /** 526 * 0x10 (bit 4) - Incorrect Coasting vtotal checking --> use debug flag to control DPCD write. 527 * Added new debug flag to control DPCD. 528 */ 529 uint32_t incorrect_vtotal_in_static_screen : 1; 530 531 /** 532 * 0x20 (bit 5) - No doubled Refresh Rate. 533 */ 534 uint32_t no_double_rr : 1; 535 536 /** 537 * Reserved bit 6-7 538 */ 539 uint32_t reserved_6_7 : 2; 540 541 /** 542 * Reserved bit 9-31 543 */ 544 uint32_t reserved_9_31 : 24; 545 } bitfields; 546 547 uint32_t u32All; 548 }; 549 550 union replay_hw_flags { 551 struct { 552 /** 553 * @allow_alpm_fw_standby_mode: To indicate whether the 554 * ALPM FW standby mode is allowed 555 */ 556 uint32_t allow_alpm_fw_standby_mode : 1; 557 558 /* 559 * @dsc_enable_status: DSC enable status in driver 560 */ 561 uint32_t dsc_enable_status : 1; 562 563 /** 564 * @fec_enable_status: receive fec enable/disable status from driver 565 */ 566 uint32_t fec_enable_status : 1; 567 568 /* 569 * @smu_optimizations_en: SMU power optimization. 570 * Only when active display is Replay capable and display enters Replay. 571 * Trigger interrupt to SMU to powerup/down. 572 */ 573 uint32_t smu_optimizations_en : 1; 574 575 /** 576 * @phy_power_state: Indicates current phy power state 577 */ 578 uint32_t phy_power_state : 1; 579 580 /** 581 * @link_power_state: Indicates current link power state 582 */ 583 uint32_t link_power_state : 1; 584 /** 585 * Use TPS3 signal when restore main link. 586 */ 587 uint32_t force_wakeup_by_tps3 : 1; 588 /** 589 * @is_alpm_initialized: Indicates whether ALPM is initialized 590 */ 591 uint32_t is_alpm_initialized : 1; 592 593 /** 594 * @alpm_mode: Indicates ALPM mode selected 595 */ 596 uint32_t alpm_mode : 2; 597 } bitfields; 598 599 uint32_t u32All; 600 }; 601 602 union fw_assisted_mclk_switch_version { 603 struct { 604 uint8_t minor : 5; 605 uint8_t major : 3; 606 }; 607 uint8_t ver; 608 }; 609 610 /** 611 * DMUB feature capabilities. 612 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 613 */ 614 struct dmub_feature_caps { 615 /** 616 * Max PSR version supported by FW. 617 */ 618 uint8_t psr; 619 uint8_t fw_assisted_mclk_switch_ver; 620 uint8_t reserved[4]; 621 uint8_t subvp_psr_support; 622 uint8_t gecc_enable; 623 uint8_t replay_supported; 624 uint8_t replay_reserved[3]; 625 uint8_t abm_aux_backlight_support; 626 }; 627 628 struct dmub_visual_confirm_color { 629 /** 630 * Maximum 10 bits color value 631 */ 632 uint16_t color_r_cr; 633 uint16_t color_g_y; 634 uint16_t color_b_cb; 635 uint16_t panel_inst; 636 }; 637 638 /** 639 * struct dmub_cursor_offload_pipe_data_dcn30_v1 - DCN30+ per pipe data. 640 */ 641 struct dmub_cursor_offload_pipe_data_dcn30_v1 { 642 uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS; 643 uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH; 644 uint32_t CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH : 16; 645 uint32_t CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT : 16; 646 uint32_t CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION : 16; 647 uint32_t CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION : 16; 648 uint32_t CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X : 16; 649 uint32_t CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y : 16; 650 uint32_t CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET : 13; 651 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE : 1; 652 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE : 3; 653 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY : 1; 654 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH : 2; 655 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK : 5; 656 uint32_t reserved0[4]; 657 uint32_t CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE : 1; 658 uint32_t CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE : 3; 659 uint32_t CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE : 1; 660 uint32_t CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN : 1; 661 uint32_t CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0 : 24; 662 uint32_t CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1 : 24; 663 uint32_t CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS : 16; 664 uint32_t CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE, : 16; 665 uint32_t reserved1[5]; 666 uint32_t HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET : 8; 667 uint32_t HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST : 8; 668 uint32_t reserved2[3]; 669 }; 670 671 /** 672 * struct dmub_cursor_offload_pipe_data_dcn401_v1 - DCN401 per pipe data. 673 */ 674 struct dmub_cursor_offload_pipe_data_dcn401_v1 { 675 uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS; 676 uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH; 677 uint32_t CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH : 16; 678 uint32_t CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT : 16; 679 uint32_t CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION : 16; 680 uint32_t CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION : 16; 681 uint32_t CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X : 16; 682 uint32_t CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y : 16; 683 uint32_t CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET : 13; 684 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE : 1; 685 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE : 3; 686 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY : 1; 687 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH : 2; 688 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK : 5; 689 uint32_t reserved0[4]; 690 uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_ENABLE : 1; 691 uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_MODE : 3; 692 uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE : 1; 693 uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN : 1; 694 uint32_t CM_CUR0_CURSOR0_COLOR0__CUR0_COLOR0 : 24; 695 uint32_t CM_CUR0_CURSOR0_COLOR1__CUR0_COLOR1 : 24; 696 uint32_t CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_BIAS_G_Y : 16; 697 uint32_t CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_SCALE_G_Y, : 16; 698 uint32_t CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_BIAS_RB_CRCB : 16; 699 uint32_t CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_SCALE_RB_CRCB : 16; 700 uint32_t reserved1[4]; 701 uint32_t HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET : 8; 702 uint32_t HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST : 8; 703 uint32_t HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR : 1; 704 uint32_t reserved2[3]; 705 }; 706 707 /** 708 * struct dmub_cursor_offload_pipe_data_v1 - Per pipe data for cursor offload. 709 */ 710 struct dmub_cursor_offload_pipe_data_v1 { 711 union { 712 struct dmub_cursor_offload_pipe_data_dcn30_v1 dcn30; /**< DCN30 cursor data. */ 713 struct dmub_cursor_offload_pipe_data_dcn401_v1 dcn401; /**< DCN401 cursor data. */ 714 uint8_t payload[96]; /**< Guarantees the cursor pipe data size per-pipe. */ 715 }; 716 }; 717 718 /** 719 * struct dmub_cursor_offload_payload_data_v1 - A payload of stream data. 720 */ 721 struct dmub_cursor_offload_payload_data_v1 { 722 uint32_t write_idx_start; /**< Write index, updated before pipe_data is written. */ 723 uint32_t write_idx_finish; /**< Write index, updated after pipe_data is written. */ 724 uint32_t pipe_mask; /**< Mask of pipes to update. */ 725 uint32_t reserved; /**< Reserved for future use. */ 726 struct dmub_cursor_offload_pipe_data_v1 pipe_data[6]; /**< Per-pipe cursor data. */ 727 }; 728 729 /** 730 * struct dmub_cursor_offload_stream_v1 - Per-stream data for cursor offload. 731 */ 732 struct dmub_cursor_offload_stream_v1 { 733 struct dmub_cursor_offload_payload_data_v1 payloads[4]; /**< A small buffer of cursor payloads. */ 734 uint32_t write_idx; /**< The index of the last written payload. */ 735 }; 736 737 /** 738 * struct dmub_cursor_offload_v1 - Cursor offload feature state. 739 */ 740 struct dmub_cursor_offload_v1 { 741 struct dmub_cursor_offload_stream_v1 offload_streams[6]; /**< Per-stream cursor offload data */ 742 }; 743 744 //============================================================================== 745 //</DMUB_TYPES>================================================================= 746 //============================================================================== 747 //< DMUB_META>================================================================== 748 //============================================================================== 749 #pragma pack(push, 1) 750 751 /* Magic value for identifying dmub_fw_meta_info */ 752 #define DMUB_FW_META_MAGIC 0x444D5542 753 754 /* Offset from the end of the file to the dmub_fw_meta_info */ 755 #define DMUB_FW_META_OFFSET 0x24 756 757 /** 758 * union dmub_fw_meta_feature_bits - Static feature bits for pre-initialization 759 */ 760 union dmub_fw_meta_feature_bits { 761 struct { 762 uint32_t shared_state_link_detection : 1; /**< 1 supports link detection via shared state */ 763 uint32_t cursor_offload_v1_support: 1; /**< 1 supports cursor offload */ 764 uint32_t reserved : 30; 765 } bits; /**< status bits */ 766 uint32_t all; /**< 32-bit access to status bits */ 767 }; 768 769 /** 770 * struct dmub_fw_meta_info - metadata associated with fw binary 771 * 772 * NOTE: This should be considered a stable API. Fields should 773 * not be repurposed or reordered. New fields should be 774 * added instead to extend the structure. 775 * 776 * @magic_value: magic value identifying DMUB firmware meta info 777 * @fw_region_size: size of the firmware state region 778 * @trace_buffer_size: size of the tracebuffer region 779 * @fw_version: the firmware version information 780 * @dal_fw: 1 if the firmware is DAL 781 * @shared_state_size: size of the shared state region in bytes 782 * @shared_state_features: number of shared state features 783 */ 784 struct dmub_fw_meta_info { 785 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 786 uint32_t fw_region_size; /**< size of the firmware state region */ 787 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 788 uint32_t fw_version; /**< the firmware version information */ 789 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 790 uint8_t reserved[3]; /**< padding bits */ 791 uint32_t shared_state_size; /**< size of the shared state region in bytes */ 792 uint16_t shared_state_features; /**< number of shared state features */ 793 uint16_t reserved2; /**< padding bytes */ 794 union dmub_fw_meta_feature_bits feature_bits; /**< static feature bits */ 795 }; 796 797 /** 798 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 799 */ 800 union dmub_fw_meta { 801 struct dmub_fw_meta_info info; /**< metadata info */ 802 uint8_t reserved[64]; /**< padding bits */ 803 }; 804 805 #pragma pack(pop) 806 807 //============================================================================== 808 //< DMUB Trace Buffer>================================================================ 809 //============================================================================== 810 #if !defined(TENSILICA) && !defined(DMUB_TRACE_ENTRY_DEFINED) 811 /** 812 * dmub_trace_code_t - firmware trace code, 32-bits 813 */ 814 typedef uint32_t dmub_trace_code_t; 815 816 /** 817 * struct dmcub_trace_buf_entry - Firmware trace entry 818 */ 819 struct dmcub_trace_buf_entry { 820 dmub_trace_code_t trace_code; /**< trace code for the event */ 821 uint32_t tick_count; /**< the tick count at time of trace */ 822 uint32_t param0; /**< trace defined parameter 0 */ 823 uint32_t param1; /**< trace defined parameter 1 */ 824 }; 825 #endif 826 827 //============================================================================== 828 //< DMUB_STATUS>================================================================ 829 //============================================================================== 830 831 /** 832 * DMCUB scratch registers can be used to determine firmware status. 833 * Current scratch register usage is as follows: 834 * 835 * SCRATCH0: FW Boot Status register 836 * SCRATCH5: LVTMA Status Register 837 * SCRATCH15: FW Boot Options register 838 */ 839 840 /** 841 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 842 */ 843 union dmub_fw_boot_status { 844 struct { 845 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 846 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 847 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 848 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 849 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 850 uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */ 851 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 852 uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */ 853 uint32_t ono_regions_enabled: 1; /**< 1 if ONO regions are enabled */ 854 } bits; /**< status bits */ 855 uint32_t all; /**< 32-bit access to status bits */ 856 }; 857 858 /** 859 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 860 */ 861 enum dmub_fw_boot_status_bit { 862 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 863 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 864 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 865 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 866 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 867 DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/ 868 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 869 DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */ 870 DMUB_FW_BOOT_STATUS_BIT_ONO_REGIONS_ENABLED = (1 << 8), /**< 1 if ONO regions are enabled */ 871 }; 872 873 /* Register bit definition for SCRATCH5 */ 874 union dmub_lvtma_status { 875 struct { 876 uint32_t psp_ok : 1; 877 uint32_t edp_on : 1; 878 uint32_t reserved : 30; 879 } bits; 880 uint32_t all; 881 }; 882 883 enum dmub_lvtma_status_bit { 884 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 885 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 886 }; 887 888 enum dmub_ips_disable_type { 889 DMUB_IPS_ENABLE = 0, 890 DMUB_IPS_DISABLE_ALL = 1, 891 DMUB_IPS_DISABLE_IPS1 = 2, 892 DMUB_IPS_DISABLE_IPS2 = 3, 893 DMUB_IPS_DISABLE_IPS2_Z10 = 4, 894 DMUB_IPS_DISABLE_DYNAMIC = 5, 895 DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF = 6, 896 DMUB_IPS_DISABLE_Z8_RETENTION = 7, 897 }; 898 899 enum dmub_ips_rcg_disable_type { 900 DMUB_IPS_RCG_ENABLE = 0, 901 DMUB_IPS0_RCG_DISABLE = 1, 902 DMUB_IPS1_RCG_DISABLE = 2, 903 DMUB_IPS_RCG_DISABLE = 3 904 }; 905 906 enum dmub_ips_in_vpb_disable_type { 907 DMUB_IPS_VPB_RCG_ONLY = 0, // Legacy behaviour 908 DMUB_IPS_VPB_DISABLE_ALL = 1, 909 DMUB_IPS_VPB_ENABLE_IPS1_AND_RCG = 2, 910 DMUB_IPS_VPB_ENABLE_ALL = 3 // Enable IPS1 Z8, IPS1 and RCG 911 }; 912 913 #define DMUB_IPS1_ALLOW_MASK 0x00000001 914 #define DMUB_IPS2_ALLOW_MASK 0x00000002 915 #define DMUB_IPS1_COMMIT_MASK 0x00000004 916 #define DMUB_IPS2_COMMIT_MASK 0x00000008 917 918 enum dmub_ips_comand_type { 919 /** 920 * Start/stop IPS residency measurements for a given IPS mode 921 */ 922 DMUB_CMD__IPS_RESIDENCY_CNTL = 0, 923 /** 924 * Query IPS residency information for a given IPS mode 925 */ 926 DMUB_CMD__IPS_QUERY_RESIDENCY_INFO = 1, 927 }; 928 929 /** 930 * enum dmub_cursor_offload_comand_type - Cursor offload subcommands. 931 */ 932 enum dmub_cursor_offload_comand_type { 933 /** 934 * Initializes the cursor offload feature. 935 */ 936 DMUB_CMD__CURSOR_OFFLOAD_INIT = 0, 937 /** 938 * Enables cursor offloading for a stream and updates the timing parameters. 939 */ 940 DMUB_CMD__CURSOR_OFFLOAD_STREAM_ENABLE = 1, 941 /** 942 * Disables cursor offloading for a given stream. 943 */ 944 DMUB_CMD__CURSOR_OFFLOAD_STREAM_DISABLE = 2, 945 /** 946 * Programs the latest data for a given stream. 947 */ 948 DMUB_CMD__CURSOR_OFFLOAD_STREAM_PROGRAM = 3, 949 }; 950 951 /** 952 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 953 */ 954 union dmub_fw_boot_options { 955 struct { 956 uint32_t pemu_env : 1; /**< 1 if PEMU */ 957 uint32_t fpga_env : 1; /**< 1 if FPGA */ 958 uint32_t optimized_init : 1; /**< 1 if optimized init */ 959 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 960 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 961 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 962 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 963 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 964 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 965 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 966 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled on DCN31 */ 967 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 968 uint32_t power_optimization: 1; 969 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 970 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 971 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 972 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 973 uint32_t enable_non_transparent_setconfig: 1; /* 1 if dpia use conventional dp lt flow*/ 974 uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/ 975 uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */ 976 uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/ 977 uint32_t ips_disable: 3; /* options to disable ips support*/ 978 uint32_t ips_sequential_ono: 1; /**< 1 to enable sequential ONO IPS sequence */ 979 uint32_t disable_sldo_opt: 1; /**< 1 to disable SLDO optimizations */ 980 uint32_t lower_hbr3_phy_ssc: 1; /**< 1 to lower hbr3 phy ssc to 0.125 percent */ 981 uint32_t override_hbr3_pll_vco: 1; /**< 1 to override the hbr3 pll vco to 0 */ 982 uint32_t disable_dpia_bw_allocation: 1; /**< 1 to disable the USB4 DPIA BW allocation */ 983 uint32_t reserved : 4; /**< reserved */ 984 } bits; /**< boot bits */ 985 uint32_t all; /**< 32-bit access to bits */ 986 }; 987 988 enum dmub_fw_boot_options_bit { 989 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 990 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 991 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 992 }; 993 994 //============================================================================== 995 //< DMUB_SHARED_STATE>========================================================== 996 //============================================================================== 997 998 /** 999 * Shared firmware state between driver and firmware for lockless communication 1000 * in situations where the inbox/outbox may be unavailable. 1001 * 1002 * Each structure *must* be at most 256-bytes in size. The layout allocation is 1003 * described below: 1004 * 1005 * [Header (256 Bytes)][Feature 1 (256 Bytes)][Feature 2 (256 Bytes)]... 1006 */ 1007 1008 /** 1009 * enum dmub_shared_state_feature_id - List of shared state features. 1010 */ 1011 enum dmub_shared_state_feature_id { 1012 DMUB_SHARED_SHARE_FEATURE__INVALID = 0, 1013 DMUB_SHARED_SHARE_FEATURE__IPS_FW = 1, 1014 DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER = 2, 1015 DMUB_SHARED_SHARE_FEATURE__DEBUG_SETUP = 3, 1016 DMUB_SHARED_STATE_FEATURE__CURSOR_OFFLOAD_V1 = 4, 1017 DMUB_SHARED_STATE_FEATURE__LAST, /* Total number of features. */ 1018 }; 1019 1020 /** 1021 * struct dmub_shared_state_ips_fw - Firmware signals for IPS. 1022 */ 1023 union dmub_shared_state_ips_fw_signals { 1024 struct { 1025 uint32_t ips1_commit : 1; /**< 1 if in IPS1 or IPS0 RCG */ 1026 uint32_t ips2_commit : 1; /**< 1 if in IPS2 */ 1027 uint32_t in_idle : 1; /**< 1 if DMCUB is in idle */ 1028 uint32_t detection_required : 1; /**< 1 if detection is required */ 1029 uint32_t ips1z8_commit: 1; /**< 1 if in IPS1 Z8 Retention */ 1030 uint32_t reserved_bits : 27; /**< Reversed */ 1031 } bits; 1032 uint32_t all; 1033 }; 1034 1035 /** 1036 * struct dmub_shared_state_ips_signals - Firmware signals for IPS. 1037 */ 1038 union dmub_shared_state_ips_driver_signals { 1039 struct { 1040 uint32_t allow_pg : 1; /**< 1 if PG is allowed */ 1041 uint32_t allow_ips1 : 1; /**< 1 is IPS1 is allowed */ 1042 uint32_t allow_ips2 : 1; /**< 1 is IPS1 is allowed */ 1043 uint32_t allow_z10 : 1; /**< 1 if Z10 is allowed */ 1044 uint32_t allow_idle: 1; /**< 1 if driver is allowing idle */ 1045 uint32_t allow_ips0_rcg : 1; /**< 1 is IPS0 RCG is allowed */ 1046 uint32_t allow_ips1_rcg : 1; /**< 1 is IPS1 RCG is allowed */ 1047 uint32_t allow_ips1z8 : 1; /**< 1 is IPS1 Z8 Retention is allowed */ 1048 uint32_t allow_dynamic_ips1 : 1; /**< 1 if IPS1 is allowed in dynamic use cases such as VPB */ 1049 uint32_t allow_dynamic_ips1_z8: 1; /**< 1 if IPS1 z8 ret is allowed in dynamic use cases such as VPB */ 1050 uint32_t reserved_bits : 22; /**< Reversed bits */ 1051 } bits; 1052 uint32_t all; 1053 }; 1054 1055 /** 1056 * IPS FW Version 1057 */ 1058 #define DMUB_SHARED_STATE__IPS_FW_VERSION 1 1059 1060 struct dmub_shared_state_debug_setup { 1061 union { 1062 struct { 1063 uint32_t exclude_points[62]; 1064 } profile_mode; 1065 }; 1066 }; 1067 1068 /** 1069 * struct dmub_shared_state_ips_fw - Firmware state for IPS. 1070 */ 1071 struct dmub_shared_state_ips_fw { 1072 union dmub_shared_state_ips_fw_signals signals; /**< 4 bytes, IPS signal bits */ 1073 uint32_t rcg_entry_count; /**< Entry counter for RCG */ 1074 uint32_t rcg_exit_count; /**< Exit counter for RCG */ 1075 uint32_t ips1_entry_count; /**< Entry counter for IPS1 */ 1076 uint32_t ips1_exit_count; /**< Exit counter for IPS1 */ 1077 uint32_t ips2_entry_count; /**< Entry counter for IPS2 */ 1078 uint32_t ips2_exit_count; /**< Exit counter for IPS2 */ 1079 uint32_t ips1_z8ret_entry_count; /**< Entry counter for IPS1 Z8 Retention */ 1080 uint32_t ips1_z8ret_exit_count; /**< Exit counter for IPS1 Z8 Retention */ 1081 uint32_t reserved[53]; /**< Reversed, to be updated when adding new fields. */ 1082 }; /* 248-bytes, fixed */ 1083 1084 /** 1085 * IPS Driver Version 1086 */ 1087 #define DMUB_SHARED_STATE__IPS_DRIVER_VERSION 1 1088 1089 /** 1090 * struct dmub_shared_state_ips_driver - Driver state for IPS. 1091 */ 1092 struct dmub_shared_state_ips_driver { 1093 union dmub_shared_state_ips_driver_signals signals; /**< 4 bytes, IPS signal bits */ 1094 uint32_t reserved[61]; /**< Reversed, to be updated when adding new fields. */ 1095 }; /* 248-bytes, fixed */ 1096 1097 /** 1098 * struct dmub_shared_state_cursor_offload_v1 - Header metadata for cursor offload. 1099 */ 1100 struct dmub_shared_state_cursor_offload_stream_v1 { 1101 uint32_t last_write_idx; /**< Last write index */ 1102 uint8_t reserved[28]; /**< Reserved bytes. */ 1103 }; /* 32-bytes, fixed */ 1104 1105 /** 1106 * struct dmub_shared_state_cursor_offload_v1 - Header metadata for cursor offload. 1107 */ 1108 struct dmub_shared_state_cursor_offload_v1 { 1109 struct dmub_shared_state_cursor_offload_stream_v1 offload_streams[6]; /**< stream state, 32-bytes each */ 1110 uint8_t reserved[56]; /**< reserved for future use */ 1111 }; /* 248-bytes, fixed */ 1112 1113 /** 1114 * enum dmub_shared_state_feature_common - Generic payload. 1115 */ 1116 struct dmub_shared_state_feature_common { 1117 uint32_t padding[62]; 1118 }; /* 248-bytes, fixed */ 1119 1120 /** 1121 * enum dmub_shared_state_feature_header - Feature description. 1122 */ 1123 struct dmub_shared_state_feature_header { 1124 uint16_t id; /**< Feature ID */ 1125 uint16_t version; /**< Feature version */ 1126 uint32_t reserved; /**< Reserved bytes. */ 1127 }; /* 8 bytes, fixed */ 1128 1129 /** 1130 * struct dmub_shared_state_feature_block - Feature block. 1131 */ 1132 struct dmub_shared_state_feature_block { 1133 struct dmub_shared_state_feature_header header; /**< Shared state header. */ 1134 union dmub_shared_feature_state_union { 1135 struct dmub_shared_state_feature_common common; /**< Generic data */ 1136 struct dmub_shared_state_ips_fw ips_fw; /**< IPS firmware state */ 1137 struct dmub_shared_state_ips_driver ips_driver; /**< IPS driver state */ 1138 struct dmub_shared_state_debug_setup debug_setup; /**< Debug setup */ 1139 struct dmub_shared_state_cursor_offload_v1 cursor_offload_v1; /**< Cursor offload */ 1140 } data; /**< Shared state data. */ 1141 }; /* 256-bytes, fixed */ 1142 1143 /** 1144 * Shared state size in bytes. 1145 */ 1146 #define DMUB_FW_HEADER_SHARED_STATE_SIZE \ 1147 ((DMUB_SHARED_STATE_FEATURE__LAST + 1) * sizeof(struct dmub_shared_state_feature_block)) 1148 1149 //============================================================================== 1150 //</DMUB_STATUS>================================================================ 1151 //============================================================================== 1152 //< DMUB_VBIOS>================================================================= 1153 //============================================================================== 1154 1155 /* 1156 * enum dmub_cmd_vbios_type - VBIOS commands. 1157 * 1158 * Command IDs should be treated as stable ABI. 1159 * Do not reuse or modify IDs. 1160 */ 1161 enum dmub_cmd_vbios_type { 1162 /** 1163 * Configures the DIG encoder. 1164 */ 1165 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 1166 /** 1167 * Controls the PHY. 1168 */ 1169 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 1170 /** 1171 * Sets the pixel clock/symbol clock. 1172 */ 1173 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 1174 /** 1175 * Enables or disables power gating. 1176 */ 1177 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 1178 /** 1179 * Controls embedded panels. 1180 */ 1181 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 1182 /** 1183 * Query DP alt status on a transmitter. 1184 */ 1185 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 1186 /** 1187 * Control PHY FSM 1188 */ 1189 DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM = 29, 1190 /** 1191 * Controls domain power gating 1192 */ 1193 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28, 1194 }; 1195 1196 //============================================================================== 1197 //</DMUB_VBIOS>================================================================= 1198 //============================================================================== 1199 //< DMUB_GPINT>================================================================= 1200 //============================================================================== 1201 1202 /** 1203 * The shifts and masks below may alternatively be used to format and read 1204 * the command register bits. 1205 */ 1206 1207 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 1208 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 1209 1210 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 1211 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 1212 1213 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 1214 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 1215 1216 /** 1217 * Command responses. 1218 */ 1219 1220 /** 1221 * Return response for DMUB_GPINT__STOP_FW command. 1222 */ 1223 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 1224 1225 /** 1226 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 1227 */ 1228 union dmub_gpint_data_register { 1229 struct { 1230 uint32_t param : 16; /**< 16-bit parameter */ 1231 uint32_t command_code : 12; /**< GPINT command */ 1232 uint32_t status : 4; /**< Command status bit */ 1233 } bits; /**< GPINT bit access */ 1234 uint32_t all; /**< GPINT 32-bit access */ 1235 }; 1236 1237 /* 1238 * enum dmub_gpint_command - GPINT command to DMCUB FW 1239 * 1240 * Command IDs should be treated as stable ABI. 1241 * Do not reuse or modify IDs. 1242 */ 1243 enum dmub_gpint_command { 1244 /** 1245 * Invalid command, ignored. 1246 */ 1247 DMUB_GPINT__INVALID_COMMAND = 0, 1248 /** 1249 * DESC: Queries the firmware version. 1250 * RETURN: Firmware version. 1251 */ 1252 DMUB_GPINT__GET_FW_VERSION = 1, 1253 /** 1254 * DESC: Halts the firmware. 1255 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 1256 */ 1257 DMUB_GPINT__STOP_FW = 2, 1258 /** 1259 * DESC: Get PSR state from FW. 1260 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 1261 */ 1262 DMUB_GPINT__GET_PSR_STATE = 7, 1263 /** 1264 * DESC: Notifies DMCUB of the currently active streams. 1265 * ARGS: Stream mask, 1 bit per active stream index. 1266 */ 1267 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 1268 /** 1269 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 1270 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 1271 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 1272 * RETURN: PSR residency in milli-percent. 1273 */ 1274 DMUB_GPINT__PSR_RESIDENCY = 9, 1275 1276 /** 1277 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 1278 */ 1279 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 1280 1281 /** 1282 * DESC: Get REPLAY state from FW. 1283 * RETURN: REPLAY state enum. This enum may need to be converted to the legacy REPLAY state value. 1284 */ 1285 DMUB_GPINT__GET_REPLAY_STATE = 13, 1286 1287 /** 1288 * DESC: Start REPLAY residency counter. Stop REPLAY resdiency counter and get value. 1289 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 1290 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 1291 * RETURN: REPLAY residency in milli-percent. 1292 */ 1293 DMUB_GPINT__REPLAY_RESIDENCY = 14, 1294 1295 /** 1296 * DESC: Copy bounding box to the host. 1297 * ARGS: Version of bounding box to copy 1298 * RETURN: Result of copying bounding box 1299 */ 1300 DMUB_GPINT__BB_COPY = 96, 1301 1302 /** 1303 * DESC: Updates the host addresses bit48~bit63 for bounding box. 1304 * ARGS: The word3 for the 64 bit address 1305 */ 1306 DMUB_GPINT__SET_BB_ADDR_WORD3 = 97, 1307 1308 /** 1309 * DESC: Updates the host addresses bit32~bit47 for bounding box. 1310 * ARGS: The word2 for the 64 bit address 1311 */ 1312 DMUB_GPINT__SET_BB_ADDR_WORD2 = 98, 1313 1314 /** 1315 * DESC: Updates the host addresses bit16~bit31 for bounding box. 1316 * ARGS: The word1 for the 64 bit address 1317 */ 1318 DMUB_GPINT__SET_BB_ADDR_WORD1 = 99, 1319 1320 /** 1321 * DESC: Updates the host addresses bit0~bit15 for bounding box. 1322 * ARGS: The word0 for the 64 bit address 1323 */ 1324 DMUB_GPINT__SET_BB_ADDR_WORD0 = 100, 1325 1326 /** 1327 * DESC: Updates the trace buffer lower 32-bit mask. 1328 * ARGS: The new mask 1329 * RETURN: Lower 32-bit mask. 1330 */ 1331 DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK = 101, 1332 1333 /** 1334 * DESC: Updates the trace buffer mask bit0~bit15. 1335 * ARGS: The new mask 1336 * RETURN: Lower 32-bit mask. 1337 */ 1338 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0 = 102, 1339 1340 /** 1341 * DESC: Updates the trace buffer mask bit16~bit31. 1342 * ARGS: The new mask 1343 * RETURN: Lower 32-bit mask. 1344 */ 1345 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1 = 103, 1346 1347 /** 1348 * DESC: Updates the trace buffer mask bit32~bit47. 1349 * ARGS: The new mask 1350 * RETURN: Lower 32-bit mask. 1351 */ 1352 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2 = 114, 1353 1354 /** 1355 * DESC: Updates the trace buffer mask bit48~bit63. 1356 * ARGS: The new mask 1357 * RETURN: Lower 32-bit mask. 1358 */ 1359 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3 = 115, 1360 1361 /** 1362 * DESC: Read the trace buffer mask bi0~bit15. 1363 */ 1364 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0 = 116, 1365 1366 /** 1367 * DESC: Read the trace buffer mask bit16~bit31. 1368 */ 1369 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD1 = 117, 1370 1371 /** 1372 * DESC: Read the trace buffer mask bi32~bit47. 1373 */ 1374 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD2 = 118, 1375 1376 /** 1377 * DESC: Updates the trace buffer mask bit32~bit63. 1378 */ 1379 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD3 = 119, 1380 1381 /** 1382 * DESC: Set IPS residency measurement 1383 * ARGS: 0 - Disable ips measurement 1384 * 1 - Enable ips measurement 1385 */ 1386 DMUB_GPINT__IPS_RESIDENCY = 121, 1387 1388 /** 1389 * DESC: Enable measurements for various task duration 1390 * ARGS: 0 - Disable measurement 1391 * 1 - Enable measurement 1392 */ 1393 DMUB_GPINT__TRACE_DMUB_WAKE_ACTIVITY = 123, 1394 1395 /** 1396 * DESC: Gets IPS residency in microseconds 1397 * ARGS: 0 - Return IPS1 residency 1398 * 1 - Return IPS2 residency 1399 * 2 - Return IPS1_RCG residency 1400 * 3 - Return IPS1_ONO2_ON residency 1401 * RETURN: Total residency in microseconds - lower 32 bits 1402 */ 1403 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_LO = 124, 1404 1405 /** 1406 * DESC: Gets IPS1 histogram counts 1407 * ARGS: Bucket index 1408 * RETURN: Total count for the bucket 1409 */ 1410 DMUB_GPINT__GET_IPS1_HISTOGRAM_COUNTER = 125, 1411 1412 /** 1413 * DESC: Gets IPS2 histogram counts 1414 * ARGS: Bucket index 1415 * RETURN: Total count for the bucket 1416 */ 1417 DMUB_GPINT__GET_IPS2_HISTOGRAM_COUNTER = 126, 1418 1419 /** 1420 * DESC: Gets IPS residency 1421 * ARGS: 0 - Return IPS1 residency 1422 * 1 - Return IPS2 residency 1423 * 2 - Return IPS1_RCG residency 1424 * 3 - Return IPS1_ONO2_ON residency 1425 * RETURN: Total residency in milli-percent. 1426 */ 1427 DMUB_GPINT__GET_IPS_RESIDENCY_PERCENT = 127, 1428 1429 /** 1430 * DESC: Gets IPS1_RCG histogram counts 1431 * ARGS: Bucket index 1432 * RETURN: Total count for the bucket 1433 */ 1434 DMUB_GPINT__GET_IPS1_RCG_HISTOGRAM_COUNTER = 128, 1435 1436 /** 1437 * DESC: Gets IPS1_ONO2_ON histogram counts 1438 * ARGS: Bucket index 1439 * RETURN: Total count for the bucket 1440 */ 1441 DMUB_GPINT__GET_IPS1_ONO2_ON_HISTOGRAM_COUNTER = 129, 1442 1443 /** 1444 * DESC: Gets IPS entry counter during residency measurement 1445 * ARGS: 0 - Return IPS1 entry counts 1446 * 1 - Return IPS2 entry counts 1447 * 2 - Return IPS1_RCG entry counts 1448 * 3 - Return IPS2_ONO2_ON entry counts 1449 * RETURN: Entry counter for selected IPS mode 1450 */ 1451 DMUB_GPINT__GET_IPS_RESIDENCY_ENTRY_COUNTER = 130, 1452 1453 /** 1454 * DESC: Gets IPS inactive residency in microseconds 1455 * ARGS: 0 - Return IPS1_MAX residency 1456 * 1 - Return IPS2 residency 1457 * 2 - Return IPS1_RCG residency 1458 * 3 - Return IPS1_ONO2_ON residency 1459 * RETURN: Total inactive residency in microseconds - lower 32 bits 1460 */ 1461 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_LO = 131, 1462 1463 /** 1464 * DESC: Gets IPS inactive residency in microseconds 1465 * ARGS: 0 - Return IPS1_MAX residency 1466 * 1 - Return IPS2 residency 1467 * 2 - Return IPS1_RCG residency 1468 * 3 - Return IPS1_ONO2_ON residency 1469 * RETURN: Total inactive residency in microseconds - upper 32 bits 1470 */ 1471 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_HI = 132, 1472 1473 /** 1474 * DESC: Gets IPS residency in microseconds 1475 * ARGS: 0 - Return IPS1 residency 1476 * 1 - Return IPS2 residency 1477 * 2 - Return IPS1_RCG residency 1478 * 3 - Return IPS1_ONO2_ON residency 1479 * RETURN: Total residency in microseconds - upper 32 bits 1480 */ 1481 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_HI = 133, 1482 /** 1483 * DESC: Setup debug configs. 1484 */ 1485 DMUB_GPINT__SETUP_DEBUG_MODE = 136, 1486 /** 1487 * DESC: Initiates IPS wake sequence. 1488 */ 1489 DMUB_GPINT__IPS_DEBUG_WAKE = 137, 1490 }; 1491 1492 /** 1493 * INBOX0 generic command definition 1494 */ 1495 union dmub_inbox0_cmd_common { 1496 struct { 1497 uint32_t command_code: 8; /**< INBOX0 command code */ 1498 uint32_t param: 24; /**< 24-bit parameter */ 1499 } bits; 1500 uint32_t all; 1501 }; 1502 1503 /** 1504 * INBOX0 hw_lock command definition 1505 */ 1506 union dmub_inbox0_cmd_lock_hw { 1507 struct { 1508 uint32_t command_code: 8; 1509 1510 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 1511 uint32_t hw_lock_client: 2; 1512 1513 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 1514 uint32_t otg_inst: 3; 1515 uint32_t opp_inst: 3; 1516 uint32_t dig_inst: 3; 1517 1518 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 1519 uint32_t lock_pipe: 1; 1520 uint32_t lock_cursor: 1; 1521 uint32_t lock_dig: 1; 1522 uint32_t triple_buffer_lock: 1; 1523 1524 uint32_t lock: 1; /**< Lock */ 1525 uint32_t should_release: 1; /**< Release */ 1526 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 1527 } bits; 1528 uint32_t all; 1529 }; 1530 1531 union dmub_inbox0_data_register { 1532 union dmub_inbox0_cmd_common inbox0_cmd_common; 1533 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 1534 }; 1535 1536 enum dmub_inbox0_command { 1537 /** 1538 * DESC: Invalid command, ignored. 1539 */ 1540 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 1541 /** 1542 * DESC: Notification to acquire/release HW lock 1543 * ARGS: 1544 */ 1545 DMUB_INBOX0_CMD__HW_LOCK = 1, 1546 }; 1547 //============================================================================== 1548 //</DMUB_GPINT>================================================================= 1549 //============================================================================== 1550 //< DMUB_CMD>=================================================================== 1551 //============================================================================== 1552 1553 /** 1554 * Size in bytes of each DMUB command. 1555 */ 1556 #define DMUB_RB_CMD_SIZE 64 1557 1558 /** 1559 * Maximum number of items in the DMUB ringbuffer. 1560 */ 1561 #define DMUB_RB_MAX_ENTRY 128 1562 1563 /** 1564 * Ringbuffer size in bytes. 1565 */ 1566 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 1567 1568 /** 1569 * Maximum number of items in the DMUB REG INBOX0 internal ringbuffer. 1570 */ 1571 #define DMUB_REG_INBOX0_RB_MAX_ENTRY 16 1572 1573 /** 1574 * Ringbuffer size in bytes. 1575 */ 1576 #define DMUB_REG_INBOX0_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_REG_INBOX0_RB_MAX_ENTRY) 1577 1578 /** 1579 * REG_SET mask for reg offload. 1580 */ 1581 #define REG_SET_MASK 0xFFFF 1582 1583 /* 1584 * enum dmub_cmd_type - DMUB inbox command. 1585 * 1586 * Command IDs should be treated as stable ABI. 1587 * Do not reuse or modify IDs. 1588 */ 1589 enum dmub_cmd_type { 1590 /** 1591 * Invalid command. 1592 */ 1593 DMUB_CMD__NULL = 0, 1594 /** 1595 * Read modify write register sequence offload. 1596 */ 1597 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 1598 /** 1599 * Field update register sequence offload. 1600 */ 1601 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 1602 /** 1603 * Burst write sequence offload. 1604 */ 1605 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 1606 /** 1607 * Reg wait sequence offload. 1608 */ 1609 DMUB_CMD__REG_REG_WAIT = 4, 1610 /** 1611 * Workaround to avoid HUBP underflow during NV12 playback. 1612 */ 1613 DMUB_CMD__PLAT_54186_WA = 5, 1614 /** 1615 * Command type used to query FW feature caps. 1616 */ 1617 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 1618 /** 1619 * Command type used to get visual confirm color. 1620 */ 1621 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 1622 /** 1623 * Command type used for all PSR commands. 1624 */ 1625 DMUB_CMD__PSR = 64, 1626 /** 1627 * Command type used for all MALL commands. 1628 */ 1629 DMUB_CMD__MALL = 65, 1630 /** 1631 * Command type used for all ABM commands. 1632 */ 1633 DMUB_CMD__ABM = 66, 1634 /** 1635 * Command type used to update dirty rects in FW. 1636 */ 1637 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 1638 /** 1639 * Command type used to update cursor info in FW. 1640 */ 1641 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 1642 /** 1643 * Command type used for HW locking in FW. 1644 */ 1645 DMUB_CMD__HW_LOCK = 69, 1646 /** 1647 * Command type used to access DP AUX. 1648 */ 1649 DMUB_CMD__DP_AUX_ACCESS = 70, 1650 /** 1651 * Command type used for OUTBOX1 notification enable 1652 */ 1653 DMUB_CMD__OUTBOX1_ENABLE = 71, 1654 1655 /** 1656 * Command type used for all idle optimization commands. 1657 */ 1658 DMUB_CMD__IDLE_OPT = 72, 1659 /** 1660 * Command type used for all clock manager commands. 1661 */ 1662 DMUB_CMD__CLK_MGR = 73, 1663 /** 1664 * Command type used for all panel control commands. 1665 */ 1666 DMUB_CMD__PANEL_CNTL = 74, 1667 1668 /** 1669 * Command type used for all CAB commands. 1670 */ 1671 DMUB_CMD__CAB_FOR_SS = 75, 1672 1673 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 1674 1675 /** 1676 * Command type used for interfacing with DPIA. 1677 */ 1678 DMUB_CMD__DPIA = 77, 1679 /** 1680 * Command type used for EDID CEA parsing 1681 */ 1682 DMUB_CMD__EDID_CEA = 79, 1683 /** 1684 * Command type used for getting usbc cable ID 1685 */ 1686 DMUB_CMD_GET_USBC_CABLE_ID = 81, 1687 /** 1688 * Command type used to query HPD state. 1689 */ 1690 DMUB_CMD__QUERY_HPD_STATE = 82, 1691 /** 1692 * Command type used for all VBIOS interface commands. 1693 */ 1694 /** 1695 * Command type used for all REPLAY commands. 1696 */ 1697 DMUB_CMD__REPLAY = 83, 1698 1699 /** 1700 * Command type used for all SECURE_DISPLAY commands. 1701 */ 1702 DMUB_CMD__SECURE_DISPLAY = 85, 1703 1704 /** 1705 * Command type used to set DPIA HPD interrupt state 1706 */ 1707 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 1708 1709 /** 1710 * Command type used for all PSP commands. 1711 */ 1712 DMUB_CMD__PSP = 88, 1713 1714 /** 1715 * Command type used for all Fused IO commands. 1716 */ 1717 DMUB_CMD__FUSED_IO = 89, 1718 1719 /** 1720 * Command type used for all LSDMA commands. 1721 */ 1722 DMUB_CMD__LSDMA = 90, 1723 1724 /** 1725 * Command type use for all IPS commands. 1726 */ 1727 DMUB_CMD__IPS = 91, 1728 1729 /** 1730 * Command type use for Cursor offload. 1731 */ 1732 DMUB_CMD__CURSOR_OFFLOAD = 92, 1733 1734 /** 1735 * Command type used for all SMART_POWER_HDR commands. 1736 */ 1737 DMUB_CMD__SMART_POWER_HDR = 93, 1738 1739 /** 1740 * Command type use for VBIOS shared commands. 1741 */ 1742 DMUB_CMD__VBIOS = 128, 1743 }; 1744 1745 /** 1746 * enum dmub_out_cmd_type - DMUB outbox commands. 1747 */ 1748 enum dmub_out_cmd_type { 1749 /** 1750 * Invalid outbox command, ignored. 1751 */ 1752 DMUB_OUT_CMD__NULL = 0, 1753 /** 1754 * Command type used for DP AUX Reply data notification 1755 */ 1756 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 1757 /** 1758 * Command type used for DP HPD event notification 1759 */ 1760 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 1761 /** 1762 * Command type used for SET_CONFIG Reply notification 1763 */ 1764 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 1765 /** 1766 * Command type used for USB4 DPIA notification 1767 */ 1768 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5, 1769 /** 1770 * Command type used for HPD redetect notification 1771 */ 1772 DMUB_OUT_CMD__HPD_SENSE_NOTIFY = 6, 1773 /** 1774 * Command type used for Fused IO notification 1775 */ 1776 DMUB_OUT_CMD__FUSED_IO = 7, 1777 }; 1778 1779 /* DMUB_CMD__DPIA command sub-types. */ 1780 enum dmub_cmd_dpia_type { 1781 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 1782 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, // will be replaced by DPIA_SET_CONFIG_REQUEST 1783 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 1784 DMUB_CMD__DPIA_SET_TPS_NOTIFICATION = 3, 1785 DMUB_CMD__DPIA_SET_CONFIG_REQUEST = 4, 1786 }; 1787 1788 /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */ 1789 enum dmub_cmd_dpia_notification_type { 1790 DPIA_NOTIFY__BW_ALLOCATION = 0, 1791 }; 1792 1793 #pragma pack(push, 1) 1794 1795 /** 1796 * struct dmub_cmd_header - Common command header fields. 1797 */ 1798 struct dmub_cmd_header { 1799 unsigned int type : 8; /**< command type */ 1800 unsigned int sub_type : 8; /**< command sub type */ 1801 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 1802 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 1803 unsigned int is_reg_based : 1; /**< 1 if register based mailbox cmd, 0 if FB based cmd */ 1804 unsigned int reserved0 : 5; /**< reserved bits */ 1805 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 1806 unsigned int reserved1 : 2; /**< reserved bits */ 1807 }; 1808 1809 /* 1810 * struct dmub_cmd_read_modify_write_sequence - Read modify write 1811 * 1812 * 60 payload bytes can hold up to 5 sets of read modify writes, 1813 * each take 3 dwords. 1814 * 1815 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 1816 * 1817 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 1818 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 1819 */ 1820 struct dmub_cmd_read_modify_write_sequence { 1821 uint32_t addr; /**< register address */ 1822 uint32_t modify_mask; /**< modify mask */ 1823 uint32_t modify_value; /**< modify value */ 1824 }; 1825 1826 /** 1827 * Maximum number of ops in read modify write sequence. 1828 */ 1829 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 1830 1831 /** 1832 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 1833 */ 1834 struct dmub_rb_cmd_read_modify_write { 1835 struct dmub_cmd_header header; /**< command header */ 1836 /** 1837 * Read modify write sequence. 1838 */ 1839 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 1840 }; 1841 1842 /* 1843 * Update a register with specified masks and values sequeunce 1844 * 1845 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 1846 * 1847 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 1848 * 1849 * 1850 * USE CASE: 1851 * 1. auto-increment register where additional read would update pointer and produce wrong result 1852 * 2. toggle a bit without read in the middle 1853 */ 1854 1855 struct dmub_cmd_reg_field_update_sequence { 1856 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 1857 uint32_t modify_value; /**< value to update with */ 1858 }; 1859 1860 /** 1861 * Maximum number of ops in field update sequence. 1862 */ 1863 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 1864 1865 /** 1866 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 1867 */ 1868 struct dmub_rb_cmd_reg_field_update_sequence { 1869 struct dmub_cmd_header header; /**< command header */ 1870 uint32_t addr; /**< register address */ 1871 /** 1872 * Field update sequence. 1873 */ 1874 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 1875 }; 1876 1877 1878 /** 1879 * Maximum number of burst write values. 1880 */ 1881 #define DMUB_BURST_WRITE_VALUES__MAX 14 1882 1883 /* 1884 * struct dmub_rb_cmd_burst_write - Burst write 1885 * 1886 * support use case such as writing out LUTs. 1887 * 1888 * 60 payload bytes can hold up to 14 values to write to given address 1889 * 1890 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 1891 */ 1892 struct dmub_rb_cmd_burst_write { 1893 struct dmub_cmd_header header; /**< command header */ 1894 uint32_t addr; /**< register start address */ 1895 /** 1896 * Burst write register values. 1897 */ 1898 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 1899 }; 1900 1901 /** 1902 * struct dmub_rb_cmd_common - Common command header 1903 */ 1904 struct dmub_rb_cmd_common { 1905 struct dmub_cmd_header header; /**< command header */ 1906 /** 1907 * Padding to RB_CMD_SIZE 1908 */ 1909 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 1910 }; 1911 1912 /** 1913 * struct dmub_cmd_reg_wait_data - Register wait data 1914 */ 1915 struct dmub_cmd_reg_wait_data { 1916 uint32_t addr; /**< Register address */ 1917 uint32_t mask; /**< Mask for register bits */ 1918 uint32_t condition_field_value; /**< Value to wait for */ 1919 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 1920 }; 1921 1922 /** 1923 * struct dmub_rb_cmd_reg_wait - Register wait command 1924 */ 1925 struct dmub_rb_cmd_reg_wait { 1926 struct dmub_cmd_header header; /**< Command header */ 1927 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 1928 }; 1929 1930 /** 1931 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 1932 * 1933 * Reprograms surface parameters to avoid underflow. 1934 */ 1935 struct dmub_cmd_PLAT_54186_wa { 1936 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 1937 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 1938 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 1939 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 1940 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 1941 struct { 1942 uint32_t hubp_inst : 4; /**< HUBP instance */ 1943 uint32_t tmz_surface : 1; /**< TMZ enable or disable */ 1944 uint32_t immediate :1; /**< Immediate flip */ 1945 uint32_t vmid : 4; /**< VMID */ 1946 uint32_t grph_stereo : 1; /**< 1 if stereo */ 1947 uint32_t reserved : 21; /**< Reserved */ 1948 } flip_params; /**< Pageflip parameters */ 1949 uint32_t reserved[9]; /**< Reserved bits */ 1950 }; 1951 1952 /** 1953 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 1954 */ 1955 struct dmub_rb_cmd_PLAT_54186_wa { 1956 struct dmub_cmd_header header; /**< Command header */ 1957 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 1958 }; 1959 1960 /** 1961 * enum dmub_cmd_mall_type - MALL commands 1962 */ 1963 enum dmub_cmd_mall_type { 1964 /** 1965 * Allows display refresh from MALL. 1966 */ 1967 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1968 /** 1969 * Disallows display refresh from MALL. 1970 */ 1971 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1972 /** 1973 * Cursor copy for MALL. 1974 */ 1975 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1976 /** 1977 * Controls DF requests. 1978 */ 1979 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1980 }; 1981 1982 /** 1983 * struct dmub_rb_cmd_mall - MALL command data. 1984 */ 1985 struct dmub_rb_cmd_mall { 1986 struct dmub_cmd_header header; /**< Common command header */ 1987 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 1988 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 1989 uint32_t tmr_delay; /**< Timer delay */ 1990 uint32_t tmr_scale; /**< Timer scale */ 1991 uint16_t cursor_width; /**< Cursor width in pixels */ 1992 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 1993 uint16_t cursor_height; /**< Cursor height in pixels */ 1994 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 1995 uint8_t debug_bits; /**< Debug bits */ 1996 1997 uint8_t reserved1; /**< Reserved bits */ 1998 uint8_t reserved2; /**< Reserved bits */ 1999 }; 2000 2001 /** 2002 * enum dmub_cmd_cab_type - CAB command data. 2003 */ 2004 enum dmub_cmd_cab_type { 2005 /** 2006 * No idle optimizations (i.e. no CAB) 2007 */ 2008 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 2009 /** 2010 * No DCN requests for memory 2011 */ 2012 DMUB_CMD__CAB_NO_DCN_REQ = 1, 2013 /** 2014 * Fit surfaces in CAB (i.e. CAB enable) 2015 */ 2016 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 2017 /** 2018 * Do not fit surfaces in CAB (i.e. no CAB) 2019 */ 2020 DMUB_CMD__CAB_DCN_SS_NOT_FIT_IN_CAB = 3, 2021 }; 2022 2023 /** 2024 * struct dmub_rb_cmd_cab - CAB command data. 2025 */ 2026 struct dmub_rb_cmd_cab_for_ss { 2027 struct dmub_cmd_header header; 2028 uint8_t cab_alloc_ways; /* total number of ways */ 2029 uint8_t debug_bits; /* debug bits */ 2030 }; 2031 2032 /** 2033 * Enum for indicating which MCLK switch mode per pipe 2034 */ 2035 enum mclk_switch_mode { 2036 NONE = 0, 2037 FPO = 1, 2038 SUBVP = 2, 2039 VBLANK = 3, 2040 }; 2041 2042 /* Per pipe struct which stores the MCLK switch mode 2043 * data to be sent to DMUB. 2044 * Named "v2" for now -- once FPO and SUBVP are fully merged 2045 * the type name can be updated 2046 */ 2047 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 2048 union { 2049 struct { 2050 uint32_t pix_clk_100hz; 2051 uint16_t main_vblank_start; 2052 uint16_t main_vblank_end; 2053 uint16_t mall_region_lines; 2054 uint16_t prefetch_lines; 2055 uint16_t prefetch_to_mall_start_lines; 2056 uint16_t processing_delay_lines; 2057 uint16_t htotal; // required to calculate line time for multi-display cases 2058 uint16_t vtotal; 2059 uint8_t main_pipe_index; 2060 uint8_t phantom_pipe_index; 2061 /* Since the microschedule is calculated in terms of OTG lines, 2062 * include any scaling factors to make sure when we get accurate 2063 * conversion when programming MALL_START_LINE (which is in terms 2064 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 2065 * is 1/2 (numerator = 1, denominator = 2). 2066 */ 2067 uint8_t scale_factor_numerator; 2068 uint8_t scale_factor_denominator; 2069 uint8_t is_drr; 2070 uint8_t main_split_pipe_index; 2071 uint8_t phantom_split_pipe_index; 2072 } subvp_data; 2073 2074 struct { 2075 uint32_t pix_clk_100hz; 2076 uint16_t vblank_start; 2077 uint16_t vblank_end; 2078 uint16_t vstartup_start; 2079 uint16_t vtotal; 2080 uint16_t htotal; 2081 uint8_t vblank_pipe_index; 2082 uint8_t padding[1]; 2083 struct { 2084 uint8_t drr_in_use; 2085 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 2086 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 2087 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 2088 uint8_t use_ramping; // Use ramping or not 2089 uint8_t drr_vblank_start_margin; 2090 } drr_info; // DRR considered as part of SubVP + VBLANK case 2091 } vblank_data; 2092 } pipe_config; 2093 2094 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 2095 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 2096 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 2097 */ 2098 uint8_t mode; // enum mclk_switch_mode 2099 }; 2100 2101 /** 2102 * Config data for Sub-VP and FPO 2103 * Named "v2" for now -- once FPO and SUBVP are fully merged 2104 * the type name can be updated 2105 */ 2106 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 2107 uint16_t watermark_a_cache; 2108 uint8_t vertical_int_margin_us; 2109 uint8_t pstate_allow_width_us; 2110 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 2111 }; 2112 2113 /** 2114 * DMUB rb command definition for Sub-VP and FPO 2115 * Named "v2" for now -- once FPO and SUBVP are fully merged 2116 * the type name can be updated 2117 */ 2118 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 2119 struct dmub_cmd_header header; 2120 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 2121 }; 2122 2123 struct dmub_flip_addr_info { 2124 uint32_t surf_addr_lo; 2125 uint32_t surf_addr_c_lo; 2126 uint32_t meta_addr_lo; 2127 uint32_t meta_addr_c_lo; 2128 uint16_t surf_addr_hi; 2129 uint16_t surf_addr_c_hi; 2130 uint16_t meta_addr_hi; 2131 uint16_t meta_addr_c_hi; 2132 }; 2133 2134 struct dmub_fams2_flip_info { 2135 union { 2136 struct { 2137 uint8_t is_immediate: 1; 2138 } bits; 2139 uint8_t all; 2140 } config; 2141 uint8_t otg_inst; 2142 uint8_t pipe_mask; 2143 uint8_t pad; 2144 struct dmub_flip_addr_info addr_info; 2145 }; 2146 2147 struct dmub_rb_cmd_fams2_flip { 2148 struct dmub_cmd_header header; 2149 struct dmub_fams2_flip_info flip_info; 2150 }; 2151 2152 struct dmub_cmd_lsdma_data { 2153 union { 2154 struct lsdma_init_data { 2155 union dmub_addr gpu_addr_base; 2156 uint32_t ring_size; 2157 } init_data; 2158 struct lsdma_tiled_copy_data { 2159 uint32_t src_addr_lo; 2160 uint32_t src_addr_hi; 2161 2162 uint32_t dst_addr_lo; 2163 uint32_t dst_addr_hi; 2164 2165 uint32_t src_x : 16; 2166 uint32_t src_y : 16; 2167 2168 uint32_t dst_x : 16; 2169 uint32_t dst_y : 16; 2170 2171 uint32_t src_width : 16; 2172 uint32_t src_height : 16; 2173 2174 uint32_t dst_width : 16; 2175 uint32_t dst_height : 16; 2176 2177 uint32_t rect_x : 16; 2178 uint32_t rect_y : 16; 2179 2180 uint32_t src_swizzle_mode : 5; 2181 uint32_t src_mip_max : 5; 2182 uint32_t src_mip_id : 5; 2183 uint32_t dst_mip_max : 5; 2184 uint32_t dst_swizzle_mode : 5; 2185 uint32_t dst_mip_id : 5; 2186 uint32_t tmz : 1; 2187 uint32_t dcc : 1; 2188 2189 uint32_t data_format : 6; 2190 uint32_t padding1 : 4; 2191 uint32_t dst_element_size : 3; 2192 uint32_t num_type : 3; 2193 uint32_t src_element_size : 3; 2194 uint32_t write_compress : 2; 2195 uint32_t cache_policy_dst : 2; 2196 uint32_t cache_policy_src : 2; 2197 uint32_t read_compress : 2; 2198 uint32_t src_dim : 2; 2199 uint32_t dst_dim : 2; 2200 uint32_t max_uncom : 1; 2201 2202 uint32_t max_com : 2; 2203 uint32_t padding : 30; 2204 } tiled_copy_data; 2205 struct lsdma_linear_copy_data { 2206 uint32_t src_lo; 2207 uint32_t src_hi; 2208 2209 uint32_t dst_lo; 2210 uint32_t dst_hi; 2211 2212 uint32_t count : 30; 2213 uint32_t cache_policy_dst : 2; 2214 2215 uint32_t tmz : 1; 2216 uint32_t cache_policy_src : 2; 2217 uint32_t padding : 29; 2218 } linear_copy_data; 2219 struct lsdma_linear_sub_window_copy_data { 2220 uint32_t src_lo; 2221 uint32_t src_hi; 2222 2223 uint32_t dst_lo; 2224 uint32_t dst_hi; 2225 2226 uint32_t src_x : 16; 2227 uint32_t src_y : 16; 2228 2229 uint32_t dst_x : 16; 2230 uint32_t dst_y : 16; 2231 2232 uint32_t rect_x : 16; 2233 uint32_t rect_y : 16; 2234 2235 uint32_t src_pitch : 16; 2236 uint32_t dst_pitch : 16; 2237 2238 uint32_t src_slice_pitch; 2239 uint32_t dst_slice_pitch; 2240 2241 uint32_t tmz : 1; 2242 uint32_t element_size : 3; 2243 uint32_t src_cache_policy : 3; 2244 uint32_t dst_cache_policy : 3; 2245 uint32_t reserved0 : 22; 2246 } linear_sub_window_copy_data; 2247 struct lsdma_reg_write_data { 2248 uint32_t reg_addr; 2249 uint32_t reg_data; 2250 } reg_write_data; 2251 struct lsdma_pio_copy_data { 2252 uint32_t src_lo; 2253 uint32_t src_hi; 2254 2255 uint32_t dst_lo; 2256 uint32_t dst_hi; 2257 2258 union { 2259 struct { 2260 uint32_t byte_count : 26; 2261 uint32_t src_loc : 1; 2262 uint32_t dst_loc : 1; 2263 uint32_t src_addr_inc : 1; 2264 uint32_t dst_addr_inc : 1; 2265 uint32_t overlap_disable : 1; 2266 uint32_t constant_fill : 1; 2267 } fields; 2268 uint32_t raw; 2269 } packet; 2270 } pio_copy_data; 2271 struct lsdma_pio_constfill_data { 2272 uint32_t dst_lo; 2273 uint32_t dst_hi; 2274 2275 union { 2276 struct { 2277 uint32_t byte_count : 26; 2278 uint32_t src_loc : 1; 2279 uint32_t dst_loc : 1; 2280 uint32_t src_addr_inc : 1; 2281 uint32_t dst_addr_inc : 1; 2282 uint32_t overlap_disable : 1; 2283 uint32_t constant_fill : 1; 2284 } fields; 2285 uint32_t raw; 2286 } packet; 2287 2288 uint32_t data; 2289 } pio_constfill_data; 2290 2291 uint32_t all[14]; 2292 } u; 2293 }; 2294 2295 struct dmub_rb_cmd_lsdma { 2296 struct dmub_cmd_header header; 2297 struct dmub_cmd_lsdma_data lsdma_data; 2298 }; 2299 2300 struct dmub_optc_state_v2 { 2301 uint32_t v_total_min; 2302 uint32_t v_total_max; 2303 uint32_t v_total_mid; 2304 uint32_t v_total_mid_frame_num; 2305 uint8_t program_manual_trigger; 2306 uint8_t tg_inst; 2307 uint8_t pad[2]; 2308 }; 2309 2310 struct dmub_optc_position { 2311 uint32_t vpos; 2312 uint32_t hpos; 2313 uint32_t frame; 2314 }; 2315 2316 struct dmub_rb_cmd_fams2_drr_update { 2317 struct dmub_cmd_header header; 2318 struct dmub_optc_state_v2 dmub_optc_state_req; 2319 }; 2320 2321 /* HW and FW global configuration data for FAMS2 */ 2322 /* FAMS2 types and structs */ 2323 enum fams2_stream_type { 2324 FAMS2_STREAM_TYPE_NONE = 0, 2325 FAMS2_STREAM_TYPE_VBLANK = 1, 2326 FAMS2_STREAM_TYPE_VACTIVE = 2, 2327 FAMS2_STREAM_TYPE_DRR = 3, 2328 FAMS2_STREAM_TYPE_SUBVP = 4, 2329 }; 2330 2331 struct dmub_rect16 { 2332 /** 2333 * Dirty rect x offset. 2334 */ 2335 uint16_t x; 2336 2337 /** 2338 * Dirty rect y offset. 2339 */ 2340 uint16_t y; 2341 2342 /** 2343 * Dirty rect width. 2344 */ 2345 uint16_t width; 2346 2347 /** 2348 * Dirty rect height. 2349 */ 2350 uint16_t height; 2351 }; 2352 2353 /* static stream state */ 2354 struct dmub_fams2_legacy_stream_static_state { 2355 uint8_t vactive_det_fill_delay_otg_vlines; 2356 uint8_t programming_delay_otg_vlines; 2357 }; //v0 2358 2359 struct dmub_fams2_subvp_stream_static_state { 2360 uint16_t vratio_numerator; 2361 uint16_t vratio_denominator; 2362 uint16_t phantom_vtotal; 2363 uint16_t phantom_vactive; 2364 union { 2365 struct { 2366 uint8_t is_multi_planar : 1; 2367 uint8_t is_yuv420 : 1; 2368 } bits; 2369 uint8_t all; 2370 } config; 2371 uint8_t programming_delay_otg_vlines; 2372 uint8_t prefetch_to_mall_otg_vlines; 2373 uint8_t phantom_otg_inst; 2374 uint8_t phantom_pipe_mask; 2375 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough) 2376 }; //v0 2377 2378 struct dmub_fams2_drr_stream_static_state { 2379 uint16_t nom_stretched_vtotal; 2380 uint8_t programming_delay_otg_vlines; 2381 uint8_t only_stretch_if_required; 2382 uint8_t pad[2]; 2383 }; //v0 2384 2385 struct dmub_fams2_cmd_legacy_stream_static_state { 2386 uint16_t vactive_det_fill_delay_otg_vlines; 2387 uint16_t programming_delay_otg_vlines; 2388 }; //v1 2389 2390 struct dmub_fams2_cmd_subvp_stream_static_state { 2391 uint16_t vratio_numerator; 2392 uint16_t vratio_denominator; 2393 uint16_t phantom_vtotal; 2394 uint16_t phantom_vactive; 2395 uint16_t programming_delay_otg_vlines; 2396 uint16_t prefetch_to_mall_otg_vlines; 2397 union { 2398 struct { 2399 uint8_t is_multi_planar : 1; 2400 uint8_t is_yuv420 : 1; 2401 } bits; 2402 uint8_t all; 2403 } config; 2404 uint8_t phantom_otg_inst; 2405 uint8_t phantom_pipe_mask; 2406 uint8_t pad0; 2407 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough) 2408 uint8_t pad1[4 - (DMUB_MAX_PHANTOM_PLANES % 4)]; 2409 }; //v1 2410 2411 struct dmub_fams2_cmd_drr_stream_static_state { 2412 uint16_t nom_stretched_vtotal; 2413 uint16_t programming_delay_otg_vlines; 2414 uint8_t only_stretch_if_required; 2415 uint8_t pad[3]; 2416 }; //v1 2417 2418 union dmub_fams2_stream_static_sub_state { 2419 struct dmub_fams2_legacy_stream_static_state legacy; 2420 struct dmub_fams2_subvp_stream_static_state subvp; 2421 struct dmub_fams2_drr_stream_static_state drr; 2422 }; //v0 2423 2424 union dmub_fams2_cmd_stream_static_sub_state { 2425 COMMON_STREAM_STATIC_SUB_STATE 2426 }; //v1 2427 2428 union dmub_fams2_stream_static_sub_state_v2 { 2429 COMMON_STREAM_STATIC_SUB_STATE 2430 }; //v2 2431 2432 struct dmub_fams2_stream_static_state { 2433 enum fams2_stream_type type; 2434 uint32_t otg_vline_time_ns; 2435 uint32_t otg_vline_time_ticks; 2436 uint16_t htotal; 2437 uint16_t vtotal; // nominal vtotal 2438 uint16_t vblank_start; 2439 uint16_t vblank_end; 2440 uint16_t max_vtotal; 2441 uint16_t allow_start_otg_vline; 2442 uint16_t allow_end_otg_vline; 2443 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed 2444 uint8_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start 2445 uint8_t contention_delay_otg_vlines; // time to budget for contention on execution 2446 uint8_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing 2447 uint8_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline 2448 union { 2449 struct { 2450 uint8_t is_drr: 1; // stream is DRR enabled 2451 uint8_t clamp_vtotal_min: 1; // clamp vtotal to min instead of nominal 2452 uint8_t min_ttu_vblank_usable: 1; // if min ttu vblank is above wm, no force pstate is needed in blank 2453 } bits; 2454 uint8_t all; 2455 } config; 2456 uint8_t otg_inst; 2457 uint8_t pipe_mask; // pipe mask for the whole config 2458 uint8_t num_planes; 2459 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough) 2460 uint8_t pad[4 - (DMUB_MAX_PLANES % 4)]; 2461 union dmub_fams2_stream_static_sub_state sub_state; 2462 }; //v0 2463 2464 struct dmub_fams2_cmd_stream_static_base_state { 2465 enum fams2_stream_type type; 2466 uint32_t otg_vline_time_ns; 2467 uint32_t otg_vline_time_ticks; 2468 uint16_t htotal; 2469 uint16_t vtotal; // nominal vtotal 2470 uint16_t vblank_start; 2471 uint16_t vblank_end; 2472 uint16_t max_vtotal; 2473 uint16_t allow_start_otg_vline; 2474 uint16_t allow_end_otg_vline; 2475 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed 2476 uint16_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start 2477 uint16_t contention_delay_otg_vlines; // time to budget for contention on execution 2478 uint16_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing 2479 uint16_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline 2480 union { 2481 struct { 2482 uint8_t is_drr : 1; // stream is DRR enabled 2483 uint8_t clamp_vtotal_min : 1; // clamp vtotal to min instead of nominal 2484 uint8_t min_ttu_vblank_usable : 1; // if min ttu vblank is above wm, no force pstate is needed in blank 2485 } bits; 2486 uint8_t all; 2487 } config; 2488 uint8_t otg_inst; 2489 uint8_t pipe_mask; // pipe mask for the whole config 2490 uint8_t num_planes; 2491 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough) 2492 uint8_t pad[4 - (DMUB_MAX_PLANES % 4)]; 2493 }; //v1 2494 2495 struct dmub_fams2_stream_static_state_v1 { 2496 struct dmub_fams2_cmd_stream_static_base_state base; 2497 union dmub_fams2_stream_static_sub_state_v2 sub_state; 2498 }; //v1 2499 2500 /** 2501 * enum dmub_fams2_allow_delay_check_mode - macroscheduler mode for breaking on excessive 2502 * p-state request to allow latency 2503 */ 2504 enum dmub_fams2_allow_delay_check_mode { 2505 /* No check for request to allow delay */ 2506 FAMS2_ALLOW_DELAY_CHECK_NONE = 0, 2507 /* Check for request to allow delay */ 2508 FAMS2_ALLOW_DELAY_CHECK_FROM_START = 1, 2509 /* Check for prepare to allow delay */ 2510 FAMS2_ALLOW_DELAY_CHECK_FROM_PREPARE = 2, 2511 }; 2512 2513 union dmub_fams2_global_feature_config { 2514 struct { 2515 uint32_t enable: 1; 2516 uint32_t enable_ppt_check: 1; 2517 uint32_t enable_stall_recovery: 1; 2518 uint32_t enable_debug: 1; 2519 uint32_t enable_offload_flip: 1; 2520 uint32_t enable_visual_confirm: 1; 2521 uint32_t allow_delay_check_mode: 2; 2522 uint32_t reserved: 24; 2523 } bits; 2524 uint32_t all; 2525 }; 2526 2527 struct dmub_cmd_fams2_global_config { 2528 uint32_t max_allow_delay_us; // max delay to assert allow from uclk change begin 2529 uint32_t lock_wait_time_us; // time to forecast acquisition of lock 2530 uint32_t num_streams; 2531 union dmub_fams2_global_feature_config features; 2532 uint32_t recovery_timeout_us; 2533 uint32_t hwfq_flip_programming_delay_us; 2534 uint32_t max_allow_to_target_delta_us; // how early DCN could assert P-State allow compared to the P-State target 2535 }; 2536 2537 union dmub_cmd_fams2_config { 2538 struct dmub_cmd_fams2_global_config global; 2539 struct dmub_fams2_stream_static_state stream; //v0 2540 union { 2541 struct dmub_fams2_cmd_stream_static_base_state base; 2542 union dmub_fams2_cmd_stream_static_sub_state sub_state; 2543 } stream_v1; //v1 2544 }; 2545 2546 struct dmub_fams2_config_v2 { 2547 struct dmub_cmd_fams2_global_config global; 2548 struct dmub_fams2_stream_static_state_v1 stream_v1[DMUB_MAX_STREAMS]; //v1 2549 }; 2550 2551 /** 2552 * DMUB rb command definition for FAMS2 (merged SubVP, FPO, Legacy) 2553 */ 2554 struct dmub_rb_cmd_fams2 { 2555 struct dmub_cmd_header header; 2556 union dmub_cmd_fams2_config config; 2557 }; 2558 2559 /** 2560 * Indirect buffer descriptor 2561 */ 2562 struct dmub_ib_data { 2563 union dmub_addr src; // location of indirect buffer in memory 2564 uint16_t size; // indirect buffer size in bytes 2565 }; 2566 2567 /** 2568 * DMUB rb command definition for commands passed over indirect buffer 2569 */ 2570 struct dmub_rb_cmd_ib { 2571 struct dmub_cmd_header header; 2572 struct dmub_ib_data ib_data; 2573 }; 2574 2575 /** 2576 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 2577 */ 2578 enum dmub_cmd_idle_opt_type { 2579 /** 2580 * DCN hardware restore. 2581 */ 2582 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 2583 2584 /** 2585 * DCN hardware save. 2586 */ 2587 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1, 2588 2589 /** 2590 * DCN hardware notify idle. 2591 */ 2592 DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2, 2593 2594 /** 2595 * DCN hardware notify power state. 2596 */ 2597 DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE = 3, 2598 2599 /** 2600 * DCN notify to release HW. 2601 */ 2602 DMUB_CMD__IDLE_OPT_RELEASE_HW = 4, 2603 }; 2604 2605 /** 2606 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 2607 */ 2608 struct dmub_rb_cmd_idle_opt_dcn_restore { 2609 struct dmub_cmd_header header; /**< header */ 2610 }; 2611 2612 /** 2613 * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 2614 */ 2615 struct dmub_dcn_notify_idle_cntl_data { 2616 uint8_t driver_idle; 2617 uint8_t skip_otg_disable; 2618 uint8_t reserved[58]; 2619 }; 2620 2621 /** 2622 * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 2623 */ 2624 struct dmub_rb_cmd_idle_opt_dcn_notify_idle { 2625 struct dmub_cmd_header header; /**< header */ 2626 struct dmub_dcn_notify_idle_cntl_data cntl_data; 2627 }; 2628 2629 /** 2630 * enum dmub_idle_opt_dc_power_state - DC power states. 2631 */ 2632 enum dmub_idle_opt_dc_power_state { 2633 DMUB_IDLE_OPT_DC_POWER_STATE_UNKNOWN = 0, 2634 DMUB_IDLE_OPT_DC_POWER_STATE_D0 = 1, 2635 DMUB_IDLE_OPT_DC_POWER_STATE_D1 = 2, 2636 DMUB_IDLE_OPT_DC_POWER_STATE_D2 = 4, 2637 DMUB_IDLE_OPT_DC_POWER_STATE_D3 = 8, 2638 }; 2639 2640 /** 2641 * struct dmub_idle_opt_set_dc_power_state_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 2642 */ 2643 struct dmub_idle_opt_set_dc_power_state_data { 2644 uint8_t power_state; /**< power state */ 2645 uint8_t pad[3]; /**< padding */ 2646 }; 2647 2648 /** 2649 * struct dmub_rb_cmd_idle_opt_set_dc_power_state - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 2650 */ 2651 struct dmub_rb_cmd_idle_opt_set_dc_power_state { 2652 struct dmub_cmd_header header; /**< header */ 2653 struct dmub_idle_opt_set_dc_power_state_data data; 2654 }; 2655 2656 /** 2657 * struct dmub_clocks - Clock update notification. 2658 */ 2659 struct dmub_clocks { 2660 uint32_t dispclk_khz; /**< dispclk kHz */ 2661 uint32_t dppclk_khz; /**< dppclk kHz */ 2662 uint32_t dcfclk_khz; /**< dcfclk kHz */ 2663 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 2664 }; 2665 2666 /** 2667 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 2668 */ 2669 enum dmub_cmd_clk_mgr_type { 2670 /** 2671 * Notify DMCUB of clock update. 2672 */ 2673 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 2674 }; 2675 2676 /** 2677 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 2678 */ 2679 struct dmub_rb_cmd_clk_mgr_notify_clocks { 2680 struct dmub_cmd_header header; /**< header */ 2681 struct dmub_clocks clocks; /**< clock data */ 2682 }; 2683 2684 /** 2685 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 2686 */ 2687 struct dmub_cmd_digx_encoder_control_data { 2688 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 2689 }; 2690 2691 /** 2692 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 2693 */ 2694 struct dmub_rb_cmd_digx_encoder_control { 2695 struct dmub_cmd_header header; /**< header */ 2696 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 2697 }; 2698 2699 /** 2700 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 2701 */ 2702 struct dmub_cmd_set_pixel_clock_data { 2703 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 2704 }; 2705 2706 /** 2707 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 2708 */ 2709 struct dmub_rb_cmd_set_pixel_clock { 2710 struct dmub_cmd_header header; /**< header */ 2711 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 2712 }; 2713 2714 /** 2715 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 2716 */ 2717 struct dmub_cmd_enable_disp_power_gating_data { 2718 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 2719 }; 2720 2721 /** 2722 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 2723 */ 2724 struct dmub_rb_cmd_enable_disp_power_gating { 2725 struct dmub_cmd_header header; /**< header */ 2726 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 2727 }; 2728 2729 /** 2730 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 2731 */ 2732 struct dmub_dig_transmitter_control_data_v1_7 { 2733 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 2734 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 2735 union { 2736 uint8_t digmode; /**< enum atom_encode_mode_def */ 2737 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 2738 } mode_laneset; 2739 uint8_t lanenum; /**< Number of lanes */ 2740 union { 2741 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 2742 } symclk_units; 2743 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 2744 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 2745 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 2746 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 2747 uint8_t reserved1; /**< For future use */ 2748 uint8_t skip_phy_ssc_reduction; 2749 uint8_t reserved2[2]; /**< For future use */ 2750 uint32_t reserved3[11]; /**< For future use */ 2751 }; 2752 2753 /** 2754 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 2755 */ 2756 union dmub_cmd_dig1_transmitter_control_data { 2757 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 2758 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 2759 }; 2760 2761 /** 2762 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 2763 */ 2764 struct dmub_rb_cmd_dig1_transmitter_control { 2765 struct dmub_cmd_header header; /**< header */ 2766 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 2767 }; 2768 2769 /** 2770 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control 2771 */ 2772 struct dmub_rb_cmd_domain_control_data { 2773 uint8_t inst : 6; /**< DOMAIN instance to control */ 2774 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */ 2775 uint8_t reserved[3]; /**< Reserved for future use */ 2776 }; 2777 2778 /** 2779 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating 2780 */ 2781 struct dmub_rb_cmd_domain_control { 2782 struct dmub_cmd_header header; /**< header */ 2783 struct dmub_rb_cmd_domain_control_data data; /**< payload */ 2784 }; 2785 2786 /** 2787 * DPIA tunnel command parameters. 2788 */ 2789 struct dmub_cmd_dig_dpia_control_data { 2790 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 2791 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 2792 union { 2793 uint8_t digmode; /** enum atom_encode_mode_def */ 2794 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 2795 } mode_laneset; 2796 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 2797 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 2798 uint8_t hpdsel; /** =0: HPD is not assigned */ 2799 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 2800 uint8_t dpia_id; /** Index of DPIA */ 2801 uint8_t fec_rdy : 1; 2802 uint8_t reserved : 7; 2803 uint32_t reserved1; 2804 }; 2805 2806 /** 2807 * DMUB command for DPIA tunnel control. 2808 */ 2809 struct dmub_rb_cmd_dig1_dpia_control { 2810 struct dmub_cmd_header header; 2811 struct dmub_cmd_dig_dpia_control_data dpia_control; 2812 }; 2813 2814 /** 2815 * SET_CONFIG Command Payload (deprecated) 2816 */ 2817 struct set_config_cmd_payload { 2818 uint8_t msg_type; /* set config message type */ 2819 uint8_t msg_data; /* set config message data */ 2820 }; 2821 2822 /** 2823 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. (deprecated) 2824 */ 2825 struct dmub_cmd_set_config_control_data { 2826 struct set_config_cmd_payload cmd_pkt; 2827 uint8_t instance; /* DPIA instance */ 2828 uint8_t immed_status; /* Immediate status returned in case of error */ 2829 }; 2830 2831 /** 2832 * SET_CONFIG Request Command Payload 2833 */ 2834 struct set_config_request_cmd_payload { 2835 uint8_t instance; /* DPIA instance */ 2836 uint8_t immed_status; /* Immediate status returned in case of error */ 2837 uint8_t msg_type; /* set config message type */ 2838 uint8_t reserved; 2839 uint32_t msg_data; /* set config message data */ 2840 }; 2841 2842 /** 2843 * DMUB command structure for SET_CONFIG command. 2844 */ 2845 struct dmub_rb_cmd_set_config_access { 2846 struct dmub_cmd_header header; /* header */ 2847 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 2848 }; 2849 2850 /** 2851 * DMUB command structure for SET_CONFIG request command. 2852 */ 2853 struct dmub_rb_cmd_set_config_request { 2854 struct dmub_cmd_header header; /* header */ 2855 struct set_config_request_cmd_payload payload; /* set config request payload */ 2856 }; 2857 2858 /** 2859 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 2860 */ 2861 struct dmub_cmd_mst_alloc_slots_control_data { 2862 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 2863 uint8_t instance; /* DPIA instance */ 2864 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 2865 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 2866 }; 2867 2868 /** 2869 * DMUB command structure for SET_ command. 2870 */ 2871 struct dmub_rb_cmd_set_mst_alloc_slots { 2872 struct dmub_cmd_header header; /* header */ 2873 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 2874 }; 2875 2876 /** 2877 * Data passed from driver to FW in a DMUB_CMD__SET_TPS_NOTIFICATION command. 2878 */ 2879 struct dmub_cmd_tps_notification_data { 2880 uint8_t instance; /* DPIA instance */ 2881 uint8_t tps; /* requested training pattern */ 2882 uint8_t reserved1; 2883 uint8_t reserved2; 2884 }; 2885 2886 /** 2887 * DMUB command structure for SET_TPS_NOTIFICATION command. 2888 */ 2889 struct dmub_rb_cmd_set_tps_notification { 2890 struct dmub_cmd_header header; /* header */ 2891 struct dmub_cmd_tps_notification_data tps_notification; /* set tps_notification data */ 2892 }; 2893 2894 /** 2895 * DMUB command structure for DPIA HPD int enable control. 2896 */ 2897 struct dmub_rb_cmd_dpia_hpd_int_enable { 2898 struct dmub_cmd_header header; /* header */ 2899 uint32_t enable; /* dpia hpd interrupt enable */ 2900 }; 2901 2902 /** 2903 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 2904 */ 2905 struct dmub_rb_cmd_dpphy_init { 2906 struct dmub_cmd_header header; /**< header */ 2907 uint8_t reserved[60]; /**< reserved bits */ 2908 }; 2909 2910 /** 2911 * enum dp_aux_request_action - DP AUX request command listing. 2912 * 2913 * 4 AUX request command bits are shifted to high nibble. 2914 */ 2915 enum dp_aux_request_action { 2916 /** I2C-over-AUX write request */ 2917 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 2918 /** I2C-over-AUX read request */ 2919 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 2920 /** I2C-over-AUX write status request */ 2921 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 2922 /** I2C-over-AUX write request with MOT=1 */ 2923 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 2924 /** I2C-over-AUX read request with MOT=1 */ 2925 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 2926 /** I2C-over-AUX write status request with MOT=1 */ 2927 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 2928 /** Native AUX write request */ 2929 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 2930 /** Native AUX read request */ 2931 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 2932 }; 2933 2934 /** 2935 * enum aux_return_code_type - DP AUX process return code listing. 2936 */ 2937 enum aux_return_code_type { 2938 /** AUX process succeeded */ 2939 AUX_RET_SUCCESS = 0, 2940 /** AUX process failed with unknown reason */ 2941 AUX_RET_ERROR_UNKNOWN, 2942 /** AUX process completed with invalid reply */ 2943 AUX_RET_ERROR_INVALID_REPLY, 2944 /** AUX process timed out */ 2945 AUX_RET_ERROR_TIMEOUT, 2946 /** HPD was low during AUX process */ 2947 AUX_RET_ERROR_HPD_DISCON, 2948 /** Failed to acquire AUX engine */ 2949 AUX_RET_ERROR_ENGINE_ACQUIRE, 2950 /** AUX request not supported */ 2951 AUX_RET_ERROR_INVALID_OPERATION, 2952 /** AUX process not available */ 2953 AUX_RET_ERROR_PROTOCOL_ERROR, 2954 }; 2955 2956 /** 2957 * enum aux_channel_type - DP AUX channel type listing. 2958 */ 2959 enum aux_channel_type { 2960 /** AUX thru Legacy DP AUX */ 2961 AUX_CHANNEL_LEGACY_DDC, 2962 /** AUX thru DPIA DP tunneling */ 2963 AUX_CHANNEL_DPIA 2964 }; 2965 2966 /** 2967 * struct aux_transaction_parameters - DP AUX request transaction data 2968 */ 2969 struct aux_transaction_parameters { 2970 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 2971 uint8_t action; /**< enum dp_aux_request_action */ 2972 uint8_t length; /**< DP AUX request data length */ 2973 uint8_t reserved; /**< For future use */ 2974 uint32_t address; /**< DP AUX address */ 2975 uint8_t data[16]; /**< DP AUX write data */ 2976 }; 2977 2978 /** 2979 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 2980 */ 2981 struct dmub_cmd_dp_aux_control_data { 2982 uint8_t instance; /**< AUX instance or DPIA instance */ 2983 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 2984 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 2985 uint8_t reserved0; /**< For future use */ 2986 uint16_t timeout; /**< timeout time in us */ 2987 uint16_t reserved1; /**< For future use */ 2988 enum aux_channel_type type; /**< enum aux_channel_type */ 2989 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 2990 }; 2991 2992 /** 2993 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 2994 */ 2995 struct dmub_rb_cmd_dp_aux_access { 2996 /** 2997 * Command header. 2998 */ 2999 struct dmub_cmd_header header; 3000 /** 3001 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 3002 */ 3003 struct dmub_cmd_dp_aux_control_data aux_control; 3004 }; 3005 3006 /** 3007 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 3008 */ 3009 struct dmub_rb_cmd_outbox1_enable { 3010 /** 3011 * Command header. 3012 */ 3013 struct dmub_cmd_header header; 3014 /** 3015 * enable: 0x0 -> disable outbox1 notification (default value) 3016 * 0x1 -> enable outbox1 notification 3017 */ 3018 uint32_t enable; 3019 }; 3020 3021 /* DP AUX Reply command - OutBox Cmd */ 3022 /** 3023 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 3024 */ 3025 struct aux_reply_data { 3026 /** 3027 * Aux cmd 3028 */ 3029 uint8_t command; 3030 /** 3031 * Aux reply data length (max: 16 bytes) 3032 */ 3033 uint8_t length; 3034 /** 3035 * Alignment only 3036 */ 3037 uint8_t pad[2]; 3038 /** 3039 * Aux reply data 3040 */ 3041 uint8_t data[16]; 3042 }; 3043 3044 /** 3045 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 3046 */ 3047 struct aux_reply_control_data { 3048 /** 3049 * Reserved for future use 3050 */ 3051 uint32_t handle; 3052 /** 3053 * Aux Instance 3054 */ 3055 uint8_t instance; 3056 /** 3057 * Aux transaction result: definition in enum aux_return_code_type 3058 */ 3059 uint8_t result; 3060 /** 3061 * Alignment only 3062 */ 3063 uint16_t pad; 3064 }; 3065 3066 /** 3067 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 3068 */ 3069 struct dmub_rb_cmd_dp_aux_reply { 3070 /** 3071 * Command header. 3072 */ 3073 struct dmub_cmd_header header; 3074 /** 3075 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 3076 */ 3077 struct aux_reply_control_data control; 3078 /** 3079 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 3080 */ 3081 struct aux_reply_data reply_data; 3082 }; 3083 3084 /* DP HPD Notify command - OutBox Cmd */ 3085 /** 3086 * DP HPD Type 3087 */ 3088 enum dp_hpd_type { 3089 /** 3090 * Normal DP HPD 3091 */ 3092 DP_HPD = 0, 3093 /** 3094 * DP HPD short pulse 3095 */ 3096 DP_IRQ = 1, 3097 /** 3098 * Failure to acquire DP HPD state 3099 */ 3100 DP_NONE_HPD = 2 3101 }; 3102 3103 /** 3104 * DP HPD Status 3105 */ 3106 enum dp_hpd_status { 3107 /** 3108 * DP_HPD status low 3109 */ 3110 DP_HPD_UNPLUG = 0, 3111 /** 3112 * DP_HPD status high 3113 */ 3114 DP_HPD_PLUG 3115 }; 3116 3117 /** 3118 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 3119 */ 3120 struct dp_hpd_data { 3121 /** 3122 * DP HPD instance 3123 */ 3124 uint8_t instance; 3125 /** 3126 * HPD type 3127 */ 3128 uint8_t hpd_type; 3129 /** 3130 * HPD status: only for type: DP_HPD to indicate status 3131 */ 3132 uint8_t hpd_status; 3133 /** 3134 * Alignment only 3135 */ 3136 uint8_t pad; 3137 }; 3138 3139 /** 3140 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 3141 */ 3142 struct dmub_rb_cmd_dp_hpd_notify { 3143 /** 3144 * Command header. 3145 */ 3146 struct dmub_cmd_header header; 3147 /** 3148 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 3149 */ 3150 struct dp_hpd_data hpd_data; 3151 }; 3152 3153 /** 3154 * Definition of a SET_CONFIG reply from DPOA. 3155 */ 3156 enum set_config_status { 3157 SET_CONFIG_PENDING = 0, 3158 SET_CONFIG_ACK_RECEIVED, 3159 SET_CONFIG_RX_TIMEOUT, 3160 SET_CONFIG_UNKNOWN_ERROR, 3161 }; 3162 3163 /** 3164 * Definition of a set_config reply 3165 */ 3166 struct set_config_reply_control_data { 3167 uint8_t instance; /* DPIA Instance */ 3168 uint8_t status; /* Set Config reply */ 3169 uint16_t pad; /* Alignment */ 3170 }; 3171 3172 /** 3173 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 3174 */ 3175 struct dmub_rb_cmd_dp_set_config_reply { 3176 struct dmub_cmd_header header; 3177 struct set_config_reply_control_data set_config_reply_control; 3178 }; 3179 3180 /** 3181 * Definition of a DPIA notification header 3182 */ 3183 struct dpia_notification_header { 3184 uint8_t instance; /**< DPIA Instance */ 3185 uint8_t reserved[3]; 3186 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */ 3187 }; 3188 3189 /** 3190 * Definition of the common data struct of DPIA notification 3191 */ 3192 struct dpia_notification_common { 3193 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header) 3194 - sizeof(struct dpia_notification_header)]; 3195 }; 3196 3197 /** 3198 * Definition of a DPIA notification data 3199 */ 3200 struct dpia_bw_allocation_notify_data { 3201 union { 3202 struct { 3203 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */ 3204 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */ 3205 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */ 3206 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */ 3207 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */ 3208 uint16_t reserved: 11; /**< Reserved */ 3209 } bits; 3210 3211 uint16_t flags; 3212 }; 3213 3214 uint8_t cm_id; /**< CM ID */ 3215 uint8_t group_id; /**< Group ID */ 3216 uint8_t granularity; /**< BW Allocation Granularity */ 3217 uint8_t estimated_bw; /**< Estimated_BW */ 3218 uint8_t allocated_bw; /**< Allocated_BW */ 3219 uint8_t reserved; 3220 }; 3221 3222 /** 3223 * union dpia_notify_data_type - DPIA Notification in Outbox command 3224 */ 3225 union dpia_notification_data { 3226 /** 3227 * DPIA Notification for common data struct 3228 */ 3229 struct dpia_notification_common common_data; 3230 3231 /** 3232 * DPIA Notification for DP BW Allocation support 3233 */ 3234 struct dpia_bw_allocation_notify_data dpia_bw_alloc; 3235 }; 3236 3237 /** 3238 * Definition of a DPIA notification payload 3239 */ 3240 struct dpia_notification_payload { 3241 struct dpia_notification_header header; 3242 union dpia_notification_data data; /**< DPIA notification payload data */ 3243 }; 3244 3245 /** 3246 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command. 3247 */ 3248 struct dmub_rb_cmd_dpia_notification { 3249 struct dmub_cmd_header header; /**< DPIA notification header */ 3250 struct dpia_notification_payload payload; /**< DPIA notification payload */ 3251 }; 3252 3253 /** 3254 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 3255 */ 3256 struct dmub_cmd_hpd_state_query_data { 3257 uint8_t instance; /**< HPD instance or DPIA instance */ 3258 uint8_t result; /**< For returning HPD state */ 3259 uint16_t pad; /** < Alignment */ 3260 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 3261 enum aux_return_code_type status; /**< for returning the status of command */ 3262 }; 3263 3264 /** 3265 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 3266 */ 3267 struct dmub_rb_cmd_query_hpd_state { 3268 /** 3269 * Command header. 3270 */ 3271 struct dmub_cmd_header header; 3272 /** 3273 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 3274 */ 3275 struct dmub_cmd_hpd_state_query_data data; 3276 }; 3277 3278 /** 3279 * struct dmub_rb_cmd_hpd_sense_notify - HPD sense notification data. 3280 */ 3281 struct dmub_rb_cmd_hpd_sense_notify_data { 3282 uint32_t old_hpd_sense_mask; /**< Old HPD sense mask */ 3283 uint32_t new_hpd_sense_mask; /**< New HPD sense mask */ 3284 }; 3285 3286 /** 3287 * struct dmub_rb_cmd_hpd_sense_notify - DMUB_OUT_CMD__HPD_SENSE_NOTIFY command. 3288 */ 3289 struct dmub_rb_cmd_hpd_sense_notify { 3290 struct dmub_cmd_header header; /**< header */ 3291 struct dmub_rb_cmd_hpd_sense_notify_data data; /**< payload */ 3292 }; 3293 3294 /* 3295 * Command IDs should be treated as stable ABI. 3296 * Do not reuse or modify IDs. 3297 */ 3298 3299 /** 3300 * PSR command sub-types. 3301 */ 3302 enum dmub_cmd_psr_type { 3303 /** 3304 * Set PSR version support. 3305 */ 3306 DMUB_CMD__PSR_SET_VERSION = 0, 3307 /** 3308 * Copy driver-calculated parameters to PSR state. 3309 */ 3310 DMUB_CMD__PSR_COPY_SETTINGS = 1, 3311 /** 3312 * Enable PSR. 3313 */ 3314 DMUB_CMD__PSR_ENABLE = 2, 3315 3316 /** 3317 * Disable PSR. 3318 */ 3319 DMUB_CMD__PSR_DISABLE = 3, 3320 3321 /** 3322 * Set PSR level. 3323 * PSR level is a 16-bit value dicated by driver that 3324 * will enable/disable different functionality. 3325 */ 3326 DMUB_CMD__PSR_SET_LEVEL = 4, 3327 3328 /** 3329 * Forces PSR enabled until an explicit PSR disable call. 3330 */ 3331 DMUB_CMD__PSR_FORCE_STATIC = 5, 3332 /** 3333 * Set vtotal in psr active for FreeSync PSR. 3334 */ 3335 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 3336 /** 3337 * Set PSR power option 3338 */ 3339 DMUB_CMD__SET_PSR_POWER_OPT = 7, 3340 }; 3341 3342 /** 3343 * Different PSR residency modes. 3344 * Different modes change the definition of PSR residency. 3345 */ 3346 enum psr_residency_mode { 3347 PSR_RESIDENCY_MODE_PHY = 0, 3348 PSR_RESIDENCY_MODE_ALPM, 3349 PSR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 3350 /* Do not add below. */ 3351 PSR_RESIDENCY_MODE_LAST_ELEMENT, 3352 }; 3353 3354 enum dmub_cmd_fams_type { 3355 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 3356 DMUB_CMD__FAMS_DRR_UPDATE = 1, 3357 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 3358 /** 3359 * For SubVP set manual trigger in FW because it 3360 * triggers DRR_UPDATE_PENDING which SubVP relies 3361 * on (for any SubVP cases that use a DRR display) 3362 */ 3363 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 3364 DMUB_CMD__FAMS2_CONFIG = 4, 3365 DMUB_CMD__FAMS2_DRR_UPDATE = 5, 3366 DMUB_CMD__FAMS2_FLIP = 6, 3367 DMUB_CMD__FAMS2_IB_CONFIG = 7, 3368 }; 3369 3370 /** 3371 * PSR versions. 3372 */ 3373 enum psr_version { 3374 /** 3375 * PSR version 1. 3376 */ 3377 PSR_VERSION_1 = 0, 3378 /** 3379 * Freesync PSR SU. 3380 */ 3381 PSR_VERSION_SU_1 = 1, 3382 /** 3383 * PSR not supported. 3384 */ 3385 PSR_VERSION_UNSUPPORTED = 0xFF, // psr_version field is only 8 bits wide 3386 }; 3387 3388 /** 3389 * PHY Link rate for DP. 3390 */ 3391 enum phy_link_rate { 3392 /** 3393 * not supported. 3394 */ 3395 PHY_RATE_UNKNOWN = 0, 3396 /** 3397 * Rate_1 (RBR) - 1.62 Gbps/Lane 3398 */ 3399 PHY_RATE_162 = 1, 3400 /** 3401 * Rate_2 - 2.16 Gbps/Lane 3402 */ 3403 PHY_RATE_216 = 2, 3404 /** 3405 * Rate_3 - 2.43 Gbps/Lane 3406 */ 3407 PHY_RATE_243 = 3, 3408 /** 3409 * Rate_4 (HBR) - 2.70 Gbps/Lane 3410 */ 3411 PHY_RATE_270 = 4, 3412 /** 3413 * Rate_5 (RBR2)- 3.24 Gbps/Lane 3414 */ 3415 PHY_RATE_324 = 5, 3416 /** 3417 * Rate_6 - 4.32 Gbps/Lane 3418 */ 3419 PHY_RATE_432 = 6, 3420 /** 3421 * Rate_7 (HBR2)- 5.40 Gbps/Lane 3422 */ 3423 PHY_RATE_540 = 7, 3424 /** 3425 * Rate_8 (HBR3)- 8.10 Gbps/Lane 3426 */ 3427 PHY_RATE_810 = 8, 3428 /** 3429 * UHBR10 - 10.0 Gbps/Lane 3430 */ 3431 PHY_RATE_1000 = 9, 3432 /** 3433 * UHBR13.5 - 13.5 Gbps/Lane 3434 */ 3435 PHY_RATE_1350 = 10, 3436 /** 3437 * UHBR10 - 20.0 Gbps/Lane 3438 */ 3439 PHY_RATE_2000 = 11, 3440 3441 PHY_RATE_675 = 12, 3442 /** 3443 * Rate 12 - 6.75 Gbps/Lane 3444 */ 3445 }; 3446 3447 /** 3448 * enum dmub_phy_fsm_state - PHY FSM states. 3449 * PHY FSM state to transit to during PSR enable/disable. 3450 */ 3451 enum dmub_phy_fsm_state { 3452 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 3453 DMUB_PHY_FSM_RESET, 3454 DMUB_PHY_FSM_RESET_RELEASED, 3455 DMUB_PHY_FSM_SRAM_LOAD_DONE, 3456 DMUB_PHY_FSM_INITIALIZED, 3457 DMUB_PHY_FSM_CALIBRATED, 3458 DMUB_PHY_FSM_CALIBRATED_LP, 3459 DMUB_PHY_FSM_CALIBRATED_PG, 3460 DMUB_PHY_FSM_POWER_DOWN, 3461 DMUB_PHY_FSM_PLL_EN, 3462 DMUB_PHY_FSM_TX_EN, 3463 DMUB_PHY_FSM_TX_EN_TEST_MODE, 3464 DMUB_PHY_FSM_FAST_LP, 3465 DMUB_PHY_FSM_P2_PLL_OFF_CPM, 3466 DMUB_PHY_FSM_P2_PLL_OFF_PG, 3467 DMUB_PHY_FSM_P2_PLL_OFF, 3468 DMUB_PHY_FSM_P2_PLL_ON, 3469 }; 3470 3471 /** 3472 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 3473 */ 3474 struct dmub_cmd_psr_copy_settings_data { 3475 /** 3476 * Flags that can be set by driver to change some PSR behaviour. 3477 */ 3478 union dmub_psr_debug_flags debug; 3479 /** 3480 * 16-bit value dicated by driver that will enable/disable different functionality. 3481 */ 3482 uint16_t psr_level; 3483 /** 3484 * DPP HW instance. 3485 */ 3486 uint8_t dpp_inst; 3487 /** 3488 * MPCC HW instance. 3489 * Not used in dmub fw, 3490 * dmub fw will get active opp by reading odm registers. 3491 */ 3492 uint8_t mpcc_inst; 3493 /** 3494 * OPP HW instance. 3495 * Not used in dmub fw, 3496 * dmub fw will get active opp by reading odm registers. 3497 */ 3498 uint8_t opp_inst; 3499 /** 3500 * OTG HW instance. 3501 */ 3502 uint8_t otg_inst; 3503 /** 3504 * DIG FE HW instance. 3505 */ 3506 uint8_t digfe_inst; 3507 /** 3508 * DIG BE HW instance. 3509 */ 3510 uint8_t digbe_inst; 3511 /** 3512 * DP PHY HW instance. 3513 */ 3514 uint8_t dpphy_inst; 3515 /** 3516 * AUX HW instance. 3517 */ 3518 uint8_t aux_inst; 3519 /** 3520 * Determines if SMU optimzations are enabled/disabled. 3521 */ 3522 uint8_t smu_optimizations_en; 3523 /** 3524 * Unused. 3525 * TODO: Remove. 3526 */ 3527 uint8_t frame_delay; 3528 /** 3529 * If RFB setup time is greater than the total VBLANK time, 3530 * it is not possible for the sink to capture the video frame 3531 * in the same frame the SDP is sent. In this case, 3532 * the frame capture indication bit should be set and an extra 3533 * static frame should be transmitted to the sink. 3534 */ 3535 uint8_t frame_cap_ind; 3536 /** 3537 * Granularity of Y offset supported by sink. 3538 */ 3539 uint8_t su_y_granularity; 3540 /** 3541 * Indicates whether sink should start capturing 3542 * immediately following active scan line, 3543 * or starting with the 2nd active scan line. 3544 */ 3545 uint8_t line_capture_indication; 3546 /** 3547 * Multi-display optimizations are implemented on certain ASICs. 3548 */ 3549 uint8_t multi_disp_optimizations_en; 3550 /** 3551 * The last possible line SDP may be transmitted without violating 3552 * the RFB setup time or entering the active video frame. 3553 */ 3554 uint16_t init_sdp_deadline; 3555 /** 3556 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 3557 */ 3558 uint8_t rate_control_caps ; 3559 /* 3560 * Force PSRSU always doing full frame update 3561 */ 3562 uint8_t force_ffu_mode; 3563 /** 3564 * Length of each horizontal line in us. 3565 */ 3566 uint32_t line_time_in_us; 3567 /** 3568 * FEC enable status in driver 3569 */ 3570 uint8_t fec_enable_status; 3571 /** 3572 * FEC re-enable delay when PSR exit. 3573 * unit is 100us, range form 0~255(0xFF). 3574 */ 3575 uint8_t fec_enable_delay_in100us; 3576 /** 3577 * PSR control version. 3578 */ 3579 uint8_t cmd_version; 3580 /** 3581 * Panel Instance. 3582 * Panel instance to identify which psr_state to use 3583 * Currently the support is only for 0 or 1 3584 */ 3585 uint8_t panel_inst; 3586 /* 3587 * DSC enable status in driver 3588 */ 3589 uint8_t dsc_enable_status; 3590 /* 3591 * Use FSM state for PSR power up/down 3592 */ 3593 uint8_t use_phy_fsm; 3594 /** 3595 * frame delay for frame re-lock 3596 */ 3597 uint8_t relock_delay_frame_cnt; 3598 /** 3599 * esd recovery indicate. 3600 */ 3601 uint8_t esd_recovery; 3602 /** 3603 * DSC Slice height. 3604 */ 3605 uint16_t dsc_slice_height; 3606 /** 3607 * Some panels request main link off before xth vertical line 3608 */ 3609 uint16_t poweroff_before_vertical_line; 3610 /** 3611 * Some panels cannot handle idle pattern during PSR entry. 3612 * To power down phy before disable stream to avoid sending 3613 * idle pattern. 3614 */ 3615 uint8_t power_down_phy_before_disable_stream; 3616 }; 3617 3618 /** 3619 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 3620 */ 3621 struct dmub_rb_cmd_psr_copy_settings { 3622 /** 3623 * Command header. 3624 */ 3625 struct dmub_cmd_header header; 3626 /** 3627 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 3628 */ 3629 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 3630 }; 3631 3632 /** 3633 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 3634 */ 3635 struct dmub_cmd_psr_set_level_data { 3636 /** 3637 * 16-bit value dicated by driver that will enable/disable different functionality. 3638 */ 3639 uint16_t psr_level; 3640 /** 3641 * PSR control version. 3642 */ 3643 uint8_t cmd_version; 3644 /** 3645 * Panel Instance. 3646 * Panel instance to identify which psr_state to use 3647 * Currently the support is only for 0 or 1 3648 */ 3649 uint8_t panel_inst; 3650 }; 3651 3652 /** 3653 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3654 */ 3655 struct dmub_rb_cmd_psr_set_level { 3656 /** 3657 * Command header. 3658 */ 3659 struct dmub_cmd_header header; 3660 /** 3661 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3662 */ 3663 struct dmub_cmd_psr_set_level_data psr_set_level_data; 3664 }; 3665 3666 struct dmub_rb_cmd_psr_enable_data { 3667 /** 3668 * PSR control version. 3669 */ 3670 uint8_t cmd_version; 3671 /** 3672 * Panel Instance. 3673 * Panel instance to identify which psr_state to use 3674 * Currently the support is only for 0 or 1 3675 */ 3676 uint8_t panel_inst; 3677 /** 3678 * Phy state to enter. 3679 * Values to use are defined in dmub_phy_fsm_state 3680 */ 3681 uint8_t phy_fsm_state; 3682 /** 3683 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 3684 * Set this using enum phy_link_rate. 3685 * This does not support HDMI/DP2 for now. 3686 */ 3687 uint8_t phy_rate; 3688 }; 3689 3690 /** 3691 * Definition of a DMUB_CMD__PSR_ENABLE command. 3692 * PSR enable/disable is controlled using the sub_type. 3693 */ 3694 struct dmub_rb_cmd_psr_enable { 3695 /** 3696 * Command header. 3697 */ 3698 struct dmub_cmd_header header; 3699 3700 struct dmub_rb_cmd_psr_enable_data data; 3701 }; 3702 3703 /** 3704 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 3705 */ 3706 struct dmub_cmd_psr_set_version_data { 3707 /** 3708 * PSR version that FW should implement. 3709 */ 3710 enum psr_version version; 3711 /** 3712 * PSR control version. 3713 */ 3714 uint8_t cmd_version; 3715 /** 3716 * Panel Instance. 3717 * Panel instance to identify which psr_state to use 3718 * Currently the support is only for 0 or 1 3719 */ 3720 uint8_t panel_inst; 3721 /** 3722 * Explicit padding to 4 byte boundary. 3723 */ 3724 uint8_t pad[2]; 3725 }; 3726 3727 /** 3728 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 3729 */ 3730 struct dmub_rb_cmd_psr_set_version { 3731 /** 3732 * Command header. 3733 */ 3734 struct dmub_cmd_header header; 3735 /** 3736 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 3737 */ 3738 struct dmub_cmd_psr_set_version_data psr_set_version_data; 3739 }; 3740 3741 struct dmub_cmd_psr_force_static_data { 3742 /** 3743 * PSR control version. 3744 */ 3745 uint8_t cmd_version; 3746 /** 3747 * Panel Instance. 3748 * Panel instance to identify which psr_state to use 3749 * Currently the support is only for 0 or 1 3750 */ 3751 uint8_t panel_inst; 3752 /** 3753 * Explicit padding to 4 byte boundary. 3754 */ 3755 uint8_t pad[2]; 3756 }; 3757 3758 /** 3759 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 3760 */ 3761 struct dmub_rb_cmd_psr_force_static { 3762 /** 3763 * Command header. 3764 */ 3765 struct dmub_cmd_header header; 3766 /** 3767 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 3768 */ 3769 struct dmub_cmd_psr_force_static_data psr_force_static_data; 3770 }; 3771 3772 /** 3773 * PSR SU debug flags. 3774 */ 3775 union dmub_psr_su_debug_flags { 3776 /** 3777 * PSR SU debug flags. 3778 */ 3779 struct { 3780 /** 3781 * Update dirty rect in SW only. 3782 */ 3783 uint8_t update_dirty_rect_only : 1; 3784 /** 3785 * Reset the cursor/plane state before processing the call. 3786 */ 3787 uint8_t reset_state : 1; 3788 } bitfields; 3789 3790 /** 3791 * Union for debug flags. 3792 */ 3793 uint32_t u32All; 3794 }; 3795 3796 /** 3797 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 3798 * This triggers a selective update for PSR SU. 3799 */ 3800 struct dmub_cmd_update_dirty_rect_data { 3801 /** 3802 * Dirty rects from OS. 3803 */ 3804 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 3805 /** 3806 * PSR SU debug flags. 3807 */ 3808 union dmub_psr_su_debug_flags debug_flags; 3809 /** 3810 * OTG HW instance. 3811 */ 3812 uint8_t pipe_idx; 3813 /** 3814 * Number of dirty rects. 3815 */ 3816 uint8_t dirty_rect_count; 3817 /** 3818 * PSR control version. 3819 */ 3820 uint8_t cmd_version; 3821 /** 3822 * Panel Instance. 3823 * Panel instance to identify which psr_state to use 3824 * Currently the support is only for 0 or 1 3825 */ 3826 uint8_t panel_inst; 3827 }; 3828 3829 /** 3830 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 3831 */ 3832 struct dmub_rb_cmd_update_dirty_rect { 3833 /** 3834 * Command header. 3835 */ 3836 struct dmub_cmd_header header; 3837 /** 3838 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 3839 */ 3840 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 3841 }; 3842 3843 /** 3844 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 3845 */ 3846 union dmub_reg_cursor_control_cfg { 3847 struct { 3848 uint32_t cur_enable: 1; 3849 uint32_t reser0: 3; 3850 uint32_t cur_2x_magnify: 1; 3851 uint32_t reser1: 3; 3852 uint32_t mode: 3; 3853 uint32_t reser2: 5; 3854 uint32_t pitch: 2; 3855 uint32_t reser3: 6; 3856 uint32_t line_per_chunk: 5; 3857 uint32_t reser4: 3; 3858 } bits; 3859 uint32_t raw; 3860 }; 3861 struct dmub_cursor_position_cache_hubp { 3862 union dmub_reg_cursor_control_cfg cur_ctl; 3863 union dmub_reg_position_cfg { 3864 struct { 3865 uint32_t cur_x_pos: 16; 3866 uint32_t cur_y_pos: 16; 3867 } bits; 3868 uint32_t raw; 3869 } position; 3870 union dmub_reg_hot_spot_cfg { 3871 struct { 3872 uint32_t hot_x: 16; 3873 uint32_t hot_y: 16; 3874 } bits; 3875 uint32_t raw; 3876 } hot_spot; 3877 union dmub_reg_dst_offset_cfg { 3878 struct { 3879 uint32_t dst_x_offset: 13; 3880 uint32_t reserved: 19; 3881 } bits; 3882 uint32_t raw; 3883 } dst_offset; 3884 }; 3885 3886 union dmub_reg_cur0_control_cfg { 3887 struct { 3888 uint32_t cur0_enable: 1; 3889 uint32_t expansion_mode: 1; 3890 uint32_t reser0: 1; 3891 uint32_t cur0_rom_en: 1; 3892 uint32_t mode: 3; 3893 uint32_t reserved: 25; 3894 } bits; 3895 uint32_t raw; 3896 }; 3897 struct dmub_cursor_position_cache_dpp { 3898 union dmub_reg_cur0_control_cfg cur0_ctl; 3899 }; 3900 struct dmub_cursor_position_cfg { 3901 struct dmub_cursor_position_cache_hubp pHubp; 3902 struct dmub_cursor_position_cache_dpp pDpp; 3903 uint8_t pipe_idx; 3904 /* 3905 * Padding is required. To be 4 Bytes Aligned. 3906 */ 3907 uint8_t padding[3]; 3908 }; 3909 3910 struct dmub_cursor_attribute_cache_hubp { 3911 uint32_t SURFACE_ADDR_HIGH; 3912 uint32_t SURFACE_ADDR; 3913 union dmub_reg_cursor_control_cfg cur_ctl; 3914 union dmub_reg_cursor_size_cfg { 3915 struct { 3916 uint32_t width: 16; 3917 uint32_t height: 16; 3918 } bits; 3919 uint32_t raw; 3920 } size; 3921 union dmub_reg_cursor_settings_cfg { 3922 struct { 3923 uint32_t dst_y_offset: 8; 3924 uint32_t chunk_hdl_adjust: 2; 3925 uint32_t reserved: 22; 3926 } bits; 3927 uint32_t raw; 3928 } settings; 3929 }; 3930 struct dmub_cursor_attribute_cache_dpp { 3931 union dmub_reg_cur0_control_cfg cur0_ctl; 3932 }; 3933 struct dmub_cursor_attributes_cfg { 3934 struct dmub_cursor_attribute_cache_hubp aHubp; 3935 struct dmub_cursor_attribute_cache_dpp aDpp; 3936 }; 3937 3938 struct dmub_cmd_update_cursor_payload0 { 3939 /** 3940 * Cursor dirty rects. 3941 */ 3942 struct dmub_rect cursor_rect; 3943 /** 3944 * PSR SU debug flags. 3945 */ 3946 union dmub_psr_su_debug_flags debug_flags; 3947 /** 3948 * Cursor enable/disable. 3949 */ 3950 uint8_t enable; 3951 /** 3952 * OTG HW instance. 3953 */ 3954 uint8_t pipe_idx; 3955 /** 3956 * PSR control version. 3957 */ 3958 uint8_t cmd_version; 3959 /** 3960 * Panel Instance. 3961 * Panel instance to identify which psr_state to use 3962 * Currently the support is only for 0 or 1 3963 */ 3964 uint8_t panel_inst; 3965 /** 3966 * Cursor Position Register. 3967 * Registers contains Hubp & Dpp modules 3968 */ 3969 struct dmub_cursor_position_cfg position_cfg; 3970 }; 3971 3972 struct dmub_cmd_update_cursor_payload1 { 3973 struct dmub_cursor_attributes_cfg attribute_cfg; 3974 }; 3975 3976 union dmub_cmd_update_cursor_info_data { 3977 struct dmub_cmd_update_cursor_payload0 payload0; 3978 struct dmub_cmd_update_cursor_payload1 payload1; 3979 }; 3980 /** 3981 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 3982 */ 3983 struct dmub_rb_cmd_update_cursor_info { 3984 /** 3985 * Command header. 3986 */ 3987 struct dmub_cmd_header header; 3988 /** 3989 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 3990 */ 3991 union dmub_cmd_update_cursor_info_data update_cursor_info_data; 3992 }; 3993 3994 /** 3995 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3996 */ 3997 struct dmub_cmd_psr_set_vtotal_data { 3998 /** 3999 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 4000 */ 4001 uint16_t psr_vtotal_idle; 4002 /** 4003 * PSR control version. 4004 */ 4005 uint8_t cmd_version; 4006 /** 4007 * Panel Instance. 4008 * Panel instance to identify which psr_state to use 4009 * Currently the support is only for 0 or 1 4010 */ 4011 uint8_t panel_inst; 4012 /* 4013 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 4014 */ 4015 uint16_t psr_vtotal_su; 4016 /** 4017 * Explicit padding to 4 byte boundary. 4018 */ 4019 uint8_t pad2[2]; 4020 }; 4021 4022 /** 4023 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 4024 */ 4025 struct dmub_rb_cmd_psr_set_vtotal { 4026 /** 4027 * Command header. 4028 */ 4029 struct dmub_cmd_header header; 4030 /** 4031 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 4032 */ 4033 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 4034 }; 4035 4036 /** 4037 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 4038 */ 4039 struct dmub_cmd_psr_set_power_opt_data { 4040 /** 4041 * PSR control version. 4042 */ 4043 uint8_t cmd_version; 4044 /** 4045 * Panel Instance. 4046 * Panel instance to identify which psr_state to use 4047 * Currently the support is only for 0 or 1 4048 */ 4049 uint8_t panel_inst; 4050 /** 4051 * Explicit padding to 4 byte boundary. 4052 */ 4053 uint8_t pad[2]; 4054 /** 4055 * PSR power option 4056 */ 4057 uint32_t power_opt; 4058 }; 4059 4060 /** 4061 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 4062 */ 4063 struct dmub_rb_cmd_psr_set_power_opt { 4064 /** 4065 * Command header. 4066 */ 4067 struct dmub_cmd_header header; 4068 /** 4069 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 4070 */ 4071 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 4072 }; 4073 4074 enum dmub_alpm_mode { 4075 ALPM_AUXWAKE = 0, 4076 ALPM_AUXLESS = 1, 4077 ALPM_UNSUPPORTED = 2, 4078 }; 4079 4080 /** 4081 * Definition of Replay Residency GPINT command. 4082 * Bit[0] - Residency mode for Revision 0 4083 * Bit[1] - Enable/Disable state 4084 * Bit[2-3] - Revision number 4085 * Bit[4-7] - Residency mode for Revision 1 4086 * Bit[8] - Panel instance 4087 * Bit[9-15] - Reserved 4088 */ 4089 4090 enum pr_residency_mode { 4091 PR_RESIDENCY_MODE_PHY = 0x0, 4092 PR_RESIDENCY_MODE_ALPM, 4093 PR_RESIDENCY_MODE_IPS2, 4094 PR_RESIDENCY_MODE_FRAME_CNT, 4095 PR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 4096 }; 4097 4098 #define REPLAY_RESIDENCY_MODE_SHIFT (0) 4099 #define REPLAY_RESIDENCY_ENABLE_SHIFT (1) 4100 #define REPLAY_RESIDENCY_REVISION_SHIFT (2) 4101 #define REPLAY_RESIDENCY_MODE2_SHIFT (4) 4102 4103 #define REPLAY_RESIDENCY_MODE_MASK (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 4104 # define REPLAY_RESIDENCY_FIELD_MODE_PHY (0x0 << REPLAY_RESIDENCY_MODE_SHIFT) 4105 # define REPLAY_RESIDENCY_FIELD_MODE_ALPM (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 4106 4107 #define REPLAY_RESIDENCY_MODE2_MASK (0xF << REPLAY_RESIDENCY_MODE2_SHIFT) 4108 # define REPLAY_RESIDENCY_FIELD_MODE2_IPS (0x1 << REPLAY_RESIDENCY_MODE2_SHIFT) 4109 # define REPLAY_RESIDENCY_FIELD_MODE2_FRAME_CNT (0x2 << REPLAY_RESIDENCY_MODE2_SHIFT) 4110 # define REPLAY_RESIDENCY_FIELD_MODE2_EN_PERIOD (0x3 << REPLAY_RESIDENCY_MODE2_SHIFT) 4111 4112 #define REPLAY_RESIDENCY_ENABLE_MASK (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 4113 # define REPLAY_RESIDENCY_DISABLE (0x0 << REPLAY_RESIDENCY_ENABLE_SHIFT) 4114 # define REPLAY_RESIDENCY_ENABLE (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 4115 4116 #define REPLAY_RESIDENCY_REVISION_MASK (0x3 << REPLAY_RESIDENCY_REVISION_SHIFT) 4117 # define REPLAY_RESIDENCY_REVISION_0 (0x0 << REPLAY_RESIDENCY_REVISION_SHIFT) 4118 # define REPLAY_RESIDENCY_REVISION_1 (0x1 << REPLAY_RESIDENCY_REVISION_SHIFT) 4119 4120 /** 4121 * Definition of a replay_state. 4122 */ 4123 enum replay_state { 4124 REPLAY_STATE_0 = 0x0, 4125 REPLAY_STATE_1 = 0x10, 4126 REPLAY_STATE_1A = 0x11, 4127 REPLAY_STATE_2 = 0x20, 4128 REPLAY_STATE_2A = 0x21, 4129 REPLAY_STATE_3 = 0x30, 4130 REPLAY_STATE_3INIT = 0x31, 4131 REPLAY_STATE_4 = 0x40, 4132 REPLAY_STATE_4A = 0x41, 4133 REPLAY_STATE_4B = 0x42, 4134 REPLAY_STATE_4C = 0x43, 4135 REPLAY_STATE_4D = 0x44, 4136 REPLAY_STATE_4E = 0x45, 4137 REPLAY_STATE_4B_LOCKED = 0x4A, 4138 REPLAY_STATE_4C_UNLOCKED = 0x4B, 4139 REPLAY_STATE_5 = 0x50, 4140 REPLAY_STATE_5A = 0x51, 4141 REPLAY_STATE_5B = 0x52, 4142 REPLAY_STATE_5A_LOCKED = 0x5A, 4143 REPLAY_STATE_5B_UNLOCKED = 0x5B, 4144 REPLAY_STATE_6 = 0x60, 4145 REPLAY_STATE_6A = 0x61, 4146 REPLAY_STATE_6B = 0x62, 4147 REPLAY_STATE_INVALID = 0xFF, 4148 }; 4149 4150 /** 4151 * Replay command sub-types. 4152 */ 4153 enum dmub_cmd_replay_type { 4154 /** 4155 * Copy driver-calculated parameters to REPLAY state. 4156 */ 4157 DMUB_CMD__REPLAY_COPY_SETTINGS = 0, 4158 /** 4159 * Enable REPLAY. 4160 */ 4161 DMUB_CMD__REPLAY_ENABLE = 1, 4162 /** 4163 * Set Replay power option. 4164 */ 4165 DMUB_CMD__SET_REPLAY_POWER_OPT = 2, 4166 /** 4167 * Set coasting vtotal. 4168 */ 4169 DMUB_CMD__REPLAY_SET_COASTING_VTOTAL = 3, 4170 /** 4171 * Set power opt and coasting vtotal. 4172 */ 4173 DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL = 4, 4174 /** 4175 * Set disabled iiming sync. 4176 */ 4177 DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED = 5, 4178 /** 4179 * Set Residency Frameupdate Timer. 4180 */ 4181 DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER = 6, 4182 /** 4183 * Set pseudo vtotal 4184 */ 4185 DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL = 7, 4186 /** 4187 * Set adaptive sync sdp enabled 4188 */ 4189 DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP = 8, 4190 /** 4191 * Set version 4192 */ 4193 DMUB_CMD__REPLAY_SET_VERSION = 9, 4194 /** 4195 * Set Replay General command. 4196 */ 4197 DMUB_CMD__REPLAY_SET_GENERAL_CMD = 16, 4198 }; 4199 4200 /** 4201 * Replay general command sub-types. 4202 */ 4203 enum dmub_cmd_replay_general_subtype { 4204 REPLAY_GENERAL_CMD_NOT_SUPPORTED = -1, 4205 /** 4206 * TODO: For backward compatible, allow new command only. 4207 * REPLAY_GENERAL_CMD_SET_TIMING_SYNC_SUPPORTED, 4208 * REPLAY_GENERAL_CMD_SET_RESIDENCY_FRAMEUPDATE_TIMER, 4209 * REPLAY_GENERAL_CMD_SET_PSEUDO_VTOTAL, 4210 */ 4211 REPLAY_GENERAL_CMD_DISABLED_ADAPTIVE_SYNC_SDP, 4212 REPLAY_GENERAL_CMD_DISABLED_DESYNC_ERROR_DETECTION, 4213 REPLAY_GENERAL_CMD_UPDATE_ERROR_STATUS, 4214 REPLAY_GENERAL_CMD_SET_LOW_RR_ACTIVATE, 4215 }; 4216 4217 struct dmub_alpm_auxless_data { 4218 uint16_t lfps_setup_ns; 4219 uint16_t lfps_period_ns; 4220 uint16_t lfps_silence_ns; 4221 uint16_t lfps_t1_t2_override_us; 4222 short lfps_t1_t2_offset_us; 4223 uint8_t lttpr_count; 4224 /* 4225 * Padding to align structure to 4 byte boundary. 4226 */ 4227 uint8_t pad[1]; 4228 }; 4229 4230 /** 4231 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 4232 */ 4233 struct dmub_cmd_replay_copy_settings_data { 4234 /** 4235 * Flags that can be set by driver to change some replay behaviour. 4236 */ 4237 union replay_debug_flags debug; 4238 4239 /** 4240 * @flags: Flags used to determine feature functionality. 4241 */ 4242 union replay_hw_flags flags; 4243 4244 /** 4245 * DPP HW instance. 4246 */ 4247 uint8_t dpp_inst; 4248 /** 4249 * OTG HW instance. 4250 */ 4251 uint8_t otg_inst; 4252 /** 4253 * DIG FE HW instance. 4254 */ 4255 uint8_t digfe_inst; 4256 /** 4257 * DIG BE HW instance. 4258 */ 4259 uint8_t digbe_inst; 4260 /** 4261 * AUX HW instance. 4262 */ 4263 uint8_t aux_inst; 4264 /** 4265 * Panel Instance. 4266 * Panel isntance to identify which psr_state to use 4267 * Currently the support is only for 0 or 1 4268 */ 4269 uint8_t panel_inst; 4270 /** 4271 * @pixel_deviation_per_line: Indicate the maximum pixel deviation per line compare 4272 * to Source timing when Sink maintains coasting vtotal during the Replay normal sleep mode 4273 */ 4274 uint8_t pixel_deviation_per_line; 4275 /** 4276 * @max_deviation_line: The max number of deviation line that can keep the timing 4277 * synchronized between the Source and Sink during Replay normal sleep mode. 4278 */ 4279 uint8_t max_deviation_line; 4280 /** 4281 * Length of each horizontal line in ns. 4282 */ 4283 uint32_t line_time_in_ns; 4284 /** 4285 * PHY instance. 4286 */ 4287 uint8_t dpphy_inst; 4288 /** 4289 * Determines if SMU optimzations are enabled/disabled. 4290 */ 4291 uint8_t smu_optimizations_en; 4292 /** 4293 * Determines if timing sync are enabled/disabled. 4294 */ 4295 uint8_t replay_timing_sync_supported; 4296 /* 4297 * Use FSM state for Replay power up/down 4298 */ 4299 uint8_t use_phy_fsm; 4300 /** 4301 * Use for AUX-less ALPM LFPS wake operation 4302 */ 4303 struct dmub_alpm_auxless_data auxless_alpm_data; 4304 /** 4305 * @hpo_stream_enc_inst: HPO stream encoder instance 4306 */ 4307 uint8_t hpo_stream_enc_inst; 4308 /** 4309 * @hpo_link_enc_inst: HPO link encoder instance 4310 */ 4311 uint8_t hpo_link_enc_inst; 4312 /** 4313 * Determines if fast resync in ultra sleep mode is enabled/disabled. 4314 */ 4315 uint8_t replay_support_fast_resync_in_ultra_sleep_mode; 4316 /** 4317 * @pad: Align structure to 4 byte boundary. 4318 */ 4319 uint8_t pad[1]; 4320 }; 4321 4322 4323 /** 4324 * Replay versions. 4325 */ 4326 enum replay_version { 4327 /** 4328 * FreeSync Replay 4329 */ 4330 REPLAY_VERSION_FREESYNC_REPLAY = 0, 4331 /** 4332 * Panel Replay 4333 */ 4334 REPLAY_VERSION_PANEL_REPLAY = 1, 4335 /** 4336 * Replay not supported. 4337 */ 4338 REPLAY_VERSION_UNSUPPORTED = 0xFF, 4339 }; 4340 4341 /** 4342 * Data passed from driver to FW in a DMUB_CMD___SET_REPLAY_VERSION command. 4343 */ 4344 struct dmub_cmd_replay_set_version_data { 4345 /** 4346 * Panel Instance. 4347 * Panel instance to identify which psr_state to use 4348 * Currently the support is only for 0 or 1 4349 */ 4350 uint8_t panel_inst; 4351 /** 4352 * PSR version that FW should implement. 4353 */ 4354 enum replay_version version; 4355 /** 4356 * PSR control version. 4357 */ 4358 uint8_t cmd_version; 4359 /** 4360 * Explicit padding to 4 byte boundary. 4361 */ 4362 uint8_t pad[2]; 4363 }; 4364 4365 /** 4366 * Definition of a DMUB_CMD__REPLAY_SET_VERSION command. 4367 */ 4368 struct dmub_rb_cmd_replay_set_version { 4369 /** 4370 * Command header. 4371 */ 4372 struct dmub_cmd_header header; 4373 /** 4374 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_VERSION command. 4375 */ 4376 struct dmub_cmd_replay_set_version_data replay_set_version_data; 4377 }; 4378 4379 /** 4380 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 4381 */ 4382 struct dmub_rb_cmd_replay_copy_settings { 4383 /** 4384 * Command header. 4385 */ 4386 struct dmub_cmd_header header; 4387 /** 4388 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 4389 */ 4390 struct dmub_cmd_replay_copy_settings_data replay_copy_settings_data; 4391 }; 4392 4393 /** 4394 * Replay disable / enable state for dmub_rb_cmd_replay_enable_data.enable 4395 */ 4396 enum replay_enable { 4397 /** 4398 * Disable REPLAY. 4399 */ 4400 REPLAY_DISABLE = 0, 4401 /** 4402 * Enable REPLAY. 4403 */ 4404 REPLAY_ENABLE = 1, 4405 }; 4406 4407 /** 4408 * Data passed from driver to FW in a DMUB_CMD__SMART_POWER_HDR_ENABLE command. 4409 */ 4410 struct dmub_rb_cmd_smart_power_hdr_enable_data { 4411 /** 4412 * SMART_POWER_HDR enable or disable. 4413 */ 4414 uint8_t enable; 4415 /** 4416 * Panel Instance. 4417 * Panel isntance to identify which replay_state to use 4418 * Currently the support is only for 0 or 1 4419 */ 4420 uint8_t panel_inst; 4421 4422 uint16_t peak_nits; 4423 /** 4424 * OTG HW instance. 4425 */ 4426 uint8_t otg_inst; 4427 /** 4428 * DIG FE HW instance. 4429 */ 4430 uint8_t digfe_inst; 4431 /** 4432 * DIG BE HW instance. 4433 */ 4434 uint8_t digbe_inst; 4435 uint8_t debugcontrol; 4436 /* 4437 * vertical interrupt trigger line 4438 */ 4439 uint32_t triggerline; 4440 4441 uint16_t fixed_max_cll; 4442 4443 uint8_t pad[2]; 4444 }; 4445 4446 /** 4447 * Data passed from driver to FW in a DMUB_CMD__REPLAY_ENABLE command. 4448 */ 4449 struct dmub_rb_cmd_replay_enable_data { 4450 /** 4451 * Replay enable or disable. 4452 */ 4453 uint8_t enable; 4454 /** 4455 * Panel Instance. 4456 * Panel isntance to identify which replay_state to use 4457 * Currently the support is only for 0 or 1 4458 */ 4459 uint8_t panel_inst; 4460 /** 4461 * Phy state to enter. 4462 * Values to use are defined in dmub_phy_fsm_state 4463 */ 4464 uint8_t phy_fsm_state; 4465 /** 4466 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 4467 * Set this using enum phy_link_rate. 4468 * This does not support HDMI/DP2 for now. 4469 */ 4470 uint8_t phy_rate; 4471 }; 4472 4473 /** 4474 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 4475 * Replay enable/disable is controlled using action in data. 4476 */ 4477 struct dmub_rb_cmd_replay_enable { 4478 /** 4479 * Command header. 4480 */ 4481 struct dmub_cmd_header header; 4482 4483 struct dmub_rb_cmd_replay_enable_data data; 4484 }; 4485 4486 /** 4487 * Data passed from driver to FW in a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4488 */ 4489 struct dmub_cmd_replay_set_power_opt_data { 4490 /** 4491 * Panel Instance. 4492 * Panel isntance to identify which replay_state to use 4493 * Currently the support is only for 0 or 1 4494 */ 4495 uint8_t panel_inst; 4496 /** 4497 * Explicit padding to 4 byte boundary. 4498 */ 4499 uint8_t pad[3]; 4500 /** 4501 * REPLAY power option 4502 */ 4503 uint32_t power_opt; 4504 }; 4505 4506 /** 4507 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4508 */ 4509 struct dmub_cmd_replay_set_timing_sync_data { 4510 /** 4511 * Panel Instance. 4512 * Panel isntance to identify which replay_state to use 4513 * Currently the support is only for 0 or 1 4514 */ 4515 uint8_t panel_inst; 4516 /** 4517 * REPLAY set_timing_sync 4518 */ 4519 uint8_t timing_sync_supported; 4520 /** 4521 * Explicit padding to 4 byte boundary. 4522 */ 4523 uint8_t pad[2]; 4524 }; 4525 4526 /** 4527 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4528 */ 4529 struct dmub_cmd_replay_set_pseudo_vtotal { 4530 /** 4531 * Panel Instance. 4532 * Panel isntance to identify which replay_state to use 4533 * Currently the support is only for 0 or 1 4534 */ 4535 uint8_t panel_inst; 4536 /** 4537 * Source Vtotal that Replay + IPS + ABM full screen video src vtotal 4538 */ 4539 uint16_t vtotal; 4540 /** 4541 * Explicit padding to 4 byte boundary. 4542 */ 4543 uint8_t pad; 4544 }; 4545 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data { 4546 /** 4547 * Panel Instance. 4548 * Panel isntance to identify which replay_state to use 4549 * Currently the support is only for 0 or 1 4550 */ 4551 uint8_t panel_inst; 4552 /** 4553 * enabled: set adaptive sync sdp enabled 4554 */ 4555 uint8_t force_disabled; 4556 4557 uint8_t pad[2]; 4558 }; 4559 struct dmub_cmd_replay_set_general_cmd_data { 4560 /** 4561 * Panel Instance. 4562 * Panel isntance to identify which replay_state to use 4563 * Currently the support is only for 0 or 1 4564 */ 4565 uint8_t panel_inst; 4566 /** 4567 * subtype: replay general cmd sub type 4568 */ 4569 uint8_t subtype; 4570 4571 uint8_t pad[2]; 4572 /** 4573 * config data with param1 and param2 4574 */ 4575 uint32_t param1; 4576 4577 uint32_t param2; 4578 }; 4579 4580 /** 4581 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4582 */ 4583 struct dmub_rb_cmd_replay_set_power_opt { 4584 /** 4585 * Command header. 4586 */ 4587 struct dmub_cmd_header header; 4588 /** 4589 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4590 */ 4591 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 4592 }; 4593 4594 /** 4595 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4596 */ 4597 struct dmub_cmd_replay_set_coasting_vtotal_data { 4598 /** 4599 * 16-bit value dicated by driver that indicates the coasting vtotal. 4600 */ 4601 uint16_t coasting_vtotal; 4602 /** 4603 * REPLAY control version. 4604 */ 4605 uint8_t cmd_version; 4606 /** 4607 * Panel Instance. 4608 * Panel isntance to identify which replay_state to use 4609 * Currently the support is only for 0 or 1 4610 */ 4611 uint8_t panel_inst; 4612 /** 4613 * 16-bit value dicated by driver that indicates the coasting vtotal high byte part. 4614 */ 4615 uint16_t coasting_vtotal_high; 4616 /** 4617 * frame skip number. 4618 */ 4619 uint16_t frame_skip_number; 4620 }; 4621 4622 /** 4623 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4624 */ 4625 struct dmub_rb_cmd_replay_set_coasting_vtotal { 4626 /** 4627 * Command header. 4628 */ 4629 struct dmub_cmd_header header; 4630 /** 4631 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4632 */ 4633 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 4634 }; 4635 4636 /** 4637 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 4638 */ 4639 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal { 4640 /** 4641 * Command header. 4642 */ 4643 struct dmub_cmd_header header; 4644 /** 4645 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4646 */ 4647 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 4648 /** 4649 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4650 */ 4651 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 4652 }; 4653 4654 /** 4655 * Definition of a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4656 */ 4657 struct dmub_rb_cmd_replay_set_timing_sync { 4658 /** 4659 * Command header. 4660 */ 4661 struct dmub_cmd_header header; 4662 /** 4663 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4664 */ 4665 struct dmub_cmd_replay_set_timing_sync_data replay_set_timing_sync_data; 4666 }; 4667 4668 /** 4669 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4670 */ 4671 struct dmub_rb_cmd_replay_set_pseudo_vtotal { 4672 /** 4673 * Command header. 4674 */ 4675 struct dmub_cmd_header header; 4676 /** 4677 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4678 */ 4679 struct dmub_cmd_replay_set_pseudo_vtotal data; 4680 }; 4681 4682 /** 4683 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 4684 */ 4685 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp { 4686 /** 4687 * Command header. 4688 */ 4689 struct dmub_cmd_header header; 4690 /** 4691 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 4692 */ 4693 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data data; 4694 }; 4695 4696 /** 4697 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 4698 */ 4699 struct dmub_rb_cmd_replay_set_general_cmd { 4700 /** 4701 * Command header. 4702 */ 4703 struct dmub_cmd_header header; 4704 /** 4705 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 4706 */ 4707 struct dmub_cmd_replay_set_general_cmd_data data; 4708 }; 4709 4710 /** 4711 * Data passed from driver to FW in DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 4712 */ 4713 struct dmub_cmd_replay_frameupdate_timer_data { 4714 /** 4715 * Panel Instance. 4716 * Panel isntance to identify which replay_state to use 4717 * Currently the support is only for 0 or 1 4718 */ 4719 uint8_t panel_inst; 4720 /** 4721 * Replay Frameupdate Timer Enable or not 4722 */ 4723 uint8_t enable; 4724 /** 4725 * REPLAY force reflash frame update number 4726 */ 4727 uint16_t frameupdate_count; 4728 }; 4729 /** 4730 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER 4731 */ 4732 struct dmub_rb_cmd_replay_set_frameupdate_timer { 4733 /** 4734 * Command header. 4735 */ 4736 struct dmub_cmd_header header; 4737 /** 4738 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4739 */ 4740 struct dmub_cmd_replay_frameupdate_timer_data data; 4741 }; 4742 4743 /** 4744 * Definition union of replay command set 4745 */ 4746 union dmub_replay_cmd_set { 4747 /** 4748 * Panel Instance. 4749 * Panel isntance to identify which replay_state to use 4750 * Currently the support is only for 0 or 1 4751 */ 4752 uint8_t panel_inst; 4753 /** 4754 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command data. 4755 */ 4756 struct dmub_cmd_replay_set_timing_sync_data sync_data; 4757 /** 4758 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command data. 4759 */ 4760 struct dmub_cmd_replay_frameupdate_timer_data timer_data; 4761 /** 4762 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command data. 4763 */ 4764 struct dmub_cmd_replay_set_pseudo_vtotal pseudo_vtotal_data; 4765 /** 4766 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command data. 4767 */ 4768 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data disabled_adaptive_sync_sdp_data; 4769 /** 4770 * Definition of DMUB_CMD__REPLAY_SET_VERSION command data. 4771 */ 4772 struct dmub_cmd_replay_set_version_data version_data; 4773 /** 4774 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command data. 4775 */ 4776 struct dmub_cmd_replay_set_general_cmd_data set_general_cmd_data; 4777 }; 4778 4779 /** 4780 * SMART POWER HDR command sub-types. 4781 */ 4782 enum dmub_cmd_smart_power_hdr_type { 4783 4784 /** 4785 * Enable/Disable SMART_POWER_HDR. 4786 */ 4787 DMUB_CMD__SMART_POWER_HDR_ENABLE = 1, 4788 /** 4789 * Get current MaxCLL value if SMART POWER HDR is enabled. 4790 */ 4791 DMUB_CMD__SMART_POWER_HDR_GETMAXCLL = 2, 4792 }; 4793 4794 /** 4795 * Definition of a DMUB_CMD__SMART_POWER_HDR command. 4796 */ 4797 struct dmub_rb_cmd_smart_power_hdr_enable { 4798 /** 4799 * Command header. 4800 */ 4801 struct dmub_cmd_header header; 4802 4803 struct dmub_rb_cmd_smart_power_hdr_enable_data data; 4804 }; 4805 4806 struct dmub_cmd_smart_power_hdr_getmaxcll_input { 4807 uint8_t panel_inst; 4808 uint8_t pad[3]; 4809 }; 4810 4811 struct dmub_cmd_smart_power_hdr_getmaxcll_output { 4812 uint16_t current_max_cll; 4813 uint8_t pad[2]; 4814 }; 4815 4816 /** 4817 * Definition of a DMUB_CMD__SMART_POWER_HDR command. 4818 */ 4819 struct dmub_rb_cmd_smart_power_hdr_getmaxcll { 4820 struct dmub_cmd_header header; /**< Command header */ 4821 /** 4822 * Data passed from driver to FW in a DMUB_CMD__SMART_POWER_HDR_GETMAXCLL command. 4823 */ 4824 union dmub_cmd_smart_power_hdr_getmaxcll_data { 4825 struct dmub_cmd_smart_power_hdr_getmaxcll_input input; /**< Input */ 4826 struct dmub_cmd_smart_power_hdr_getmaxcll_output output; /**< Output */ 4827 uint32_t output_raw; /**< Raw data output */ 4828 } data; 4829 }; 4830 4831 /** 4832 * Set of HW components that can be locked. 4833 * 4834 * Note: If updating with more HW components, fields 4835 * in dmub_inbox0_cmd_lock_hw must be updated to match. 4836 */ 4837 union dmub_hw_lock_flags { 4838 /** 4839 * Set of HW components that can be locked. 4840 */ 4841 struct { 4842 /** 4843 * Lock/unlock OTG master update lock. 4844 */ 4845 uint8_t lock_pipe : 1; 4846 /** 4847 * Lock/unlock cursor. 4848 */ 4849 uint8_t lock_cursor : 1; 4850 /** 4851 * Lock/unlock global update lock. 4852 */ 4853 uint8_t lock_dig : 1; 4854 /** 4855 * Triple buffer lock requires additional hw programming to usual OTG master lock. 4856 */ 4857 uint8_t triple_buffer_lock : 1; 4858 } bits; 4859 4860 /** 4861 * Union for HW Lock flags. 4862 */ 4863 uint8_t u8All; 4864 }; 4865 4866 /** 4867 * Instances of HW to be locked. 4868 * 4869 * Note: If updating with more HW components, fields 4870 * in dmub_inbox0_cmd_lock_hw must be updated to match. 4871 */ 4872 struct dmub_hw_lock_inst_flags { 4873 /** 4874 * OTG HW instance for OTG master update lock. 4875 */ 4876 uint8_t otg_inst; 4877 /** 4878 * OPP instance for cursor lock. 4879 */ 4880 uint8_t opp_inst; 4881 /** 4882 * OTG HW instance for global update lock. 4883 * TODO: Remove, and re-use otg_inst. 4884 */ 4885 uint8_t dig_inst; 4886 /** 4887 * Explicit pad to 4 byte boundary. 4888 */ 4889 uint8_t pad; 4890 }; 4891 4892 /** 4893 * Clients that can acquire the HW Lock Manager. 4894 * 4895 * Note: If updating with more clients, fields in 4896 * dmub_inbox0_cmd_lock_hw must be updated to match. 4897 */ 4898 enum hw_lock_client { 4899 /** 4900 * Driver is the client of HW Lock Manager. 4901 */ 4902 HW_LOCK_CLIENT_DRIVER = 0, 4903 /** 4904 * PSR SU is the client of HW Lock Manager. 4905 */ 4906 HW_LOCK_CLIENT_PSR_SU = 1, 4907 HW_LOCK_CLIENT_SUBVP = 3, 4908 /** 4909 * Replay is the client of HW Lock Manager. 4910 */ 4911 HW_LOCK_CLIENT_REPLAY = 4, 4912 HW_LOCK_CLIENT_FAMS2 = 5, 4913 HW_LOCK_CLIENT_CURSOR_OFFLOAD = 6, 4914 /** 4915 * Invalid client. 4916 */ 4917 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 4918 }; 4919 4920 /** 4921 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 4922 */ 4923 struct dmub_cmd_lock_hw_data { 4924 /** 4925 * Specifies the client accessing HW Lock Manager. 4926 */ 4927 enum hw_lock_client client; 4928 /** 4929 * HW instances to be locked. 4930 */ 4931 struct dmub_hw_lock_inst_flags inst_flags; 4932 /** 4933 * Which components to be locked. 4934 */ 4935 union dmub_hw_lock_flags hw_locks; 4936 /** 4937 * Specifies lock/unlock. 4938 */ 4939 uint8_t lock; 4940 /** 4941 * HW can be unlocked separately from releasing the HW Lock Mgr. 4942 * This flag is set if the client wishes to release the object. 4943 */ 4944 uint8_t should_release; 4945 /** 4946 * Explicit padding to 4 byte boundary. 4947 */ 4948 uint8_t pad; 4949 }; 4950 4951 /** 4952 * Definition of a DMUB_CMD__HW_LOCK command. 4953 * Command is used by driver and FW. 4954 */ 4955 struct dmub_rb_cmd_lock_hw { 4956 /** 4957 * Command header. 4958 */ 4959 struct dmub_cmd_header header; 4960 /** 4961 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 4962 */ 4963 struct dmub_cmd_lock_hw_data lock_hw_data; 4964 }; 4965 4966 /** 4967 * ABM command sub-types. 4968 */ 4969 enum dmub_cmd_abm_type { 4970 /** 4971 * Initialize parameters for ABM algorithm. 4972 * Data is passed through an indirect buffer. 4973 */ 4974 DMUB_CMD__ABM_INIT_CONFIG = 0, 4975 /** 4976 * Set OTG and panel HW instance. 4977 */ 4978 DMUB_CMD__ABM_SET_PIPE = 1, 4979 /** 4980 * Set user requested backklight level. 4981 */ 4982 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 4983 /** 4984 * Set ABM operating/aggression level. 4985 */ 4986 DMUB_CMD__ABM_SET_LEVEL = 3, 4987 /** 4988 * Set ambient light level. 4989 */ 4990 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 4991 /** 4992 * Enable/disable fractional duty cycle for backlight PWM. 4993 */ 4994 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 4995 4996 /** 4997 * unregister vertical interrupt after steady state is reached 4998 */ 4999 DMUB_CMD__ABM_PAUSE = 6, 5000 5001 /** 5002 * Save and Restore ABM state. On save we save parameters, and 5003 * on restore we update state with passed in data. 5004 */ 5005 DMUB_CMD__ABM_SAVE_RESTORE = 7, 5006 5007 /** 5008 * Query ABM caps. 5009 */ 5010 DMUB_CMD__ABM_QUERY_CAPS = 8, 5011 5012 /** 5013 * Set ABM Events 5014 */ 5015 DMUB_CMD__ABM_SET_EVENT = 9, 5016 5017 /** 5018 * Get the current ACE curve. 5019 */ 5020 DMUB_CMD__ABM_GET_ACE_CURVE = 10, 5021 5022 /** 5023 * Get current histogram data 5024 */ 5025 DMUB_CMD__ABM_GET_HISTOGRAM_DATA = 11, 5026 }; 5027 5028 /** 5029 * LSDMA command sub-types. 5030 */ 5031 enum dmub_cmd_lsdma_type { 5032 /** 5033 * Initialize parameters for LSDMA. 5034 * Ring buffer is mapped to the ring buffer 5035 */ 5036 DMUB_CMD__LSDMA_INIT_CONFIG = 0, 5037 /** 5038 * LSDMA copies data from source to destination linearly 5039 */ 5040 DMUB_CMD__LSDMA_LINEAR_COPY = 1, 5041 /** 5042 * LSDMA copies data from source to destination linearly in sub window 5043 */ 5044 DMUB_CMD__LSDMA_LINEAR_SUB_WINDOW_COPY = 2, 5045 /** 5046 * Send the tiled-to-tiled copy command 5047 */ 5048 DMUB_CMD__LSDMA_TILED_TO_TILED_COPY = 3, 5049 /** 5050 * Send the poll reg write command 5051 */ 5052 DMUB_CMD__LSDMA_POLL_REG_WRITE = 4, 5053 /** 5054 * Send the pio copy command 5055 */ 5056 DMUB_CMD__LSDMA_PIO_COPY = 5, 5057 /** 5058 * Send the pio constfill command 5059 */ 5060 DMUB_CMD__LSDMA_PIO_CONSTFILL = 6, 5061 }; 5062 5063 struct abm_ace_curve { 5064 /** 5065 * @offsets: ACE curve offsets. 5066 */ 5067 uint32_t offsets[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 5068 5069 /** 5070 * @thresholds: ACE curve thresholds. 5071 */ 5072 uint32_t thresholds[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 5073 5074 /** 5075 * @slopes: ACE curve slopes. 5076 */ 5077 uint32_t slopes[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 5078 }; 5079 5080 struct fixed_pt_format { 5081 /** 5082 * @sign_bit: Indicates whether one bit is reserved for the sign. 5083 */ 5084 bool sign_bit; 5085 5086 /** 5087 * @num_int_bits: Number of bits used for integer part. 5088 */ 5089 uint8_t num_int_bits; 5090 5091 /** 5092 * @num_frac_bits: Number of bits used for fractional part. 5093 */ 5094 uint8_t num_frac_bits; 5095 5096 /** 5097 * @pad: Explicit padding to 4 byte boundary. 5098 */ 5099 uint8_t pad; 5100 }; 5101 5102 struct abm_caps { 5103 /** 5104 * @num_hg_bins: Number of histogram bins. 5105 */ 5106 uint8_t num_hg_bins; 5107 5108 /** 5109 * @num_ace_segments: Number of ACE curve segments. 5110 */ 5111 uint8_t num_ace_segments; 5112 5113 /** 5114 * @pad: Explicit padding to 4 byte boundary. 5115 */ 5116 uint8_t pad[2]; 5117 5118 /** 5119 * @ace_thresholds_format: Format of the ACE thresholds. If not programmable, it is set to 0. 5120 */ 5121 struct fixed_pt_format ace_thresholds_format; 5122 5123 /** 5124 * @ace_offsets_format: Format of the ACE offsets. If not programmable, it is set to 0. 5125 */ 5126 struct fixed_pt_format ace_offsets_format; 5127 5128 /** 5129 * @ace_slopes_format: Format of the ACE slopes. 5130 */ 5131 struct fixed_pt_format ace_slopes_format; 5132 }; 5133 5134 /** 5135 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 5136 * Requirements: 5137 * - Padded explicitly to 32-bit boundary. 5138 * - Must ensure this structure matches the one on driver-side, 5139 * otherwise it won't be aligned. 5140 */ 5141 struct abm_config_table { 5142 /** 5143 * Gamma curve thresholds, used for crgb conversion. 5144 */ 5145 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 5146 /** 5147 * Gamma curve offsets, used for crgb conversion. 5148 */ 5149 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 5150 /** 5151 * Gamma curve slopes, used for crgb conversion. 5152 */ 5153 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 5154 /** 5155 * Custom backlight curve thresholds. 5156 */ 5157 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 5158 /** 5159 * Custom backlight curve offsets. 5160 */ 5161 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 5162 /** 5163 * Ambient light thresholds. 5164 */ 5165 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 5166 /** 5167 * Minimum programmable backlight. 5168 */ 5169 uint16_t min_abm_backlight; // 122B 5170 /** 5171 * Minimum reduction values. 5172 */ 5173 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 5174 /** 5175 * Maximum reduction values. 5176 */ 5177 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 5178 /** 5179 * Bright positive gain. 5180 */ 5181 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 5182 /** 5183 * Dark negative gain. 5184 */ 5185 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 5186 /** 5187 * Hybrid factor. 5188 */ 5189 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 5190 /** 5191 * Contrast factor. 5192 */ 5193 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 5194 /** 5195 * Deviation gain. 5196 */ 5197 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 5198 /** 5199 * Minimum knee. 5200 */ 5201 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 5202 /** 5203 * Maximum knee. 5204 */ 5205 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 5206 /** 5207 * Unused. 5208 */ 5209 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 5210 /** 5211 * Explicit padding to 4 byte boundary. 5212 */ 5213 uint8_t pad3[3]; // 229B 5214 /** 5215 * Backlight ramp reduction. 5216 */ 5217 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 5218 /** 5219 * Backlight ramp start. 5220 */ 5221 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 5222 }; 5223 5224 /** 5225 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 5226 */ 5227 struct dmub_cmd_abm_set_pipe_data { 5228 /** 5229 * OTG HW instance. 5230 */ 5231 uint8_t otg_inst; 5232 5233 /** 5234 * Panel Control HW instance. 5235 */ 5236 uint8_t panel_inst; 5237 5238 /** 5239 * Controls how ABM will interpret a set pipe or set level command. 5240 */ 5241 uint8_t set_pipe_option; 5242 5243 /** 5244 * Unused. 5245 * TODO: Remove. 5246 */ 5247 uint8_t ramping_boundary; 5248 5249 /** 5250 * PwrSeq HW Instance. 5251 */ 5252 uint8_t pwrseq_inst; 5253 5254 /** 5255 * Explicit padding to 4 byte boundary. 5256 */ 5257 uint8_t pad[3]; 5258 }; 5259 5260 /** 5261 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 5262 */ 5263 struct dmub_rb_cmd_abm_set_pipe { 5264 /** 5265 * Command header. 5266 */ 5267 struct dmub_cmd_header header; 5268 5269 /** 5270 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 5271 */ 5272 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 5273 }; 5274 5275 /** 5276 * Type of backlight control method to be used by ABM module 5277 */ 5278 enum dmub_backlight_control_type { 5279 /** 5280 * PWM Backlight control 5281 */ 5282 DMU_BACKLIGHT_CONTROL_PWM = 0, 5283 /** 5284 * VESA Aux-based backlight control 5285 */ 5286 DMU_BACKLIGHT_CONTROL_VESA_AUX = 1, 5287 /** 5288 * AMD DPCD Aux-based backlight control 5289 */ 5290 DMU_BACKLIGHT_CONTROL_AMD_AUX = 2, 5291 }; 5292 5293 /** 5294 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 5295 */ 5296 struct dmub_cmd_abm_set_backlight_data { 5297 /** 5298 * Number of frames to ramp to backlight user level. 5299 */ 5300 uint32_t frame_ramp; 5301 5302 /** 5303 * Requested backlight level from user. 5304 */ 5305 uint32_t backlight_user_level; 5306 5307 /** 5308 * ABM control version. 5309 */ 5310 uint8_t version; 5311 5312 /** 5313 * Panel Control HW instance mask. 5314 * Bit 0 is Panel Control HW instance 0. 5315 * Bit 1 is Panel Control HW instance 1. 5316 */ 5317 uint8_t panel_mask; 5318 5319 /** 5320 * AUX HW Instance. 5321 */ 5322 uint8_t aux_inst; 5323 5324 /** 5325 * Explicit padding to 4 byte boundary. 5326 */ 5327 uint8_t pad[1]; 5328 5329 /** 5330 * Backlight control type. 5331 * Value 0 is PWM backlight control. 5332 * Value 1 is VAUX backlight control. 5333 * Value 2 is AMD DPCD AUX backlight control. 5334 */ 5335 enum dmub_backlight_control_type backlight_control_type; 5336 5337 /** 5338 * Minimum luminance in nits. 5339 */ 5340 uint32_t min_luminance; 5341 5342 /** 5343 * Maximum luminance in nits. 5344 */ 5345 uint32_t max_luminance; 5346 5347 /** 5348 * Minimum backlight in pwm. 5349 */ 5350 uint32_t min_backlight_pwm; 5351 5352 /** 5353 * Maximum backlight in pwm. 5354 */ 5355 uint32_t max_backlight_pwm; 5356 }; 5357 5358 /** 5359 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 5360 */ 5361 struct dmub_rb_cmd_abm_set_backlight { 5362 /** 5363 * Command header. 5364 */ 5365 struct dmub_cmd_header header; 5366 5367 /** 5368 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 5369 */ 5370 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 5371 }; 5372 5373 /** 5374 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 5375 */ 5376 struct dmub_cmd_abm_set_level_data { 5377 /** 5378 * Set current ABM operating/aggression level. 5379 */ 5380 uint32_t level; 5381 5382 /** 5383 * ABM control version. 5384 */ 5385 uint8_t version; 5386 5387 /** 5388 * Panel Control HW instance mask. 5389 * Bit 0 is Panel Control HW instance 0. 5390 * Bit 1 is Panel Control HW instance 1. 5391 */ 5392 uint8_t panel_mask; 5393 5394 /** 5395 * Explicit padding to 4 byte boundary. 5396 */ 5397 uint8_t pad[2]; 5398 }; 5399 5400 /** 5401 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 5402 */ 5403 struct dmub_rb_cmd_abm_set_level { 5404 /** 5405 * Command header. 5406 */ 5407 struct dmub_cmd_header header; 5408 5409 /** 5410 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 5411 */ 5412 struct dmub_cmd_abm_set_level_data abm_set_level_data; 5413 }; 5414 5415 /** 5416 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5417 */ 5418 struct dmub_cmd_abm_set_ambient_level_data { 5419 /** 5420 * Ambient light sensor reading from OS. 5421 */ 5422 uint32_t ambient_lux; 5423 5424 /** 5425 * ABM control version. 5426 */ 5427 uint8_t version; 5428 5429 /** 5430 * Panel Control HW instance mask. 5431 * Bit 0 is Panel Control HW instance 0. 5432 * Bit 1 is Panel Control HW instance 1. 5433 */ 5434 uint8_t panel_mask; 5435 5436 /** 5437 * Explicit padding to 4 byte boundary. 5438 */ 5439 uint8_t pad[2]; 5440 }; 5441 5442 /** 5443 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5444 */ 5445 struct dmub_rb_cmd_abm_set_ambient_level { 5446 /** 5447 * Command header. 5448 */ 5449 struct dmub_cmd_header header; 5450 5451 /** 5452 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5453 */ 5454 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 5455 }; 5456 5457 /** 5458 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 5459 */ 5460 struct dmub_cmd_abm_set_pwm_frac_data { 5461 /** 5462 * Enable/disable fractional duty cycle for backlight PWM. 5463 * TODO: Convert to uint8_t. 5464 */ 5465 uint32_t fractional_pwm; 5466 5467 /** 5468 * ABM control version. 5469 */ 5470 uint8_t version; 5471 5472 /** 5473 * Panel Control HW instance mask. 5474 * Bit 0 is Panel Control HW instance 0. 5475 * Bit 1 is Panel Control HW instance 1. 5476 */ 5477 uint8_t panel_mask; 5478 5479 /** 5480 * Explicit padding to 4 byte boundary. 5481 */ 5482 uint8_t pad[2]; 5483 }; 5484 5485 /** 5486 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 5487 */ 5488 struct dmub_rb_cmd_abm_set_pwm_frac { 5489 /** 5490 * Command header. 5491 */ 5492 struct dmub_cmd_header header; 5493 5494 /** 5495 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 5496 */ 5497 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 5498 }; 5499 5500 /** 5501 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 5502 */ 5503 struct dmub_cmd_abm_init_config_data { 5504 /** 5505 * Location of indirect buffer used to pass init data to ABM. 5506 */ 5507 union dmub_addr src; 5508 5509 /** 5510 * Indirect buffer length. 5511 */ 5512 uint16_t bytes; 5513 5514 5515 /** 5516 * ABM control version. 5517 */ 5518 uint8_t version; 5519 5520 /** 5521 * Panel Control HW instance mask. 5522 * Bit 0 is Panel Control HW instance 0. 5523 * Bit 1 is Panel Control HW instance 1. 5524 */ 5525 uint8_t panel_mask; 5526 5527 /** 5528 * Explicit padding to 4 byte boundary. 5529 */ 5530 uint8_t pad[2]; 5531 }; 5532 5533 /** 5534 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 5535 */ 5536 struct dmub_rb_cmd_abm_init_config { 5537 /** 5538 * Command header. 5539 */ 5540 struct dmub_cmd_header header; 5541 5542 /** 5543 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 5544 */ 5545 struct dmub_cmd_abm_init_config_data abm_init_config_data; 5546 }; 5547 5548 /** 5549 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 5550 */ 5551 5552 struct dmub_cmd_abm_pause_data { 5553 5554 /** 5555 * Panel Control HW instance mask. 5556 * Bit 0 is Panel Control HW instance 0. 5557 * Bit 1 is Panel Control HW instance 1. 5558 */ 5559 uint8_t panel_mask; 5560 5561 /** 5562 * OTG hw instance 5563 */ 5564 uint8_t otg_inst; 5565 5566 /** 5567 * Enable or disable ABM pause 5568 */ 5569 uint8_t enable; 5570 5571 /** 5572 * Explicit padding to 4 byte boundary. 5573 */ 5574 uint8_t pad[1]; 5575 }; 5576 5577 /** 5578 * Definition of a DMUB_CMD__ABM_PAUSE command. 5579 */ 5580 struct dmub_rb_cmd_abm_pause { 5581 /** 5582 * Command header. 5583 */ 5584 struct dmub_cmd_header header; 5585 5586 /** 5587 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 5588 */ 5589 struct dmub_cmd_abm_pause_data abm_pause_data; 5590 }; 5591 5592 /** 5593 * Data passed from driver to FW in a DMUB_CMD__ABM_QUERY_CAPS command. 5594 */ 5595 struct dmub_cmd_abm_query_caps_in { 5596 /** 5597 * Panel instance. 5598 */ 5599 uint8_t panel_inst; 5600 5601 /** 5602 * Explicit padding to 4 byte boundary. 5603 */ 5604 uint8_t pad[3]; 5605 }; 5606 5607 /** 5608 * Data passed from FW to driver in a DMUB_CMD__ABM_QUERY_CAPS command. 5609 */ 5610 struct dmub_cmd_abm_query_caps_out { 5611 /** 5612 * SW Algorithm caps. 5613 */ 5614 struct abm_caps sw_caps; 5615 5616 /** 5617 * ABM HW caps. 5618 */ 5619 struct abm_caps hw_caps; 5620 }; 5621 5622 /** 5623 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 5624 */ 5625 struct dmub_rb_cmd_abm_query_caps { 5626 /** 5627 * Command header. 5628 */ 5629 struct dmub_cmd_header header; 5630 5631 /** 5632 * Data passed between FW and driver in a DMUB_CMD__ABM_QUERY_CAPS command. 5633 */ 5634 union { 5635 struct dmub_cmd_abm_query_caps_in abm_query_caps_in; 5636 struct dmub_cmd_abm_query_caps_out abm_query_caps_out; 5637 } data; 5638 }; 5639 5640 /** 5641 * enum dmub_abm_ace_curve_type - ACE curve type. 5642 */ 5643 enum dmub_abm_ace_curve_type { 5644 /** 5645 * ACE curve as defined by the SW layer. 5646 */ 5647 ABM_ACE_CURVE_TYPE__SW = 0, 5648 /** 5649 * ACE curve as defined by the SW to HW translation interface layer. 5650 */ 5651 ABM_ACE_CURVE_TYPE__SW_IF = 1, 5652 }; 5653 5654 /** 5655 * enum dmub_abm_histogram_type - Histogram type. 5656 */ 5657 enum dmub_abm_histogram_type { 5658 /** 5659 * ACE curve as defined by the SW layer. 5660 */ 5661 ABM_HISTOGRAM_TYPE__SW = 0, 5662 /** 5663 * ACE curve as defined by the SW to HW translation interface layer. 5664 */ 5665 ABM_HISTOGRAM_TYPE__SW_IF = 1, 5666 }; 5667 5668 /** 5669 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 5670 */ 5671 struct dmub_rb_cmd_abm_get_ace_curve { 5672 /** 5673 * Command header. 5674 */ 5675 struct dmub_cmd_header header; 5676 5677 /** 5678 * Address where ACE curve should be copied. 5679 */ 5680 union dmub_addr dest; 5681 5682 /** 5683 * Type of ACE curve being queried. 5684 */ 5685 enum dmub_abm_ace_curve_type ace_type; 5686 5687 /** 5688 * Indirect buffer length. 5689 */ 5690 uint16_t bytes; 5691 5692 /** 5693 * eDP panel instance. 5694 */ 5695 uint8_t panel_inst; 5696 5697 /** 5698 * Explicit padding to 4 byte boundary. 5699 */ 5700 uint8_t pad; 5701 }; 5702 5703 /** 5704 * Definition of a DMUB_CMD__ABM_GET_HISTOGRAM command. 5705 */ 5706 struct dmub_rb_cmd_abm_get_histogram { 5707 /** 5708 * Command header. 5709 */ 5710 struct dmub_cmd_header header; 5711 5712 /** 5713 * Address where Histogram should be copied. 5714 */ 5715 union dmub_addr dest; 5716 5717 /** 5718 * Type of Histogram being queried. 5719 */ 5720 enum dmub_abm_histogram_type histogram_type; 5721 5722 /** 5723 * Indirect buffer length. 5724 */ 5725 uint16_t bytes; 5726 5727 /** 5728 * eDP panel instance. 5729 */ 5730 uint8_t panel_inst; 5731 5732 /** 5733 * Explicit padding to 4 byte boundary. 5734 */ 5735 uint8_t pad; 5736 }; 5737 5738 /** 5739 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 5740 */ 5741 struct dmub_rb_cmd_abm_save_restore { 5742 /** 5743 * Command header. 5744 */ 5745 struct dmub_cmd_header header; 5746 5747 /** 5748 * OTG hw instance 5749 */ 5750 uint8_t otg_inst; 5751 5752 /** 5753 * Enable or disable ABM pause 5754 */ 5755 uint8_t freeze; 5756 5757 /** 5758 * Explicit padding to 4 byte boundary. 5759 */ 5760 uint8_t debug; 5761 5762 /** 5763 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 5764 */ 5765 struct dmub_cmd_abm_init_config_data abm_init_config_data; 5766 }; 5767 5768 /** 5769 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 5770 */ 5771 5772 struct dmub_cmd_abm_set_event_data { 5773 5774 /** 5775 * VB Scaling Init. Strength Mapping 5776 * Byte 0: 0~255 for VB level 0 5777 * Byte 1: 0~255 for VB level 1 5778 * Byte 2: 0~255 for VB level 2 5779 * Byte 3: 0~255 for VB level 3 5780 */ 5781 uint32_t vb_scaling_strength_mapping; 5782 /** 5783 * VariBright Scaling Enable 5784 */ 5785 uint8_t vb_scaling_enable; 5786 /** 5787 * Panel Control HW instance mask. 5788 * Bit 0 is Panel Control HW instance 0. 5789 * Bit 1 is Panel Control HW instance 1. 5790 */ 5791 uint8_t panel_mask; 5792 5793 /** 5794 * Explicit padding to 4 byte boundary. 5795 */ 5796 uint8_t pad[2]; 5797 }; 5798 5799 /** 5800 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 5801 */ 5802 struct dmub_rb_cmd_abm_set_event { 5803 /** 5804 * Command header. 5805 */ 5806 struct dmub_cmd_header header; 5807 5808 /** 5809 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 5810 */ 5811 struct dmub_cmd_abm_set_event_data abm_set_event_data; 5812 }; 5813 5814 /** 5815 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 5816 */ 5817 struct dmub_cmd_query_feature_caps_data { 5818 /** 5819 * DMUB feature capabilities. 5820 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 5821 */ 5822 struct dmub_feature_caps feature_caps; 5823 }; 5824 5825 /** 5826 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 5827 */ 5828 struct dmub_rb_cmd_query_feature_caps { 5829 /** 5830 * Command header. 5831 */ 5832 struct dmub_cmd_header header; 5833 /** 5834 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 5835 */ 5836 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 5837 }; 5838 5839 /** 5840 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5841 */ 5842 struct dmub_cmd_visual_confirm_color_data { 5843 /** 5844 * DMUB visual confirm color 5845 */ 5846 struct dmub_visual_confirm_color visual_confirm_color; 5847 }; 5848 5849 /** 5850 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5851 */ 5852 struct dmub_rb_cmd_get_visual_confirm_color { 5853 /** 5854 * Command header. 5855 */ 5856 struct dmub_cmd_header header; 5857 /** 5858 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5859 */ 5860 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 5861 }; 5862 5863 /** 5864 * enum dmub_cmd_panel_cntl_type - Panel control command. 5865 */ 5866 enum dmub_cmd_panel_cntl_type { 5867 /** 5868 * Initializes embedded panel hardware blocks. 5869 */ 5870 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 5871 /** 5872 * Queries backlight info for the embedded panel. 5873 */ 5874 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 5875 /** 5876 * Sets the PWM Freq as per user's requirement. 5877 */ 5878 DMUB_CMD__PANEL_DEBUG_PWM_FREQ = 2, 5879 }; 5880 5881 /** 5882 * struct dmub_cmd_panel_cntl_data - Panel control data. 5883 */ 5884 struct dmub_cmd_panel_cntl_data { 5885 uint32_t pwrseq_inst; /**< pwrseq instance */ 5886 uint32_t current_backlight; /* in/out */ 5887 uint32_t bl_pwm_cntl; /* in/out */ 5888 uint32_t bl_pwm_period_cntl; /* in/out */ 5889 uint32_t bl_pwm_ref_div1; /* in/out */ 5890 uint8_t is_backlight_on : 1; /* in/out */ 5891 uint8_t is_powered_on : 1; /* in/out */ 5892 uint8_t padding[3]; 5893 uint32_t bl_pwm_ref_div2; /* in/out */ 5894 uint8_t reserved[4]; 5895 }; 5896 5897 /** 5898 * struct dmub_rb_cmd_panel_cntl - Panel control command. 5899 */ 5900 struct dmub_rb_cmd_panel_cntl { 5901 struct dmub_cmd_header header; /**< header */ 5902 struct dmub_cmd_panel_cntl_data data; /**< payload */ 5903 }; 5904 5905 struct dmub_optc_state { 5906 uint32_t v_total_max; 5907 uint32_t v_total_min; 5908 uint32_t tg_inst; 5909 }; 5910 5911 struct dmub_rb_cmd_drr_update { 5912 struct dmub_cmd_header header; 5913 struct dmub_optc_state dmub_optc_state_req; 5914 }; 5915 5916 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 5917 uint32_t pix_clk_100hz; 5918 uint8_t max_ramp_step; 5919 uint8_t pipes; 5920 uint8_t min_refresh_in_hz; 5921 uint8_t pipe_count; 5922 uint8_t pipe_index[4]; 5923 }; 5924 5925 struct dmub_cmd_fw_assisted_mclk_switch_config { 5926 uint8_t fams_enabled; 5927 uint8_t visual_confirm_enabled; 5928 uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive 5929 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS]; 5930 }; 5931 5932 struct dmub_rb_cmd_fw_assisted_mclk_switch { 5933 struct dmub_cmd_header header; 5934 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 5935 }; 5936 5937 /** 5938 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5939 */ 5940 struct dmub_cmd_lvtma_control_data { 5941 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 5942 uint8_t bypass_panel_control_wait; 5943 uint8_t reserved_0[2]; /**< For future use */ 5944 uint8_t pwrseq_inst; /**< LVTMA control instance */ 5945 uint8_t reserved_1[3]; /**< For future use */ 5946 }; 5947 5948 /** 5949 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5950 */ 5951 struct dmub_rb_cmd_lvtma_control { 5952 /** 5953 * Command header. 5954 */ 5955 struct dmub_cmd_header header; 5956 /** 5957 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5958 */ 5959 struct dmub_cmd_lvtma_control_data data; 5960 }; 5961 5962 /** 5963 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5964 */ 5965 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 5966 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 5967 uint8_t is_usb; /**< is phy is usb */ 5968 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 5969 uint8_t is_dp4; /**< is dp in 4 lane */ 5970 }; 5971 5972 /** 5973 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5974 */ 5975 struct dmub_rb_cmd_transmitter_query_dp_alt { 5976 struct dmub_cmd_header header; /**< header */ 5977 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 5978 }; 5979 5980 struct phy_test_mode { 5981 uint8_t mode; 5982 uint8_t pat0; 5983 uint8_t pad[2]; 5984 }; 5985 5986 /** 5987 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 5988 */ 5989 struct dmub_rb_cmd_transmitter_set_phy_fsm_data { 5990 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 5991 uint8_t mode; /**< HDMI/DP/DP2 etc */ 5992 uint8_t lane_num; /**< Number of lanes */ 5993 uint32_t symclk_100Hz; /**< PLL symclock in 100hz */ 5994 struct phy_test_mode test_mode; 5995 enum dmub_phy_fsm_state state; 5996 uint32_t status; 5997 uint8_t pad; 5998 }; 5999 6000 /** 6001 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 6002 */ 6003 struct dmub_rb_cmd_transmitter_set_phy_fsm { 6004 struct dmub_cmd_header header; /**< header */ 6005 struct dmub_rb_cmd_transmitter_set_phy_fsm_data data; /**< payload */ 6006 }; 6007 6008 /** 6009 * Maximum number of bytes a chunk sent to DMUB for parsing 6010 */ 6011 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 6012 6013 /** 6014 * Represent a chunk of CEA blocks sent to DMUB for parsing 6015 */ 6016 struct dmub_cmd_send_edid_cea { 6017 uint16_t offset; /**< offset into the CEA block */ 6018 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 6019 uint16_t cea_total_length; /**< total length of the CEA block */ 6020 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 6021 uint8_t pad[3]; /**< padding and for future expansion */ 6022 }; 6023 6024 /** 6025 * Result of VSDB parsing from CEA block 6026 */ 6027 struct dmub_cmd_edid_cea_amd_vsdb { 6028 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 6029 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 6030 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 6031 uint16_t min_frame_rate; /**< Maximum frame rate */ 6032 uint16_t max_frame_rate; /**< Minimum frame rate */ 6033 }; 6034 6035 /** 6036 * Result of sending a CEA chunk 6037 */ 6038 struct dmub_cmd_edid_cea_ack { 6039 uint16_t offset; /**< offset of the chunk into the CEA block */ 6040 uint8_t success; /**< 1 if this sending of chunk succeeded */ 6041 uint8_t pad; /**< padding and for future expansion */ 6042 }; 6043 6044 /** 6045 * Specify whether the result is an ACK/NACK or the parsing has finished 6046 */ 6047 enum dmub_cmd_edid_cea_reply_type { 6048 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 6049 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 6050 }; 6051 6052 /** 6053 * Definition of a DMUB_CMD__EDID_CEA command. 6054 */ 6055 struct dmub_rb_cmd_edid_cea { 6056 struct dmub_cmd_header header; /**< Command header */ 6057 union dmub_cmd_edid_cea_data { 6058 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 6059 struct dmub_cmd_edid_cea_output { /**< output with results */ 6060 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 6061 union { 6062 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 6063 struct dmub_cmd_edid_cea_ack ack; 6064 }; 6065 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 6066 } data; /**< Command data */ 6067 6068 }; 6069 6070 /** 6071 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 6072 */ 6073 struct dmub_cmd_cable_id_input { 6074 uint8_t phy_inst; /**< phy inst for cable id data */ 6075 }; 6076 6077 /** 6078 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 6079 */ 6080 struct dmub_cmd_cable_id_output { 6081 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 6082 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 6083 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 6084 uint8_t RESERVED :2; /**< reserved means not defined */ 6085 }; 6086 6087 /** 6088 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 6089 */ 6090 struct dmub_rb_cmd_get_usbc_cable_id { 6091 struct dmub_cmd_header header; /**< Command header */ 6092 /** 6093 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 6094 */ 6095 union dmub_cmd_cable_id_data { 6096 struct dmub_cmd_cable_id_input input; /**< Input */ 6097 struct dmub_cmd_cable_id_output output; /**< Output */ 6098 uint8_t output_raw; /**< Raw data output */ 6099 } data; 6100 }; 6101 6102 enum dmub_cmd_fused_io_sub_type { 6103 DMUB_CMD__FUSED_IO_EXECUTE = 0, 6104 DMUB_CMD__FUSED_IO_ABORT = 1, 6105 }; 6106 6107 enum dmub_cmd_fused_request_type { 6108 FUSED_REQUEST_READ, 6109 FUSED_REQUEST_WRITE, 6110 FUSED_REQUEST_POLL, 6111 }; 6112 6113 enum dmub_cmd_fused_request_status { 6114 FUSED_REQUEST_STATUS_SUCCESS, 6115 FUSED_REQUEST_STATUS_BEGIN, 6116 FUSED_REQUEST_STATUS_SUBMIT, 6117 FUSED_REQUEST_STATUS_REPLY, 6118 FUSED_REQUEST_STATUS_POLL, 6119 FUSED_REQUEST_STATUS_ABORTED, 6120 FUSED_REQUEST_STATUS_FAILED = 0x80, 6121 FUSED_REQUEST_STATUS_INVALID, 6122 FUSED_REQUEST_STATUS_BUSY, 6123 FUSED_REQUEST_STATUS_TIMEOUT, 6124 FUSED_REQUEST_STATUS_POLL_TIMEOUT, 6125 }; 6126 6127 struct dmub_cmd_fused_request { 6128 uint8_t status; 6129 uint8_t type : 2; 6130 uint8_t _reserved0 : 3; 6131 uint8_t poll_mask_msb : 3; // Number of MSB to zero out from last byte before comparing 6132 uint8_t identifier; 6133 uint8_t _reserved1; 6134 uint32_t timeout_us; 6135 union dmub_cmd_fused_request_location { 6136 struct dmub_cmd_fused_request_location_i2c { 6137 uint8_t is_aux : 1; // False 6138 uint8_t ddc_line : 3; 6139 uint8_t over_aux : 1; 6140 uint8_t _reserved0 : 3; 6141 uint8_t address; 6142 uint8_t offset; 6143 uint8_t length; 6144 } i2c; 6145 struct dmub_cmd_fused_request_location_aux { 6146 uint32_t is_aux : 1; // True 6147 uint32_t ddc_line : 3; 6148 uint32_t address : 20; 6149 uint32_t length : 8; // Automatically split into 16B transactions 6150 } aux; 6151 } u; 6152 uint8_t buffer[0x30]; // Read: out, write: in, poll: expected 6153 }; 6154 6155 struct dmub_rb_cmd_fused_io { 6156 struct dmub_cmd_header header; 6157 struct dmub_cmd_fused_request request; 6158 }; 6159 6160 /** 6161 * Command type of a DMUB_CMD__SECURE_DISPLAY command 6162 */ 6163 enum dmub_cmd_secure_display_type { 6164 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 6165 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 6166 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY, 6167 DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_STOP_UPDATE, 6168 DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_WIN_NOTIFY 6169 }; 6170 6171 #define MAX_ROI_NUM 2 6172 6173 struct dmub_cmd_roi_info { 6174 uint16_t x_start; 6175 uint16_t x_end; 6176 uint16_t y_start; 6177 uint16_t y_end; 6178 uint8_t otg_id; 6179 uint8_t phy_id; 6180 }; 6181 6182 struct dmub_cmd_roi_window_ctl { 6183 uint16_t x_start; 6184 uint16_t x_end; 6185 uint16_t y_start; 6186 uint16_t y_end; 6187 bool enable; 6188 }; 6189 6190 struct dmub_cmd_roi_ctl_info { 6191 uint8_t otg_id; 6192 uint8_t phy_id; 6193 struct dmub_cmd_roi_window_ctl roi_ctl[MAX_ROI_NUM]; 6194 }; 6195 6196 /** 6197 * Definition of a DMUB_CMD__SECURE_DISPLAY command 6198 */ 6199 struct dmub_rb_cmd_secure_display { 6200 struct dmub_cmd_header header; 6201 /** 6202 * Data passed from driver to dmub firmware. 6203 */ 6204 struct dmub_cmd_roi_info roi_info; 6205 struct dmub_cmd_roi_ctl_info mul_roi_ctl; 6206 }; 6207 6208 /** 6209 * Command type of a DMUB_CMD__PSP command 6210 */ 6211 enum dmub_cmd_psp_type { 6212 DMUB_CMD__PSP_ASSR_ENABLE = 0 6213 }; 6214 6215 /** 6216 * Data passed from driver to FW in a DMUB_CMD__PSP_ASSR_ENABLE command. 6217 */ 6218 struct dmub_cmd_assr_enable_data { 6219 /** 6220 * ASSR enable or disable. 6221 */ 6222 uint8_t enable; 6223 /** 6224 * PHY port type. 6225 * Indicates eDP / non-eDP port type 6226 */ 6227 uint8_t phy_port_type; 6228 /** 6229 * PHY port ID. 6230 */ 6231 uint8_t phy_port_id; 6232 /** 6233 * Link encoder index. 6234 */ 6235 uint8_t link_enc_index; 6236 /** 6237 * HPO mode. 6238 */ 6239 uint8_t hpo_mode; 6240 6241 /** 6242 * Reserved field. 6243 */ 6244 uint8_t reserved[7]; 6245 }; 6246 6247 /** 6248 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 6249 */ 6250 struct dmub_rb_cmd_assr_enable { 6251 /** 6252 * Command header. 6253 */ 6254 struct dmub_cmd_header header; 6255 6256 /** 6257 * Assr data. 6258 */ 6259 struct dmub_cmd_assr_enable_data assr_data; 6260 6261 /** 6262 * Reserved field. 6263 */ 6264 uint32_t reserved[3]; 6265 }; 6266 6267 /** 6268 * Current definition of "ips_mode" from driver 6269 */ 6270 enum ips_residency_mode { 6271 IPS_RESIDENCY__IPS1_MAX, 6272 IPS_RESIDENCY__IPS2, 6273 IPS_RESIDENCY__IPS1_RCG, 6274 IPS_RESIDENCY__IPS1_ONO2_ON, 6275 IPS_RESIDENCY__IPS1_Z8_RETENTION, 6276 IPS_RESIDENCY__PG_ONO_LAST_SEEN_IN_IPS, 6277 IPS_RESIDENCY__PG_ONO_CURRENT_STATE 6278 }; 6279 6280 #define NUM_IPS_HISTOGRAM_BUCKETS 16 6281 6282 /** 6283 * IPS residency statistics to be sent to driver - subset of struct dmub_ips_residency_stats 6284 */ 6285 struct dmub_ips_residency_info { 6286 uint32_t residency_millipercent; 6287 uint32_t entry_counter; 6288 uint32_t histogram[NUM_IPS_HISTOGRAM_BUCKETS]; 6289 uint64_t total_time_us; 6290 uint64_t total_inactive_time_us; 6291 uint32_t ono_pg_state_at_collection; 6292 uint32_t ono_pg_state_last_seen_in_ips; 6293 }; 6294 6295 /** 6296 * Data passed from driver to FW in a DMUB_CMD__IPS_RESIDENCY_CNTL command. 6297 */ 6298 struct dmub_cmd_ips_residency_cntl_data { 6299 uint8_t panel_inst; 6300 uint8_t start_measurement; 6301 uint8_t padding[2]; // align to 4-byte boundary 6302 }; 6303 6304 struct dmub_rb_cmd_ips_residency_cntl { 6305 struct dmub_cmd_header header; 6306 struct dmub_cmd_ips_residency_cntl_data cntl_data; 6307 }; 6308 6309 /** 6310 * Data passed from FW to driver in a DMUB_CMD__IPS_QUERY_RESIDENCY_INFO command. 6311 */ 6312 struct dmub_cmd_ips_query_residency_info_data { 6313 union dmub_addr dest; 6314 uint32_t size; 6315 uint32_t ips_mode; 6316 uint8_t panel_inst; 6317 uint8_t padding[3]; // align to 4-byte boundary 6318 }; 6319 6320 struct dmub_rb_cmd_ips_query_residency_info { 6321 struct dmub_cmd_header header; 6322 struct dmub_cmd_ips_query_residency_info_data info_data; 6323 }; 6324 6325 /** 6326 * struct dmub_cmd_cursor_offload_init_data - Payload for cursor offload init command. 6327 */ 6328 struct dmub_cmd_cursor_offload_init_data { 6329 union dmub_addr state_addr; /**< State address for dmub_cursor_offload */ 6330 uint32_t state_size; /**< State size for dmub_cursor_offload */ 6331 }; 6332 6333 /** 6334 * struct dmub_rb_cmd_cursor_offload_init - Data for initializing cursor offload. 6335 */ 6336 struct dmub_rb_cmd_cursor_offload_init { 6337 struct dmub_cmd_header header; 6338 struct dmub_cmd_cursor_offload_init_data init_data; 6339 }; 6340 6341 /** 6342 * struct dmub_cmd_cursor_offload_stream_data - Payload for cursor offload stream command. 6343 */ 6344 struct dmub_cmd_cursor_offload_stream_data { 6345 uint32_t otg_inst: 4; /**< OTG instance to control */ 6346 uint32_t reserved: 28; /**< Reserved for future use */ 6347 uint32_t line_time_in_ns; /**< Line time in ns for the OTG */ 6348 uint32_t v_total_max; /**< OTG v_total_max */ 6349 }; 6350 6351 /** 6352 * struct dmub_rb_cmd_cursor_offload_stream_cntl - Controls a stream for cursor offload. 6353 */ 6354 struct dmub_rb_cmd_cursor_offload_stream_cntl { 6355 struct dmub_cmd_header header; 6356 struct dmub_cmd_cursor_offload_stream_data data; 6357 }; 6358 6359 /** 6360 * union dmub_rb_cmd - DMUB inbox command. 6361 */ 6362 union dmub_rb_cmd { 6363 /** 6364 * Elements shared with all commands. 6365 */ 6366 struct dmub_rb_cmd_common cmd_common; 6367 /** 6368 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 6369 */ 6370 struct dmub_rb_cmd_read_modify_write read_modify_write; 6371 /** 6372 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 6373 */ 6374 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 6375 /** 6376 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 6377 */ 6378 struct dmub_rb_cmd_burst_write burst_write; 6379 /** 6380 * Definition of a DMUB_CMD__REG_REG_WAIT command. 6381 */ 6382 struct dmub_rb_cmd_reg_wait reg_wait; 6383 /** 6384 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 6385 */ 6386 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 6387 /** 6388 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 6389 */ 6390 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 6391 /** 6392 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 6393 */ 6394 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 6395 /** 6396 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 6397 */ 6398 struct dmub_rb_cmd_dpphy_init dpphy_init; 6399 /** 6400 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 6401 */ 6402 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 6403 /** 6404 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command. 6405 */ 6406 struct dmub_rb_cmd_domain_control domain_control; 6407 /** 6408 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 6409 */ 6410 struct dmub_rb_cmd_psr_set_version psr_set_version; 6411 /** 6412 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 6413 */ 6414 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 6415 /** 6416 * Definition of a DMUB_CMD__PSR_ENABLE command. 6417 */ 6418 struct dmub_rb_cmd_psr_enable psr_enable; 6419 /** 6420 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 6421 */ 6422 struct dmub_rb_cmd_psr_set_level psr_set_level; 6423 /** 6424 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 6425 */ 6426 struct dmub_rb_cmd_psr_force_static psr_force_static; 6427 /** 6428 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 6429 */ 6430 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 6431 /** 6432 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 6433 */ 6434 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 6435 /** 6436 * Definition of a DMUB_CMD__HW_LOCK command. 6437 * Command is used by driver and FW. 6438 */ 6439 struct dmub_rb_cmd_lock_hw lock_hw; 6440 /** 6441 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 6442 */ 6443 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 6444 /** 6445 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 6446 */ 6447 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 6448 /** 6449 * Definition of a DMUB_CMD__PLAT_54186_WA command. 6450 */ 6451 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 6452 /** 6453 * Definition of a DMUB_CMD__MALL command. 6454 */ 6455 struct dmub_rb_cmd_mall mall; 6456 6457 /** 6458 * Definition of a DMUB_CMD__CAB command. 6459 */ 6460 struct dmub_rb_cmd_cab_for_ss cab; 6461 6462 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 6463 6464 /** 6465 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 6466 */ 6467 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 6468 6469 /** 6470 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 6471 */ 6472 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 6473 6474 /** 6475 * Definition of DMUB_CMD__PANEL_CNTL commands. 6476 */ 6477 struct dmub_rb_cmd_panel_cntl panel_cntl; 6478 6479 /** 6480 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 6481 */ 6482 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 6483 6484 /** 6485 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 6486 */ 6487 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 6488 6489 /** 6490 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 6491 */ 6492 struct dmub_rb_cmd_abm_set_level abm_set_level; 6493 6494 /** 6495 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 6496 */ 6497 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 6498 6499 /** 6500 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 6501 */ 6502 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 6503 6504 /** 6505 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 6506 */ 6507 struct dmub_rb_cmd_abm_init_config abm_init_config; 6508 6509 /** 6510 * Definition of a DMUB_CMD__ABM_PAUSE command. 6511 */ 6512 struct dmub_rb_cmd_abm_pause abm_pause; 6513 6514 /** 6515 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 6516 */ 6517 struct dmub_rb_cmd_abm_save_restore abm_save_restore; 6518 6519 /** 6520 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 6521 */ 6522 struct dmub_rb_cmd_abm_query_caps abm_query_caps; 6523 6524 /** 6525 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 6526 */ 6527 struct dmub_rb_cmd_abm_get_ace_curve abm_get_ace_curve; 6528 6529 /** 6530 * Definition of a DMUB_CMD__ABM_GET_HISTOGRAM command. 6531 */ 6532 struct dmub_rb_cmd_abm_get_histogram abm_get_histogram; 6533 6534 /** 6535 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 6536 */ 6537 struct dmub_rb_cmd_abm_set_event abm_set_event; 6538 6539 /** 6540 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 6541 */ 6542 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 6543 6544 /** 6545 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 6546 */ 6547 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 6548 6549 /** 6550 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 6551 */ 6552 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 6553 6554 /** 6555 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 6556 */ 6557 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 6558 struct dmub_rb_cmd_drr_update drr_update; 6559 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 6560 6561 /** 6562 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 6563 */ 6564 struct dmub_rb_cmd_lvtma_control lvtma_control; 6565 /** 6566 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 6567 */ 6568 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 6569 /** 6570 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 6571 */ 6572 struct dmub_rb_cmd_transmitter_set_phy_fsm set_phy_fsm; 6573 /** 6574 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 6575 */ 6576 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 6577 /** 6578 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 6579 */ 6580 struct dmub_rb_cmd_set_config_access set_config_access; // (deprecated) 6581 /** 6582 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 6583 */ 6584 struct dmub_rb_cmd_set_config_request set_config_request; 6585 /** 6586 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 6587 */ 6588 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 6589 /** 6590 * Definition of a DMUB_CMD__DPIA_SET_TPS_NOTIFICATION command. 6591 */ 6592 struct dmub_rb_cmd_set_tps_notification set_tps_notification; 6593 /** 6594 * Definition of a DMUB_CMD__EDID_CEA command. 6595 */ 6596 struct dmub_rb_cmd_edid_cea edid_cea; 6597 /** 6598 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 6599 */ 6600 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 6601 6602 /** 6603 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 6604 */ 6605 struct dmub_rb_cmd_query_hpd_state query_hpd; 6606 /** 6607 * Definition of a DMUB_CMD__SECURE_DISPLAY command. 6608 */ 6609 struct dmub_rb_cmd_secure_display secure_display; 6610 6611 /** 6612 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 6613 */ 6614 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 6615 /** 6616 * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 6617 */ 6618 struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle; 6619 /** 6620 * Definition of a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 6621 */ 6622 struct dmub_rb_cmd_idle_opt_set_dc_power_state idle_opt_set_dc_power_state; 6623 /** 6624 * Definition of a DMUB_CMD__REPLAY_SET_VERSION command. 6625 */ 6626 struct dmub_rb_cmd_replay_set_version replay_set_version; 6627 /* 6628 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 6629 */ 6630 struct dmub_rb_cmd_replay_copy_settings replay_copy_settings; 6631 /** 6632 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 6633 */ 6634 struct dmub_rb_cmd_replay_enable replay_enable; 6635 /** 6636 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 6637 */ 6638 struct dmub_rb_cmd_replay_set_power_opt replay_set_power_opt; 6639 /** 6640 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 6641 */ 6642 struct dmub_rb_cmd_replay_set_coasting_vtotal replay_set_coasting_vtotal; 6643 /** 6644 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 6645 */ 6646 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal replay_set_power_opt_and_coasting_vtotal; 6647 6648 struct dmub_rb_cmd_replay_set_timing_sync replay_set_timing_sync; 6649 /** 6650 * Definition of a DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 6651 */ 6652 struct dmub_rb_cmd_replay_set_frameupdate_timer replay_set_frameupdate_timer; 6653 /** 6654 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 6655 */ 6656 struct dmub_rb_cmd_replay_set_pseudo_vtotal replay_set_pseudo_vtotal; 6657 /** 6658 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 6659 */ 6660 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp replay_disabled_adaptive_sync_sdp; 6661 /** 6662 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 6663 */ 6664 struct dmub_rb_cmd_replay_set_general_cmd replay_set_general_cmd; 6665 /** 6666 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 6667 */ 6668 struct dmub_rb_cmd_assr_enable assr_enable; 6669 6670 struct dmub_rb_cmd_fams2 fams2_config; 6671 6672 struct dmub_rb_cmd_ib ib_fams2_config; 6673 6674 struct dmub_rb_cmd_fams2_drr_update fams2_drr_update; 6675 6676 struct dmub_rb_cmd_fams2_flip fams2_flip; 6677 6678 struct dmub_rb_cmd_fused_io fused_io; 6679 6680 /** 6681 * Definition of a DMUB_CMD__LSDMA command. 6682 */ 6683 struct dmub_rb_cmd_lsdma lsdma; 6684 6685 struct dmub_rb_cmd_ips_residency_cntl ips_residency_cntl; 6686 6687 struct dmub_rb_cmd_ips_query_residency_info ips_query_residency_info; 6688 /** 6689 * Definition of a DMUB_CMD__CURSOR_OFFLOAD_INIT command. 6690 */ 6691 struct dmub_rb_cmd_cursor_offload_init cursor_offload_init; 6692 /** 6693 * Definition of a DMUB_CMD__CURSOR_OFFLOAD control commands. 6694 * - DMUB_CMD__CURSOR_OFFLOAD_STREAM_ENABLE 6695 * - DMUB_CMD__CURSOR_OFFLOAD_STREAM_DISABLE 6696 * - DMUB_CMD__CURSOR_OFFLOAD_STREAM_PROGRAM 6697 * - DMUB_CMD__CURSOR_OFFLOAD_STREAM_UPDATE_DRR 6698 */ 6699 struct dmub_rb_cmd_cursor_offload_stream_cntl cursor_offload_stream_ctnl; 6700 /** 6701 * Definition of a DMUB_CMD__SMART_POWER_HDR_ENABLE command. 6702 */ 6703 struct dmub_rb_cmd_smart_power_hdr_enable smart_power_hdr_enable; 6704 /** 6705 * Definition of a DMUB_CMD__DMUB_CMD__SMART_POWER_HDR_GETMAXCLL command. 6706 */ 6707 struct dmub_rb_cmd_smart_power_hdr_getmaxcll smart_power_hdr_getmaxcll; 6708 }; 6709 6710 /** 6711 * union dmub_rb_out_cmd - Outbox command 6712 */ 6713 union dmub_rb_out_cmd { 6714 /** 6715 * Parameters common to every command. 6716 */ 6717 struct dmub_rb_cmd_common cmd_common; 6718 /** 6719 * AUX reply command. 6720 */ 6721 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 6722 /** 6723 * HPD notify command. 6724 */ 6725 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 6726 /** 6727 * SET_CONFIG reply command. 6728 */ 6729 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 6730 /** 6731 * DPIA notification command. 6732 */ 6733 struct dmub_rb_cmd_dpia_notification dpia_notification; 6734 /** 6735 * HPD sense notification command. 6736 */ 6737 struct dmub_rb_cmd_hpd_sense_notify hpd_sense_notify; 6738 struct dmub_rb_cmd_fused_io fused_io; 6739 }; 6740 #pragma pack(pop) 6741 6742 6743 //============================================================================== 6744 //</DMUB_CMD>=================================================================== 6745 //============================================================================== 6746 //< DMUB_RB>==================================================================== 6747 //============================================================================== 6748 6749 /** 6750 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 6751 */ 6752 struct dmub_rb_init_params { 6753 void *ctx; /**< Caller provided context pointer */ 6754 void *base_address; /**< CPU base address for ring's data */ 6755 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 6756 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 6757 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 6758 }; 6759 6760 /** 6761 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 6762 */ 6763 struct dmub_rb { 6764 void *base_address; /**< CPU address for the ring's data */ 6765 uint32_t rptr; /**< Read pointer for consumer in bytes */ 6766 uint32_t wrpt; /**< Write pointer for producer in bytes */ 6767 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 6768 6769 void *ctx; /**< Caller provided context pointer */ 6770 void *dmub; /**< Pointer to the DMUB interface */ 6771 }; 6772 6773 /** 6774 * @brief Checks if the ringbuffer is empty. 6775 * 6776 * @param rb DMUB Ringbuffer 6777 * @return true if empty 6778 * @return false otherwise 6779 */ 6780 static inline bool dmub_rb_empty(struct dmub_rb *rb) 6781 { 6782 return (rb->wrpt == rb->rptr); 6783 } 6784 6785 /** 6786 * @brief gets number of outstanding requests in the RB 6787 * 6788 * @param rb DMUB Ringbuffer 6789 * @return true if full 6790 */ 6791 static inline uint32_t dmub_rb_num_outstanding(struct dmub_rb *rb) 6792 { 6793 uint32_t data_count; 6794 6795 if (rb->wrpt >= rb->rptr) 6796 data_count = rb->wrpt - rb->rptr; 6797 else 6798 data_count = rb->capacity - (rb->rptr - rb->wrpt); 6799 6800 return data_count / DMUB_RB_CMD_SIZE; 6801 } 6802 6803 /** 6804 * @brief gets number of free buffers in the RB 6805 * 6806 * @param rb DMUB Ringbuffer 6807 * @return true if full 6808 */ 6809 static inline uint32_t dmub_rb_num_free(struct dmub_rb *rb) 6810 { 6811 uint32_t data_count; 6812 6813 if (rb->wrpt >= rb->rptr) 6814 data_count = rb->wrpt - rb->rptr; 6815 else 6816 data_count = rb->capacity - (rb->rptr - rb->wrpt); 6817 6818 /* +1 because 1 entry is always unusable */ 6819 data_count += DMUB_RB_CMD_SIZE; 6820 6821 return (rb->capacity - data_count) / DMUB_RB_CMD_SIZE; 6822 } 6823 6824 /** 6825 * @brief Checks if the ringbuffer is full 6826 * 6827 * @param rb DMUB Ringbuffer 6828 * @return true if full 6829 * @return false otherwise 6830 */ 6831 static inline bool dmub_rb_full(struct dmub_rb *rb) 6832 { 6833 uint32_t data_count; 6834 6835 if (rb->wrpt >= rb->rptr) 6836 data_count = rb->wrpt - rb->rptr; 6837 else 6838 data_count = rb->capacity - (rb->rptr - rb->wrpt); 6839 6840 /* -1 because 1 entry is always unusable */ 6841 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 6842 } 6843 6844 /** 6845 * @brief Pushes a command into the ringbuffer 6846 * 6847 * @param rb DMUB ringbuffer 6848 * @param cmd The command to push 6849 * @return true if the ringbuffer was not full 6850 * @return false otherwise 6851 */ 6852 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 6853 const union dmub_rb_cmd *cmd) 6854 { 6855 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 6856 const uint8_t *src = (const uint8_t *)cmd; 6857 uint8_t i; 6858 6859 if (rb->capacity == 0) 6860 return false; 6861 6862 if (dmub_rb_full(rb)) 6863 return false; 6864 6865 // copying data 6866 for (i = 0; i < DMUB_RB_CMD_SIZE; i++) 6867 *dst++ = *src++; 6868 6869 rb->wrpt += DMUB_RB_CMD_SIZE; 6870 6871 if (rb->wrpt >= rb->capacity) 6872 rb->wrpt %= rb->capacity; 6873 6874 return true; 6875 } 6876 6877 /** 6878 * @brief Pushes a command into the DMUB outbox ringbuffer 6879 * 6880 * @param rb DMUB outbox ringbuffer 6881 * @param cmd Outbox command 6882 * @return true if not full 6883 * @return false otherwise 6884 */ 6885 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 6886 const union dmub_rb_out_cmd *cmd) 6887 { 6888 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 6889 const uint8_t *src = (const uint8_t *)cmd; 6890 6891 if (rb->capacity == 0) 6892 return false; 6893 6894 if (dmub_rb_full(rb)) 6895 return false; 6896 6897 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 6898 6899 rb->wrpt += DMUB_RB_CMD_SIZE; 6900 6901 if (rb->wrpt >= rb->capacity) 6902 rb->wrpt %= rb->capacity; 6903 6904 return true; 6905 } 6906 6907 /** 6908 * @brief Returns the next unprocessed command in the ringbuffer. 6909 * 6910 * @param rb DMUB ringbuffer 6911 * @param cmd The command to return 6912 * @return true if not empty 6913 * @return false otherwise 6914 */ 6915 static inline bool dmub_rb_front(struct dmub_rb *rb, 6916 union dmub_rb_cmd **cmd) 6917 { 6918 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 6919 6920 if (dmub_rb_empty(rb)) 6921 return false; 6922 6923 *cmd = (union dmub_rb_cmd *)rb_cmd; 6924 6925 return true; 6926 } 6927 6928 /** 6929 * @brief Determines the next ringbuffer offset. 6930 * 6931 * @param rb DMUB inbox ringbuffer 6932 * @param num_cmds Number of commands 6933 * @param next_rptr The next offset in the ringbuffer 6934 */ 6935 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 6936 uint32_t num_cmds, 6937 uint32_t *next_rptr) 6938 { 6939 if (rb->capacity == 0) 6940 return; 6941 6942 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 6943 6944 if (*next_rptr >= rb->capacity) 6945 *next_rptr %= rb->capacity; 6946 } 6947 6948 /** 6949 * @brief Returns a pointer to a command in the inbox. 6950 * 6951 * @param rb DMUB inbox ringbuffer 6952 * @param cmd The inbox command to return 6953 * @param rptr The ringbuffer offset 6954 * @return true if not empty 6955 * @return false otherwise 6956 */ 6957 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 6958 union dmub_rb_cmd **cmd, 6959 uint32_t rptr) 6960 { 6961 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 6962 6963 if (dmub_rb_empty(rb)) 6964 return false; 6965 6966 *cmd = (union dmub_rb_cmd *)rb_cmd; 6967 6968 return true; 6969 } 6970 6971 /** 6972 * @brief Returns the next unprocessed command in the outbox. 6973 * 6974 * @param rb DMUB outbox ringbuffer 6975 * @param cmd The outbox command to return 6976 * @return true if not empty 6977 * @return false otherwise 6978 */ 6979 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 6980 union dmub_rb_out_cmd *cmd) 6981 { 6982 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 6983 uint64_t *dst = (uint64_t *)cmd; 6984 uint8_t i; 6985 6986 if (dmub_rb_empty(rb)) 6987 return false; 6988 6989 // copying data 6990 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 6991 *dst++ = *src++; 6992 6993 return true; 6994 } 6995 6996 /** 6997 * @brief Removes the front entry in the ringbuffer. 6998 * 6999 * @param rb DMUB ringbuffer 7000 * @return true if the command was removed 7001 * @return false if there were no commands 7002 */ 7003 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 7004 { 7005 if (rb->capacity == 0) 7006 return false; 7007 7008 if (dmub_rb_empty(rb)) 7009 return false; 7010 7011 rb->rptr += DMUB_RB_CMD_SIZE; 7012 7013 if (rb->rptr >= rb->capacity) 7014 rb->rptr %= rb->capacity; 7015 7016 return true; 7017 } 7018 7019 /** 7020 * @brief Flushes commands in the ringbuffer to framebuffer memory. 7021 * 7022 * Avoids a race condition where DMCUB accesses memory while 7023 * there are still writes in flight to framebuffer. 7024 * 7025 * @param rb DMUB ringbuffer 7026 */ 7027 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 7028 { 7029 uint32_t rptr = rb->rptr; 7030 uint32_t wptr = rb->wrpt; 7031 7032 if (rb->capacity == 0) 7033 return; 7034 7035 while (rptr != wptr) { 7036 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 7037 uint8_t i; 7038 7039 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 7040 (void)READ_ONCE(*data++); 7041 7042 rptr += DMUB_RB_CMD_SIZE; 7043 if (rptr >= rb->capacity) 7044 rptr %= rb->capacity; 7045 } 7046 } 7047 7048 /** 7049 * @brief Initializes a DMCUB ringbuffer 7050 * 7051 * @param rb DMUB ringbuffer 7052 * @param init_params initial configuration for the ringbuffer 7053 */ 7054 static inline void dmub_rb_init(struct dmub_rb *rb, 7055 struct dmub_rb_init_params *init_params) 7056 { 7057 rb->base_address = init_params->base_address; 7058 rb->capacity = init_params->capacity; 7059 rb->rptr = init_params->read_ptr; 7060 rb->wrpt = init_params->write_ptr; 7061 } 7062 7063 /** 7064 * @brief Copies output data from in/out commands into the given command. 7065 * 7066 * @param rb DMUB ringbuffer 7067 * @param cmd Command to copy data into 7068 */ 7069 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 7070 union dmub_rb_cmd *cmd) 7071 { 7072 // Copy rb entry back into command 7073 uint8_t *rd_ptr = (rb->rptr == 0) ? 7074 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 7075 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 7076 7077 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 7078 } 7079 7080 //============================================================================== 7081 //</DMUB_RB>==================================================================== 7082 //============================================================================== 7083 #endif /* _DMUB_CMD_H_ */ 7084